Display driving method, timing controller, data driving chip and display device

Abstract

The present application discloses a display driving method, a timing controller, a data driving chip and a display device, which relate to the field of display technology and can improve the poor display of staggered lines in the display of overloaded pictures. A display driving method is applied to a timing controller, and the display driving method comprises: detecting the next frame picture signal of a display panel to determine whether the next frame picture is an overloaded picture; when the next frame picture is the overloaded picture, sending a data driving signal package corresponding to the next frame picture to each data driving chip respectively, and the data driving signal package comprises an odd-numbered row pixel data control signal or an even-numbered row pixel data control signal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display driving method, a timing controller, a data driving chip and a display device. Background Art

[0002] At present, for large-size, high-resolution, and high-refresh-rate display panels, due to load reasons, overloaded images will have COF (Chip on FPC, the driver chip is fixed on the flexible circuit board) Block (large-area defects caused by COF), driver chip temperature exceeding the specification, and other problems. The usual improvement method is to use the image detection function to detect special images, such as overloaded images, and then turn on the Smart_TP (brightness deviation elimination technology) mode, that is, control the odd-numbered frame display to only open odd-numbered lines, and the even-numbered frame display to only open even-numbered lines, and the odd and even frames are combined to realize the display of special images, which can reduce the display load of overloaded images, improve display effects, and avoid display defects.

[0003] However, the anti-interference ability of Smart_TP function is poor. Once an error or interference frame occurs at the front end, or an error occurs at the receiving end of the driver chip due to interference, it is easy to cause the undesirable phenomenon of wrong line. Summary of the invention

[0004] The embodiments of the present application provide a display driving method, a timing controller, a data driving chip and a display device, which can improve the defective staggered display in the overloaded picture display.

[0005] According to a first aspect of an embodiment of the present application, a display driving method is provided, which is applied to a timing controller. The display driving method includes:

[0006] Detecting the next frame image signal of the display panel to determine whether the next frame image is a reloaded image;

[0007] When the next frame is the overloaded frame, a data driving signal package corresponding to the next frame is sent to each data driving chip respectively, and the data driving signal package includes an odd-numbered row pixel data control signal or an even-numbered row pixel data control signal.

[0008] In some implementations, the data driving signal package further includes a reload enable signal, and the reload enable signal is used to control the frame start pulse reset of the data driving chip when the next frame is the reload frame.

[0009] In some embodiments, the data driving signal package further includes valid data, and the valid data is used to drive the corresponding pixel to be illuminated with a corresponding grayscale brightness.

[0010] In some implementations, detecting the next frame image signal of the display panel to determine whether the next frame image is a reloaded image includes:

[0011] Receive the next frame image signal of the display panel sent by the control mainboard;

[0012] It is detected whether the next frame picture signal is an interlaced display signal. When the next frame picture signal is the interlaced display signal, it is determined that the next frame display picture is the overloaded picture.

[0013] In some embodiments, the data driving signal package further includes a clock synchronization communication signal, and the clock synchronization communication signal is used to control the communication between the clock controller and the data driving chip;

[0014] When the reload enable signal is in a high level state, the reload enable signal is valid, and when the reload enable signal is in a low level state, the reload enable signal is invalid.

[0015] In some implementations, the display driving method further includes:

[0016] When the next frame is the overloaded frame, a scan drive signal corresponding to the next frame is sent to each scan drive chip respectively, and the scan drive signal is used to drive the corresponding odd-numbered row pixel drive circuit to turn on or the corresponding even-numbered row pixel drive circuit to turn on.

[0017] According to a second aspect of an embodiment of the present application, a display driving method is provided, which is applied to a data driving chip. The display driving method includes:

[0018] Receiving a data driving signal package sent by a timing controller, wherein the data driving signal package includes an odd-numbered row pixel data control signal or an even-numbered row pixel data control signal;

[0019] Based on the odd-numbered row pixel data control signal, control the odd-numbered row pixel display; or,

[0020] Based on the even-numbered row pixel data control signal, the even-numbered row pixel display is controlled.

[0021] In some implementations, the data driving signal packet further includes a reload enable signal, and the display driving method further includes:

[0022] In the case that the next frame is a reloaded frame, based on the reload enable signal, the count of the frame start pulse of the next frame is controlled to be cleared and re-counted.

[0023] In some implementations, the display driving method further includes:

[0024] According to the count value of the frame start pulse, it is determined whether the current frame picture corresponding to the count value is an odd-numbered row pixel display picture or an even-numbered row pixel display picture.

[0025] In some implementations, the data driving signal packet further includes valid data, and the display driving method further includes:

[0026] Based on the valid data, the corresponding pixel is driven to be illuminated to a grayscale brightness corresponding to the valid data.

[0027] In some implementations, controlling the odd-numbered row pixel display based on the odd-numbered row pixel data control signal includes:

[0028] Based on the odd-numbered row pixel data control signal, control the output of the corresponding valid data to the odd-numbered row pixels;

[0029] The controlling the display of pixels in even-numbered rows based on the even-numbered row pixel data control signal comprises:

[0030] Based on the even-numbered row pixel data control signal, the corresponding valid data is controlled to be output to the even-numbered row pixels.

[0031] According to a third aspect of an embodiment of the present application, a timing controller is provided, comprising:

[0032] a first memory, wherein the first memory stores a computer program;

[0033] A first processor, wherein the first processor is configured to implement the display driving method as described in the first aspect when executing the computer program.

[0034] According to a fourth aspect of an embodiment of the present application, a data driver chip is provided, comprising:

[0035] a second memory, wherein the second memory stores a computer program;

[0036] A second processor, wherein the second processor is configured to implement the display driving method as described in the second aspect when executing the computer program.

[0037] According to a fifth aspect of the embodiments of the present application, a display device is provided, including:

[0038] A timing controller as described in the third aspect.

[0039] In some embodiments, the display device further includes:

[0040] As in the data driving chip of the fourth aspect, the data driving chip is electrically connected to the timing controller.

[0041] The display driving method, timing controller, data driving chip and display device provided by the embodiments of the present application detect the next frame picture signal of the display panel through the timing controller to determine whether the next frame picture is a reloaded picture. When the next frame picture is a reloaded picture, the odd-row pixel data control signal or the even-row pixel data control signal corresponding to the next frame picture is sent to each data driving chip respectively. Then, the data driving chip performs display driving for the interlaced display of the reloaded picture based on the odd-row pixel data control signal or the even-row pixel data control signal. The data driving chip does not need to control the odd-row pixel display or the even-row pixel display based on the frame start pulse count. The data control signals received by multiple data driving chips are synchronous, and different data driving chips will not receive different pixel row drives, that is, all data driving chips receive odd-row pixel data control signals or even-row pixel data control signals, which can avoid poor display of staggered rows between different data driving chips due to errors caused by interference with the frame start pulse count. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic flow chart of a display driving method provided in an embodiment of the present application;

[0043] Figure 2 A schematic diagram of a data signal structure of a data drive signal package provided in an embodiment of the present application;

[0044] Figure 3 A schematic flow chart of another display driving method provided in an embodiment of the present application;

[0045] Figure 4 A control timing diagram corresponding to a display driving method provided in an embodiment of the present application;

[0046] Figure 5 A schematic structural block diagram of a timing controller provided in an embodiment of the present application;

[0047] Figure 6 A schematic structural block diagram of a data driver chip provided in an embodiment of the present application;

[0048] Figure 7 A schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification are described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0050] In this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. The term "more than two" includes two or more than two situations.

[0051] At present, for large-size, high-resolution, and high-refresh-frequency display panels, due to load reasons, overloaded screens will cause problems such as COF Block and over-specification of driver chip temperature. The usual improvement method is to use the screen detection function to detect special screens, such as overloaded screens, and then turn on the Smart_TP mode, that is, control the odd-numbered frame display to only open odd-numbered lines, and the even-numbered frame display to only open even-numbered lines. The odd and even frames are combined to realize the display of special screens, which can reduce the display load of overloaded screens, improve the display effect, and avoid poor display. However, the anti-interference ability of the Smart_TP function is poor. Once an error or interference frame occurs at the front end, or an error occurs at the receiving end of the driver chip due to interference, it is easy to cause the undesirable phenomenon of wrong lines.

[0052] In view of this, the embodiments of the present application provide a display driving method, a timing controller, a data driving chip and a display device, which can improve the staggered display defect occurring in the overloaded picture display.

[0053] In a first aspect of an embodiment of the present application, a display driving method is provided, which is applied to a timing controller. Figure 1 Schematic flow chart of a display driving method provided in an embodiment of the present application. Figure 1 As shown, the display driving method provided in the embodiment of the present application includes:

[0054] S100: Detect the next frame image signal of the display panel to determine whether the next frame image is a heavy-loaded image. The image signal corresponding to the heavy-loaded image is an interlaced display image signal. The overloaded image has a large load and displays more information. Interlaced display can reduce the load of the display image. Interlaced display of the heavy-loaded image in a display panel with a large resolution and a high refresh rate will not affect the display effect. The human eye cannot distinguish the interlaced display in each frame, and two adjacent frames can form a complete display image.

[0055] S200: When the next frame is a reloaded frame, a data driving signal package corresponding to the next frame is sent to each data driving chip, wherein the data driving signal package includes an odd-numbered row pixel data control signal or an even-numbered row pixel data control signal. The odd-numbered row pixel data control signal can drive the odd-numbered row pixel display of the display panel to realize the interlaced display of the reloaded frame; the even-numbered row pixel data control signal can drive the even-numbered row pixel display of the display panel to realize the interlaced display of the reloaded frame.

[0056] It should be noted that for large-size, high-resolution, and high-refresh-frequency panels, due to load reasons, overloaded screens will have problems such as COF Block and over-specification of driver chip temperature. The PDF (Pattern Detect Function) function of TCON (timing controller) can be used to detect special screens and turn on the Smart_TP+GOA Dual Scan mode. The GOA Dual Scan mode changes the timing of GOA (Gate On Array). STV (frame start signal) is divided into STVA and STVB. STVA controls the display of odd rows, and STVB controls the display of even rows. Specifically, STVA controls the gate opening of the driving TFT (thin-film transistor) of the odd-numbered row pixels, that is, STVA scans the odd-numbered row pixels, and STVB controls the gate opening of the driving TFT of the even-numbered row pixels. STVB scans the even-numbered row pixels. The odd-numbered frame display only turns on the driving circuit of the odd-numbered row, and the even-numbered frame display only turns on the driving circuit of the even-numbered row. The odd and even frames are combined to realize the special screen display. Taking 8K resolution and 288Hz refresh rate as an example, the COF temperature of the overloaded screen is 135℃, which exceeds the temperature specification. After turning on the Smart_TP function, the COF temperature is 85℃, which meets the temperature specification. However, the existing Smart TP function is to send a Smart_TP function start signal to the data driver chip through the timing controller. The data driver chip determines whether the next frame of the display screen drives the odd-numbered rows of pixels to display or the even-numbered rows of pixels to display based on the Smart_TP function start signal and the current GSP (GatestartPulse, frame start pulse) count. The GSP count is a count of the frames of the display screen. For example, the GSP count is 4, which means that the current display screen is the 4th frame of the display screen. Exemplarily, when the data driver chip receives the Smart_TP function start signal sent by the timing controller and recognizes that the GSP count of the current frame is 4, the GSP count of the next frame is 5, and the data driver chip can automatically determine that the next frame of the screen drives the odd-numbered rows of pixels to display, that is, drives the 1st row of pixels, the 3rd row of pixels, the 5th row of pixels... to display. However, the GSP counting has poor anti-interference ability. Once an error or interference frame occurs at the front end, or a GSP counting error occurs at the receiving end of the driver chip due to interference, the data driver chip will drive the wrong pixel display. Usually, a large-size display panel is equipped with two or more data driver chips. The GSP counting error of a data driver chip will cause different data driver chips to drive different rows of pixel display, which will cause the display panel to display the wrong row.

[0057] It should be noted that the execution subject of the display driving method steps provided in the embodiment of the present application may be a timing controller.

[0058] The display driving method provided in the embodiment of the present application detects the next frame picture signal of the display panel through the timing controller to determine whether the next frame picture is an overloaded picture. When the next frame picture is an overloaded picture, the odd-row pixel data control signal or the even-row pixel data control signal corresponding to the next frame picture is sent to each data driving chip respectively. Then, the data driving chip performs display driving for the interlaced display of the overloaded picture based on the odd-row pixel data control signal or the even-row pixel data control signal. The data driving chip does not need to control the odd-row pixel display or the even-row pixel display based on the GSP count. The data control signals received by multiple data driving chips are synchronous, and different data driving chips will not receive different pixel row drives, that is, all data driving chips receive odd-row pixel data control signals or even-row pixel data control signals, which can avoid poor display of different rows between different data driving chips due to errors caused by interference with the GSP count.

[0059] In some implementations, step S100 may include:

[0060] Receive the next frame image signal of the display panel sent by the control mainboard. The control mainboard may be integrated with a main controller of the display device or display panel, and the main controller may be burned with the image signals of all display images.

[0061] Detect whether the next frame image signal is an interlaced display signal. If the next frame image signal is an interlaced display signal, determine that the next frame image is an overloaded image. The main controller can determine which frames are overloaded images in advance based on the amount of information on the display image or other evaluation indicators. After data analysis, the image signals corresponding to the odd and even frames corresponding to the overloaded images can be obtained, that is, the image signal of each frame image corresponding to the overloaded image is a signal that drives the interlaced display. Then, the timing controller can determine whether the next frame image signal corresponds to an overloaded image by identifying whether the display signal is an interlaced display signal.

[0062] In some embodiments, the data drive signal package also includes a reload enable signal, which is used to control the frame start pulse reset of the data drive chip when the next frame is a reloaded picture. Exemplarily, the reload enable signal TP_EN can be represented by high and low levels. When the reload enable signal TP_EN is in a high level state, the reload enable signal is valid, and the high level state can be represented by binary as 1; when the reload enable signal TP_EN is in a low level state, the reload enable signal is invalid, and the low level state can be represented by binary as 0. If the TP_EN output is 1, it means that the interlaced display function of the reloaded picture is started, and if the TP_EN output is 0, it means that the interlaced display function of the reloaded picture is not started. Similarly, if the TP_EN output changes from 0 to 1, the interlaced display function of the reloaded picture can be controlled to start, and if the TP_EN output changes from 1 to 0, the interlaced display function of the reloaded picture can be controlled to be turned off.

[0063] Exemplarily, a valid reload enable signal is used to control the frame start pulse reset of the data driver chip. The reset of the frame start pulse can be to reset the count after the count is cleared. Then, upon receiving the signal TP_EN=1, the GSP clears the count and restarts the count from 1. The count value of the frame start pulse can be used to determine whether the current frame is an odd-numbered row pixel display screen or an even-numbered row pixel display screen. Exemplarily, within the timing interval of TP_EN=1, the count value of the GSP is 3, which means that the current frame is an odd-numbered frame, and the odd-numbered row pixels are lit and displayed.

[0064] In the display driving method provided in the embodiment of the present application, the overload enable signal is used to control the count reset of the frame start pulse, but the count value of the frame start pulse is no longer used to determine the display drive of the data driver chip for the count row pixels or the even row pixels. On the basis of realizing the interlaced display of the overloaded picture, it can avoid the poor display of the wrong row between different data driver chips caused by the interference and error of the GSP count.

[0065] In some embodiments, the data drive signal package also includes valid data, and the valid data is used to drive the corresponding pixel to be lit up to the corresponding grayscale brightness. Exemplarily, the display panel takes an organic light-emitting display panel as an example, and the valid data is a data signal, which is transmitted to the source of the pixel's driving TFT through a data signal line. The source receives the valid data to drive the anode and cathode of the light-emitting device to form a loop. The voltage or current of the source can determine the current between the anode and cathode of the light-emitting device, and then determine the brightness of the light emitted by the light-emitting device, which plays a role in controlling the brightness of the pixel. The brightness of the pixel is the display grayscale. Then the valid data can be the driving voltage or current of the source terminal or drain terminal corresponding to the pixel.

[0066] In some implementations, the data driving signal package further includes a clock synchronization communication signal, and the clock synchronization communication signal is used to control the communication between the clock controller and the data driving chip.

[0067] For example, Figure 2 Schematic diagram of a data signal structure of a data drive signal package provided in an embodiment of the present application. Figure 2 As shown, the data drive signal packet is in the form of CEDS (Clock Embedded Differential Signal), including a clock synchronization bit CT, a control bit Control Packet and valid data Data, and the first valid data First Data is close to the control bit Control Packet and the valid data Data. The clock synchronization bit CT can be used to place the clock synchronization communication signal, and the control bit Control Packet can be used to place the heavy load enable signal TP_EN and the heavy load control signal TP_Control. Exemplarily, TP_Control=0 can represent the odd-numbered row pixel data control signal, and TP_Control=1 can represent the even-numbered row pixel data control signal. CTRS, CTR1 and CTR2 can place different control signals.

[0068] Illustratively, Table 1 shows the signal structure of the control bit CTR2.

[0069]

[0070] Table 1

[0071] As shown in Table 1, Packet is a message grouping, or can be understood as a data-driven signal bit, Bit No is the specific data bit number of the control bit CTR2, a total of 28 bits of data, bits 0 to 21 correspond to the clock signal CK, bit 22 corresponds to the overload enable signal TP_EN, bit 23 corresponds to the overload control signal TP_Control, bits 24 and 25 are empty bits NC, bits 26 and 27 of DMY can also be understood as blank bits, then CK and DMY can be used as identification bits, Packet Name is the message name, Table 1 is only exemplary and is not a specific limitation of the present application.

[0072] In some embodiments, when the next frame is a heavy-loaded frame, a scan drive signal corresponding to the next frame is sent to each scan driver chip, and the scan drive signal is used to drive the corresponding odd-numbered row pixel drive circuit to turn on or the corresponding even-numbered row pixel drive circuit to turn on. Specifically, it can be realized by the frame start signal STV, STVA controls the scanning of odd-numbered row pixels, and STVB controls the scanning of even-numbered row pixels. In the process of displaying the picture, the scan drive signal and the data drive signal are implemented in cooperation with each other. The scan drive signal is used to turn on the drive circuit of the row pixel, for example, to turn on the gate of the drive TFT of the row pixel to turn on the TFT, and the data drive signal transmits the data signal to the source or drain of the drive TFT to drive the light-emitting device to emit light, and the display of different pixels constitutes the display picture. In the display process of the heavy-loaded picture, the scan drive signal drives the odd-numbered row pixel drive circuit in the same frame picture, and the timing controller sends the odd-numbered row data control signal; the scan drive signal drives the even-numbered row pixel drive circuit in the same frame picture, and the timing controller sends the even-numbered row data control signal.

[0073] A second aspect of the embodiments of the present application provides a display driving method, which is applied to a data driving chip. Figure 3 A schematic flow chart of another display driving method provided in an embodiment of the present application. Figure 3 As shown, the display driving method of the embodiment of the present application includes:

[0074] S300: receiving a data driving signal packet sent by a timing controller, wherein the data driving signal packet includes an odd-numbered row pixel data control signal or an even-numbered row pixel data control signal. It should be noted that the data driving signal packet for the next frame is usually received when the current frame is displayed, and is used to prepare for driving the display driver for the next frame.

[0075] S400: Based on the odd-numbered pixel data control signal, control the display of the odd-numbered pixel rows. In the case where the received odd-numbered pixel data control signal is used, the data driver chip can control the display of the odd-numbered pixel rows based on the odd-numbered pixel data control signal, and the even-numbered pixel rows are not displayed, then the corresponding odd-numbered pixel rows of the current frame are displayed, and the next frame is the even-numbered pixel rows displayed, and the adjacent odd-numbered pixel rows and the even-numbered pixel rows can form a complete display screen.

[0076] or,

[0077] S500: Control the display of even-numbered row pixels based on the even-numbered row pixel data control signal. In the case where the even-numbered row pixel data control signal is received, the data driver chip can control the display of even-numbered row pixels based on the even-numbered row pixel data control signal, and the odd-numbered row pixels are not displayed, then the even-numbered row pixels of the corresponding current frame are displayed, and the odd-numbered row pixels of the next frame are displayed, and the adjacent odd-numbered row pixel display screen and the even-numbered row pixel display screen can form a complete display screen.

[0078] It should be noted that for large-size, high-resolution, and high-refresh-frequency panels, due to load reasons, overloaded screens will have problems such as COF Block and over-specification of driver chip temperature. The PDF function of TCON can be used to detect special screens and turn on the Smart_TP+GOA Dual Scan mode. The GOA Dual Scan mode changes the timing of GOA. STV is divided into STVA and STVB. STVA controls the display of odd rows, and STVB controls the display of even rows. The odd-numbered frame display only turns on the drive circuit of the odd rows, and the even-numbered frame display only turns on the drive circuit of the even rows. The odd and even frames are merged to realize special screen display. Taking 8K resolution and 288Hz refresh rate as an example, the COF temperature of the overloaded screen is 135℃, which exceeds the temperature specification. After turning on the Smart_TP function, the COF temperature is 85℃, which meets the temperature specification. However, the existing Smart_TP function is to send a Smart_TP function start signal to the data driver chip through the timing controller. The data driver chip determines whether to drive the odd-numbered rows of pixels to display or the even-numbered rows of pixels to display in the next frame of display according to the Smart_TP function start signal and based on the current GSP count. The GSP count is a count of the frames of the display. For example, if the GSP count is 4, it means that the current display is the 4th frame of the display. Exemplarily, when the data driver chip receives the Smart_TP function start signal sent by the timing controller and recognizes that the GSP count of the current frame is 4, the GSP count of the next frame is 5, and the data driver chip can automatically determine that the next frame drives the odd-numbered rows of pixels to display, that is, drives the 1st row of pixels, the 3rd row of pixels, the 5th row of pixels... to display. However, the GSP counting has poor anti-interference ability. Once an error or interference frame occurs at the front end, or a GSP counting error occurs at the receiving end of the driver chip due to interference, the data driver chip will drive the wrong pixel display. Usually, a large-size display panel is equipped with two or more data driver chips. The GSP counting error of a data driver chip will cause different data driver chips to drive different rows of pixel display, which will cause the display panel to display the wrong row.

[0079] It should be noted that the execution subject of the display driving method steps provided in the embodiment of the present application may be a data driving chip.

[0080] The display driving method provided in the embodiment of the present application is based on the odd-row pixel data control signal or the even-row pixel data control signal sent by the timing controller. The data driving chip performs display driving based on the odd-row pixel data control signal or the even-row pixel data control signal, which can realize interlaced display of heavy-loaded pictures. The data driving chip does not need to control the odd-row pixel display or the even-row pixel display based on the GSP count, which can avoid poor misaligned display between different data driving chips due to errors caused by interference with the GSP count.

[0081] In some implementations, the data driving signal packet further includes a reload enable signal. When the next frame is a reloaded frame, the reload enable signal is valid. The display driving method further includes:

[0082] In the case where the next frame is a reloaded picture, based on the reload enable signal, the count of the frame start pulse of the next frame is controlled to be cleared and re-counted. It should be noted that, when the current frame is a non-reloaded picture and the next frame is a reloaded picture, the reload enable signal is valid, and the count of the frame start pulse can be controlled to be cleared and re-counted from the next reloaded picture.

[0083] In some implementations, the display driving method further includes:

[0084] According to the count value of the frame start pulse, it is determined whether the current frame picture corresponding to the count value is an odd-numbered row pixel display picture or an even-numbered row pixel display picture.

[0085] In some implementations, the data driving signal packet further includes valid data, and the display driving method further includes:

[0086] Based on the valid data, the corresponding pixel is driven to be illuminated to the grayscale brightness corresponding to the valid data.

[0087] In some implementations, step S400 may include:

[0088] Based on the odd-numbered row pixel data control signal, control the output of corresponding valid data to the odd-numbered row pixels;

[0089] Step S500 may include:

[0090] Based on the even-numbered row pixel data control signal, the corresponding valid data is controlled to be output to the even-numbered row pixels.

[0091] Exemplary, reference Figure 2, CEDS, including CT, control packet and Data, accurately defines the Smart_TP function through Control Packet. Control Packet includes TP_EN and TP_Control. It is the TP_Control sent by the timing controller to confirm the parity line instead of confirming through GSP, which can avoid errors or interference frames in the front end.

[0092] In a specific example, TP_Control=0 is defined, and the data driver chip only outputs odd-numbered row data to odd-numbered row pixels, that is, outputs corresponding valid data to the 1st row of pixels, the 3rd row of pixels, the 5th row of pixels, etc., and the data driver chip only receives and does not output valid data corresponding to even-numbered row pixels, that is, does not output valid data to the 2nd row of pixels, the 4th row of pixels, the 6th row of pixels, etc.; TP_Control=1 is defined, and the data driver chip only outputs odd-numbered row data to even-numbered row pixels, that is, outputs corresponding valid data to the 3rd row of pixels, the 4th row of pixels, the 6th row of pixels, etc., and the data driver chip only receives and does not output valid data corresponding to odd-numbered row pixels, that is, does not output valid data to the 1st row of pixels, the 3rd row of pixels, the 5th row of pixels, etc. Specific implementation process: After the control mainboard transmits the screen signal of the overloaded screen to the timing controller, the front end detects it through PDF to the special timing controller, and changes TP_EN to 1 to turn on the Smart_TP function. In the first frame, TP_Control is 0, the data driver chip only outputs odd-numbered row data, STVB is blanked in this frame, the drive circuit corresponding to the even-numbered row pixels is not turned on, that is, the gate of the drive TFT corresponding to the even-numbered row pixels is closed; in the second frame, TP_Control is 1, the data driver chip only outputs even-numbered row data, STVA is blanked in this frame, the drive circuit corresponding to the odd-numbered row pixels is not turned on, that is, the gate of the drive TFT corresponding to the odd-numbered row pixels is closed; the odd and even frames are confirmed by GSP counting. It should be noted that TP_Control is 1, which can be represented by a high level, and TP_Control is 0, which can be represented by a low level.

[0093] Exemplarily, Table 2 is a table of corresponding relations for the output of the 1st, 2nd and 3rd frames of the overloaded screen. Table 2 shows the output of some pixel rows of the 3 frames. After PDF is turned on, TP_EN changes from 0 to 1, and the Smart_TP function is turned on. In the 1st frame, TP_Control is 0, which can be a low-level state. This frame is an odd frame. 1-1 is the 1st row of data in the 1st frame, which is an odd row of data. The data driver chip outputs the valid data corresponding to 1-1, and the state is O; 1-2 is the 2nd row of data in the 1st frame, which is an even row of data. The data driver chip only receives but does not output, and maintains the data output of 1-1, and the state is X; 1-3, 1-4, ... and so on. In the second frame, TP_Control is 1, which can be a high-level state. This is an even frame. 2-1 is the first row of data in the second frame, which is an odd row of data. The data driver chip only receives but does not output, and maintains the data output of the last row of the previous frame, that is, maintains the 1-3 output; 2-2 is the second row of data in the second frame, which is an even row of data. The data driver chip directly outputs, 2-3, 2-4, ... and so on; the third frame, the fourth frame ... and so on, are not listed one by one here.

[0094]

[0095] Table 2

[0096] For example, Figure 4 A control timing diagram corresponding to a display driving method provided in an embodiment of the present application. Figure 4As shown, taking 256 grayscale display as an example, ODD represents the voltage V1 corresponding to 255 grayscale, and EVEN represents the voltage V18 corresponding to 0 grayscale. In CEDS, 1_1 (ODD) means that the first row of pixels in the first frame displays 255 grayscale, 1_2 (EVEN) means that the second pixel in the first frame displays 0 grayscale, 1_3 (ODD) means that the third row of pixels in the first frame displays 255 grayscale, and 1_4 (EVEN) means that the fourth row of pixels in the first frame displays 0 grayscale, then the corresponding first frame is an odd-numbered row of pixels; 2_1 (EVEN) means that the first row of pixels in the second frame displays 0 grayscale, 2_2 (ODD) means that the second pixel in the second frame displays 255 grayscale, 2_3 (EVEN) means that the third row of pixels in the second frame displays 0 grayscale, and 2_4 (ODD) means that the fourth row of pixels in the second frame displays 255 grayscale, then the corresponding second frame is an even-numbered row of pixels. PacketData is the message data packet of CEDS. TP_EN low level means Smart_TP OFF, i.e. Smart_TP function is off, TP_EN high level means Smart_TP ON, i.e. Smart_TP function is on. TP_Control is low level, which means the output of data driver chip Output = ODD line data, i.e. odd-numbered row pixel data, TP_Control is high level, which means the output of data driver chip Output = ENEN line data, i.e. even-numbered row pixel data. GSP jumps to high level at the beginning of each frame to count. Int SOE is the scan drive signal, i.e. in the first frame, odd-numbered rows are high level, and in the second frame, even-numbered rows are high level. Figure 4 The dashed lines in the timing diagram of Int SOE shown represent the suppression of the signal.

[0097] It should be noted that, by detecting the timing of TP_Control, it can be determined whether the driving method provided in the embodiment of the present application is used to drive the display panel to display the picture.

[0098] According to a third aspect of the embodiments of the present application, a timing controller is provided. Figure 5 This is a schematic structural block diagram of a timing controller provided in an embodiment of the present application. Figure 5 As shown, the timing controller provided in the embodiment of the present application includes:

[0099] A first memory 600, wherein a computer program is stored in the first memory 600;

[0100] The first processor 700 is configured to implement the display driving method as described in the first aspect when executing the computer program.

[0101] In a fourth aspect of the embodiments of the present application, a data driver chip is provided. Figure 6 This is a schematic structural block diagram of a data driver chip provided in an embodiment of the present application. Figure 6 As shown, the data driver chip provided in the embodiment of the present application includes:

[0102] A second memory 800, wherein the second memory 800 stores a computer program;

[0103] The second processor 900 is used to implement the display driving method as described in the second aspect when executing the computer program.

[0104] According to a third aspect of the embodiments of the present application, a display device is provided. Figure 7 Schematic diagram of a display device provided in an embodiment of the present application. Figure 7 As shown, the display device provided in the embodiment of the present application includes: a timing controller TCON, and the timing controller TCON is used to execute the display driving method as described in the first aspect.

[0105] In some embodiments, reference Figure 7 The display device provided in the embodiment of the present application further includes: a data driver chip Driver IC, the data driver chip Driver IC is used to execute the display driving method as described in the second aspect. The timing controller TCON is electrically connected to the data driver chip Driver IC, and the data driver chip Driver IC is electrically connected to the pixels in the display panel panel. Figure 5 The number of the data driver chips Driver IC shown is 3, which is only for illustration and is not a specific limitation of the present application.

[0106] The display device provided in the embodiment of the present application is provided with a timing controller and a data driver chip. The timing controller detects the next frame picture signal of the display panel to determine whether the next frame picture is an overloaded picture. When the next frame picture is an overloaded picture, the odd-row pixel data control signal or the even-row pixel data control signal corresponding to the next frame picture is sent to each data driver chip respectively. Then, the data driver chip performs display driving for the interlaced display of the overloaded picture based on the odd-row pixel data control signal or the even-row pixel data control signal. The data driver chip does not need to control the odd-row pixel display or the even-row pixel display based on the GSP count, so that poor misaligned display between different data driver chips caused by errors due to interference with the GSP count can be avoided.

[0107] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0108] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-readable program code.

[0109] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0110] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0111] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0112] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes a process of a display driving method.

[0113] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integration. Available media can be magnetic media, (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid state disk (solid state disk, SSD)), etc.

[0114] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0115] In the several embodiments provided in the present application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0116] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0117] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0118] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0119] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0120] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0121] Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalents, this specification is also intended to include these modifications and variations.

Claims

1. A display driving method, characterized in that: Applied to a timing controller, the display driving method comprises: Detecting the next frame image signal of the display panel to determine whether the next frame image is a reloaded image; When the next frame is the overloaded frame, a data driving signal packet corresponding to the next frame is sent to each data driving chip, wherein the data driving signal packet includes an odd-numbered row pixel data control signal or an even-numbered row pixel data control signal; The data driving signal package further includes a reload enable signal. When the next frame is a reloaded frame, based on the reload enable signal, the count of the frame start pulse of the next frame is controlled to be cleared and re-counted. According to the count value of the frame start pulse, it is determined whether the current frame picture corresponding to the count value is an odd-numbered row pixel display picture or an even-numbered row pixel display picture.

2. The display driving method according to claim 1, characterized in that: The data driving signal package further includes a reload enable signal, and the reload enable signal is used to control the frame start pulse reset of the data driving chip when the next frame picture is the reload picture.

3. The display driving method according to claim 1, characterized in that: The data driving signal package also includes valid data, and the valid data is used to drive the corresponding pixel to be illuminated with a corresponding grayscale brightness.

4. The display driving method according to claim 1, characterized in that: The detecting the next frame image signal of the display panel to determine whether the next frame image is a reloaded image includes: Receive the next frame image signal of the display panel sent by the control mainboard; It is detected whether the next frame picture signal is an interlaced display signal. If the next frame picture signal is the interlaced display signal, it is determined that the next frame picture is the overloaded picture.

5. The display driving method according to claim 2, characterized in that: The data driving signal package also includes a clock synchronization communication signal, and the clock synchronization communication signal is used to control the communication between the clock controller and the data driving chip; When the reload enable signal is in a high level state, the reload enable signal is valid, and when the reload enable signal is in a low level state, the reload enable signal is invalid.

6. The display driving method according to claim 1, characterized in that: Also includes: When the next frame is the overloaded frame, a scan drive signal corresponding to the next frame is sent to each scan drive chip respectively, and the scan drive signal is used to drive the corresponding odd-numbered row pixel drive circuit to turn on or the corresponding even-numbered row pixel drive circuit to turn on.

7. A display driving method, characterized in that: Applied to a data driving chip, the display driving method comprises: Receiving a data driving signal package sent by a timing controller, wherein the data driving signal package includes an odd-numbered row pixel data control signal or an even-numbered row pixel data control signal; Based on the odd-numbered row pixel data control signal, control the odd-numbered row pixel display; or, Based on the even-numbered row pixel data control signal, control the display of the even-numbered row pixels; The data driving signal package also includes a reload enable signal, In the case where the next frame is a reloaded frame, based on the reload enable signal, the count of the frame start pulse of the next frame is controlled to be cleared and re-counted; According to the count value of the frame start pulse, it is determined whether the current frame picture corresponding to the count value is an odd-numbered row pixel display picture or an even-numbered row pixel display picture.

8. The display driving method according to claim 7, characterized in that: The data driving signal packet also includes valid data, and the display driving method further includes: Based on the valid data, the corresponding pixel is driven to be illuminated to a grayscale brightness corresponding to the valid data.

9. The display driving method according to claim 8, characterized in that: The controlling the odd-numbered row pixel display based on the odd-numbered row pixel data control signal comprises: Based on the odd-numbered row pixel data control signal, control the output of the corresponding valid data to the odd-numbered row pixels; The controlling the display of pixels in even-numbered rows based on the even-numbered row pixel data control signal comprises: Based on the even-numbered row pixel data control signal, the corresponding valid data is controlled to be output to the even-numbered row pixels.

10. A timing controller, characterized in that: include: a first memory, wherein the first memory stores a computer program; A first processor, wherein the first processor is configured to implement the display driving method according to any one of claims 1 to 6 when executing the computer program.

11. A data drive chip, characterized in that: include: a second memory, wherein the second memory stores a computer program; A second processor, wherein the second processor is configured to implement the display driving method according to any one of claims 7 to 9 when executing the computer program.

12. A display device, characterized in that: include: The timing controller as claimed in claim 10.

13. The display device according to claim 12, characterized in that: Also includes: The data driver chip according to claim 11, wherein the data driver chip is electrically connected to the timing controller.

Images