A duty cycle regulator

Abstract

The present invention relates to a duty cycle regulator, comprising: a first duty cycle regulation DCA module, the first DCA module comprising M parallel regulation units, each regulation unit comprising a NAND gate and an NMOS transistor, each regulation unit being configured to: cause a timing delay inputted to the NAND gate from a low level to a high level to prevent the NMOS from being turned on at a rising edge of a signal, thereby preventing the NMOS from changing the rising edge of the signal; and cause a timing delay inputted to the NAND gate from a high level to a low level to cause the NMOS to be turned on at a falling edge of the signal, thereby delaying the falling edge of the signal and increasing the duty cycle of the signal.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and more particularly, to a duty cycle regulator. Background Art

[0002] For some semiconductor devices, there may be a need to adjust the duty cycle. In some cases, it may be desirable to adjust only the falling edge while keeping the rising edge unchanged.

[0003] For example, for DDR5, the duty cycle of the bidirectional data control pin (DQS) internal clock can be adjusted according to Section 4.41 of the JEDEC (Solid State Electronics Association) FESD79-5A specification standard. However, the duty cycle adjustment may affect the tDQSCK timing, which is not expected. Summary of the Invention

[0004] The present invention relates to a duty cycle regulator, comprising: a first duty cycle regulation DCA module, wherein the first DCA module comprises M parallel-connected regulation units, each regulation unit comprising a NAND gate and an NMOS transistor, and each regulation unit being configured to: cause a timing delay inputted to the NAND gate from a low level to a high level to prevent the NMOS from being turned on at a rising edge of a signal, thereby preventing the NMOS from changing the rising edge of the signal; and cause a timing delay inputted to the NAND gate from a high level to a low level to cause the NMOS to be turned on at a falling edge of a signal, thereby delaying the falling edge of the signal, thereby increasing the duty cycle. The duty cycle of the signal, and / or a second duty cycle adjustment DCA module, the second DCA module includes N parallel adjustment units, each adjustment unit includes a NAND gate and a PMOS transistor, and each adjustment unit is configured to: a timing delay of the input to the NAND gate from a low level to a high level causes the PMOS to not be turned on at the rising edge of the signal, so that the PMOS does not change the rising edge of the signal; and a timing delay of the input to the NAND gate from a high level to a low level causes the PMOS to be turned on at the falling edge of the signal, so that the PMOS advances the falling edge of the signal to reduce the duty cycle of the signal.

[0005] In the duty cycle regulator described above, the gate of the NMOS is coupled to the output of the NAND gate, the drain of the NMOS is coupled to the input signal whose duty cycle is to be adjusted, and the source of the NMOS is coupled to ground; and / or the gate of the PMOS is coupled to the output of the NAND gate, the drain of the PMOS is coupled to the input signal whose duty cycle is to be adjusted, and the source of the PMOS is coupled to a power supply.

[0006] As described above, in the first DCA module, the duty cycle regulator includes an inverter between the NAND gate and the NMOS.

[0007] As described above, the input signal passes through an inverter before being input to the drain of the NMOS or the PMOS, and the final output signal of the duty cycle regulator includes an inverter before it.

[0008] In the duty cycle regulator as described above, the first input of the NAND gate of each regulating unit is a high level or a low level. When the first input is a high level, the high level controls the regulating unit to be in a valid state, and when the first input is a low level, the low level controls the regulating unit to be in an invalid state. The second input line of the NAND gate of each regulating unit includes a delay device, so that the second input of the NAND gate of each regulating unit is a delayed input signal, and the state of each regulating unit can be independently controlled.

[0009] As described above, the delay amount generated by the delay device on the input signal is set to: at least make the entire rising edge of the signal whose duty cycle is to be adjusted fall within the low level area of the delayed input signal, and correspondingly, make the entire falling edge of the signal whose duty cycle is to be adjusted fall within the high level area of the delayed input signal.

[0010] The duty cycle regulator as described above is provided in a delay phase-locked loop (DLL) circuit, and the change of the falling edge is performed during the DLL locking period.

[0011] The duty cycle regulator as described above is arranged after the MIMIC circuit in the DLL circuit.

[0012] As described above, when the duty cycle regulator includes both the first DCA module and the second DCA module, the first DCA module and the second DCA module are connected in parallel.

[0013] As described above for the duty cycle regulator, M is equal to N.

[0014] The duty cycle regulator as described above includes a duty cycle regulator for the internal clock of the DDR5 single-phase bidirectional data control pin DQS.

[0015] As described above, each duty cycle regulator includes the first DCA module and the second DCA module connected in parallel, wherein the first DCA module includes 7 adjustment units and the second DCA module includes 7 adjustment units; the duty cycle regulator is configured to use the mode register MR43 OP[2:0] to specify the step of duty cycle adjustment, and use MR43 OP[3] to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7.

[0016] As described above, the duty cycle regulator, the 14 steps are realized by utilizing different state combinations of 14 regulating units connected in parallel.

[0017] As described above, the first DCA module is configured to execute steps +1 to +7, and the second DCA module is configured to execute step adjustments -1 to -7, and wherein steps +1 to +7 correspond to 1 to 7 of the 7 adjustment units in the first DCA module being valid, and steps -1 to -7 correspond to 1 to 7 of the 7 adjustment units in the second DCA module being valid.

[0018] As described above, the duty cycle regulator has an adjustment range of 2ps-4ps for each step, and a total adjustment range of 28ps-56ps for 14 steps.

[0019] The present invention also relates to a delay phase-locked loop (DLL) circuit, which includes the duty cycle regulator as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to further illustrate various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It should be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope of protection claimed in the present invention.

[0021] In addition, it should be understood that the drawings illustrate the main connection relationships of the various components, rather than all connection relationships. Moreover, for the purpose of explaining the technical solutions of the present invention, the drawings show exemplary components. More or fewer components may be included in actual applications.

[0022] Figure 1 is a schematic diagram showing the duty cycle adjustment range and step adjustment;

[0023] Figure 2a-2b is a schematic diagram of an adjustment unit of a first duty cycle adjustment (DCA) module for increasing a signal duty cycle and a timing diagram thereof;

[0024] Figure 3a-3b is a schematic diagram of an adjustment unit of a second DCA module for reducing a signal duty cycle and its timing diagram;

[0025] Figure 4 This is a circuit diagram of a duty cycle regulator that can increase and decrease the duty cycle of a signal;

[0026] Figure 5a-5b is a schematic diagram of a delay-locked loop (DLL) circuit including a duty cycle regulator and a timing diagram of an output signal of the duty cycle regulator circuit; and

[0027] Figure 6 It is a schematic diagram of the correspondence between the mode register control bits and the steps used for duty cycle adjustment and the control signals received by each adjustment unit in the DDR5 application scenario of the present invention. DETAILED DESCRIPTION

[0028] The following detailed description refers to the accompanying drawings. The accompanying drawings illustrate, by way of example, specific embodiments in which the claimed subject matter may be practiced. It should be understood that the following specific embodiments are intended to provide specific descriptions of typical examples for illustrative purposes and should not be construed as limiting the present invention. Persons skilled in the art, provided they fully understand the spirit and purpose of the present invention, may make appropriate modifications and adjustments to the disclosed embodiments without departing from the spirit and scope of the claimed subject matter.

[0029] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of each described embodiment. However, it will be apparent to one of ordinary skill in the art that the various described embodiments can be practiced without these specific details. Unless otherwise defined, technical and scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0030] The terms "first", "second", etc. in the specification and claims of this application do not imply any order, quantity or importance, but are merely used to distinguish different components or features. An embodiment is an exemplary implementation or example. References in the specification to "an embodiment", "one embodiment", "some embodiments", "various embodiments" or "other embodiments" mean that the specific features, configurations or characteristics described in conjunction with the embodiment are included in at least some embodiments of the present technology, but not necessarily all embodiments. The various appearances of "an embodiment", "one embodiment", or "some embodiments" do not necessarily refer to the same embodiment. Elements or aspects from one embodiment may be combined with elements or aspects of another embodiment.

[0031] One embodiment of the present invention relates to a duty cycle regulator including a first DCA module. The first DCA module may include M parallel-connected regulation units. Each regulation unit may include a NAND gate and an NMOS transistor. Each regulation unit may be configured to: delay the input to the NAND gate from a low level to a high level so that the NMOS transistor is not turned on at the rising edge of the signal, thereby not changing the rising edge of the signal; and delay the input to the NAND gate from a high level to a low level so that the NMOS transistor is turned on at the falling edge of the signal, thereby delaying the falling edge of the signal and increasing the duty cycle of the signal.

[0032] Another embodiment of the present invention relates to a duty cycle regulator including a second DCA module. The second DCA module may include N parallel-connected regulation units. Each regulation unit may include a NAND gate and a PMOS transistor. Each regulation unit may be configured to: delay the input to the NAND gate from a low level to a high level so that the PMOS transistor is not turned on at the rising edge of the signal, thereby not changing the rising edge of the signal; and delay the input to the NAND gate from a high level to a low level so that the PMOS transistor is turned on at the falling edge of the signal, thereby bringing the falling edge of the signal forward and reducing the duty cycle of the signal.

[0033] Another embodiment of the present invention may be directed to a duty cycle regulator including the first DCA module and the second DCA module. The first DCA module and the second DCA module may be connected in parallel to achieve both increasing and decreasing the duty cycle, as described in more detail below.

[0034] Since the technical solution of the present invention adjusts the falling edge of the signal, in applications such as DDR5, the duty cycle adjustment will not change or affect the tDQSCK timing, thereby adjusting the duty cycle of the input signal without affecting the tDQSCK timing. In a more preferred embodiment, the duty cycle adjuster of the present invention can be set in a delay-locked loop (DLL) circuit, which not only makes the output duty cycle-adjusted signal have the same phase as the clock signal CLK, but also ensures that the duty cycle of the output signal is correct after adjustment, as described in more detail below.

[0035] The following description primarily focuses on DDR5. However, it should be understood that the present invention's duty cycle adjustment techniques are not limited to DDR5. The present invention's technical solutions can be used in any scenario requiring duty cycle adjustment. In particular, the present invention's techniques are particularly beneficial when it is desirable to adjust the falling edge while maintaining the rising edge unchanged.

[0036] For DDR5, the DDR5 duty cycle regulator can be applied to the bidirectional data control pin (DQS) clock tree according to Section 4.41 of the JEDEC (Solid State Electronics Association) FESD79-5A specification. Different mode register definitions can be used for single-phase and multi-phase DQS internal clocks. For example, mode register MR43 OP[3:0] can be used for single-phase DQS internal clock, while MR43 OP[7:0] or MR44 OP[3:0] can be used for multi-phase DQS internal clock. When applied to DDR5, the present invention is mainly aimed at duty cycle adjustment of single-phase DQS internal clock, where MR43 OP[2:0] can be used to specify the step of duty cycle adjustment, and OP[3] can be used to specify the positive or negative sign of the step. In general, circuit design needs to comply with JEDEC specification requirements.

[0037] DQS duty cycle adjustment can be located before the DQS clock tree or equivalent. Duty cycle adjustment requires a locked DLL state and will affect the DQS and DQ duty cycle in the following operations:

[0038] a) read;

[0039] b) Read the preamble training;

[0040] c) Read the training pattern;

[0041] d) Mode register read.

[0042] In a solution where the DQS clock tree uses a single-phase clock, the duty cycle of all DQS signals of each device can be adjusted directly based on the internal clock controlled by the duty cycle adjustment code. Note that tDQSCK should not be changed by the duty cycle adjustment code.

[0043] Global duty cycle adjustment uses the "Duty cycle adjustment for single-phase clock" mode register bit, MR43:OP[3:0]. Positive duty cycle adjustment results in a larger duty cycle, while negative duty cycle adjustment results in a smaller duty cycle.

[0044] Figure 1A schematic diagram showing the range and steps of duty cycle adjustment. As an example and not limitation, when the duty cycle regulator is applied to DDR5, the mode register MR43 can be used to specify 7 steps of positive and negative adjustment, i.e., -7 to +7. Therefore, a total of 14 steps can be included. For the DDR5 single-phase clock scheme, changing the falling edge of the pulse signal for duty cycle adjustment can keep tDQSCK unchanged. As described above, for a single-phase clock, MR43 OP[2:0] can be used to specify the step of duty cycle adjustment, and OP[3] can be used to specify the positive or negative sign of the step. In the present invention, the delay of each step can be about 2ps-4ps, so the total duty cycle adjustment range of 14 steps can be about 28ps-56ps.

[0045] Figure 2a-2b Schematic diagram of a regulating unit of the first DCA module for increasing the signal duty cycle and its timing diagram. Each regulating unit may include a NAND gate 202 and an NMOS transistor 206. Figure 2b The timing diagram of this embodiment shows that the main design concept of each adjustment unit is that: the timing delay of the input NAND gate 202 switching from a low level to a high level prevents the NMOS 206 from being turned on at the rising edge of the signal (i.e., the drive current of the NMOS 206 is invalid), so that the NMOS 206 does not change the rising edge of the signal; and the timing delay of the input NAND gate 202 switching from a high level to a low level causes the NMOS 206 to be turned on at the falling edge of the signal (i.e., the drive current of the NMOS 206 is valid), so that the NMOS 206 postpones the falling edge of the signal to increase the duty cycle of the signal. Since the high-level portion of the signal is widened at the falling edge without affecting the rising edge, the technical solution of the present invention can keep tDQSCK unchanged.

[0046] The first input of the NAND gate 202 of each regulating unit can be a high level or a low level. When the first input is a high level (for example, Figure 2a C_D shown in <0> = "H"), the high level can control the adjustment unit to be in an effective state, that is, to enable the adjustment unit. When the first input is a low level (for example, C_D <0> = "L"), the low level can control the regulating unit to be in an invalid state, that is, the regulating unit is not enabled. The second input line of the NAND gate 202 of each regulating unit can include a delay device 208, so that the second input of the NAND gate 202 of each regulating unit is a delayed input signal. For example, in combination with Figure 2b , the second input of the NAND gate 202 may be the delayed input signal IN_D.

[0047] In an embodiment of the present invention, as combined with Figure 2bAs shown in the timing diagram of FIG, the delay amount generated by the delay device 208 on the input signal IN can be set to at least make the entire rising edge of the signal whose duty cycle is to be adjusted (which can be, for example, the input signal IN, or if the inverter 210 is used, the input signal IN after passing through the inverter 210) fall within the low level region of the delayed signal IN_D (such as Figure 2b The shape “||” on the left is shown in the box), and accordingly, the entire falling edge of the signal whose duty cycle is to be adjusted falls at least in the high level region of the signal IN_D whose timing is delayed (for example, Figure 2b (as framed by the shape “||” on the right). Figure 2b Two delay devices 208 are shown, which can be buffers. However, this is only exemplary and not limiting. Based on the above delay setting requirements, other numbers and / or types of delay devices can be set.

[0048] The gate (G) of NMOS 206 can be coupled to the output of NAND gate 202. The drain (D) of NMOS 206 can be coupled to an input signal whose duty cycle is to be adjusted. The input signal whose duty cycle is to be adjusted can be, for example, the signal IN, or an IN signal (similar to OUT) having a certain phase delay after passing through the inverter 210. The inverter 210 can be added due to the operating characteristics of the NMOS. The source (S) of NMOS 206 can be coupled to ground. As described above, based on the operating characteristics of the NMOS, the input signal IN can pass through the inverter 210 before being input to the drain of the NMOS 206. In addition, when the inverter 210 is added, an inverter 212 can be added before the final output of the output signal OUT so that the input signal IN and the output signal OUT are in phase. It should be understood that the "coupling" used in this article can include direct connection or indirect connection.

[0049] In a further embodiment, based on the working characteristics of NMOS, in order to achieve the above control effect, Figure 2a The regulation unit may include an inverter 204 between the NAND gate 202 and the NMOS transistor 206. The signal output from the inverter 204 may be as follows: Figure 2b CD <0> As shown. Figure 2b As shown by the shape “||” on the left, during the rising edge of the input signal IN and the output signal OUT (as described above, due to the effect of the inverter, the phase of OUT can be delayed compared to IN), the signal CD input to the NMOS 206 <0> is at a low level, so NMOS 206 is not driven and has no effect on the signal OUT. Figure 2bAs shown by the shape “||” on the right, during the falling edge of the input signal IN and the output signal OUT, the signal CD input to the NMOS 206 <0> is at a high level, so the NMOS 206 is driven, and the NMOS 206 can affect the signal OUT. Due to the working characteristics of the NMOS, the NMOS 206 will slow down the falling edge, thereby delaying the falling edge and increasing the duty cycle.

[0050] The present invention can connect multiple Figure 2a The number of adjustment units shown can be set according to actual needs. The state of each adjustment unit can be independently controlled. During use, some, all, or none of the adjustment units can be enabled according to the actual duty cycle adjustment needs to achieve the desired duty cycle increase.

[0051] Figure 3a-3b Schematic diagram of a regulating unit of the second DCA module for reducing the signal duty cycle and its timing diagram. Each regulating unit may include a NAND gate 302 and a PMOS transistor 306. Figure 3b The timing diagram of this embodiment shows that the main design concept of each adjustment unit can be configured to: delay the input NAND gate 302 from a low level to a high level so that the PMOS 306 is not turned on at the rising edge of the signal (i.e., the drive current of the PMOS 306 is invalid), so that the PMOS 306 does not change the rising edge of the signal; and delay the input NAND gate 302 from a high level to a low level so that the PMOS 306 is turned on at the falling edge of the signal (i.e., the drive current of the PMOS 306 is valid), so that the PMOS 306 advances the falling edge of the signal to reduce the signal's duty cycle. Since the high-level portion of the signal is shortened at the falling edge, it has no effect on the rising edge. Therefore, the technical solution of the present invention can keep tDQSCK unchanged.

[0052] The first input of the NAND gate 302 of each adjustment unit can be a high level or a low level. When the first input is a high level (for example, Figure 3a C_D shown in <0> = "H"), the high level can control the adjustment unit to be in an effective state, that is, to enable the adjustment unit. When the first input is a low level (for example, C_D <0> = "L"), the low level can control the regulating unit to be in an invalid state, that is, the regulating unit is not enabled. The second input line of the NAND gate 302 of each regulating unit can include a delay device 308, so that the second input of the NAND gate 302 of each regulating unit is a delayed input signal. For example, in combination with Figure 3b , the second input of the NAND gate 302 may be the delayed input signal IN_D.

[0053] In an embodiment of the present invention, as combined with Figure 3b As shown in the timing diagram of FIG, the delay amount generated by the delay device 308 on the input signal IN can be set to at least make the entire rising edge of the signal whose duty cycle is to be adjusted (which can be, for example, the input signal IN, or if the inverter 310 is used, the input signal IN after passing through the inverter 310) fall within the low level region of the delayed signal IN_D (such as Figure 3b The shape “||” on the left is shown in the box), and accordingly, the entire falling edge of the signal whose duty cycle is to be adjusted falls at least in the high level region of the signal IN_D whose timing is delayed (for example, Figure 3b Since the output of the NAND gate 302 is directly coupled to the PMOS 306, the entire rising edge of the input signal IN or the phase-delayed input signal IN (similar to the phase of OUT) falls on the output CUb of the NAND gate 302. <0> The entire falling edge of the input signal IN or the phase-delayed input signal IN (similar to the phase of OUT) falls on the output CUb of the NAND gate 302 <0> low level area. Figure 3b Two delay devices 308 are shown, which can be buffers. However, this is only exemplary and not limiting. Based on the above delay amount setting requirements, other numbers and / or types of delay devices can be set.

[0054] The gate (G) of PMOS 306 can be coupled to the output of NAND gate 302. The drain (D) of PMOS 306 can be coupled to an input signal whose duty cycle is to be adjusted. The input signal whose duty cycle is to be adjusted can be, for example, signal IN, or an IN signal with a certain phase delay after passing through inverter 310 (similar to OUT). Inverter 310 can be added due to the operating characteristics of PMOS. The source (S) of PMOS 306 can be coupled to a power supply. As described above, based on the operating characteristics of PMOS, the input signal IN can pass through inverter 310 before being input to the drain of PMOS 306. In addition, when inverter 310 is added, inverter 312 can be added before the final output of output signal OUT so that the input signal IN and the output signal OUT are in phase. It should be understood that the "coupling" used in this article can include direct connection or indirect connection.

[0055] like Figure 3bAs shown by the shape “||” on the left, during the rising edge of the input signal IN and the output signal OUT (as described above, due to the effect of the inverter, the phase of OUT can be delayed compared to IN), the signal CUb input to the PMOS 306 <0> is at a high level, so PMOS 306 is not driven and PMOS 306 has no effect on signal OUT. Figure 3b As shown by the shape “||” on the right, during the falling edge of the input signal IN and the output signal OUT, the signal CUb input to the PMOS 306 <0> = is at a low level, so PMOS 306 is driven and can affect signal OUT. Due to the working characteristics of PMOS, PMOS 306 will accelerate the falling edge, thereby advancing the falling edge and reducing the duty cycle.

[0056] The present invention can connect multiple Figure 3a The number of adjustment units shown can be set according to actual needs. The state of each adjustment unit can be independently controlled. During use, according to the actual duty cycle adjustment needs, some, all, or none of the adjustment units can be enabled to achieve the desired duty cycle reduction.

[0057] Figure 4 This is a circuit diagram of a duty cycle regulator that can increase and decrease the duty cycle of a signal. Figure 4 The duty cycle regulator may include the first DCA module and the second DCA module. The first DCA module and the second DCA module may be connected in parallel. Furthermore, in a preferred embodiment, the number of regulation units in the first DCA module may be the same as the number of regulation units in the second DCA module. A mixer including PMOS and NMOS transistors enables the duty cycle regulator to shift the falling edge of a signal forward or backward to increase or decrease the duty cycle.

[0058] In the application of DDR5 single-phase DQS, the first DCA module may include 7 adjustment units, and the second DCA module may include 7 adjustment units. As described above, the duty cycle regulator can be configured to use the mode register MR43 OP[2:0] to specify the step of duty cycle adjustment, and use MR43 OP[3] to specify the positive or negative sign of the step. The step may include 14 steps from -7 to +7. The 14 steps are achieved by utilizing different state combinations of 14 adjustment units in parallel. The first DCA module can be configured to execute steps +1 to +7. The second DCA module can be configured to execute steps -1 to -7. As combined Figure 4As shown, steps +1 to +7 correspond to 1 to 7 of the 7 adjustment units in the first DCA module being valid, and steps -1 to -7 correspond to 1 to 7 of the 7 adjustment units in the second DCA module being valid, respectively.

[0059] The states of the 14 adjustment units can be controlled independently. Therefore, the amount of duty cycle increase / decrease (the amount of delay applied) can be increased / decreased by activating the corresponding number of adjustment units according to actual needs.

[0060] Figure 5a-5b 1 is a schematic diagram of a DLL circuit including a duty cycle regulator according to the present invention and a timing diagram of an output signal of the duty cycle regulator circuit. Figure 5a As shown, in addition to the above-mentioned duty cycle regulator 512, the DLL circuit may also include some other circuits, such as one or more of the following items: a phase detector 502, which can be used to detect whether the phase of the clock signal CLK is consistent with the phase of the DLL output signal (for example, DCA_OUT); a DLL control 504, which can be used to output a control signal to control the voltage adjustment (for example, U voltage is increased, D voltage is decreased) according to the comparison result of the phase detector; a charge pump 506, which can be used to output a voltage control signal (VCTRL) according to the control signal output by the DLL control; a voltage-controlled delay line (VCDL) 508, which can be used to perform voltage control according to the voltage control signal; a MIMIC circuit 510, which can be used to simulate the circuit components between CLK and DCA_OUT to simulate the influence of various factors on the input CLK clock signal in the DLL circuit, especially the influence of the duty cycle. The MIMIC circuit 510 can be coupled to the duty cycle regulator 512. The working principle of the duty cycle regulator 512 is as described above and will not be repeated here. Using the present invention as Figure 5a The circuit diagram shown in FIG. 1 not only makes the output DCA_OUT signal have the same phase as CLK, but also the duty cycle of the output DCA_OUT signal is correct after adjustment. In addition, since the present invention sets the duty cycle regulator in the loop of the DLL circuit, as shown in FIG. Figure 2a and 3a As shown, after the phase of the input signal IN is affected by passing through the inverter (e.g., one or more of 210, 212, 310, or 312), it can be realigned to the rising edge of the clock signal CLK in the DLL circuit after the DLL is locked, and only the falling edge is adjusted, as shown in FIG. Figure 5b As shown in the timing diagram, this avoids affecting the tDQSCK timing.

[0061] Figure 6This is a diagram showing the correspondence between the mode register control bit and the step adjustment and the control signal received by each adjustment unit in the DDR5 application scenario of the present invention. One of the inputs C_D of the NAND gate of each adjustment unit is <m>or C_U <n>(exist Figure 6 In the example of , m and n can both be "1" or "0." "1" can indicate a high potential, and "0" can indicate a low potential.

[0062] Step = 0 (+0 or -0 as indicated by the dashed box) means that none of the 14 regulation units are enabled, thereby applying no delay to the signal. Steps = +1 to +7 correspond to 1 to 7 NMOS regulation units being enabled, thereby increasing the duty cycle by a corresponding amount. Steps = -1 to -7 correspond to 1 to 7 PMOS regulation units being enabled, thereby decreasing the duty cycle by a corresponding amount.

[0063] As described herein, for ease of understanding, this specification is mainly described with reference to DDR5 as an example. However, the present invention is not limited to application in DDR5, but can be used in any use scenario where duty cycle adjustment is required. In particular, the technology of the present application is more beneficial for situations where the falling edge needs to be adjusted while the rising edge remains unchanged. In other application scenarios, the corresponding parameters may change. For example, the duty cycle adjustment step may be a number of steps other than the 14 adjustment steps from -7 to +7. Other parameters may also change and are not limited to the specific forms described in this article, and are not listed here one by one.

[0064] The basic concepts of the present invention have been described above. It will be apparent to those skilled in the art that the above disclosure is merely illustrative and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are suggested in the present application, and such modifications, improvements, and amendments remain within the spirit and scope of the embodiments of the present application.< / n> < / m>

Claims

1. A duty cycle regulator, comprising: a first duty cycle adjustment module, the first duty cycle adjustment module comprising M adjustment units connected in parallel, each adjustment unit comprising a NAND gate and an NMOS transistor, each adjustment unit being configured to: delay the timing of the input to the NAND gate from a low level to a high level so that the NMOS is not turned on at the rising edge of the signal, thereby the NMOS does not change the rising edge of the signal; and delay the timing of the input to the NAND gate from a high level to a low level so that the NMOS is turned on at the falling edge of the signal, thereby the NMOS postpones the falling edge of the signal to increase the duty cycle of the signal, and / or A second duty cycle adjustment module includes N parallel adjustment units, each adjustment unit includes a NAND gate and a PMOS transistor, and each adjustment unit is configured to: a timing delay from a low level to a high level input to the NAND gate causes the PMOS to not be turned on at the rising edge of the signal, so that the PMOS does not change the rising edge of the signal; and a timing delay from a high level to a low level input to the NAND gate causes the PMOS to be turned on at the falling edge of the signal, so that the PMOS advances the falling edge of the signal to reduce the duty cycle of the signal.

2. The duty cycle regulator according to claim 1, wherein: The gate of the NMOS is coupled to the output of the NAND gate, the drain of the NMOS is coupled to an input signal whose duty cycle is to be adjusted, and the source of the NMOS is coupled to ground; and / or A gate of the PMOS is coupled to the output of the NAND gate, a drain of the PMOS is coupled to an input signal whose duty cycle is to be adjusted, and a source of the PMOS is coupled to a power supply.

3. The duty cycle regulator according to claim 2, wherein: In the first duty cycle adjustment module, an inverter is included between the NAND gate and the NMOS.

4. The duty cycle regulator according to claim 2, wherein: The input signal passes through an inverter before being input to the drain of the NMOS or the PMOS, and the duty cycle regulator includes an inverter before the final output signal.

5. The duty cycle regulator according to claim 2, wherein: The first input of the NAND gate of each regulating unit is a high level or a low level. When the first input is a high level, the high level controls the regulating unit to be in an effective state. When the first input is a low level, the low level controls the regulating unit to be in an ineffective state. The second input line of the NAND gate of each regulating unit includes a delay device, so that the second input of the NAND gate of each regulating unit is a delayed input signal, and wherein The state of each regulating unit can be controlled independently.

6. The duty cycle regulator according to claim 5, wherein: The delay amount generated by the delay device on the input signal is set to: at least make the entire rising edge of the signal whose duty cycle is to be adjusted fall within the low level area of the delayed input signal, and correspondingly, make the entire falling edge of the signal whose duty cycle is to be adjusted fall within the high level area of the delayed input signal.

7. The duty cycle regulator according to claim 1, wherein: The duty cycle regulator is arranged in a delay phase locked loop (DLL) circuit, and the change of the falling edge is performed during the DLL locking period.

8. The duty cycle regulator according to claim 7, wherein: The duty cycle regulator is arranged after the MIMIC circuit in the DLL circuit.

9. The duty cycle regulator according to claim 1, wherein: When the duty cycle regulator includes both the first duty cycle adjustment module and the second duty cycle adjustment module, the first duty cycle adjustment module and the second duty cycle adjustment module are connected in parallel.

10. The duty cycle regulator according to claim 9, wherein: M equals N.

11. The duty cycle regulator according to any one of claims 1 to 10, characterized in that: The duty cycle regulator includes a duty cycle regulator for the internal clock of the DDR5 single-phase bidirectional data control pin DQS.

12. The duty cycle regulator according to claim 11, wherein: Each duty cycle regulator includes the first duty cycle regulating module and the second duty cycle regulating module connected in parallel, wherein the first duty cycle regulating module includes 7 regulating units, and the second duty cycle regulating module includes 7 regulating units; The duty cycle regulator is configured to use the mode register MR43 OP[2:0] to specify the step of duty cycle regulation and use MR43 OP[3] to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7.

13. The duty cycle regulator according to claim 12, wherein: The 14 steps are realized by utilizing different state combinations of 14 regulating units connected in parallel.

14. The duty cycle regulator according to claim 13, wherein: The first duty cycle adjustment module is configured to perform step adjustments of +1 to +7, the second duty cycle adjustment module is configured to perform step adjustments of -1 to -7, and wherein Steps +1 to +7 correspond to 1 to 7 of the 7 adjustment units in the first duty cycle adjustment module being valid, and steps -1 to -7 correspond to 1 to 7 of the 7 adjustment units in the second duty cycle adjustment module being valid.

15. The duty cycle regulator according to claim 12, wherein: The adjustment range of each step is 2ps-4ps, and the total adjustment range of 14 steps is 28ps-56ps.

16. A delay phase-locked loop (DLL) circuit, comprising the duty cycle regulator according to any one of claims 1 to 15.

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