Erasure tail comparator scheme

Abstract

A method of performing an erase operation on a non-volatile storage device is disclosed. The method includes applying a first erase pulse to a first set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation, determining an upper tail of a threshold voltage distribution of the first set of non-volatile storage elements after applying the first erase pulse, determining a difference between the upper tail of the first set of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second set of non-volatile storage elements, and disabling the erase operation on the first set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles if the difference is greater than or equal to a threshold amount.

Description

TECHNICAL FIELD

[0001] This application relates to non-volatile memory devices and operations of non-volatile memory devices. BACKGROUND

[0002] This section provides background information related to the technical field of the disclosure and as such is not necessarily prior art.

[0003] Semiconductor memory devices have become more prevalent in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0004] Charge storage materials, such as floating gates, or charge trapping materials can be used in such memory devices to store charge representative of a data state. Charge trapping materials can be arranged vertically in three-dimensional (3D) stacked memory structures, or arranged horizontally in two-dimensional (2D) memory structures. One example of a 3D memory structure is a bit cost scalable (BiCS) architecture that includes a stack of alternating conductive layers and dielectric layers. SUMMARY

[0005] This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features and advantages.

[0006] It is an object of the present disclosure to provide memory devices and methods of operating the memory devices that address and overcome the disadvantages described herein.

[0007] Accordingly, one aspect of the present disclosure is to provide a method of performing an erase operation on a non-volatile storage device. The method includes applying a first erase pulse to a first group of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation; determining an upper tail of a threshold voltage distribution of the first group of non-volatile storage elements after applying the first erase pulse; determining a difference between the upper tail of the first group of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second group of non-volatile storage elements; and disabling the erase operation on the first group of non-volatile storage elements in a second erase cycle of the plurality of erase cycles if the difference is greater than or equal to a threshold amount.

[0008] Further, one aspect of the present disclosure is to provide a non-volatile storage device. The non-volatile storage device includes a set of non-volatile storage elements; and one or more managing circuits in communication with the set of non-volatile storage elements. The one or more managing circuits are configured to: apply a first erase pulse to a first set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of an erase operation; determine an upper tail of a threshold voltage distribution of the first set of non-volatile storage elements after applying the first erase pulse; determine a difference between the upper tail of the first set of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second set of non-volatile storage elements; and disable the erase operation on the first set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles if the difference is greater than or equal to a threshold amount.

[0009] However, one aspect of the present disclosure is to provide a controller in communication with a set of memory cells of a memory device. The controller is configured to: apply a first erase pulse to a first set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of an erase operation; determine an upper tail of a threshold voltage distribution of the first set of non-volatile storage elements after applying the first erase pulse; determine a difference between the upper tail of the first set of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second set of non-volatile storage elements; and disable the erase operation on the first set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles if the difference is greater than or equal to a threshold amount.

[0010] Additional areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0011] With reference now to the drawing, and in particular to FIG. 1 thereof, a diagrammatic representation of an example machine in the form of a computer system 100 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed is depicted.

[0012] FIG. 1A is a block diagram of an example memory device;

[0013] FIG. 1B is a block diagram of an example control circuit including a program circuit, a count circuit, and a determination circuit;

[0014] FIG. 2 depicts a block of memory cells in an example two-dimensional configuration of a memory array of FIG. 1A

[0015] FIG. 3A depicts a cross-sectional view of an example floating gate memory cell in a NAND string;

[0016] FIG. 3B depicts a block of memory cells in an example two-dimensional configuration of a memory array of FIG. 3A ​A sectional view of the structure;

[0017] FIG. 4A A cross-sectional view of an exemplary charge-trapping memory cell in a NAND string is depicted;

[0018] FIG. 4B It depicts the section taken along line 429. FIG. 4A A sectional view of the structure;

[0019] FIG. 5A Depicting FIG. 1A An exemplary block diagram of the sensing block SB1;

[0020] FIG. 5B Depicting FIG. 1A Another exemplary block diagram of the sensing block SB1;

[0021] FIG. 6A yes FIG. 1A A perspective view of a set of blocks in an exemplary three-dimensional configuration of a memory array;

[0022] FIG. 6B Depicting FIG. 6A An exemplary cross-sectional view of a portion of a block;

[0023] FIG. 6C Depicting FIG. 6B A diagram showing the diameter of memory holes in a stack;

[0024] FIG. 6D Depicting FIG. 6B A close-up view of the stacked area 622;

[0025] FIG. 7A Depicting FIG. 6B A top view of an exemplary stacked word line layer WLL0;

[0026] FIG. 7B Depicting FIG. 6B A top view of an exemplary top dielectric layer DL19 of the stack;

[0027] FIG. 8A Depicting FIG. 7A An example NAND string in sub-blocks SBa to SBd;

[0028] FIG. 8B Another exemplary view depicting the NAND string in the sub-block;

[0029] FIG. 8C A top view depicting an exemplary stacked layer of letter lines;

[0030] FIG. 9 The distribution of Vth of memory cells is depicted in an exemplary one-pass programming operation with four data states;

[0031] FIG. 10 The distribution of Vth of memory cells is depicted in an exemplary one-pass programming operation with eight data states;

[0032] FIG. 11 The distribution of Vth of memory cells is depicted in an exemplary one-pass programming operation with sixteen data states;

[0033] FIG. 12 A method for an erase tail comparator scheme according to the embodiment described herein is described;

[0034] FIG. 13 The above provides a reference for implementation. FIG. 12 An exemplary illustration of the erase threshold distribution after the erase tail comparator scheme described above;

[0035] FIG. 14 Another method for implementing the erase tail-line region comparator scheme according to the implementation scheme described herein is described; and

[0036] FIG. 15 Another method for implementing the tail plane comparator scheme according to the implementation scheme described herein is described. Detailed Implementation

[0037] In the following description, details are set forth to provide an understanding of this disclosure. In some instances, certain circuits, structures, and techniques have not been described or shown in detail so as not to obscure this disclosure.

[0038] Generally, this disclosure relates to a type of nonvolatile memory device that is well-suited to many applications. The nonvolatile memory device and associated methods of its formation will be described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are merely intended to clearly describe the concepts, features, advantages, and objects of the invention, allowing those skilled in the art to understand and practice this disclosure. Specifically, exemplary embodiments are provided so that this disclosure will be comprehensive and will fully convey the scope to those skilled in the art. Numerous specific details, such as examples of specific components, apparatus, and methods, are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that specific details are not required, exemplary embodiments may be embodied in many different forms, and none should be construed as limiting the scope of this disclosure. In some exemplary embodiments, well-known processes, well-known apparatus structures, and well-known techniques are not described in detail.

[0039] Various terminology is used to refer to particular system components. Different companies may refer to components by different names — this document does not intend to distinguish between names of different companies. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" or "couples" is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection can be through a direct connection, or through an indirect connection via other devices and connections.

[0040] Additionally, when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the substrate's surface, or intervening layers can also be present. Furthermore, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under, and can also be present in intervening layers. Also, it should be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0041] A programming operation of a set of memory cells of a memory device typically involves applying a series of program voltages to the memory cells after providing the memory cells in an erased state. Each program voltage is provided in a program cycle (also referred to as a program-verify iteration). For example, a program voltage can be applied to a word line that is connected to a control gate of a memory cell. In one approach, an incremental step pulse programming is performed in which the program voltage is increased by a step size in each program cycle. A verify operation can be performed after each program voltage to determine whether the memory cell has completed programming. When programming of a memory cell is completed, the memory cell can be locked from further programming while programming of other memory cells continues in subsequent program cycles.

[0042] Each memory cell can be associated with a data state in accordance with write data in a program command. Based on the data state of the memory cell, the memory cell will remain in an erased state or be programmed to a data state different from the erased state (a programmed data state). For example, in a one bit-per-cell memory device (single level cell (SLC)), there are two data states, including an erased state and one higher data state. In a two bit-per-cell memory device (multi-level cell (MLC)), there are four data states, including an erased state and three higher data states, referred to as A, B, and C data states (see FIG. 9 ). In a three bit-per-cell memory device (triple level cell (TLC)), there are eight data states, including an erased state and seven higher data states, referred to as A, B, C, D, E, F, and G data states (see FIG. 10). In a four-bit-per-cell memory device (quad-level cell (QLC)), there are sixteen data states, including an erase state and fifteen higher data states, referred to as Er, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F data states (see FIG. 11 Each memory cell can store a data state (e.g., a binary value) and is programmed to a threshold voltage state corresponding to the data state. Each state represents a different value and is assigned a voltage window including a range of possible threshold voltages.

[0043] When a program command is issued, the write data is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state to which the cell will be programmed. Each program data state is associated with a verify voltage such that a memory cell having a given data state is considered to have completed programming when a sense operation determines that its threshold voltage (Vth) is above the associated verify voltage. The sense operation can determine whether a memory cell has a Vth above the associated verify voltage by applying the associated verify voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state such that Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state such that Vth is higher than the control gate voltage.

[0044] The verify voltage used to determine that a memory cell has completed programming can be referred to as a final verify voltage or a lockout verify voltage. In some cases, an additional verify voltage can be used to determine that a memory cell is near completion of programming. This additional verify voltage can be referred to as an offset verify voltage and can be lower than the final verify voltage. When a memory cell is near completion of programming, the programming speed of the memory cell can be reduced, such as by raising the voltage of the corresponding bit line during one or more subsequent program voltages. For example, in FIG. 9 , a memory cell to be programmed to the A data state can be subjected to a verify test at VvAL (an offset verify voltage for the A data state) and VvA (a final verify voltage for the A data state).

[0045] Erasing can be performed across a memory array, individual blocks, or another unit of cells. In one implementation, a group of memory cells is erased by raising the p-well of the memory cells to an erase voltage for a sufficient period of time. The erase pulse moves the threshold voltage of the memory cells toward (or beyond) an erase target level, which can be lower than 0 volts. In some implementations, after the erase pulse is applied, an erase verify operation is performed to determine whether the threshold voltage of the memory cells has at least reached the erase target level. The erase pulse and erase verify are repeated with each cycle using a higher amplitude erase pulse until the erase verify passes.

[0046] The erase operation can be completed in multiple cycles (e.g., two cycles). For example, an erase voltage (VERA) can be used for a first cycle, and the erase voltage can be increased by a boost voltage (dVERA) and used for a second cycle. The number of cycles implemented in the erase operation can be limited by the time of the erase operation (tERASE). If the number of cycles used in the erase operation is increased, the time to perform the erase operation will increase. The double pulse erase operation can meet the time of the erase operation tERASE. However, over time, particularly at the end of the life of the product, it can become more difficult to erase some memory devices. In some cases, three cycles can be needed if the second pulse does not pass erase verification.

[0047] Defects (e.g., such as a word line to memory hole short, a word line to dummy word line short, etc.) can cause a single word line or a few word lines to “erase slower”. The slower erasing word lines can cause uncorrectable error correction code (UECC) failures (due to high Er->A), which can cause user data corruption. This has become one of the major issues for parts per million defective (DPPM).

[0048] Conventionally, two device modes have been used to offset the slower erase issues described above. These device modes include an erase cycle comparator and a tail detect read (TDR). The erase cycle comparator mode looks for cycle differences between two adjacent planes. The erase cycle comparator mode is quantized to two or three cycles. For example, in some cases, a defective block can pass an erase operation in two or three cycles. If the failure criteria is set to one cycle, this can cause false triggers and overkill good blocks that are not defective. If the failure criteria is relaxed to two cycles, it can be too loose to catch defective blocks. In addition, the single word line slower erase issue can not be reflected on the erase cycles. Thus, the erase cycle comparator is not an effective method to capture the slower erase word line issue.

[0049] The TDR mode can be used to detect shallower erase issues. The TDR mode involves using an AR read data word line prior to PGM to detect shallower erase tails. The TDR is done in a single word line read fashion, which results in a large tPROG impact. Thus, the TDR mode for data word line erase tail detection is not typically implemented.

[0050] To address the above concerns, the embodiments described herein are directed to an erase tail wordline zone comparator mode. The erase tail wordline zone comparator mode is implemented to catch slower erase wordline issues, thus preventing user data corruption. For example, the erase tail wordline zone comparator mode includes dividing the wordlines into different wordline zones; performing an erase verify voltage (VCG ERV) scan to detect erase tails after a first erase pulse; and comparing the erase tails across different wordline zones to detect slower erase wordline issues. If the erase tail difference between different wordline zones exceeds a failure criterion, the mode will terminate the erase operation on the block and mark it as defective.

[0051] To further address the above concerns, the embodiments described herein are directed to an erase tail plane comparator mode. The erase tail plane comparator mode is proposed as a more efficient method to detect slower erase planes. The mode involves comparing the erase upper tail of a plane after a first erase pulse with the erase upper tail of different planes to detect slower erase planes; and terminating the erase operation on the slower plane after the first erase pulse while other planes continue normal erase.

[0052] To help further illustrate the foregoing, there will now be described FIG. 1A . FIG. 1A is a block diagram of an example memory device. The memory device 100 can include one or more memory dies 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuitry 128 includes a plurality of sense blocks SB1, SB2,..., SBp (sense circuitry) and allows a page of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0053] As described with reference to FIG. 1A the controller 122 is included in the same memory device 100 as the one or more memory dies 108. For example, in some embodiments, the memory device can include NAND flash dies that are located in columns adjacent to each other; however, in some embodiments, the memory device can include NAND flash dies that are stacked on top of each other. Further, in some embodiments, the memory device can include stacked NAND flash dies and a controller as a separate die within the package.

[0054] The memory structure can be a 2D memory structure or a 3D memory structure. The memory structure can include one or more arrays of memory cells including a 3D array. The memory structure can include a monolithic three-dimensional memory structure in which a plurality of memory levels are formed above (rather than in) a single substrate such as a wafer, without intervening substrates. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active regions disposed above a silicon substrate. The memory structure can be in a non-volatile memory device having circuitry associated with the operation of the memory cells whether the associated circuitry is above the substrate or within the substrate.

[0055] The control circuitry 110 cooperates with the read / write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip level control of memory operations. A storage region 113 can be provided, for example, for storing parameters described herein.

[0056] The on-chip address decoder 114 provides an address interface between an address interface used by a host or memory controller and the hardware addresses used by the decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. This power control module can include drivers for the word lines, SGS and SGD transistors, and source lines. In one approach, a sense block can include a bit line driver. The SGS transistors are select gate transistors at the source end of a NAND string, and the SGD transistors are select gate transistors at the drain end of a NAND string.

[0057] In some implementations, some of the components can be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) can be considered at least one control circuit configured to perform the actions described herein. For example, the control circuit can include any one or a combination of the control circuit 110, the state machine 112, the decoders 114 / 132, the power control module 116, the sense block SBb, the sense block SB2,... SBp, the read / write circuits 128, the controller 122, etc.

[0058] The control circuit can include a program circuit configured to program memory cells of a word line of a block and verify the set of memory cells. The control circuit can also include a count circuit configured to determine a number of memory cells verified to be in a data state. The control circuit can also include a determination circuit configured to determine whether the block has a failure based on the number.

[0059] For example, FIG. 1B is a block diagram of an exemplary control circuit 150 including a programming circuit 151, a counting circuit 152, and a determination circuit 153. The programming circuit can include software, firmware, and / or hardware. The counting circuit can include software, firmware, and / or hardware. The determination circuit can include software, firmware, and / or hardware.

[0060] The off-chip controller 122 can include a processor 122c, storage devices (memory) such as a ROM 122a and a RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct a number of read errors caused when the upper tail of the Vth distribution becomes too high. However, in some cases there can be uncorrectable errors. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0061] The storage devices include code, such as a set of instructions, and the processor can operate to execute the set of instructions to provide the functionality described herein. Alternatively, or in addition, the processor can access code from the storage devices 126a of the memory structure, such as a reserved area of memory cells in one or more word lines.

[0062] For example, the controller 122 can use code to access the memory structure, such as for program, read, and erase operations. The code can include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller during a boot or startup process and enables the controller to access the memory structure. The controller can use the code to control one or more memory structures. Upon power up, the processor 122c fetches the boot code from the ROM 122a or the storage devices 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0063] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smartphone, a tablet, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drives, solid state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host can also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices in communication with the one or more processors.

[0064] Other types of non-volatile memory can be used in addition to NAND flash memory.

[0065] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), and other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, a flash memory device can be configured in a NAND or a NOR configuration.

[0066] The memory devices can be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as resistive-switching or phase-change materials, and optional steering elements, such as diodes or transistors. Further, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements that include charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0067] Multiple memory elements can be configured so that they are connected in series or so that each element can be individually accessed. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of series-connected transistors that includes memory cells and SG transistors.

[0068] A NAND memory array can be configured so that the array is composed of multiple strings of memory, where a string is composed of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured so that each element can be individually accessed, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0069] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional memory structures or three-dimensional memory structures.

[0070] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an x-y directional plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate can be a wafer on or in which layers of the memory elements are formed, or it can be a carrier substrate that is attached to the memory elements after they are formed. As non-limiting examples, the substrate can comprise a semiconductor, such as silicon.

[0071] The memory elements can be arranged in a single memory device level in an ordered array, such as in a plurality of rows and / or columns. However, the memory elements can be arranged in irregular or non-orthogonal configurations. The memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0072] A three-dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, forming a three-dimensional structure (i.e., x, y, and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to a major surface of the substrate).

[0073] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to a major surface of the substrate, i.e., along the y direction), each column having a plurality of memory elements. The columns can be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0074] By way of non-limiting example, in a three-dimensional NAND memory array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., x-y) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, in which some NAND strings contain memory elements in a single memory level, while other strings contain memory elements across multiple memory levels. Three-dimensional memory arrays can also be designed in NOR configurations, as well as ReRAM configurations.

[0075] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the underlying memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or may have intervening layers between memory device classes.

[0076] Two-dimensional arrays can then be formed individually and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0077] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0078] Those skilled in the art will recognize that this technology is not limited to the two-dimensional and three-dimensional exemplary structures described herein, but covers all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0079] FIG. 2 Depicting FIG. 1AFigure 2 illustrates a block of memory cells in an exemplary two-dimensional configuration of a memory array 126. A memory array can include many blocks. Each exemplary block 200, 210 includes a plurality of NAND strings and corresponding bit lines, e.g., BL0, BL1... shared among blocks. Each NAND string is connected at one end to a drain select gate (SGD) and a control gate of that drain select gate is connected via a common SGD line. The NAND string is connected at its other end to a source select gate, which in turn is connected to a common source line 220. Sixteen word lines, e.g., WL0 to WL15, extend between the source select gates and the drain select gates. In some cases, dummy word lines that do not contain user data can also be used in a memory array adjacent to the select gate transistors. Such dummy word lines can shield edge data word lines from certain edge effects.

[0080] One type of non-volatile storage that can be provided in a memory array is floating gate storage. See FIG. 3A and FIG. 3B Other types of non-volatile storage can also be used. For example, charge trap memory cells use a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. See FIG. 4A and FIG. 4B A three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductive substrate over the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a finite region. The stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A split gate configuration can provide a similar cell, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0081] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, with an ONO dielectric layer extending over a channel between a source and a drain diffusion. Charges for one data bit are located in the dielectric layer adjacent to the drain, and charges for the other data bit are located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by reading the binary states of spatially separate charge storage regions within the dielectric. Other types of non-volatile storage are also known.

[0082] FIG. 3AA cross-sectional view of an exemplary floating gate memory cell in a NAND string is depicted. Bit lines or NAND string direction goes into the page, and word line direction is from left to right. For example, word line 324 extends across NAND strings including respective channel regions 306, 316, and 326. Memory cell 300 includes control gate 302, floating gate 304, tunnel oxide layer 305, and channel region 306. Memory cell 310 includes control gate 312, floating gate 314, tunnel oxide layer 315, and channel region 316. Memory cell 320 includes control gate 322, floating gate 321, tunnel oxide layer 325, and channel region 326. Each memory cell is in a different respective NAND string. Also depicted is a polysilicon interpoly dielectric (IPD) layer 328. The control gates are part of the word lines. FIG. 3B A cross-sectional view taken along line 329 is provided.

[0083] The control gate wraps around the floating gate, increasing the surface contact area between the control gate and the floating gate. This results in higher IPD capacitance, resulting in higher coupling ratios, which makes programming and erasing easier. However, as NAND memory devices are scaled down, the spacing between adjacent cells becomes smaller, so there is little room for the control gate and IPD between two adjacent floating gates. As an alternative, as shown in FIG. 4A and FIG. 4B flat or planar memory cells have been developed in which the control gate is flat or planar; that is, the control gate does not wrap around the floating gate, and the only contact of the control gate to the charge storage layer is from above. In this case, there is no advantage to having a high floating gate. Instead, the floating gate is made thinner. In addition, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the ballistic electron transport problem, in which electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0084] FIG. 3B A cross-sectional view of the structure of FIG. 3A taken along line 329 is depicted. NAND string 330 includes SGS transistor 331, exemplary memory cells 300, 333...334, and 335, and SGD transistor 336. As an example of each memory cell, memory cell 300 includes control gate 302, IPD layer 328, floating gate 304, and tunnel oxide layer 305, consistent with FIG. 3A The pass through in the IPD layer in the SGS and SGD transistors allows the control gate layer and the floating gate layer to communicate. For example, the control gate layer and the floating gate layer can be polysilicon, and the tunnel oxide layer can be silicon oxide. The IPD layer can be a stack of nitride (N) and oxide (O), such as in an N-O-N-O-N configuration.

[0085] NAND strings can be formed on a substrate including a p-type substrate region 355, an n-type well 356, and a p-type well 357. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type wells. A channel voltage Vch can be directly applied to the channel region of the substrate.

[0086] FIG. 4A A cross-sectional view of an exemplary charge-trapping memory cell in a NAND string is depicted. This view is taken in the word-line direction of the memory cell, which includes a planar control gate and a charge-trapping region, as... FIG. 1A A 2D example of a memory cell in the memory cell array 126. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator such as a SiN film to store electrons, compared to floating-gate MOSFET technology which uses conductors such as doped polysilicon to store electrons. For example, a word line (WL) 424 extends across a NAND string, which includes corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. An IPD layer 428, charge-trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunnel layers 409, 407, and 408 are located below the word line. Each charge-trapping layer extends continuously within the corresponding NAND string.

[0087] Memory cell 400 includes a control gate 402, a charge trapping layer 404, a polysilicon layer 405, and a portion of a channel region 406. Memory cell 410 includes a control gate 412, a charge trapping layer 414, a polysilicon layer 415, and a portion of a channel region 416. Memory cell 420 includes a control gate 422, a charge trapping layer 421, a polysilicon layer 425, and a portion of a channel region 426.

[0088] A planar control gate is used here, instead of a control gate wrapped around a floating gate. One advantage is that the charge trapping layer can be made thinner than the floating gate. Additionally, memory cells can be placed closer together.

[0089] FIG. 4B It depicts the section taken along line 429. FIG. 4A A cross-sectional view of the structure. This view shows a NAND string 430 with a planar control gate and a charge trapping layer. The NAND string 430 includes an SGS transistor 431, exemplary memory cells 400, 433…434 and 435, and an SGD transistor 435.

[0090] A NAND string can be formed on a substrate that includes a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well 457. A channel voltage Vch can be applied directly to a channel region of the substrate. The memory cell 400 includes a control gate 402 and an IPD layer 428 over a charge trapping layer 404, a polysilicon layer 405, a tunnel layer 409, and a channel region 406.

[0091] For example, the control gate layer can be polysilicon, and the tunnel layer can be silicon oxide. The IPD layer can be a stack of high-k dielectrics such as AlOx or HfOx that help increase the coupling ratio between the control gate layer and the charge trapping or charge storage layer. The charge trapping layer can be, for example, a mixture of silicon nitride and silicon oxide.

[0092] The SGD and SGS transistors have the same configuration as the memory cells but have a longer channel length to ensure that the current is turned off in the NAND string that is inhibited.

[0093] In this example, the layers 404, 405, and 409 extend continuously in the NAND string. In another approach, portions of the layers 404, 405, and 409 between the control gates 402, 412, and 422 can be removed, thereby exposing a top surface of the channel 406.

[0094] FIG. 5A An example block diagram of a sense block SB1 of FIG. 1A is depicted. In one approach, the sense block includes a plurality of sense circuits. Each sense circuit is associated with a data latch. For example, example sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different respective sense blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sense circuits to be divided and processed by respective processors in each sense block. For example, a sense circuit controller 560 in SB1 can communicate with the set of sense circuits and latches. The sense circuit controller can include a pre-charge circuit 561 that provides a voltage to each sense circuit for setting a pre-charge voltage. In one possible approach, the voltage is provided to each sense circuit independently, e.g., via a database 503 and a local bus such as FIG. 5B LBUS1 or LBUS2 in FIG. 5B In another possible approach, a common voltage is provided to each sense circuit simultaneously, e.g., via a line 505 in FIG. 2The memory 562 can store code executable by the processor to perform the functions described herein. These functions can include reading latches associated with the sense circuit, setting bit values in the latches, and providing a voltage for setting a pre-charge level in a sense node of the sense circuit. More example details of the sense circuit controller and the sense circuits 550a and 551a are provided below.

[0095] FIG. 5B Another example block diagram of a sense block SB1 is depicted. FIG. 1A The sense circuit controller 560 is in communication with a plurality of sense circuits including example sense circuits 550a and 551a also shown in FIG. 5A The sense circuit 550a includes a latch 550b including a trip latch 526, an offset verify latch 527, and a data state latch 528. The sense circuit also includes a voltage clamp structure 521, such as a transistor, that sets a pre-charge voltage at a sense node 522. A sense node to bit line (BL) switch 523 selectively allows the sense node to communicate with a bit line 525, e.g., the sense node is electrically connected to the bit line so that the sense node voltage can decay. The bit line 525 is connected to one or more memory cells, such as memory cell MC1. A voltage clamp structure 524 can set a voltage on the bit line, such as during a sense operation or during a program voltage. A local bus LBUS1 allows the sense circuit controller to communicate with components in the sense circuit, such as the latch 550b and the voltage clamp structure in some cases. To communicate with the sense circuit 550a, the sense circuit controller provides a voltage to the transistor 504 via line 502 to connect the LBUS1 with the data bus DBUS 503. The communication can include sending data to and / or receiving data from the sense circuit.

[0096] For example, the sense circuit controller can communicate with different sense circuits in a time-multiplexed manner, for example. In one approach, the line 505 can be connected to the voltage clamp structure in each sense circuit.

[0097] Sensing circuit 551a includes latches 551b, including a trip latch 546, an offset verification latch 547, and a data status latch 548. A voltage clamping structure 541 is used to set a pre-charge voltage at sensing node 542. A sensing node-to-bit line (BL) switch 543 selectively allows the sensing node to communicate with bit line 545, and a voltage clamping structure 544 can set a voltage on the bit line. Bit line 545 is connected to one or more memory cells, such as memory cell MC2. Local bus LBUS2 allows the sensing circuit controller to communicate with components in the sensing circuit, such as latches 551b and the voltage clamping structure in some cases. To communicate with sensing circuit 551a, the sensing circuit controller provides voltage to transistor 506 via line 501 to connect LBUS2 to DBUS.

[0098] The sensing circuit 550a may be a first sensing circuit including a first trip latch 526, and the sensing circuit 551a may be a second sensing circuit including a second trip latch 546.

[0099] Sensing circuit 550a is an example of a first sensing circuit including a first sensing node 522, wherein the first sensing circuit is associated with a first memory cell MC1 and a first bit line 525. Sensing circuit 551a is an example of a second sensing circuit including a second sensing node 542, wherein the second sensing circuit is associated with a second memory cell MC2 and a second bit line 545.

[0100] FIG. 6A yes FIG. 1A This is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of a memory array 126. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements), and a peripheral region 604 having circuitry for use by the blocks. For example, the circuitry may include a voltage driver 605 connectable to a control gate layer of the block. In one approach, control gate layers at a common height within the blocks are commonly driven. The substrate 601 may also carry circuitry beneath the blocks, along with one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. These blocks are formed in a middle region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals from the circuitry. Each block includes a stacked region of memory cells, where alternating stacked layers represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upwards to the upper metal layers to form connections with conductive paths. Although four blocks are depicted as an example, two or more blocks extending in the x and / or y directions can be used.

[0101] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0102] FIG. 6B Depicting FIG. 6A An exemplary cross-sectional view of a portion of a block. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0 to WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. Furthermore, regions comprising NAND strings NS1 and NS2 are depicted in the stack. Each NAND string encompasses a memory via 618 or 619, which is filled with material forming memory cells adjacent to the word lines. FIG. 6D The stacked region 622 is shown in more detail below.

[0103] The stack includes a substrate 611, an insulating film 612 on the substrate, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack. Metal-filled slots 617 and 620 may be provided periodically across the stack as interconnects extending through the stack, such as to connect the source line to a line above the stack. The slots may be used during word line formation and subsequently filled with metal. A portion of a bit line BL0 is also depicted. A conductive via 621 connects the drain terminal 615 to BL0.

[0104] FIG. 6C Depicting FIG. 6B A diagram showing the diameter of memory holes in a stack. The vertical axis is perpendicular to... FIG. 6B The stacking alignment is shown, and the widths (wMH), such as diameters, of memory holes 618 and 619 are depicted. FIG. 6A Word line layers WLL0 to WLL10 are repeated as examples, and are located at corresponding heights z0 to z10 in the stack. In such memory devices, the memory vias etched through the stack have very high aspect ratios. For example, a depth-to-diameter ratio of approximately 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory via can vary along the length of the via. Typically, the diameter of the memory via gradually decreases from its top to its bottom. That is, the memory via is tapered, narrowing at the bottom of the stack. In some cases, it narrows slightly at the top of the hole near the select gate, so that the diameter of the memory via slightly widens before gradually decreasing from its top to its bottom.

[0105] Due to the non-uniformity of memory hole width, programming speed including programming slope and erase speed of a memory cell can vary based on the location of the memory cell along the memory hole (e.g., based on the height of the memory cell in the stack). For smaller diameter memory holes, the electric field across the tunnel oxide is relatively strong, making the programming and erase speed relatively high. One approach is to define groups of adjacent word lines that are similar in memory hole diameter (e.g., within a defined range of diameters) and apply an optimized verify scheme for each word line in the group. Different groups can have different optimized verify schemes.

[0106] FIG. 6D A close-up view of a region 622 of the stack of FIG. 6B is depicted. Memory cells are formed at the intersection of a word line layer and a memory hole at different levels of the stack. In this example, SGD transistors 680 and 681 are disposed above dummy memory cells 682 and 683 and data memory cells MC. Multiple layers can be deposited along the sidewall (SW) of the memory hole 630 and / or within each word line layer (e.g., using atomic layer deposition). For example, each column (e.g., a pillar formed of material within the memory hole) can include a charge trapping layer or film 663 (such as SiN or other nitride), a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. The word line layers can include a blocking oxide / high-k material 660, a metal blocking layer 661, and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided in the memory hole. In other approaches, some of the layers can be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars can form columnar active areas (AA) of a NAND string.

[0107] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0108] Each of the memory holes can be filled with a plurality of annular layers including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. A core region of each of the memory holes is filled with a bulk material, and the plurality of annular layers is located between the core region and the word line in each of the memory holes.

[0109] The NAND strings can be considered to have floating body channels, as the length of the channel is not formed on the substrate. Further, the NAND strings are provided by multiple word line layers stacked on top of one another and separated from one another by dielectric layers.

[0110] FIG. 7A A top view of an exemplary word line layer WLL0 of the stack is depicted. FIG. 6B As mentioned, the 3D memory device can include a stack of alternating conductive layers and dielectric layers. The conductive layers provide the control gates of the SG transistors and the memory cells. The layers for the SG transistors are the SG layers, and the layers for the memory cells are the word line layers. Further, the memory holes are formed in the stack and filled with charge-trapping material and channel material. Thus, vertical NAND strings are formed. The source lines are connected to the NAND strings below the stack and the bit lines are connected to the NAND strings above the stack.

[0111] The blocks BLK in the 3D memory device can be divided into sub-blocks, where each sub-block includes a group of NAND strings with a common SGD control line. For example, see SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBa, SBb, SBc, and SBd, respectively. The sub-blocks SBa, SBb, SBc, and SBd can also be referred to herein as strings of memory cells of word lines. As described, the strings of memory cells of word lines can include multiple memory cells belonging to the same sub-block and also disposed in the same word line layer and / or configured to have their control gates biased by and / or with the same word line and / or word line voltage.

[0112] Further, the word line layers in a block can be divided into regions. Each region in a respective sub-block can extend between slits that are periodically formed in the stack to handle the word line layers during the manufacturing process of the memory device. The handling can include replacing a sacrificial material of the word line layers with metal. In general, the distance between the slits should be relatively small to account for the limitation of the distance that an etchant can travel laterally to remove the sacrificial material and that the metal can travel to fill the voids created by the removal of the sacrificial material. For example, the distance between the slits can allow for a few rows of memory holes between adjacent slits. The layout of the memory holes and the slits should also account for the limitation of the number of bit lines that can extend across the regions when each bit line is connected to a different memory cell. After the word line layers are handled, the slits can optionally be filled with metal to provide interconnects through the stack.

[0113] The figures and other figures are not necessarily drawn to scale. In practice, the regions can be longer in the x-direction relative to the y-direction to accommodate additional memory holes.

[0114] In this example, there are four rows of memory holes between adjacent slits. A row here is a set of memory holes aligned in the x-direction. In addition, the rows of memory holes are arranged in an interleaved pattern to increase the density of memory holes. The word line layers or word lines are divided into regions WLL0a, WLL0b, WLL0c, and WLL0d that are each connected by a connector 713. In one approach, the last region of a word line layer in a block can be connected to the first region of a word line layer in the next block. The connectors in turn are connected to a voltage driver for the word line layer. Region WLL0a has exemplary memory holes 710 and 711 along line 712. Region WLL0b has exemplary memory holes 714 and 715. Region WLL0c has exemplary memory holes 716 and 717. Region WLL0d has exemplary memory holes 718 and 719. The memory holes are also shown in FIG. 7B FIG. 3. Each memory hole can be part of a respective NAND string. For example, memory holes 710, 714, 716, and 718 can be part of NAND strings NS0 SBa, NS0 SBb, NS0 SBc, and NS0 SBd, respectively.

[0115] Each circle represents a cross-section of a memory hole at a word line layer or SG layer. Exemplary circles shown in dashed lines represent memory cells provided by the material in the memory hole and the adjacent word line layer. For example, memory cells 720 and 721 are in WLL0a, memory cells 724 and 725 are in WLL0b, memory cells 726 and 727 are in WLL0c, and memory cells 728 and 729 are in WLL0d. These memory cells are at a common height in the stack.

[0116] Metal-filled slits 701, 702, 703, and 704 (e.g., metal interconnects) can be located between and adjacent to the edges of regions WLL0a through WLL0d. The metal-filled slits provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack can be connected to a conductive line above the stack, where the conductive line is connected to a voltage driver in a peripheral region of the memory device. See also FIG. 8A For more details on FIG. 7A sub-blocks SBa through SBd.

[0117] FIG. 7B depicted FIG. 6Btop view of an exemplary top dielectric layer DL19 of the stack. The dielectric layer is divided into regions DL19a, DL19b, DL19c, and DL19d. Each region can be connected to a respective voltage driver. This allows simultaneous programming of a group of memory cells in one region of a word line layer, where each memory cell is in a respective NAND string connected to a respective bit line. A voltage can be set on each bit line to allow or disallow programming during each programming voltage.

[0118] Region DL19a has exemplary memory holes 710 and 711 along a line 712a that coincides with bit line BLO. Many bit lines extend over the memory holes and are connected to the memory holes, as indicated by the “X” symbols. BLO is connected to a group of memory holes that includes memory holes 711, 715, 717, and 719. Another exemplary bit line BL1 is connected to a group of memory holes that includes memory holes 710, 714, 716, and 718. Also depicted are FIG. 7A metal-filled slits 701, 702, 703, and 704 in the stack as they extend vertically through the stack. Bit lines can be numbered in the x-direction across the DL19 layer in the order BLO to BL23.

[0119] Different subsets of bit lines are connected to cells in different rows. For example, BLO, BL4, BL8, BL12, BL16, and BL20 are connected to cells in a first row of cells at the right-hand edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to cells in an adjacent row of cells adjacent to the first row at the right-hand edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to cells in a first row of cells at the left-hand edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to cells in an adjacent row of cells adjacent to the first row at the left-hand edge.

[0120] FIG. 8A exemplary NAND strings in sub-blocks SBa to SBd of the stack. The sub-blocks are consistent with the structure of FIG. 7A FIG. 6B The conductive layers in the stack are depicted for reference on the left-hand side. Each sub-block includes a plurality of NAND strings, one exemplary NAND string of which is depicted. For example, SBa includes exemplary NAND string NS0_SBa, SBb includes exemplary NAND string NS0_SBb, SBc includes exemplary NAND string NS0_SBc, and SBd includes exemplary NAND string NS0_SBd.

[0121] ​In addition, NSO_SBb includes SGS transistors 820 and 821, dummy memory cells 822 and 823, data memory cells 824, 825, 826, 827, 828, 829, 830, 831, 832, 833, and 834, dummy memory cells 835 and 836, and SGD transistors 837 and 838.

[0122] NSO_SBb includes SGS transistors 820 and 821, dummy memory cells 822 and 823, data memory cells 824, 825, 826, 827, 828, 829, 830, 831, 832, 833, and 834, dummy memory cells 835 and 836, and SGD transistors 837 and 838.

[0123] NSO_SBb includes SGS transistors 820 and 821, dummy memory cells 822 and 823, data memory cells 824, 825, 826, 827, 828, 829, 830, 831, 832, 833, and 834, dummy memory cells 835 and 836, and SGD transistors 837 and 838.

[0124] NSO_SBb includes SGS transistors 820 and 821, dummy memory cells 822 and 823, data memory cells 824, 825, 826, 827, 828, 829, 830, 831, 832, 833, and 834, dummy memory cells 835 and 836, and SGD transistors 837 and 838.

[0125] At a given height in a block, a set of memory cells in each sub-block is at a common height. For example, a set of memory cells including memory cell 804 is in a plurality of memory cells formed in a tapered memory hole in a stack of alternating conductive layers and dielectric layers. The set of memory cells is at a particular height z0 in the stack. Another set of memory cells including memory cell 824 connected to one word line (WLL0) is also at the particular height. In another approach, a set of memory cells including memory cell 812 connected to another word line (e.g., WLL8) is at another height (z8) in the stack.

[0126] FIG. 8BAnother exemplary view of NAND strings within a sub-block is depicted. The NAND strings include NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd, which have 48 word lines WL0 to WL47 in this example. Each sub-block includes a set of NAND strings extending along the x-direction and having a common SGD line, such as SGD0, SGD1, SGD2, or SGD3. In this simplified example, each NAND string contains only one SGD transistor and one SGS transistor. The NAND strings NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd are located in sub-blocks SBa, SBb, SBc, and SBd, respectively. Furthermore, an exemplary group of word lines G0, G1, and G2 is depicted.

[0127] FIG. 8C A schematic diagram of three types of interleaved string architectures 101, 103, and 105 for BiCS memories (e.g., NAND) is shown in general. Referring to string architecture 101, strings are shown in rows 107-0 to 107-7 of architecture 101. Each row is shown with four ends of a string. Strings may be connected to adjacent strings at the ends (not visible below this view). The first set of rows 107-0 to 107-3 is shown to the left of dummy row 108. The second set of rows 107-4 to 107-7 is shown to the right of dummy row 108. Dummy row 108 separates the two sets of rows in eight interleaved rows. Source line 109 is located at the edge of the first set and away from dummy row 108. Source line 109-2 is located at the edge of the second set and away from dummy row 108 and source line 109.

[0128] The interleaved string architectures 103 and 105 of the BiCS memory are similar to the interleaved string architecture 101, except that the former adds additional groups. Architecture 103 is twice the size of architecture 101 and consists of sixteen strings, with each group of four strings separated by dummy lines. Architecture 105 is larger than both architectures 101 and 103. Architecture 105 consists of twenty strings, with each group of four strings separated by dummy lines 108.

[0129] These architectures 101, 103, and 105 may include chips beneath an array structure, for example, control circuitry beneath a memory array that may include groups of memory strings. Utilizing the chips beneath the array structure, the strings may include direct strap contacts for source lines for read and erase operations.

[0130] Erasing can be performed on the entire memory array, individual blocks, or another unit of cells. In one implementation, a group of memory cells is erased by raising the p-well of the memory cells to an erase voltage for a sufficient period of time. The erase pulse moves the threshold voltage of the memory cells toward (or beyond) an erase target level, which can be below 0 volts. In some implementations, after the erase pulse is applied, an erase verify operation is performed to determine whether the threshold voltage of the memory cells has reached at least the erase target level. The erase pulse and erase verify are repeated with each cycle using a higher amplitude erase pulse until the erase verify passes.

[0131] The erase operation can be completed in multiple cycles (e.g., two cycles). For example, an erase voltage (VERA) can be used for a first cycle, and the erase voltage can be increased by a boost voltage (dVERA) and used for a second cycle. The number of cycles implemented in an erase operation can be limited by the time of the erase operation (tERASE). If the number of cycles used in an erase operation is increased, the time to perform the erase operation will increase. A two-pulse erase operation can meet the time of the erase operation tERASE. However, over time, particularly at the end of a product’s life, it can become more difficult to erase some memory devices. In some cases, three cycles can be needed if the second pulse does not pass the erase verify.

[0132] Defects (e.g., such as a word line to memory hole short, a word line to dummy word line short, etc.) can cause a single word line or a few word lines to “erase slower.” The slower erasing word lines can cause uncorrectable error correction code (UECC) failures (due to high Er->A), which can result in user data corruption. This has become one of the major issues for parts per million defective (DPPM).

[0133] Conventionally, two device modes have been used to offset the slower erase issues described above. These device modes include an erase cycle comparator and a tail detect read (TDR). The erase cycle comparator mode looks for cycle differences between two adjacent planes. The erase cycle comparator mode is quantized to two or three cycles. For example, in some cases, a defective block can pass an erase operation in two or three cycles. If the failure criteria is set to one cycle, this can result in false triggers and overkill of good blocks that are not defective. If the failure criteria is relaxed to two cycles, it can be too loose to catch defective blocks. In addition, the single word line slower erase issue can not be reflected on the erase cycles. Thus, the erase cycle comparator is not an effective method to capture the slower erase word line issue.

[0134] TDR mode can be used to detect shallow erase issues. TDR mode involves using AR to read data word lines before PGM to detect shallow erase tails. TDR is performed in a single-word-line read manner, which results in a significant tPROG impact. Therefore, TDR mode is typically not implemented for data word line erase tail detection.

[0135] To address the aforementioned issues, the implementation described herein relates to an erase tail word line region comparator mode. This mode is implemented to capture slow erase word line issues, thereby preventing user data corruption. For example, the erase tail word line region comparator mode includes: dividing the word line into distinct word line regions; performing an erase verification voltage (VCG_ERV) scan to detect the erase tail after the first erase pulse; and comparing the erase tail across different word line regions to detect slow erase word line issues. If the difference in erase tails between different word line regions exceeds a failure criterion, this mode terminates the erase operation on the block and marks it as defective.

[0136] To further address the aforementioned issues, the implementation described herein relates to an erase tail plane comparator mode. An erase tail plane comparator mode is proposed as a more efficient method for detecting slower erase planes. This mode involves: comparing the erase tail of the plane after the first erase pulse with the erase tails of different planes to detect slower erase planes; and terminating the erase operation on the slower plane after the first erase pulse, while other planes continue to be erased normally.

[0137] To explore the foregoing in more detail, the following will now be described. FIG. 12 . FIG. 12 A method 1200 for erasing a tail comparator scheme according to an embodiment described herein is depicted. In some embodiments, method 1200 may be implemented by a controller, control circuitry, processor, etc., as described elsewhere in this document. FIG. 12 As shown, method 1200 begins at step 1202. In step 1202, in the first erase cycle of a plurality of erase cycles of the erase operation, a first erase pulse is applied to a first group of non-volatile memory elements. For example, refer to FIG. 1A and 1B The control circuit 110 may apply a first erase pulse to a set of non-volatile memory elements (e.g., memory device 126a). In some embodiments, the control circuit 110 may cooperate with the read / write circuit 128 to perform memory operations on the memory structure 126. Alternatively, in some embodiments, this step may be achieved by raising the p-well to the erase voltage for a sufficient period of time and grounding the word line of the selected block while the source line and bit line float.

[0138] In step 1204, after applying the first erase pulse, an upper tail of the threshold voltage distribution of the first set of non-volatile storage elements is determined. For example, continuing with reference to FIG. 1A to FIG. 1B , the control circuit 110 can determine the upper tail of the threshold voltage distribution of the first set of non-volatile storage elements (e.g., storage device 126A). More specifically, the control circuit 110 can determine a reference point on the threshold distribution after the first erase pulse in step 1202. The reference point referred to herein is the “upper tail Vth” because the reference point is generally at the uppermost end of the Vth distribution. In some embodiments, the reference point on the threshold distribution can be determined using an erase verify level scan.

[0139] To help further illustrate, the erase verify level scan can include: first applying a voltage (e.g., 2V) to a word line (e.g., an even word line, an odd word line, or both an even word line and an odd word line) and one or more NAND strings (e.g., one, two, three, or five NAND strings); and performing a bit scan operation, where a count is determined based on a number of memory cells or NAND strings storing a logical value of “0”. If the number of memory cells storing a data state of “0” is less than a threshold amount, such as a bit scan pass fail standard (e.g., BSPF E VE), an erase verify voltage (VCG ERV) is stepped down (e.g., by 0.5V) and applied to the word line. The BSPF standard relates to a number of failed bits allowed in the operation. The process is repeated until the number of memory cells storing a data state of “0” is greater than or equal to the threshold amount, such as the BSPF standard. To help further illustrate, the following sequence of voltages can be applied until the count is greater than or equal to the BSPF standard: 2V, 1.5V, 1V, 0.5V, 0V, etc. Once the count is equal to or greater than the threshold amount, the applied voltage can be used as the reference point on the threshold distribution and can be indicated as the upper tail of the first set of non-volatile storage elements.

[0140] In step 1206, a difference between the upper tail of the first set of non-volatile storage elements and the upper tail of the threshold voltage distribution of the second set of non-volatile storage elements is determined. For example, continuing with reference to FIG. 1A and FIG. 1B , the control circuit 110 can compare the upper tail of the first set of non-volatile storage elements to the upper tail of the threshold voltage distribution of the second set of non-volatile storage elements and determine a difference between the upper tail of the first set of non-volatile storage elements and the upper tail of the threshold voltage distribution of the second set of non-volatile storage elements.

[0141] In step 1208, if the difference is greater than or equal to a threshold amount, then erase operations on the first set of non-volatile storage elements are disabled in a second erase cycle of the plurality of erase cycles. For example, continuing with reference to FIG. 1A and FIG. 1BIf the difference is greater than or equal to the threshold amount, the control circuit 110 can disable an erase operation on the first set of non-volatile storage elements. In contrast, in some embodiments, with continued reference to FIG. 1A and FIG. 1B If the difference is less than the threshold amount, the control circuit 110 can apply a second erase pulse to the first set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles.

[0142] FIG. 13 An exemplary illustration of an erase threshold distribution following implementation of the erase tail comparator scheme described above with reference to FIG. 12 is provided. In FIG. 13 , an erase threshold distribution 1302 is depicted following application of a first erase voltage pulse to a set of non-volatile storage elements as described in step 1202 of FIG. 12 . Further, in FIG. 13 , a step-wise decrease of an erase verification voltage (VCG ERV) is depicted at 1304 to determine an upper tail of the threshold voltage distribution of the set of non-volatile storage elements as described in step 1204 of FIG. 12 .

[0143] Further, in FIG. 13 , an erase verification voltage is represented at 1306. In some embodiments, an erase verification operation can be performed to determine whether the threshold voltage of a non-volatile storage element in the set of non-volatile storage elements has at least reached an erase target level. For example, with continued reference to FIG. 1A and FIG. 1B , the control circuit 110 can perform the erase verification operation by reading data of the memory cell based on the erase verification voltage. To help further illustrate, when the read data has a first logic level (e.g., “1”), the data of the memory cell can be determined to be a fail bit; when the read data has a second logic level (e.g., “0”), the data of the memory cell can be determined to be a pass bit. A fail bit counter included in the memory device 100 can count the fail bits. The verify voltage can be set such that based on an amount of degradation from the erase cycle and a distribution of the memory cell calculated through experiments during a manufacturing process, the number of fail bits is equal to or less than the number of error checking and correction (ECC) bits.

[0144] To help further explore the above in more detail, a method 1400 of implementing an erase tail word line region comparator scheme according to embodiments described herein will now be described. FIG. 14 . FIG. 14 A method 1400 of implementing an erase tail word line region comparator scheme according to embodiments described herein is depicted. In some embodiments, the method 1400 can be implemented by a controller, control circuit, processor, etc. as described in other sections herein. As FIG. 14As shown, the method 1400 begins at step 1402. In step 1402, the erase operation can begin on the non-volatile storage device.

[0145] In FIG. 14 step 1404, a first erase voltage pulse is applied to a set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation. As described, with continued reference to FIG. 1A and FIG. 1B , the control circuit 110 can apply a first erase voltage pulse (VERA) to a set of non-volatile storage elements (e.g., storage device 126A).

[0146] In step 1406, an erase verify voltage (VCG ERV) scan is performed in each word line region after the application of the first erase pulse. For example, with continued reference to FIG. 1A and FIG. 1B , the control circuit 110 can perform an erase verify voltage scan in each word line region on even digit lines, odd digit lines, or both even and odd digit lines. More specifically, the control circuit 110 can determine a reference point on the threshold distribution after the first erase pulse in step 1402. In some embodiments, the erase verify voltage scan can be used to determine the reference point on the threshold distribution. For example, in each word line region, the erase verify level scan can include: first applying a voltage (e.g., 2V) to the word lines (e.g., even digit lines, odd digit lines, or both even and odd digit lines) and one or more NAND strings (e.g., one, two, three, or five NAND strings); and performing a bit scan operation, where a count is determined based on a number of memory cells or NAND strings storing a logical value of “0”. A sequence of voltages can be applied until the count is greater than or equal to a BSPF standard: 2V, 1.5V, 1V, 0.5V, 0V, etc.

[0147] In step 1408, it is determined whether a number of non-volatile storage elements in the set of non-volatile storage elements storing a logical value is greater than or equal to a threshold amount. For example, with continued reference to FIG. 1A and FIG. 1B , the control circuit 110 can determine whether a number of memory cells storing a data state of “0” is greater than or equal to a threshold amount, such as a bit scan pass fail standard (e.g., BSPF EV). If the count is less than the threshold amount, in step 1410, the erase verify voltage (VCG ERV) is stepped down (e.g., by 0.5V) and applied to the word lines. This process is repeated until the number of memory cells storing a data state of “0” is greater than or equal to the threshold amount.

[0148] At step 1412, once the count is equal to or greater than the threshold amount, the applied erase verify voltage can be used as a reference point on the threshold distribution and can be output as the erase lower tail. This step can be performed for each word line region. For example, after the first erase pulse, in each word line region, a VCG ERV scan can be performed with BSPF to detect the erase upper tail location for each word line region. More specifically, the VCG ERV scan can start at 2.0 V and decrease by a step size of 0.5 V. Additionally, an erase verify is performed with a VCG ERV of 2.0 V and a count of "0" bits to see if the bit count has reached the BSPF. The BSPF can be shared with the erase verify BSPF EVA. If the "0" bit count is less than the BSPF, the VCG ERV will decrease by 0.5 V and another erase verify is performed at a VCG ERV of 1.5 V and another count of "0" bits to see if the "0" bit count reaches the BSPF. If the "0" bit count is greater than or equal to the BSPF EVA, the VCG ERV value is output as the erase upper tail location for that word line region.

[0149] At step 1414, the erase tails are compared across different word line regions to see if the difference reaches a failure criterion (e.g., delta_ErTail). For example, continuing with reference to FIG. 1A and FIG. 1B the control circuit 110 can compare the erase tails of different word line regions to see if the difference reaches a failure criterion.

[0150] As shown at step 1416, if the erase tail difference between word line regions reaches a failure criterion, the erase operation on the block is disabled and the state of the block is set to erase failure and the block is marked as defective. For example, continuing with reference to FIG. 1A and FIG. 1B the control circuit 110 disables the erase operation on the block and sets the state of the block to erase failure and marks the block as defective.

[0151] As shown at step 1418, if the erase tail difference between word line regions is less than the failure criterion, the block will continue with normal erase. For example, continuing with reference to FIG. 1A and FIG. 1B the control circuit 110 can continue the erase operation on the block. The erase tail detection will be completed on each word line region. The erase tails from different word line regions are then compared to determine if the difference reaches a failure criterion. If the difference is less than the failure criterion, the block will receive a second erase pulse followed by a regular erase verify. If the erase tail difference is greater than the failure criterion, it will terminate the erase operation on the defective block and mark the defective block.

[0152] In some implementations, various parameters for implementing the erase tail comparator scheme described herein can be programmed into a specific memory device (e.g., a programmable ROM). For example, a first parameter may be able to disable or enable the erase tail word line region comparator scheme, a second parameter may allow selection of even-numbered lines, odd-numbered lines, or both even-numbered and odd-numbered lines for the erase verification voltage scan, and a third parameter may allow selection of one, two, three, or five strings for the erase verification voltage scan. Another parameter determines the number of word line regions into which the word lines will be divided (e.g., two, three, six, or nine word line regions). Another parameter may include an erase verification voltage offset for the starting erase verification voltage. For example, for TLC, the erase verification voltage may be 0.8V; therefore, the starting erase verification voltage may have options of 3.0V, 2.5V, 2.0V, and 1.5V. Similarly, for SLC, the starting erase verification voltage may have options of 3.8V, 3.3V, 2.8V, and 2.3V. Additionally, another parameter may be able to select the step size (e.g., 0.5V, 0.4V, 0.2V, 0.1V, etc.) used in the erase verification voltage scan during erase tail detection. In some implementations, the bit omission used for erase tail detection may be shared with erase verification (e.g., BSPF_EV_MLC). Another parameter may determine the failure criterion (e.g., 0.2V, 0.3V, 0.4V, 0.5V, etc.).

[0153] To help explore the above content in more detail, the following will now be described. FIG. 15 . FIG. 15 A method 1500 for implementing an erase tail plane comparator scheme according to the embodiments described herein is described. In some embodiments, method 1500 may be implemented by a controller, control circuitry, processor, etc., as described in other parts of this document. FIG. 15 As shown, method 1500 begins at step 1502. In step 1502, the multi-plane erasure operation may begin on the non-volatile storage device.

[0154] exist FIG. 15 In step 1504, in the first erase cycle of the plurality of erase cycles in the erase operation, a first erase voltage pulse is applied to a group of non-volatile memory elements. As described, continue to refer to FIG. 1A and FIG. 1B The control circuit 110 can apply a first erase voltage pulse (VERA) to a group of non-volatile storage elements (e.g., storage device 126A).

[0155] In step 1506, an erase verification voltage (VCG_ERV) scan is performed after a first erase pulse is applied to the even-numbered or odd-numbered lines of each plane. For example, continue to refer to FIG. 1A and FIG. 1B, the control circuit 110 can perform an erase verify voltage sweep on even digit lines, odd digit lines, or both even and odd digit lines in each plane. More specifically, the control circuit 110 can determine a reference point on the threshold distribution after the first erase pulse in step 1502. In some embodiments, the reference point on the threshold distribution can be determined using an erase verify voltage sweep. For example, in each plane, the erase verify level sweep can include first applying a voltage (e.g., 2V) to the word lines (e.g., even digit lines, odd digit lines, or both even and odd digit lines) and one or more NAND strings (e.g., one, two, three, or five NAND strings); and performing a bit-scan operation, where a count is determined based on the number of memory cells or NAND strings storing a logical value of “0.” A sequence of voltages can be applied until the count is greater than or equal to a BSPF standard: 2V, 1.5V, 1V, 0.5V, 0V, etc.

[0156] In step 1508, a determination is made as to whether the number of non-volatile storage elements storing a logical value in the set of non-volatile storage elements is greater than or equal to a threshold amount. For example, continuing with the example from FIG. 1A and FIG. 1B , the control circuit 110 can determine whether the number of memory cells storing a data state of “0” is greater than or equal to a threshold amount (such as a bit-scan pass fail standard (e.g., BSPF_EV)). If the count is less than the threshold amount, then in step 1510, the erase verify voltage (VCG_ERV) is stepped down (e.g., by 0.5V) and applied to the word lines. This process is repeated until the number of memory cells storing a data state of “0” is greater than or equal to the threshold amount.

[0157] In step 1512, once the count is equal to or greater than the threshold amount, the applied erase verify voltage can be used as a reference point on the threshold distribution and can be output as an erase overtail position. This step can be performed for each plane. For example, after the first erase pulse, a VCG_ERV sweep can be performed with BSPF to detect the erase overtail position for each plane. More specifically, the VCG_ERV sweep can start at 2.0V and decrease in step size of 0.5V. Additionally, an erase verify is performed with a VCG_ERV of 2.0V and a count of “0” bits to see if the bit count has reached the BSPF. The BSPF can be shared with the erase verify BSPF_EVA. If the “0” bit count is less than the BSPF, then the VCG_ERV will be decreased by 0.5V, and another erase verify is performed at a VCG_ERV of 1.5V, and another count of “0” bits is performed to see if the “0” bit count reaches the BSPF. If the “0” bit count is greater than or equal to the BSPF_EVE, then the VCG_ERV value is output as the erase overtail position for that word line region.

[0158] In step 1514, the erase tails are compared across different planes to determine if the difference in erase tails between the planes reaches a failure criterion (e.g., delta_ErTail). For example, continuing with the example from FIG. 1A and FIG. 1B , the control circuit 110 can compare the erase tails of different planes to see if the difference reaches a failure criterion.

[0159] As shown in step 1516, if the difference in erase tails between the planes reaches the failure criterion, the erase operation is disabled on the plane with the higher erase tail, and the state of the plane is set to erase failure and the block is marked as defective. For example, continuing with the example from FIG. 1A and FIG. 1B , the control circuit 110 disables the erase operation on the plane with the higher erase tail, and sets the state of the plane to erase failure.

[0160] As shown in step 1518, if the difference in erase tails between the planes is less than the failure criterion, the block will continue to erase normally. For example, continuing with the example from FIG. 1A and FIG. 1B FIG. 15 FIG. 15 FIG. 15 FIG. 15 FIG. 1A FIG. 1B FIG. 1A FIG. 1B FIG. 1A FIG. 1B FIG. 1A FIG. 1B FIG. 1A FIG. 1B FIG. 1A FIG. 1B , the control circuit 110 can continue the erase operation on the planes. The erase tails from the different planes are then compared to determine if the difference reaches a failure criterion. If the difference is less than the failure criterion, the planes will receive a second erase pulse, after which a regular erase verification is performed. If the difference in erase tails is greater than the failure criterion, the erase operation is disabled on the plane with the higher erase tail, and the plane is marked as defective.

[0161] In some embodiments, various parameters for implementing the erase tail comparator schemes described herein can be programmed into a particular memory device (e.g., programmable ROM). For example, a first parameter can enable or disable the erase tail plane comparator scheme, a second parameter can allow for selecting even digit lines, odd digit lines, or both even and odd digit lines for the erase verify voltage scan, and a third parameter can allow for selecting one, two, three, or five strings for the erase verify voltage scan. Another parameter can include an erase verify voltage offset for a starting erase verify voltage. For example, for TLC, the erase verify voltage can be 0.8V; thus, the starting erase verify voltage can have options of 3.0V, 2.5V, 2.0V, and 1.5V. As another example, for SLC, the starting erase verify voltage can have options of 3.8V, 3.3V, 2.8V, and 2.3V. Additionally, another parameter can enable selection of a step size (e.g., 0.5V, 0.4V, 0.2V, 0.1V, etc.) used in the erase verify voltage scan in the erase tail detection. In some embodiments, the bit ignore for erase tail detection can be shared with erase verify (e.g., BSPF_EV_MLC). Another parameter can determine the failure criterion (e.g., 0.2V, 0.3V, 0.4V, 0.5V, etc.).

[0162] The foregoing detailed description of the application has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the application and its practical application to thereby enable others skilled in the art to best utilize the application in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the application be defined by the claims appended hereto.

Claims

1. A method of performing an erase operation on a non-volatile storage device, comprising: applying a first erase pulse to a first set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation; determining an upper tail of a threshold voltage distribution of the first set of non-volatile storage elements after applying the first erase pulse; determining a difference between the upper tail of the first set of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second set of non-volatile storage elements; and if the difference is greater than or equal to a threshold amount, disabling the erase operation on the first set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles.

2. The method of claim 1, further comprising: if the difference is less than a threshold amount, applying a second erase pulse to the first set of non-volatile storage elements in the second erase cycle of the plurality of erase cycles.

3. The method of claim 1, wherein determining the upper tail of the threshold voltage distribution of the first set of non-volatile storage elements comprises: applying a first voltage to one or more word lines of the first set of non-volatile storage elements; determining a number of non-volatile storage elements of the first set of non-volatile storage elements that store a logical value; determining a reference point on a threshold distribution based on the number of non-volatile storage elements that store the logical value; and identifying the upper tail of the first set of non-volatile storage elements as the reference point on the threshold distribution.

4. The method of claim 1, wherein the first set of non-volatile storage elements are arranged in a first plane and the second set of non-volatile storage elements are arranged in a second plane.

5. The method of claim 4, further comprising: if the difference is greater than or equal to the threshold amount, disabling the erase operation on the first plane; and continuing to perform the erase operation on the second plane.

6. The method of claim 1, wherein the first set of non-volatile storage elements have a first word line region and the second set of non-volatile storage elements have a second word line region.

7. The method of claim 1, further comprising: if the difference is greater than or equal to the threshold amount, designating a block including the first set of non-volatile storage elements as a failed erase operation.

8. A non-volatile storage device, comprising: a set of non-volatile storage elements; and one or more management circuits in communication with the set of non-volatile storage elements and configured to: apply a first erase pulse to a first set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of an erase operation; determine an upper tail of a threshold voltage distribution of the first set of non-volatile storage elements after applying the first erase pulse; determine a difference between the upper tail of the first set of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second set of non-volatile storage elements; and if the difference is greater than or equal to a threshold amount, disable the erase operation on the first set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles. if the difference is greater than or equal to a threshold amount, then disabling the erase operation on the first set of non-volatile storage elements in a second erase cycle of the multiple erase cycles.

9. The non-volatile storage device of claim 8, wherein the one or more managing circuits are further configured to apply a second erase pulse to the first set of non-volatile storage elements in the second erase cycle of the multiple erase cycles if the difference is less than a threshold amount.

10. The non-volatile storage device of claim 8, wherein the one or more managing circuits are further configured to apply a first voltage to one or more word lines of the first set of non-volatile storage elements; determining a number of non-volatile storage elements of the first set of non-volatile storage elements that store a logical value; determining a reference point on a threshold distribution based on the number of non-volatile storage elements that store the logical value; and identifying the upper tail of the first set of non-volatile storage elements as the reference point on the threshold distribution.

11. The non-volatile storage device of claim 8, wherein the first set of non-volatile storage elements are arranged in a first plane and the second set of non-volatile storage elements are arranged in a second plane.

12. The non-volatile storage device of claim 11, wherein the one or more managing circuits are further configured to disable the erase operation on the first plane if the difference is greater than or equal to the threshold amount; and continue to perform the erase operation on the second plane.

13. The non-volatile storage device of claim 8, wherein the first set of non-volatile storage elements have a first word line region and the second set of non-volatile storage elements have a second word line region.

14. The non-volatile storage device of claim 8, wherein the one or more managing circuits are further configured to: designate a block including the first set of non-volatile storage elements as a failed erase operation if the difference is greater than or equal to the threshold amount.

15. A controller in communication with a set of non-volatile storage elements of a memory device, the controller configured to: apply a first erase pulse to a first set of non-volatile storage elements in a first erase cycle of a multiple erase cycles of an erase operation; determine an upper tail of a threshold voltage distribution of the first set of non-volatile storage elements after applying the first erase pulse; determine a difference between the upper tail of the first set of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second set of non-volatile storage elements; and if the difference is greater than or equal to a threshold amount, then disabling the erase operation on the first set of non-volatile storage elements in a second erase cycle of the multiple erase cycles.

16. The controller of claim 15, wherein the controller is further configured to: apply a second erase pulse to the first set of non-volatile storage elements in the second erase cycle of the multiple erase cycles if the difference is less than a threshold amount.

17. The controller of claim 15, wherein the controller is further configured to: apply a first voltage to one or more word lines of the first set of non-volatile storage elements; determine a number of non-volatile storage elements in the first set of non-volatile storage elements that store a logical value; determine a reference point on a threshold distribution based on the number of non-volatile storage elements that store the logical value; and identify the upper tail of the first set of non-volatile storage elements as the reference point on the threshold distribution.

18. The controller of claim 15, wherein the first set of non-volatile storage elements are arranged in a first plane and the second set of non-volatile storage elements are arranged in a second plane.

19. The controller of claim 18, wherein the controller is further configured to: disable the erase operation on the first plane if the difference is greater than or equal to the threshold amount; and continue performing the erase operation on the second plane.

20. The controller of claim 15, wherein the first set of non-volatile storage elements have a first word line region and the second set of non-volatile storage elements have a second word line region.

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