A fast RAM detection method, system, detection device and storage medium

Abstract

Embodiments of the present application relate to a kind of fast RAM detection method, system, detection equipment and storage medium, the method comprises: when the MCU is powered on, the memory space of RAM is detected in the unit of first quantity of bytes, and the RAM detection result is obtained, the first quantity is determined according to running memory space and the length of byte in advance;Based on the RAM detection result, the power-on result corresponding to the MCU is determined.Through again the MCU is powered on, the data of RAM memory space is detected in the unit of first quantity of bytes, and the fast RAM detection of RAM memory space is completed.Thereby, the technical effects that can realize shortening detection time and keeping fault coverage unchanged can be realized.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of RAM detection, and in particular to a fast RAM detection method, system, detection device and storage medium. BACKGROUND

[0002] In the development process of embedded software, the safety requirement of the system is higher and higher. As an important component in the embedded field, the failure rate of the microcontroller unit (MCU) increases with the service life.

[0003] As a part of the MCU, the RAM detection directly affects the start result of the MCU. The traditional RAM detection is to detect all the memory space of the RAM according to each bit when the MCU is powered on. This results in long detection time, high hardware cost and low accuracy. There are generally high failure rate and low test efficiency. In addition, some detection algorithms can provide good fault coverage, but the diagnosis time is long and the form is complex.

[0004] Therefore, how to solve the problems of long detection time and low fault coverage is a technical problem to be solved at present. SUMMARY

[0005] In view of this, in order to solve the above technical problems of long detection time and low fault coverage, embodiments of the present application provide a fast RAM detection method, system, detection device and storage medium.

[0006] In a first aspect, the embodiments of the present application provide a fast RAM detection method, comprising:

[0007] When the MCU is powered on, the memory space of the RAM is detected in units of a first number of bytes to obtain a RAM detection result, the first number being determined in advance according to the length of the running memory space and the byte;

[0008] Based on the RAM detection result, the power-on result corresponding to the MCU is determined.

[0009] In one possible implementation, the RAM detection of the memory space of the RAM in units of the first number of bytes comprises:

[0010] The memory space of the RAM is detected through five detection steps set in advance; the five detection steps are as follows:

[0011] In the first detection step, the memory space of the RAM is detected in units of the first number of bytes according to the detection rule of diagnosing adjacent bits;

[0012] In the second detection step, the memory space of the RAM is detected according to the detection rule of the diagnostic interval 1 bit, and the detection is performed in the first number of bytes;

[0013] In the third detection step, the memory space of the RAM is detected according to the detection rule of the diagnostic interval 2 bit, and the detection is performed in the first number of bytes;

[0014] In the fourth detection step, the memory space of the RAM is detected according to the detection rule of the diagnostic interval 3 bit, and the detection is performed in the first number of bytes;

[0015] In the fifth detection step, the memory space of the RAM is detected according to the reset detection rule, and the detection is performed in the first number of bytes.

[0016] In a possible implementation, the method further comprises:

[0017] verifying the RAM detection result;

[0018] When the RAM detection result is successful, the memory space of the RAM is detected in the second number of bytes every preset time, wherein the second number is less than the first number, and the second number is determined according to the running memory space and the length of the byte in advance;

[0019] When the RAM detection result is failed, the MCU is powered off;

[0020] and,

[0021] When the RAM detection result is failed, the RAM detection result is displayed.

[0022] In a possible implementation, the RAM detection of the memory space of the RAM in the second number of bytes comprises:

[0023] The memory space of the RAM is detected through the five detection steps set in advance; the five detection steps are specifically as follows:

[0024] In the first detection step, the memory space of the RAM is detected according to the detection rule of the diagnostic adjacent bit, and the detection is performed in the second number of bytes;

[0025] In the second detection step, the memory space of the RAM is detected according to the detection rule of the diagnostic interval 1 bit, and the detection is performed in the second number of bytes;

[0026] In the third detection step, according to a detection rule of a bit of the diagnostic interval 2, the RAM detection is performed on the memory space of the RAM in units of the second number of bytes;

[0027] In the fourth detection step, according to a detection rule of a bit of the diagnostic interval 3, the RAM detection is performed on the memory space of the RAM in units of the second number of bytes;

[0028] In the fifth detection step, according to a reset detection rule, the RAM detection is performed on the memory space of the RAM in units of the second number of bytes.

[0029] In a possible implementation, the power-off processing of the MCU includes:

[0030] controlling the MCU to stop sending a feeding signal to a hardware watchdog, so that the hardware watchdog disconnects the MCU from an external power supply.

[0031] In a second aspect, an embodiment of the present application provides a fast RAM detection system using a fast RAM detection method, including:

[0032] a RAM detection module and an MCU;

[0033] The RAM detection module is configured to perform RAM detection on a memory space of the RAM in units of a first number of bytes when the MCU is powered on, to obtain a RAM detection result; and determine a power-on result corresponding to the MCU based on the RAM detection result.

[0034] The RAM detection module is further configured to, when the RAM detection result is successful, perform RAM detection on the memory space of the RAM in units of a second number of bytes every preset time.

[0035] In a possible implementation, the system further includes a hardware watchdog and a power supply module.

[0036] The power supply module is configured to supply power to the MCU.

[0037] The hardware watchdog is configured to, when the MCU stops sending a feeding signal to the hardware watchdog, disconnect the MCU from the power supply module.

[0038] In a possible implementation, the system further includes a display module.

[0039] The display module is configured to, when the RAM detection result is unsuccessful, display the RAM detection result.

[0040] In a third aspect, an embodiment of the present application provides a detection device, comprising: a processor and a memory, the processor being configured to execute a fast RAM detection program stored in the memory to implement the fast RAM detection method according to any one of the first aspect.

[0041] In a fourth aspect, an embodiment of the present application provides a storage medium, the storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the fast RAM detection method according to any one of the first aspect.

[0042] The fast RAM detection method, system, detection device and storage medium provided by the embodiment of the present application can improve the RAM detection speed by performing RAM detection on the memory space of the RAM in units of a first number of bytes when the MCU is powered on, while fully covering the fault coverage rate, and obtaining the RAM detection result, the first number being determined in advance according to the length of the running memory space and the byte; the size of the first number of bytes is defined by the system running memory space; based on the RAM detection result, the power-on result corresponding to the MCU is determined; the RAM detection result is fed back to the MCU, and the power-on result is obtained through the analysis of the MCU; by the present solution, the detection time can be shortened, and the technical effect of maintaining the fault coverage rate unchanged can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0044] Figure 1 A flowchart of a fast RAM detection method provided by an embodiment of the present application;

[0045] Figure 2 A flowchart of another fast RAM detection method provided by an embodiment of the present application;

[0046] Figure 3 A flowchart of another fast RAM detection method provided by an embodiment of the present application;

[0047] Figure 4 A structural diagram of a fast RAM detection system provided by an embodiment of the present application;

[0048] Figure 5 A structural diagram of a detection device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0050] The terms "include" and "have" in the embodiments of the present application are used to represent an open-ended inclusion, and refer to the presence of additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second" are used only as labels, and are not intended to limit the number of objects. In addition, different elements and regions in the drawings are only schematically shown, and thus the present application is not limited to the sizes or distances shown in the drawings.

[0051] In order to facilitate the understanding of the embodiments of the present application, further explanation and description will be made below with reference to the drawings in specific embodiments, and the embodiments do not constitute a limitation on the embodiments of the present application.

[0052] RAM is commonly known as running memory, which is a component used to temporarily store data in a mobile phone, which is equivalent to a memory stick in a computer. It can be read and written at any time, and the speed is very fast, and is usually used as a temporary data storage medium for operating systems or other programs running. The RAM will lose its storage content when power is off, so it is mainly used to store programs used for a short time.

[0053] RAM detection refers to the RAM test of a system in order to improve the reliability of the system. Through the RAM test, the damage problem caused by the failure of the memory to the system can be effectively found and solved.

[0054] The fault coverage of RAM detection refers to the ratio of the number of faults detected by the software module being tested to the total number of faults of the software being tested. The higher the fault coverage, the smaller the error of the test result, and the more stable the performance of the system.

[0055] Figure 1 A flowchart of a fast RAM detection method provided by the embodiments of the present application is shown. The execution subject of the present application is MCU. According to the provided diagram, the fast RAM detection method comprises: Figure 1 The fast RAM detection method comprises:

[0056] S101, when the MCU is powered on, the memory space of the RAM is detected in units of a first number of bytes, and a RAM detection result is obtained, the first number being determined in advance according to the length of the running memory space and the byte.

[0057] The embodiment of the present application is applied to RAM detection when the MCU is powered on. The first number of bytes can be understood as fast detection of RAM with multi-byte length as the detection unit. The multi-byte length can be understood as detection of the memory space of the RAM with two-byte length, four-byte length or eight-byte length as the detection unit. The size of the first number of bytes is determined by the running memory of the system where the MCU is located. In a 16-bit running memory system, the first number of bytes can be understood as two-byte length as the detection unit, and the memory space of the RAM is detected two bytes at a time. In a 32-bit running memory system, the first number of bytes can be understood as detection of the memory space of the RAM with two-byte length or four-byte length as the detection frequency. Similarly, in a 64-bit running memory system, the first number of bytes can be understood as detection of the memory space of the RAM with two-byte length, four-byte length or eight-byte length as the detection frequency. At the same time, the first number of bytes and the detection rule set can keep the fault coverage rate unchanged.

[0058] Further, when the MCU is powered on, the RAM detection is started. The memory space of the RAM is detected with the first number of bytes as the detection frequency. When the memory space of the RAM is completely detected, the corresponding RAM detection result is obtained.

[0059] S102, based on the RAM detection result, determine the corresponding power-on result of the MCU.

[0060] The RAM detection result can be understood as the corresponding RAM detection result measured by detecting the memory space of the RAM. The RAM detection result is used to represent whether the RAM detection process is successful. If the RAM detection is successful, the MCU can run normally, and the MCU is successfully powered on. If the RAM detection is not successful, any first number of bytes in the memory space of the RAM is found to be not successfully detected, the MCU will interrupt the detection of the RAM, and the corresponding result of the MCU being not successfully powered on is obtained. Based on the RAM detection result, the MCU is processed differently, and the corresponding power-on result is obtained.

[0061] The embodiment of the application provides a kind of fast RAM detection method, by when the MCU is powered on, open RAM detection;By the memory space of RAM is detected with the first number of bytes as a unit;When RAM memory space is all detected, the corresponding RAM detection result is obtained;While RAM detection, keep fault coverage unchanged;According to RAM detection result, different processing is made to MCU, and the corresponding power-on result of MCU is determined;Complete the fast detection of the memory space of RAM detection in MCU with power on;Further realize the technical effect of shortening detection time, and keeping fault coverage unchanged.

[0062] Figure 2 Another flow diagram of the fast RAM detection provided by the embodiment of the application is provided.According to the content shown in Figure 2 Specifically, the fast RAM detection includes:

[0063] S201, when the MCU is powered on, the memory space of RAM is detected with the first number of bytes as a unit, and the RAM detection result is obtained, and the first number is determined according to the running memory space and the length of byte in advance.

[0064] The first number of bytes can be understood as fast detection of RAM with multiple byte length as detection unit. The multiple bytes can be understood as detection of the memory space of RAM with two byte length as detection unit, four byte length as detection unit or eight byte length as detection unit. The size of the first number of bytes is determined by the running memory of the system where the MCU is located. In a 16-bit running memory system, the first number of bytes can be understood as two byte length as detection unit, and the memory space of RAM is detected two bytes by two bytes. In a 32-bit running memory system, the first number of bytes can be understood as detection of the memory space of RAM with two byte length or four byte length as detection frequency. Similarly, in a 64-bit running memory system, the first number of bytes can be understood as detection of the memory space of RAM with two byte length, four byte length or eight byte length as detection frequency.

[0065] In a possible implementation scenario, the first number of bytes is four bytes, and the memory space of the RAM is detected by four-byte four-byte detection frequency. One byte is eight bits long. For a 32-bit running memory, 32 bits are equivalent to four bytes. When the MCU is powered on, the address of the 32-bit RAM memory space is detected, and each detection needs to read / write four bytes of the RAM address unit. After one detection, the entire memory space of the RAM can be detected. Similarly, for example, for a 64-bit running space system, that is, an eight-byte running space, according to the requirement that each detection needs to read / write four bytes of the RAM address unit, the entire memory space of the RAM can be detected twice, the detection time is shortened, and fast RAM detection is achieved.

[0066] S202, the memory space of the RAM is detected by the five detection steps.

[0067] The memory space of the RAM is detected by taking the first number of bytes as a detection unit. The first number of bytes can also be understood as two bytes, four bytes, or eight bytes, which is determined according to the system running space.

[0068] Further, in each RAM detection with the first number of bytes as a unit, the read / write operation of the data in the memory space of the RAM is implemented by setting five detection steps. In the process of reading data, as long as the read data and the written data are different, it indicates that the RAM detection fails, and the system enters a fault state.

[0069] S203, in the first detection step, the memory space of the RAM is detected by taking the first number of bytes as a unit according to the detection rule of diagnosing adjacent bits.

[0070] The detection rule of adjacent bits can be understood as setting different data for adjacent two bits, that is, in each byte length, the data of the first bit and the second bit is different, the data of the second bit and the third bit is different, the data of the third bit and the fourth bit is different, the data of the fourth bit and the fifth bit is different, and so on, to obtain new detection data. The data of the memory space of the RAM corresponding to adjacent two bytes can be different, but the data contained in each byte is set according to the detection principle of adjacent bits, so as to achieve the effect of diagnosing the fault coverage of adjacent bit data in the memory space of the RAM.

[0071] Further, by taking the first number of bytes as a detection unit, the memory space of the RAM is written with data, and the corresponding data is read out; the data obtained by the corresponding NOT operation is written again, and the corresponding data after the NOT operation is read out again, to complete the read / write processing of the data. In each data reading process, it is determined whether the data written in the memory space of the RAM is the same as the data read, if not, the RAM detection fails, and the system fault state is entered. At the same time, the fault coverage of the adjacent bit positions in the memory space of the RAM is diagnosed.

[0072] In a possible example scenario, for example, taking two bytes as the first number of bytes, corresponding to sixteen bit positions, according to the first step, in each byte length, the data of the adjacent bit positions is set to different data, 0101010101010101 is written into the two bytes of the RAM address from the low address to the high address in sequence, and the two bytes are read; and 0101010101010101 is inverted to 1010101010101010, and the two bytes are read. Because the data of the adjacent two bit positions is different, the RAM detection fault condition of the adjacent bit positions can be diagnosed.

[0073] Alternatively, for the first number of bytes with two bytes as the detection unit, 1010101010101010 can also be written into the two bytes of the RAM address from the low address bit to the high address bit in sequence, and the same as the following steps, the RAM detection fault condition of the adjacent bit positions can also be diagnosed, while the RAM detection of the memory space of the RAM is performed, the effect of maintaining the fault coverage is unchanged.

[0074] S204, in the second detection step, according to the detection rule of interval 1 bit position, the first number of bytes is taken as a unit to perform RAM detection on the memory space of the RAM.

[0075] The detection rule of interval 1 bit position can be understood as setting different data for interval 1 bit position, that is, in each byte length, the data of the first bit position and the third bit position is different, the data of the third bit position and the fifth bit position is different, the data of the second bit position and the fourth bit position is different, the data of the fourth bit position and the sixth bit position is different, and so on, to obtain new detection data. The data of the adjacent two bytes corresponding to the memory space of the RAM can be different, but the data contained in each byte is set according to the detection rule of interval 1 bit position, to achieve the effect of diagnosing the fault coverage of the adjacent bit positions in the memory space of the RAM.

[0076] Further, by taking the first number of bytes as a detection unit, the memory space of the RAM is written data, and the corresponding data is read out; the data obtained by writing the corresponding exclusive OR operation is written again, and the corresponding data after exclusive OR is read out again, to complete the read / write processing of the data. In the process of reading data each time, it is necessary to judge whether the data written in the memory space of the RAM and the data read are the same, if not, the RAM detection fails, and enters the system fault state. At the same time, the fault coverage of the interval 1-bit bit in the memory space of the RAM is diagnosed.

[0077] In a possible example scenario, for example, taking two bytes as an example of the first number of bytes, corresponding to sixteen bit positions; according to the second step, that is, in each byte length, the data of the interval 1-bit bit is set to different data, write 0011001100110011 into the two bytes in the RAM address from the low address to the high address in order, read the two bytes; and take the exclusive OR of 0011001100110011 to rewrite it as 1100110011001100, read the two bytes. Because the interval 1-bit bit data is different, the RAM detection fault condition of diagnosing the interval 1-bit bit can be realized.

[0078] Alternatively, for the first number of bytes with two byte lengths as a detection unit, according to the detection rule of the interval 1-bit bit, a plurality of read / write data of the memory space of the RAM can be obtained. For example, 0110011001100110 can also be written into the two bytes in the RAM address from the low address bit to the high address bit in order, and the same effect of diagnosing the RAM detection fault condition of the interval 1-bit bit can be achieved according to the same subsequent steps, while the RAM detection of the memory space of the RAM is performed, the effect of maintaining the fault coverage unchanged is maintained.

[0079] S205, in the third detection step, according to the detection principle of diagnosing the interval 2-bit bit, the first number of bytes is taken as a unit to detect the RAM of the memory space.

[0080] The detection rule of the interval 2-bit bit can be understood as setting different data of the interval 2-bit bit, that is, in each byte length, the first bit position and the fourth bit position data are different, the fourth bit position and the seventh bit position data are different, the second bit position and the fifth bit position data are different, the fifth bit position and the eighth bit position data are different, and so on, to obtain new detection data. The data of the memory space of the RAM corresponding to the adjacent two bytes can be different, but the data contained in each byte is set according to the detection principle of the interval 2-bit bit, so as to achieve the effect of diagnosing the fault coverage of the interval 2-bit bit data in the memory space of the RAM.

[0081] Further, by taking the first number of bytes as a detection unit, the memory space of the RAM is written with data, and the corresponding data is read out; the data obtained by writing the corresponding negation operation is written again, and the corresponding data after negation is read out again, to complete the read / write processing of the data. In each data reading process, it is necessary to judge whether the data written in the memory space of the RAM and the data read are the same. If not, the RAM detection fails, and the system fault state is entered. At the same time, the fault coverage of the interval 2-bit bit in the memory space of the RAM is diagnosed.

[0082] In a possible example scenario, for example, taking two bytes as an example of the first number of bytes, corresponding to sixteen bit positions; according to the third step, that is, in each byte length, the interval 2-bit data is set to different data, 1100011111000111 is written into the two bytes of the RAM address from the low address to the high address in order, and the two bytes are read; and 1100011111000111 is negated to be rewritten as 0011100000111000, and the two bytes are read. Because the interval 2-bit data is different, the RAM detection fault condition of diagnosing the interval 2-bit can be realized.

[0083] Alternatively, for the first number of bytes with two bytes as a detection unit, according to the detection rule of the interval 2-bit, a plurality of read / write data of the memory space of the RAM can be obtained. For example, 0111000100111000 can also be written into the two bytes of the RAM address from the low address bit to the high address bit in order, and the same as the following steps, the RAM detection fault condition of diagnosing the interval 2-bit can also be realized, while the memory space of the RAM is detected, the effect of keeping the fault coverage unchanged is maintained.

[0084] S206, in the fourth detection step, according to the detection rule of diagnosing the interval 3-bit, the first number of bytes is taken as a unit to detect the RAM of the memory space.

[0085] Among them, the detection rule of the interval 3-bit can be understood as setting different data of the interval 3-bit, that is, in each byte length, the first bit and the fifth bit are different, the second bit and the sixth bit are different, the third bit and the seventh bit are different, and so on, to obtain new detection data. The data of the memory space of the RAM corresponding to the adjacent two bytes can be different, but the data contained in each byte is set according to the detection principle of the interval 3-bit, so as to achieve the effect of diagnosing the fault coverage of the interval 3-bit data in the memory space of the RAM.

[0086] Further, by taking the first number of bytes as a detection unit, the memory space of the RAM is written data, and the corresponding data is read out; the data obtained by writing the corresponding exclusive OR operation is written again, and the corresponding data after exclusive OR is read out again, to complete the read / write processing of the data. In each data reading process, it is necessary to judge whether the data written in the memory space of the RAM and the data read are the same. If not, the RAM detection fails, and the system fault state is entered. At the same time, the fault coverage of the interval 3-bit bit in the memory space of the RAM is diagnosed.

[0087] In a possible example scenario, for example, taking two bytes as an example of the first number of bytes, corresponding to sixteen bits; according to the fourth step, that is, in each byte length, the interval 3-bit data is set to different data, 0000111100001111 is written into the two bytes in the RAM address from the low address to the high address in order, and the two bytes are read; and 0000111100001111 is inverted to 1111000011110000, and the two bytes are read. Because the interval 3-bit data is different, the RAM detection fault condition of diagnosing the interval 3-bit can be realized.

[0088] Alternatively, for the first number of bytes with two bytes as a detection unit, according to the detection rule of the interval 3-bit, a plurality of read / write data of the memory space of the RAM can be obtained. For example, 1001011010010110 can also be written into the two bytes in the RAM address from the low address bit to the high address bit in order, and the same as the following steps, the RAM detection fault condition of diagnosing the interval 3-bit can also be realized, while the memory space of the RAM is detected, the effect of keeping the fault coverage unchanged is maintained.

[0089] S207、In the fifth detection step, according to the reset detection rule, the memory space of the RAM is detected by taking the first number of bytes as a unit.

[0090] Among them, the reset detection rule can be understood as setting all "0" or all "1" to the data of the memory space of the RAM, and detecting the reset of the memory space of the RAM. According to the reset detection principle, the data in the memory space of the RAM is reset, the last processing step of the RAM detection is completed, and the effect of diagnosing the fault coverage of the data in the memory space of the RAM is achieved.

[0091] Further, by taking the first number of bytes as a detection unit, the memory space of the RAM is written with data, and the corresponding data is read out; the data obtained by writing the corresponding NOT operation is written again, and the corresponding data after the NOT operation is read out again, to complete the read / write processing of the data. In each data reading process, it is determined whether the data written in the memory space of the RAM is the same as the data read, if not, the RAM detection fails, and the system fault state is entered. At the same time, the fault coverage of the reset detection in the memory space of the RAM is diagnosed.

[0092] In a possible example scenario, for example, taking two bytes as an example of the first number of bytes, corresponding to sixteen bits; according to the fifth step, that is, in each byte length, the data of the memory space of the RAM is set to all "0" or all "1", 0000000011111111 is written into the two bytes in the RAM address from the low address to the high address in order, and the two bytes are read; and 0000000011111111 is inverted to rewrite 1111111100000000, and the two bytes are read. The reset processing of the RAM detection can be realized.

[0093] Alternatively, for the first number of bytes with two bytes as a detection unit, according to the reset detection rule, a plurality of read / write data of the memory space of the RAM can be obtained. For example, 0000000000000000 can also be written into the two bytes in the RAM address from the low address bit to the high address bit in order, and the same as the same step behind, the reset processing of the RAM detection is also realized, and the corresponding fault condition is diagnosed at the same time, while the RAM detection of the memory space of the RAM is performed, the fault coverage is kept unchanged.

[0094] In a possible example scenario, by taking the first number of bytes as a detection unit to perform RAM detection on the memory space of the RAM, combining the five steps, a specific example is as follows: taking four bytes as the first number of bytes, according to the fast RAM detection method provided by the application, the read / write data can be hexadecimal numbers at all times, and can also be other numbers, which is not limited here; the specific detection steps include:

[0095] The first detection step: write 0x55555555, read 0x55555555, write 0xAAAAAAAA, read 0xAAAAAAAA;

[0096] The second detection step: write 0x33333333, read 0x33333333, write 0xCCCCCCCC, read 0xCCCCCCCC;

[0097] The third detection step is: writing 0xC7C7C7C7, reading 0xC7C7C7C7, writing 0x38383838, and reading 0x38383838.

[0098] The fourth detection step is: writing 0x0F0F0F0F, reading 0x0F0F0F0F, writing 0xF0F0F0F0, and reading 0xF0F0F0F0.

[0099] The fifth detection step is: writing 0x00000000, reading 0x00000000, writing 0xFFFFFFFF, and reading 0xFFFFFFFF.

[0100] In each reading data process, it is necessary to judge whether the data written in the memory space of the RAM and the data read are the same. If not, the RAM detection fails, and the system enters a fault state.

[0101] S208, checking the RAM detection result.

[0102] Further, the RAM detection result is obtained through the set detection rule. In the above five steps, the RAM detection result is checked and judged in each step. Different RAM detection results affect the power-on result of the MCU.

[0103] S209, when the RAM detection result is successful, the memory space of the RAM is detected every preset time, and the second number of bytes is used as the unit, wherein the second number is less than the first number, and the second number is determined according to the running memory space and the length of the byte in advance.

[0104] The second number of bytes can be understood as having the same meaning as the first number of bytes, but the length of the second number of bytes is set to be less than the length of the first number of bytes. In a 16-bit running memory system, the second number of bytes can be understood as a byte length detection unit, and the memory space of the RAM is detected byte by byte. In a 32-bit running memory system, the second number of bytes can be used to detect the memory space of the RAM at a detection frequency of one byte length or two byte lengths. The preset time can be understood as a specified time, and the periodic detection of the RAM is started when the RAM detection is successful. The specified time mentioned here can be set according to the detection time of one byte, and when the RAM detection is successful, the MCU enters the main function to perform the periodic detection of the RAM.

[0105] Further, when the RAM detection result is successful, that is, when the MCU is powered on, the entire detection of the memory space of the RAM is completed through the rapid RAM detection, the MCU is successfully powered on, and can normally run. According to the set time, for example, the preset time is the time of running a single byte, in the 32-bit system running space, the data of the first byte in the memory space of the RAM is detected in each cycle, the data of the second byte in the memory space of the RAM is detected in the second cycle time, and so on, so as to complete the RAM detection of the 32-bit system running space.

[0106] S210, when the RAM detection result is failed, the MCU is powered off.

[0107] The power-off processing can be understood as the power-off protection processing of the MCU, and the power supply connection of the MCU is disconnected, so as to protect the MCU from being damaged.

[0108] Further, when the RAM detection result is failed, it indicates that after the MCU is powered on, the RAM detection finds that the read / write data of the memory space of the RAM is wrong, which leads to the failure of the RAM detection, the MCU is disconnected with the external power supply, the MCU and other devices are protected from being damaged due to the RAM detection error, the MCU is well protected, and the safety of the MCU detection is improved.

[0109] S211, when the RAM detection result is failed, the RAM detection result is displayed.

[0110] The display can be understood as displaying the RAM detection failure information on the display device through the hardware display device.

[0111] Further, when the RAM detection result is failed, the RAM detection result is displayed on the corresponding display device through the display device, and the visual RAM detection result is provided.

[0112] The rapid RAM detection method provided by the embodiment of the application comprises the following steps: when the MCU is powered on, the memory space of the RAM is detected according to a first number of bytes as a unit; through the set five detection steps, the RAM detection is completed while the fault coverage rate is kept unchanged, and the corresponding RAM detection result is obtained; when the RAM detection result is successful, the MCU power-on RAM detection is completed; the RAM is periodically detected according to a second number of bytes as a unit in each preset time period; when the RAM detection result is failed, the MCU is powered off to protect the MCU from being damaged, and the display device is used to display the RAM detection result, so as to realize the rapid EAM detection, shorten the detection time, and keep the fault coverage rate unchanged.

[0113] Figure 3The flowchart of another fast RAM detection method provided by the embodiment of the present application is shown in the figure. The figure is introduced on the basis of the second embodiment. According to the figure, the fast RAM detection specifically comprises the following steps. Figure 3 The figure shows that the fast RAM detection specifically comprises the following steps.

[0114] S301, when the MCU is powered on, performing RAM detection on the memory space of the RAM in a first number of bytes, to obtain a RAM detection result, the first number being determined in advance according to the running memory space and the length of the byte.

[0115] The first number of bytes can be understood as fast detection of the RAM in a multi-byte length. The multi-byte length can be understood as detection of the memory space of the RAM in a two-byte length, a four-byte length or an eight-byte length. The size of the first number of bytes is determined by the running memory of the system in which the MCU is located. In a 16-bit running memory system, the first number of bytes can be understood as detection of the memory space of the RAM in a two-byte length. In a 32-bit running memory system, the first number of bytes can be understood as detection of the memory space of the RAM in a two-byte length or a four-byte length. Similarly, in a 64-bit running memory system, the first number of bytes can be understood as detection of the memory space of the RAM in a two-byte length, a four-byte length or an eight-byte length.

[0116] In a possible implementation scenario, the first number of bytes is four bytes, and the memory space of the RAM is detected in a four-byte detection frequency. One byte is eight bits. For a 32-bit running memory, 32 bits are equivalent to four bytes. When the MCU is powered on, the address of the 32-bit RAM memory space is detected, and each detection needs to read / write a four-byte RAM address unit. After one detection, the entire memory space of the RAM can be detected. Similarly, for example, for a 64-bit running memory system, i.e. an eight-byte running memory, if each detection needs to read / write a four-byte RAM address unit, then two detections are needed to complete the entire detection of the memory space of the RAM, so as to shorten the detection time and achieve the effect of fast RAM detection.

[0117] S302, verifying the RAM detection result.

[0118] Further, the RAM detection result is obtained through a set detection rule. The RAM detection result is verified and judged in each of the above five steps. Different RAM detection results affect the power-on result of the MCU.

[0119] S303, when the RAM detection result is successful, every preset time, the memory space of the RAM is detected in a second number of bytes, wherein the second number is less than the first number, and the second number is determined in advance according to the running memory space and the length of the byte.

[0120] Further, when the RAM detection result is successful, that is, when the MCU is powered on, the complete detection of the memory space of the RAM is completed through the rapid RAM detection, and the MCU is successfully powered on and can run normally. According to the set time, for example, the preset time is the time of running a single byte, in the 32-bit system running space, the data of the first byte in the memory space of the RAM is detected in each cycle, the data of the second byte in the memory space of the RAM is detected in the second cycle time, and so on, to complete the RAM detection of the 32-bit system running space.

[0121] S304, the memory space of the RAM is detected through the five detection steps set in advance.

[0122] Among them, the memory space of the RAM is detected by taking the second number of bytes as the detection unit. The second number of bytes here can also be understood as one byte, two bytes or four bytes, which is determined according to the system running space.

[0123] Further, in each RAM detection with the second number of bytes as the unit, the read / write operation of the data in the memory space of the RAM is realized by setting five detection steps. In the process of reading data, as long as the read data and the written data are not the same, it means that the RAM detection fails, and the system fault state is entered.

[0124] S305, in the first detection step, the memory space of the RAM is detected in the second number of bytes according to the detection rule of diagnosing adjacent bit positions.

[0125] Among them, the detection rule of adjacent bit positions can be understood as setting different data for adjacent two bit positions, that is, in each byte length, the data of the first bit position and the second bit position is different, the data of the second bit position and the third bit position is different, the data of the third bit position and the fourth bit position is different, the data of the fourth bit position and the fifth bit position is different, and so on, to obtain new detection data. The data of the memory space of the RAM corresponding to the adjacent two bytes can be different, but the data contained in each byte is set according to the detection principle of adjacent bit positions, so as to achieve the effect of diagnosing the fault coverage rate of the adjacent bit data in the memory space of the RAM.

[0126] Further, according to the detection rule of the interval 1-bit bit, the second quantity of bytes is taken as a detection unit to write data in the memory space of the RAM, and corresponding data is read out; then the data obtained by the corresponding NOT operation is written again, and the corresponding data after the NOT operation is read out again, to complete the read / write processing of the data. In each reading data process, it is determined whether the written data and the read data in the memory space of the RAM are the same, if not, the RAM detection fails, and the system fault state is entered. At the same time, the fault coverage of the interval 1-bit bit in the memory space of the RAM is diagnosed.

[0127] In a possible example scenario, for example, taking the second quantity of bytes as one byte length, corresponding to eight bit positions; according to the first step, that is, in each byte length, the data of the adjacent bit positions is set to be different data, 01010101 is written in a byte in the RAM address from the low address to the high address in sequence, and the two bytes are read; and 01010101 is inverted to be rewritten as 10101010, and the two bytes are read. Because the data of the adjacent two bit positions is different, the RAM detection fault condition of the adjacent bit positions can be diagnosed.

[0128] Alternatively, for the second quantity of bytes taken as a detection unit of one byte length, 10101010 can also be written in a byte in the RAM address from the low address bit to the high address bit in sequence, and the corresponding steps are the same, and the RAM detection fault condition of the adjacent bit positions can also be diagnosed, while the RAM detection of the memory space of the RAM is performed, the effect of keeping the fault coverage unchanged is maintained.

[0129] S306, in the second detection step, according to the detection rule of the interval 1-bit bit, the second quantity of bytes is taken as a unit to perform RAM detection on the memory space of the RAM.

[0130] Further, according to the detection rule of the interval 1-bit bit, the second quantity of bytes is taken as a detection unit to write data in the memory space of the RAM, and corresponding data is read out; then the data obtained by the corresponding NOT operation is written again, and the corresponding data after the NOT operation is read out again, to complete the read / write processing of the data. In each reading data process, it is determined whether the written data and the read data in the memory space of the RAM are the same, if not, the RAM detection fails, and the system fault state is entered. At the same time, the fault coverage of the interval 1-bit bit in the memory space of the RAM is diagnosed.

[0131] In a possible example scenario, for example, taking the second number of bytes as one byte length, corresponding to eight bits; according to the second step, that is, in each byte length, the data with interval 1 bit is set as different data, 00110011 is written in two bytes of the RAM address from the low address to the high address in sequence, the two bytes are read; and 00110011 is inverted to be rewritten as 11001100, the two bytes are read. Because the interval 1 bit data is different, the RAM detection fault condition of diagnosing the interval 1 bit can be realized.

[0132] Alternatively, for the second number of bytes with one byte length as a detection unit, according to the detection rule of the interval 1 bit, the read / write data of the memory space of a variety of RAMs can be obtained. For example, 01100110 can also be written in one byte of the RAM address from the low address bit to the high address bit in sequence, and the same as the same step behind, the RAM detection fault condition of diagnosing the interval 1 bit can also be realized, while the RAM detection of the memory space of the RAM is performed, the effect of maintaining the fault coverage rate is unchanged.

[0133] S307, in the third detection step, according to the detection rule of diagnosing the interval 2 bits, the memory space of the RAM is detected with the second number of bytes as a unit.

[0134] Further, according to the detection rule of the interval 2 bits described above, the data of the memory space of the RAM is written with the second number of bytes as a detection unit, and the corresponding data is read out; the data obtained by the corresponding inverse operation is written again, and the corresponding data after the inverse operation is read out again, to complete the read / write processing of the data. In each reading data process, whether the written data and the read data in the memory space of the RAM are the same is judged, if not, the RAM detection fails, and the system fault state is entered. At the same time, the fault coverage rate of the interval 2 bits in the memory space of the RAM is diagnosed.

[0135] In a possible example scenario, for example, taking the second number of bytes as one byte length, corresponding to eight bits; according to the third step, that is, in each byte length, the data with interval 2 bits is set as different data, 11000111 is written in one byte of the RAM address from the low address to the high address in sequence, the two bytes are read; and 11000111 is inverted to be rewritten as 00111000, the two bytes are read. Because the interval 2 bit data is different, the RAM detection fault condition of diagnosing the interval 2 bit can be realized.

[0136] Optionally, for the second number of bytes as a detection unit of one byte length, according to the detection rule of interval 3-bit bit, the read / write data of the memory space of various RAMs can be obtained. For example, 10010110 can also be written into one byte in the RAM address from the low address bit to the high address bit of the RAM in sequence, and the same effect of implementing the diagnosis of interval 3-bit bit RAM detection failure can be achieved, and the effect of maintaining the fault coverage unchanged while performing the RAM detection on the memory space of the RAM is maintained.

[0137] In the fourth detection step S308, according to the detection rule of diagnosing interval 3-bit bit, the memory space of the RAM is detected in units of the second number of bytes.

[0138] Further, according to the detection rule of interval 3-bit bit described above, the data is written in the memory space of the RAM in units of the second number of bytes, and the corresponding data is read out; the data obtained by performing the inverse operation is written again, and the corresponding data after the inverse operation is read out again, so as to complete the read / write processing of the data. In each reading data process, it is judged whether the written data and the read data in the memory space of the RAM are the same. If not, the RAM detection fails, and the system fault state is entered. At the same time, the fault coverage of interval 3-bit bit in the memory space of the RAM is diagnosed.

[0139] In a possible example scenario, for example, taking the second number of bytes as one byte length as an example, corresponding to eight-bit bits; according to the fourth step, that is, in each byte length, the interval 3-bit bit data is set to be different data, 00001111 is written into one byte in the RAM address from the low address to the high address of the RAM in sequence, and this one byte is read; and 00001111 is inverted to 11110000, and this one byte is read. Because the interval 3-bit bit data is different, the diagnosis of interval 3-bit bit RAM detection failure can be achieved.

[0140] Optionally, for the second number of bytes as a detection unit of one byte length, according to the detection rule of interval 3-bit bit, the read / write data of the memory space of various RAMs can be obtained. For example, 10010110 can also be written into one byte in the RAM address from the low address bit to the high address bit of the RAM in sequence, and the same effect of implementing the diagnosis of interval 3-bit bit RAM detection failure can be achieved, and the effect of maintaining the fault coverage unchanged while performing the RAM detection on the memory space of the RAM is maintained.

[0141] In the fifth detection step S309, according to the reset detection rule, the memory space of the RAM is detected in units of the second number of bytes.

[0142] Further, according to the reset detection rule described above, the memory space of the RAM is written with data and corresponding data is read out as a detection unit of the second number of bytes; the data obtained by writing the corresponding NOT operation is written again, and the corresponding data after the NOT operation is read out again to complete the read / write processing of the data. In the process of reading the data each time, it is judged whether the data written in the memory space of the RAM is the same as the data read, if not, the RAM detection fails, and enters the system fault state. At the same time, the fault coverage of the reset detection in the memory space of the RAM is diagnosed.

[0143] In a possible example scenario, for example, taking the second number of bytes as an example of one byte length, corresponding to eight bits; according to the fifth step, that is, in each byte length, the data of the memory space of the RAM is set to all "0" or all "1", 00000000 is written in a byte of the RAM address from the low address to the high address in order, and this byte is read; and 00000000 is inverted to rewrite 11111111, and this byte is read. The reset processing of the RAM detection can be realized.

[0144] Alternatively, for the second number of bytes as a detection unit of one byte length, according to the reset detection rule, two kinds of read / write data of the memory space of the RAM can be obtained. For example, 11111111 can also be written in a byte of the RAM address from the low address bit to the high address bit in order, and the same as the same step behind, the reset processing of the RAM detection is also realized, and the corresponding fault condition is diagnosed at the same time, and the effect of maintaining the fault coverage unchanged while the RAM detection of the memory space of the RAM is maintained.

[0145] In a possible example scenario, combining the five steps, the memory space of the RAM is detected by the second number of bytes as a detection unit, and a specific example is as follows: the second number of bytes is set to one byte, according to the fast RAM detection method provided by the application, and taking binary numbers as an example, the specific detection steps include:

[0146] The first detection step: write 01010101, read 01010101, write 10101010, read 10101010;

[0147] The second detection step: write 00110011, read 00110011, write 11001100, read 11001100;

[0148] The third detection step: write 11000111, read 11000111, write 00111000, read 00111000;

[0149] Fourth detection step: write 00001111, read 00001111, write 11110000, read 11110000;

[0150] Fifth detection step: write 00000000, read 00000000, write 11111111, read 11111111.

[0151] In each reading process, it is judged whether the data written in the memory space of the RAM and the data read are the same, and if not, the RAM detection fails and enters a system fault state.

[0152] For diagnosing fault conditions, the following examples are provided to illustrate the rapid RAM detection method provided by the embodiments of the application, which has the effect of maintaining the fault coverage of the RAM detection unchanged while improving the RAM detection time and maintaining a high fault coverage.

[0153] For example: 13 indicates the fault order of the first and third bits in the current byte from high to low order: 12345678

[0154] ↓↓↓↓↓↓↓↓

[0155] First step: write 01010101

[0156] The faults between adjacent bits can be diagnosed;

[0157] The faults between 13, 15, 17, 35, 37, 57, 24, 26, 28, 46, 48, 68 cannot be diagnosed;

[0158] Second step: write 00110011

[0159] The faults between 13, 17, 35, 57, 24, 28, 46, 68 which are 1-bit apart can be diagnosed;

[0160] The faults between 15, 37, 26, 48 cannot be diagnosed;

[0161] Third step: write 11000111

[0162] The faults between 15, 37, 48 which are 2-bit apart can be diagnosed;

[0163] The fault between 26 cannot be diagnosed;

[0164] Fourth step: write 00001111

[0165] The fault between 26 which is 3-bit apart can be diagnosed;

[0166] Fifth step: write 00000000

[0167] The reset processing is completed, and the RAM detection is performed.

[0168] According to the five detection steps, the fast RAM detection is completed while maintaining a high fault coverage.

[0169] S310, when the RAM detection result is failure, the MCU is powered off.

[0170] Further, when the RAM detection result is failure, it indicates that the RAM memory space read / write data is incorrect after the MCU is powered on, resulting in RAM detection failure. The MCU will disconnect the connection with the external power supply to protect the MCU and other devices from damage, which effectively protects the MCU and improves the safety of MCU detection.

[0171] S311, control the MCU to stop sending feeding signals to the hardware watchdog to make the hardware watchdog disconnect the MCU and the external power supply.

[0172] The hardware watchdog can be understood as a monitoring device outside the MCU, which is used to monitor the working state of the MCU. The feeding signal can be understood as a power supply request sent by the MCU to the hardware watchdog periodically, and the corresponding response signal is fed back to the MCU by the hardware watchdog to ensure the normal power supply of the MCU. When the RAM detection fails, that is, the MCU fails to power on, the MCU stops sending feeding signals to the hardware watchdog, the hardware watchdog detects that the MCU processing is abnormal, and then disconnects the MCU and the external power supply to perform power-off processing, thereby protecting the MCU and other devices from damage.

[0173] S312, when the RAM detection result is failure, the RAM detection result is displayed.

[0174] Here, display can be understood as displaying the RAM detection failure information on the display device through the hardware display device.

[0175] Further, when the RAM detection result is failure, the RAM detection result is displayed on the corresponding display device through the display device to provide a clear RAM detection result.

[0176] The embodiment of the application provides a fast RAM detection method, when the MCU is powered on, a first number of bytes are set as a detection unit to perform fast detection on the memory space of the RAM, and a RAM detection result is obtained accordingly; when the RAM detection result is successful, the main function of the MCU is entered to perform periodical detection on the RAM; a second number of bytes are set as a detection unit to perform periodical detection on the memory space of the RAM by the same detection rule, without affecting the running of other functions in the main function, and the effect of fast RAM detection is achieved again; when the RAM detection result is failed, the RAM detection result is displayed through an external display device, and meanwhile the MCU stops feeding signals to the hardware watchdog, so that the power supply is cut off, the device is protected from being damaged, fast RAM detection is achieved, the detection time is shortened, and the technical effect of maintaining fault coverage is achieved.

[0177] Figure 4 A structural diagram of a fast RAM detection system provided by the embodiment of the application is shown in the figure. Figure 4 As shown in the figure, the structure of the fast RAM detection system comprises a RAM detection module 41 and an MCU 42.

[0178] The RAM detection module 41 is configured to perform RAM detection on the memory space of the RAM in a unit of a first number of bytes when the MCU 42 is powered on, and obtain a RAM detection result; and determine the power-on result corresponding to the MCU 42 based on the RAM detection result.

[0179] The RAM detection module 41 is further configured to perform RAM detection on the memory space of the RAM in a unit of a second number of bytes every preset time when the RAM detection result is successful.

[0180] The structure of the system further comprises a hardware watchdog 43 and a power module 44.

[0181] The power module 44 is configured to supply power for the MCU 42.

[0182] The hardware watchdog 43 is configured to disconnect the MCU 42 and the power module 44 when the MCU 42 stops sending feeding signals to the hardware watchdog 43.

[0183] The structure of the system further comprises a display module 45.

[0184] The display module 45 is configured to display the RAM detection result when the RAM detection result is failed.

[0185] The RAM detection module 41 is connected to the first input end of the MCU 42; the second input end of the MCU 42 is connected to the first output end of the hardware watchdog 43, the first output end is connected to the input end of the hardware watchdog 43, the second output end is connected to the display module 45; the second output end of the hardware watchdog 43 is connected to the power module 44.

[0186] In a possible application scenario, when the MCU is powered on, the program executes the power-on RAM detection module, and performs read-write operation on the whole memory space of the RAM, if the RAM detection succeeds, the periodic detection of the RAM is performed in the main function of the MCU. If the RAM detection fails, the display module will report the RAM detection failure, and the MCU cannot feed the hardware watchdog in time, and the power supply is cut off; during the whole process, no other hardware devices are damaged. Further, the fast RAM detection is realized, the detection time is shortened, and the high fault coverage is maintained.

[0187] The fast RAM detection system provided by the embodiment of the application comprises a RAM detection module, an MCU, a hardware watchdog, a power module and a display module, when the MCU is powered on, the fast RAM detection is started, and the corresponding RAM detection result is obtained; when the RAM detection result is successful, the periodic detection of the RAM is performed in the main function of the MCU; when the RAM detection result is failed, the connection of the power module is cut off by the hardware watchdog, and the failed detection information is displayed on the display module, thereby avoiding the damage of the device, realizing the fast RAM detection, shortening the detection time, and maintaining the high fault coverage.

[0188] Figure 5 A structural schematic diagram of a detection device is provided for the embodiment of the application, Figure 5 The detection device 500 shown in the figure comprises at least one processor 501, a memory 502, at least one network interface 504 and other user interfaces 503. Various components in the detection device 500 are coupled together through a bus system 505. It can be understood that the bus system 505 is used to realize the connection communication between the components. In addition to the data bus, the bus system 505 also comprises a power supply bus, a control bus and a state signal bus. However, for the purpose of clear illustration, all kinds of buses are marked as the bus system 505 in the figure. Figure 5

[0189] The user interface 503 can comprise a display, a keyboard or a clicking device (for example, a mouse, a trackball, a touchpad or a touch screen, etc.).

[0190] ​It is to be appreciated that the memory 502 in the embodiments of the present application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a Random Access Memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synch link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 502 described herein is intended to include, without being limited to, these and any other suitable types of memory.

[0191] In some embodiments, the memory 502 stores the following elements, executable units or data structures, or a subset of them, or an extended set of them: an operating system 5021 and an application program 5022.

[0192] Among them, the operating system 5021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application program 5022 includes various application programs, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The program for implementing the method embodiments of the present application can be included in the application program 5022.

[0193] In the embodiments of the present application, by calling the programs or instructions stored in the memory 502, specifically, the programs or instructions stored in the application program 5022, the processor 501 is used to execute the method steps provided by each method embodiment, for example, including:

[0194] When the MCU is powered on, the memory space of the RAM is detected in a first number of bytes, to obtain a RAM detection result, the first number being determined in advance according to the running memory space and the length of the byte; and based on the RAM detection result, a power-on result corresponding to the MCU is determined.

[0195] The method disclosed by the embodiments of the present application can be applied to the processor 501 or implemented by the processor 501. The processor 501 can be an integrated circuit chip having a signal processing capability. In the implementation process, the steps of the above method can be completed by the integrated logic circuits or the instructions in the software form of the hardware in the processor 501. The processor 501 described above can be a general processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware decoding processor for execution, or executed by a combination of hardware and software units in the decoding processor. The software unit can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register or other mature storage media in the art. The storage medium is located in the memory 502, and the processor 501 reads the information in the memory 502, and combines the hardware to complete the steps of the above method.

[0196] It can be understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described in the present application, or a combination thereof.

[0197] For software implementation, the techniques described herein can be implemented by means of a unit for performing the functions described herein. The software codes can be stored in a memory and executed by a processor. The memory can be implemented in or outside the processor.

[0198] The detection device provided by the embodiment can be the detection device shown in Figure 5 , and can perform all steps of the fast RAM detection method shown in Figures 1-3 , thereby achieving the technical effects of the fast RAM detection method shown in Figures 1-3 . For brevity, details are not described here. Figures 1-3

[0199] The embodiment of the application further provides a storage medium (computer readable storage medium). The storage medium stores one or more programs. The storage medium can include a volatile memory such as a random access memory, and the memory can also include a non-volatile memory such as a read-only memory, a flash memory, a hard disk or a solid state disk, and the memory can also include a combination of the above kinds of memories.

[0200] When the one or more programs in the storage medium can be executed by one or more processors to implement the fast RAM detection method executed on the detection device side.

[0201] The processor is configured to execute the fast RAM detection program stored in the memory to implement the following steps of the fast RAM detection method executed on the detection device side:

[0202] When the MCU is powered on, the memory space of the RAM is detected in units of a first number of bytes to obtain a RAM detection result, and the first number is determined in advance according to the running memory space and the length of the byte; based on the RAM detection result, a power-on result corresponding to the MCU is determined.

[0203] Those skilled in the art should further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0204] ​The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and

[0205] The above detailed description describes the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for detecting a fast RAM, characterized by, The application relates to a method for detecting a memory space of a RAM (Random Access Memory) of a micro control unit (MCU) and a device thereof. When the MCU is powered on, the memory space of the RAM is detected in a first number of bytes to obtain a RAM detection result, wherein the first number is determined according to the running memory space and the length of a byte in advance; Based on the RAM detection result, a power-on result corresponding to the MCU is determined; The RAM detection of the memory space of the RAM in the first number of bytes comprises: The memory space of the RAM is detected through five detection steps set in advance; the five detection steps are as follows: In the first detection step, the memory space of the RAM is detected in the first number of bytes according to a detection rule for diagnosing adjacent bit positions; In the second detection step, the memory space of the RAM is detected in the first number of bytes according to a detection rule for diagnosing bit positions with an interval of 1 bit; In the third detection step, the memory space of the RAM is detected in the first number of bytes according to a detection rule for diagnosing bit positions with an interval of 2 bits; In the fourth detection step, the memory space of the RAM is detected in the first number of bytes according to a detection rule for diagnosing bit positions with an interval of 3 bits; In the fifth detection step, the memory space of the RAM is detected in the first number of bytes according to a reset detection rule; The RAM detection result is checked; When the RAM detection result is successful, the memory space of the RAM is detected in a second number of bytes every preset time, wherein the second number is smaller than the first number, and the second number is determined according to the running memory space and the length of a byte in advance; When the RAM detection result is unsuccessful, the MCU is powered off; And When the RAM detection result is unsuccessful, the RAM detection result is displayed.

2. The method of claim 1, wherein, The RAM detection of the memory space of the RAM in the second number of bytes comprises: The memory space of the RAM is detected through five detection steps set in advance; the five detection steps are as follows: In the first detection step, the memory space of the RAM is detected in the second number of bytes according to a detection rule for diagnosing adjacent bit positions; In the second detection step, the memory space of the RAM is detected in the second number of bytes according to a detection rule for diagnosing bit positions with an interval of 1 bit; In the third detection step, the memory space of the RAM is detected in the second number of bytes according to a detection rule for diagnosing bit positions with an interval of 2 bits; In the fourth detection step, the memory space of the RAM is detected in the second number of bytes according to a detection rule for diagnosing bit positions with an interval of 3 bits; In the fifth detection step, the memory space of the RAM is detected in the second number of bytes according to a reset detection rule.

3. The method of claim 1, wherein, The power-off processing on the MCU comprises: controlling the MCU to stop sending feeding signals to the hardware watchdog, so that the hardware watchdog disconnects the MCU from the external power supply.

4. A fast RAM detection system using a fast RAM detection method, characterized by, comprise: a RAM detection module and an MCU; the RAM detection module is configured to, when the MCU is powered on, perform RAM detection on the memory space of the RAM in units of a first number of bytes to obtain a RAM detection result, the first number being determined in advance according to the length of the running memory space and a byte, and determine a power-on result corresponding to the MCU based on the RAM detection result; the RAM detection module is further configured to verify the RAM detection result; when the RAM detection result is successful, performing RAM detection on the memory space of the RAM in units of a second number of bytes every preset time, the second number being smaller than the first number, and the second number being determined in advance according to the length of the running memory space and a byte; when the RAM detection result is unsuccessful, performing power-off processing on the MCU; and when the RAM detection result is unsuccessful, displaying the RAM detection result. The RAM detection module is specifically configured to perform RAM detection on the memory space of the RAM through five detection steps set in advance, and the five detection steps are specifically as follows: in a first detection step, performing RAM detection on the memory space of the RAM in units of the first number of bytes according to a detection rule of diagnosing adjacent bit positions; in a second detection step, performing RAM detection on the memory space of the RAM in units of the first number of bytes according to a detection rule of diagnosing bit positions with an interval of 1; in a third detection step, performing RAM detection on the memory space of the RAM in units of the first number of bytes according to a detection rule of diagnosing bit positions with an interval of 2; in a fourth detection step, performing RAM detection on the memory space of the RAM in units of the first number of bytes according to a detection rule of diagnosing bit positions with an interval of 3; in a fifth detection step, performing RAM detection on the memory space of the RAM in units of the first number of bytes according to a reset detection rule.

5. The system of claim 4, wherein, The system further comprises a hardware watchdog and a power supply module; the power supply module is configured to supply power to the MCU; the hardware watchdog is configured to disconnect the MCU from the power supply module when the MCU stops sending feeding signals to the hardware watchdog.

6. The system of claim 4, wherein, The system further comprises a display module; the display module is configured to display the RAM detection result when the RAM detection result is unsuccessful.

7. A computer device, comprising: comprise: a processor and a memory, the processor being configured to execute a fast RAM detection program stored in the memory to implement the fast RAM detection method in any one of claims 1-3.

8. A storage medium, characterized by The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the fast RAM detection method in any one of claims 1-3.

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