Method for manufacturing semiconductor structure and semiconductor structure

Abstract

The present application provides a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate, the substrate including a substrate, a stacked structure, and a dielectric layer stacked in sequence, the substrate also including multiple channel structures, the channel structures being located in the stacked structure and extending into the dielectric layer; removing a portion of the dielectric layer to form a groove in the dielectric layer, the groove exposing a portion of the corresponding channel structure, at least one sidewall of the groove having a stepped structure, the stepped structure including at least one step. The method forms a stepped structure on at least one sidewall of the groove, the stepped structure including at least one step, and the energy of the photoresist flowing into the groove varies with the steps, with the lower the step, the less energy the photoresist flows into the groove. Therefore, the ripples generated near the groove are reduced, thereby alleviating discoloration, thereby solving the problem in the prior art of excessive ripples generated near the alignment mark groove, which causes discoloration during spin coating of the photoresist.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure, a semiconductor structure, a three-dimensional memory, and a storage system. Background Art

[0002] The manufacturing of semiconductor devices, such as three-dimensional memory, goes through a series of process flows, such as etching and photolithography. The traditional manufacturing process includes 300 to 400 steps, each of which affects the final morphology of each device on the semiconductor chip, that is, affects the characteristic dimensions of the device, and thus affects the various electrical properties of the device.

[0003] Due to the complexity of 3D memory structures, overlay (OVL) alignment operations between structures are essential in the 3D memory manufacturing process, such as gate line slit (GLS) alignment and alignment of the lower channel hole (LCH) and upper channel hole (UCH).

[0004] However, in the prior art, a relatively large groove is formed during the process of forming the alignment mark, which has an adverse effect on the critical dimension (CD) of the development in the subsequent GLS process.

[0005] Therefore, there is an urgent need for a method for reducing the generation of ripples near the grooves during subsequent spin coating of the photoresist.

[0006] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain some information that does not form the prior art known in this country to those skilled in the art. Summary of the Invention

[0007] The main purpose of the present application is to provide a method for manufacturing a semiconductor structure, a semiconductor structure, a three-dimensional memory and a storage system to solve the problem in the prior art that a large number of ripples are generated near the groove of the alignment mark, resulting in discoloration when spin-coating the photoresist.

[0008] To achieve the above-mentioned objectives, according to one aspect of the present application, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate, the substrate comprising a substrate, a stacked structure, and a dielectric layer stacked in sequence, the substrate further comprising a plurality of channel structures, the channel structures being located in the stacked structure and extending into the dielectric layer; removing a portion of the dielectric layer to form a groove in the dielectric layer, the groove exposing a corresponding portion of the channel structure, at least one sidewall of the groove having a step structure, the step structure comprising at least one step.

[0009] Furthermore, removing part of the dielectric layer to form a groove in the dielectric layer includes: removing part of the dielectric layer to form a first preliminary groove in the dielectric layer so that part of the channel structure is exposed; and removing part of the dielectric layer from at least one sidewall of the first preliminary groove to form the groove.

[0010] Furthermore, removing part of the dielectric layer to form a groove in the dielectric layer includes: removing part of the dielectric layer to form a second preliminary groove in the dielectric layer; removing part of the dielectric layer at the bottom wall of the second preliminary groove to form the groove, so that part of the channel structure is exposed.

[0011] Furthermore, after removing part of the dielectric layer and forming a groove in the dielectric layer, the method further includes: forming a hard mask layer on the exposed surface of the dielectric layer in the groove and on both sides of the groove, wherein the hard mask layer covers the channel structure in the groove; and forming a photoresist layer on the exposed surface of the hard mask layer.

[0012] Furthermore, a hard mask layer is formed in the groove and on the exposed surface of the dielectric layer on both sides of the groove, including: forming an oxide layer in the groove and on the exposed surface of the dielectric layer on both sides of the groove, the oxide layer covering the channel structure in the groove; forming a carbon layer on the exposed surface of the oxide layer; forming a silicon oxynitride layer on the exposed surface of the carbon layer, the oxide layer, the carbon layer and the silicon oxynitride layer forming the hard mask layer.

[0013] Furthermore, forming a photoresist layer on the exposed surface of the hard mask layer includes: spin coating photoresist on the exposed surface of the hard mask layer to form the photoresist layer.

[0014] Furthermore, the depth of the groove ranges from 50 to 350 nm.

[0015] Furthermore, the width of the first preliminary groove is in the range of 30 to 35 μm.

[0016] Furthermore, the dielectric layer includes at least one of the following: silicon oxide, silicon oxynitride and silicon oxycarbide.

[0017] Furthermore, the material of the channel structure includes polysilicon.

[0018] According to another aspect of the present application, a semiconductor structure is provided, comprising a substrate, a stacked structure, a dielectric layer, and a channel structure, wherein the stacked structure covers the surface of the substrate; the dielectric layer is located on a surface of the stacked structure away from the substrate, the dielectric layer includes a groove, at least one sidewall of the groove has a step structure, and the step structure includes at least one step; the channel structure includes a plurality of channel structures, the channel structures are located in the stacked structure and extend into the dielectric layer, and some of the channel structures extend into the groove.

[0019] Furthermore, the depth of the groove ranges from 50 to 350 nm.

[0020] Furthermore, the dielectric layer includes at least one of the following: silicon oxide, silicon oxynitride and silicon oxycarbide.

[0021] Furthermore, the material of the channel structure includes polysilicon.

[0022] According to another aspect of the present application, a three-dimensional memory is provided, comprising a semiconductor structure obtained by using any of the methods described or any of the semiconductor structures described.

[0023] According to another aspect of the present application, a storage system is provided, including a storage controller and the three-dimensional memory, wherein the three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0024] Applying the technical solution of the present application, in the method for manufacturing the semiconductor structure, first, a base is provided, the base comprising a substrate, a stacked structure, and a dielectric layer stacked in sequence, the base further comprising a plurality of channel structures, the channel structures being located in the stacked structure and extending into the dielectric layer; a portion of the dielectric layer is removed to form a groove in the dielectric layer, the groove exposing a corresponding portion of the channel structure, at least one sidewall of the groove having a step structure, the step structure comprising at least one step. In the subsequent process, as the thickness of the formed epitaxial layer increases, the groove will gradually become shallower and affect the mark. Therefore, the groove needs to have a certain depth. However, the deeper the groove is, the greater the energy of the photoresist flowing into the groove during the subsequent spin coating of the photoresist, and the more ripples are generated near the groove. This method forms a step structure on at least one side wall of the groove, and the step structure includes at least one step. The energy of the photoresist flowing into the groove at different steps is different. The lower the step, the less energy the photoresist flowing into the groove. Therefore, the ripples generated near the groove are reduced, thereby alleviating the discoloration phenomenon, thereby solving the problem in the prior art that more ripples are generated near the groove of the alignment mark, resulting in discoloration when the photoresist is spin coated. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0026] Figure 1 A schematic structural diagram of a substrate according to a typical embodiment of the present application is shown;

[0027] Figure 2 A schematic diagram of the structure after forming a first preliminary groove according to an embodiment of the present application is shown;

[0028] Figure 3 A schematic diagram of the structure after forming the second preliminary groove according to an embodiment of the present application is shown;

[0029] Figure 4 A schematic structural diagram of a semiconductor structure according to a typical embodiment of the present application is shown;

[0030] Figure 5 A schematic diagram of the structure after forming a photoresist according to an embodiment of the present application is shown;

[0031] Figure 6 A schematic diagram of a three-dimensional structure of a semiconductor structure according to an embodiment of the present application is shown;

[0032] Figure 7 A schematic top view of a three-dimensional structure of a semiconductor structure according to an embodiment of the present application is shown.

[0033] The above drawings include the following reference numerals:

[0034] 10. Substrate; 20. Stacked structure; 30. Dielectric layer; 40. Channel structure; 50. Recess; 51. First preliminary recess; 52. Second preliminary recess; 60. Hard mask layer; 70. Photoresist layer. DETAILED DESCRIPTION

[0035] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0036] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0037] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element or intervening elements may be present. Moreover, in the specification and claims, when it is described that an element is "connected to" another element, the element may be "directly connected to" the other element or "connected to" the other element through a third element.

[0038] As introduced in the background technology, in the prior art, many ripples are generated near the grooves of the alignment mark, resulting in discoloration when spin-coating the photoresist. In order to solve the above problem, the present application proposes a method for manufacturing a semiconductor structure, a semiconductor structure, a three-dimensional memory and a storage system.

[0039] In a typical embodiment of the present application, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate, such as Figure 1 As shown, the substrate includes a substrate 10, a stacking structure 20 and a dielectric layer 30 stacked in sequence, and the substrate further includes a plurality of channel structures 40, the channel structures 40 are located in the stacking structure 20 and extend into the dielectric layer 30; Figure 4 As shown, a portion of the dielectric layer 30 is removed to form a groove 50 in the dielectric layer 30 . The groove 50 exposes a portion of the corresponding channel structure 40 . At least one sidewall of the groove 50 has a step structure, and the step structure includes at least one step.

[0040] In the method for manufacturing the semiconductor structure, a substrate is first provided, the substrate comprising a substrate, a stacked structure, and a dielectric layer stacked in sequence, the substrate further comprising a plurality of channel structures, the channel structures being located within the stacked structure and extending into the dielectric layer; a portion of the dielectric layer is removed to form a groove in the dielectric layer, the groove exposing a portion of the corresponding channel structure, at least one sidewall of the groove having a stepped structure, the stepped structure comprising at least one step. In subsequent processes, as the thickness of the formed epitaxial layer increases, the groove gradually becomes shallower, affecting the marking, so the groove requires a certain depth. However, the deeper the groove, the greater the energy of the photoresist flowing into the groove during subsequent spin coating of the photoresist, resulting in more ripples near the groove. The method forms a stepped structure on at least one sidewall of the groove, the stepped structure comprising at least one step, and the energy of the photoresist flowing into the groove varies with the steps, with the lower the step, the less energy the photoresist flows into the groove. Thus, the ripples near the groove are reduced, thereby alleviating the discoloration phenomenon, thereby solving the problem of the prior art in which more ripples are generated near the groove of the alignment mark, resulting in discoloration during spin coating of the photoresist.

[0041] Specifically, in the prior art, alignment marks are typically formed by etching a recessed mark on the substrate. After forming the upper channel hole, a gate line slit topological transfer (GLSTT) process is used to directly align the recess and the channel structure therein, thereby improving alignment accuracy. When forming the alignment mark, a portion of the dielectric layer is removed, forming a relatively large recess. Part of the channel structure is exposed within the recess. Due to the required height of the channel structure and the limitations of chemical mechanical polishing (CMP) on the dielectric layer etching process, the recess has a relatively large depth. During the subsequent GLS formation process, spin-coating the photoresist can produce ripples near the deep recess, resulting in discoloration, which adversely affects the critical dimension (CD) of the subsequent GLS development process. The shallower the groove, the less obvious the ripples generated near the groove. Shallowing the groove depth can solve the ripple problem. However, due to the complexity of the three-dimensional memory structure, the alignment and photolithography alignment marks will gradually become blurred as the dielectric layer formed on the substrate becomes thicker, posing an accuracy problem. Therefore, there are certain requirements for the groove depth.

[0042] In practical applications, the more side walls of the groove forming the step structure, the less ripples are generated near the groove. The step structure includes at least one step. If the number of steps is too large, the process is relatively complicated. In a specific embodiment of the present application, Figure 6 As shown in the schematic diagram of the three-dimensional structure of the semiconductor structure, the groove 50 partially exposes the channel structure 40 , and the four sidewalls of the groove 50 all have a step structure, and the step structure includes one step. Figure 7 for Figure 6 Top view of the structure shown.

[0043] Specifically, the substrate material is silicon, which can be either single crystal silicon or polycrystalline silicon. The stacked structure comprises an insulating dielectric layer and a sacrificial layer alternately arranged in sequence. The insulating dielectric layer includes, but is not limited to, silicon dioxide, and the sacrificial layer includes, but is not limited to, silicon nitride. The sacrificial layer and the insulating dielectric layer can be alternately deposited in sequence using methods such as chemical vapor deposition and atomic layer deposition. The number of stacked layers can be 8, 32, 64, etc. The greater the number of stacked layers, the higher the degree of integration.

[0044] In one embodiment of the present application, removing part of the dielectric layer to form a groove in the dielectric layer includes: Figure 2 As shown, a portion of the dielectric layer 30 is removed, and a first preliminary groove 51 is formed in the dielectric layer 30, so that a portion of the channel structure 40 is exposed; Figure 4 As shown, a portion of the dielectric layer 30 is removed from at least one sidewall of the first preliminary groove 51 to form the groove 50. The method of first removing a portion of the dielectric layer to form a first preliminary groove, and then removing a portion of at least one sidewall of the first preliminary groove to form a stepped structure, is simple and easy to operate. After removing a portion of the dielectric layer, the channel structure within the first preliminary groove protrudes from the first preliminary groove. The exposed portion of the channel structure can serve as a photolithography alignment mark, eliminating the need to use a zero mask to form the photolithography alignment mark on the substrate. This simplifies the process, saves masks, reduces device manufacturing costs, and avoids the problem of inaccurate alignment caused by the gradual blurring of the photolithography alignment mark as the dielectric layer formed on the substrate thickens.

[0045] Specifically, a portion of the above-mentioned dielectric layer is removed to form a first preliminary groove in the above-mentioned dielectric layer. Dry etching can be used, and a chemical mechanical polishing combined with dry etching method can be used to remove a portion of the above-mentioned dielectric layer from at least one sidewall of the above-mentioned first preliminary groove to form the above-mentioned groove. Dry etching can be used. The depth of the above-mentioned first preliminary groove is 90 to 110 nm.

[0046] In another specific embodiment of the present application, a step enables the groove to form two sub-grooves of different widths. The number of steps can be increased according to actual conditions. When the depth of the first preliminary groove is deeper, the number of steps can be appropriately increased so that the depth of each sub-groove is between 40 and 60 nm. When the depth of the sub-grooves is relatively consistent, that is, the height of the sub-steps is consistent, the energy subsequently flowing into the groove can be evenly distributed by multiple steps, thereby reducing the ripples generated near the groove and alleviating the discoloration phenomenon.

[0047] In another embodiment of the present application, after removing part of the dielectric layer, a groove is formed in the dielectric layer, including: Figure 3 As shown, a portion of the dielectric layer 30 is removed to form a second preliminary groove 52 in the dielectric layer 30; Figure 4 As shown, a portion of the dielectric layer 30 at the bottom wall of the second preliminary groove 52 is removed to form the groove 50 , so that a portion of the channel structure 40 is exposed.

[0048] In order to facilitate alignment measurement of the gate gap and the channel structure in subsequent processes, in another embodiment of the present application, after a portion of the dielectric layer is removed and a groove is formed in the dielectric layer, the method further includes: Figure 4 and Figure 5 As shown, a hard mask layer 60 is formed in the groove 50 and on the exposed surface of the dielectric layer 30 on both sides of the groove 50, and the hard mask layer 60 covers the channel structure 40 in the groove 50; a photoresist layer 70 is formed on the exposed surface of the hard mask layer 60.

[0049] In another embodiment of the present application, a hard mask layer is formed on the exposed surface of the dielectric layer in the groove and on both sides of the groove, comprising: forming an oxide layer on the exposed surface of the dielectric layer in the groove and on both sides of the groove, the oxide layer covering the channel structure in the groove; forming a carbon layer on the exposed surface of the oxide layer; and forming a silicon oxynitride layer on the exposed surface of the carbon layer, wherein the oxide layer, the carbon layer, and the silicon oxynitride layer form the hard mask layer. The hard mask layer formed by the oxide layer, the carbon layer, and the silicon oxynitride layer has good etch resistance and good planarization properties. The silicon oxynitride layer, also known as a dielectric anti-reflection layer, can reduce reflection of light from a wide range of light sources on its surface, thereby reducing deformation or dimensional deviation of the photoresist pattern.

[0050] In practical applications, the oxide layer, the carbon layer, and the silicon oxynitride layer may be formed by chemical vapor deposition.

[0051] In order to form a flat and uniform photoresist layer, in another embodiment of the present application, forming the photoresist layer on the exposed surface of the hard mask layer includes: spin coating photoresist on the exposed surface of the hard mask layer to form the photoresist layer.

[0052] In practical applications, after forming a photoresist layer, a gate slit opening pattern is formed on the photoresist layer. Specifically, after the gate slit opening pattern in the mask is positioned and aligned with the photoresist layer, the gate slit opening pattern is formed on the photoresist layer through exposure and development processes.

[0053] In another embodiment of the present application, the depth of the groove ranges from 50 to 350 nm. The deeper the groove, the greater the energy of the photoresist flowing into the groove during subsequent spin coating of the photoresist, resulting in more ripples near the groove. If the groove is too shallow, the groove gradually becomes shallower as the epitaxial layer formed in the subsequent process thickens, affecting the mark.

[0054] In order to obtain an alignment mark in a suitable range and make subsequent alignment more accurate, in another embodiment of the present application, the width of the first preliminary groove is in the range of 30 to 35 μm.

[0055] In another embodiment of the present application, the dielectric layer comprises at least one of the following: silicon oxide, silicon oxynitride, and silicon oxycarbide. The silicon oxide, silicon oxynitride, and silicon oxycarbide serve as a protective layer to protect the stacked structure from damage.

[0056] In another embodiment of the present application, the material of the channel structure includes polysilicon. Polysilicon has a high hardness and can prevent the overall structure from collapsing when the sacrificial layer of the stacked structure is removed in a subsequent process.

[0057] Specifically, the method for forming the channel structure includes: forming a plurality of channel holes in the stacked structure; forming a charge trapping layer on the inner wall of the channel hole; and forming a polysilicon channel layer in the channel hole.

[0058] In another typical embodiment of the present application, a semiconductor structure is provided, such as Figure 4 As shown, it includes a substrate 10, a stacking structure 20, a dielectric layer 30 and a channel structure 40, wherein the stacking structure 20 covers the surface of the substrate 10; the dielectric layer 30 is located on the surface of the stacking structure 20 away from the substrate 10, the dielectric layer 30 includes a groove 50, at least one sidewall of the groove 50 has a step structure, and the step structure includes at least one step; the channel structure 40 includes a plurality of channel structures arranged along a first direction, the first direction is a direction perpendicular to the thickness of the substrate 10, the channel structure is located in the stacking structure 20 and extends into the dielectric layer 30, and part of the channel structure 40 extends into the groove 50.

[0059] The semiconductor structure comprises a substrate, a stacked structure, a dielectric layer, and a channel structure, wherein the stacked structure covers the surface of the substrate; the dielectric layer is located on a surface of the stacked structure away from the substrate; the dielectric layer comprises a groove, at least one sidewall of the groove has a step structure, and the step structure comprises at least one step; the channel structure comprises a plurality of channel structures arranged along a first direction, the first direction being a direction perpendicular to the thickness of the substrate; the channel structure is located in the stacked structure and extends into the dielectric layer, and a portion of the channel structure extends into the groove. In the subsequent process, as the thickness of the formed epitaxial layer increases, the groove will gradually become shallower and affect the mark. Therefore, the groove needs a certain depth. However, the deeper the groove is, the greater the energy of the photoresist flowing into the groove during the subsequent spin coating of the photoresist, and the more ripples are generated near the groove. At least one side wall of the above-mentioned groove in this structure is a step structure, and the above-mentioned step structure includes at least one step. The energy of the photoresist flowing into the groove at different steps is different. The lower the step, the less energy the photoresist flowing into the groove. Therefore, the ripples generated near the groove are reduced, thereby alleviating the discoloration phenomenon, thereby solving the problem in the prior art that more ripples are generated near the groove of the alignment mark, resulting in discoloration when the photoresist is spin-coated.

[0060] In practical applications, the more side walls of the groove forming the step structure, the less ripples are generated near the groove. The step structure includes at least one step. If the number of steps is too large, the process is relatively complicated. In a specific embodiment of the present application, Figure 6 As shown in the schematic diagram of the three-dimensional structure of the semiconductor structure, the groove 50 partially exposes the channel structure 40 , and the four sidewalls of the groove 50 all have a step structure, and the step structure includes one step. Figure 7 for Figure 6 Top view of the structure shown.

[0061] Specifically, the substrate material is silicon, which can be either single crystal silicon or polycrystalline silicon. The stacked structure comprises an insulating dielectric layer and a sacrificial layer alternately arranged in sequence. The insulating dielectric layer includes, but is not limited to, silicon dioxide, and the sacrificial layer includes, but is not limited to, silicon nitride. The sacrificial layer and the insulating dielectric layer can be alternately deposited in sequence using methods such as chemical vapor deposition and atomic layer deposition. The number of stacked layers can be 8, 32, 64, etc. The greater the number of stacked layers, the higher the degree of integration.

[0062] In another embodiment of the present application, the depth of the groove ranges from 50 to 350 nm. The deeper the groove, the greater the energy of the photoresist flowing into the groove during subsequent spin coating of the photoresist, resulting in more ripples near the groove. If the groove is too shallow, the groove gradually becomes shallower as the epitaxial layer formed in the subsequent process thickens, affecting the mark.

[0063] In another embodiment of the present application, the dielectric layer includes at least one of the following: silicon oxide, silicon oxynitride, and silicon oxycarbide. The silicon oxide, silicon oxynitride, and silicon oxycarbide serve as a protective layer to protect the stacked structure from damage.

[0064] In another embodiment of the present application, the material of the channel structure includes polysilicon. Polysilicon has a high hardness and can prevent the overall structure from collapsing when the sacrificial layer of the stacked structure is removed in a subsequent process.

[0065] Specifically, the method for forming the channel structure includes: forming a plurality of channel holes in the stacked structure; forming a charge trapping layer on the inner wall of the channel hole; and forming a polysilicon channel layer in the channel hole.

[0066] In another typical embodiment of the present application, a three-dimensional memory is provided, comprising a semiconductor structure obtained by any of the above methods or any of the above semiconductor structures.

[0067] In another typical embodiment of the present application, a storage system is provided, including a storage controller and the above-mentioned three-dimensional memory, wherein the above-mentioned three-dimensional memory is configured to store data, and the above-mentioned storage controller is coupled to the above-mentioned three-dimensional memory and configured to control the above-mentioned three-dimensional memory.

[0068] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the technical solution of the present application will be described in detail below with reference to specific embodiments and comparative examples.

[0069] Example

[0070] The method for manufacturing the semiconductor structure in this embodiment includes the following steps:

[0071] Provide a substrate, such as Figure 1 As shown, the substrate includes a substrate 10, a stacking structure 20 and a dielectric layer 30 stacked in sequence, and the substrate further includes a plurality of channel structures 40. The channel structures 40 are located in the stacking structure 20 and extend into the dielectric layer 30.

[0072] Specifically, the substrate material is silicon, which can be either single crystal silicon or polycrystalline silicon. The stacked structure comprises an insulating dielectric layer and a sacrificial layer alternately arranged in sequence. The insulating dielectric layer includes but is not limited to silicon dioxide, and the sacrificial layer includes but is not limited to silicon nitride. Chemical vapor deposition, atomic layer deposition, and other methods can be used to alternately deposit the sacrificial layer and the insulating dielectric layer. The number of stacked layers can be 8, 32, 64, etc. The more layers stacked, the higher the integration density. The dielectric layer includes at least one of the following: silicon oxide, silicon oxynitride, and silicon oxycarbide, to protect the stacked structure from damage.

[0073] like Figure 2 As shown, a portion of the dielectric layer 30 is removed, and a first preliminary groove 51 is formed in the dielectric layer 30 so that a portion of the channel structure 40 is exposed;

[0074] like Figure 4 As shown, a portion of the dielectric layer 30 on at least one sidewall of the first preliminary groove 51 is removed to form the groove 50;

[0075] like Figure 4 and Figure 5 As shown, a hard mask layer 60 is formed in the groove 50 and on the exposed surface of the dielectric layer 30 on both sides of the groove 50, specifically comprising: forming an oxide layer on the exposed surface of the structure after the groove is formed; forming a carbon layer on the exposed surface of the oxide layer; forming a silicon oxynitride layer on the exposed surface of the carbon layer, wherein the oxide layer, the carbon layer and the silicon oxynitride layer form the hard mask layer;

[0076] like Figure 5 As shown, a photoresist layer 70 is formed on the exposed surface of the hard mask layer 60 .

[0077] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0078] 1) In the method for manufacturing the semiconductor structure of the present application, first, a base is provided, the base comprising a substrate, a stacked structure, and a dielectric layer stacked in sequence, the base further comprising a plurality of channel structures, the channel structures being located in the stacked structure and extending into the dielectric layer; a portion of the dielectric layer is removed to form a groove in the dielectric layer, the groove exposing a portion of the corresponding channel structure, at least one sidewall of the groove having a step structure, and the step structure comprising at least one step. In the subsequent process, as the thickness of the formed epitaxial layer increases, the groove will gradually become shallower and affect the mark. Therefore, the groove needs to have a certain depth. However, the deeper the groove is, the greater the energy of the photoresist flowing into the groove during the subsequent spin coating of the photoresist, and the more ripples are generated near the groove. This method forms a step structure on at least one side wall of the above-mentioned groove. The above-mentioned step structure includes at least one step. The energy of the photoresist flowing into the groove at different steps is different. The lower the step, the less energy the photoresist flowing into the groove. Therefore, the ripples generated near the groove are reduced, thereby alleviating the discoloration phenomenon, thereby solving the problem in the prior art that more ripples are generated near the groove of the alignment mark, resulting in discoloration when the photoresist is spin-coated.

[0079] 2) The semiconductor structure of the present application includes a substrate, a stacked structure, a dielectric layer and a channel structure, wherein the stacked structure covers the surface of the substrate; the dielectric layer is located on the surface of the stacked structure away from the substrate, the dielectric layer includes a groove, at least one sidewall of the groove has a step structure, and the step structure includes at least one step; the channel structure includes a plurality of channel structures arranged along a first direction, the first direction being a direction perpendicular to the thickness of the substrate, the channel structure is located in the stacked structure and extends into the dielectric layer, and part of the channel structure extends into the groove. In the subsequent process, as the thickness of the formed epitaxial layer increases, the groove will gradually become shallower and affect the mark. Therefore, the groove needs a certain depth. However, the deeper the groove is, the greater the energy of the photoresist flowing into the groove during the subsequent spin coating of the photoresist, and the more ripples are generated near the groove. At least one side wall of the above-mentioned groove in this structure is a step structure, and the above-mentioned step structure includes at least one step. The energy of the photoresist flowing into the groove at different steps is different. The lower the step, the less energy the photoresist flowing into the groove. Therefore, the ripples generated near the groove are reduced, thereby alleviating the discoloration phenomenon, thereby solving the problem in the prior art that more ripples are generated near the groove of the alignment mark, resulting in discoloration when the photoresist is spin-coated.

[0080] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate, a stacking structure, and a dielectric layer stacked in sequence, the substrate further comprising a plurality of channel structures, the channel structures being located in the stacking structure and extending into the dielectric layer; A portion of the dielectric layer is removed to form a groove in the dielectric layer, wherein the groove exposes a portion of the corresponding channel structure, and the exposed portion of the channel structure serves as a photolithography alignment mark. At least one sidewall of the groove has a step structure, and the step structure includes at least one step, so that the energy of the photoresist flowing into the groove varies at different steps, and the lower the step, the less energy the photoresist flowing into the groove. The stacked structure is an insulating dielectric layer and a sacrificial layer arranged in sequence, the insulating dielectric layer includes at least silicon dioxide, the sacrificial layer includes at least silicon nitride, and the channel structure includes multiple channel structures arranged along a first direction, which is a direction perpendicular to the thickness of the substrate.

2. The method according to claim 1, characterized in that Removing a portion of the dielectric layer to form a groove in the dielectric layer includes: removing a portion of the dielectric layer to form a first preliminary groove in the dielectric layer so that a portion of the channel structure is exposed; A portion of the dielectric layer on at least one sidewall of the first preliminary groove is removed to form the groove.

3. The method according to claim 1, characterized in that Removing a portion of the dielectric layer to form a groove in the dielectric layer includes: removing a portion of the dielectric layer to form a second preliminary groove in the dielectric layer; A portion of the dielectric layer on the bottom wall of the second preliminary groove is removed to form the groove, so that a portion of the channel structure is exposed.

4. The method according to claim 1, wherein After removing a portion of the dielectric layer and forming a groove in the dielectric layer, the method further includes: forming a hard mask layer in the groove and on the exposed surface of the dielectric layer on both sides of the groove, wherein the hard mask layer covers the channel structure in the groove; A photoresist layer is formed on the exposed surface of the hard mask layer.

5. The method according to claim 4, characterized in that Forming a hard mask layer in the groove and on the exposed surface of the dielectric layer on both sides of the groove, comprising: forming an oxide layer in the groove and on the exposed surface of the dielectric layer on both sides of the groove, wherein the oxide layer covers the channel structure in the groove; forming a carbon layer on the exposed surface of the oxide layer; A silicon oxynitride layer is formed on the exposed surface of the carbon layer, and the oxide layer, the carbon layer, and the silicon oxynitride layer form the hard mask layer.

6. The method according to claim 4, characterized in that forming a photoresist layer on the exposed surface of the hard mask layer, comprising: The photoresist is spin-coated on the exposed surface of the hard mask layer to form the photoresist layer.

7. The method according to claim 1, characterized in that The depth of the groove ranges from 50 to 350 nm.

8. The method according to claim 2, characterized in that The width of the first preliminary groove is in the range of 30-35 μm.

9. The method according to claim 1, characterized in that The dielectric layer includes at least one of the following: silicon oxide, silicon oxynitride, and silicon oxycarbide.

10. The method according to claim 1, characterized in that The material of the channel structure includes polysilicon.

11. A semiconductor structure, characterized in that include: substrate; a stacked structure covering the surface of the substrate; a dielectric layer located on a surface of the stacked structure away from the substrate, the dielectric layer comprising a groove, at least one sidewall of the groove having a step structure, the step structure comprising at least one step; Multiple channel structures, the channel structures are located in the stacked structure and extend into the dielectric layer, some of the channel structures extend into the groove, and some of the channel structures serve as photolithography alignment marks, the stacked structure is an insulating dielectric layer and a sacrificial layer arranged in sequence, the insulating dielectric layer includes at least silicon dioxide, and the sacrificial layer includes at least silicon nitride, and the channel structure includes multiple channel structures arranged along a first direction, and the first direction is a direction perpendicular to the thickness of the substrate.

12. The structure according to claim 11, characterized in that The depth of the groove ranges from 50 to 350 nm.

13. The structure according to claim 11, characterized in that The dielectric layer includes at least one of the following: silicon oxide, silicon oxynitride, and silicon oxycarbide.

14. The structure according to claim 11, characterized in that The material of the channel structure includes polysilicon.

15. A three-dimensional memory, characterized in that: The method comprises a semiconductor structure obtained by the method according to any one of claims 1 to 10 or a semiconductor structure according to any one of claims 11 to 14.

16. A storage system, characterized in that: The invention comprises a memory controller and the three-dimensional memory of claim 15 , wherein the three-dimensional memory is configured to store data, and the memory controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

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