Wafer level packaging method and wafer level packaging structure

Abstract

The present invention provides a wafer-level packaging method and a wafer-level packaging structure. The wafer-level packaging method comprises the following steps: forming at least one circle of edge sealing layer on a bonding surface of a device wafer or a bonding surface of a protective layer in an area corresponding to an invalid area at an edge of the device wafer; forming a support layer on a bonding surface of the device wafer or a bonding surface of the protective layer in an area corresponding to a peripheral area surrounding a chip functional area in the device wafer; bonding the device wafer to the protective layer by using the support layer and the edge sealing layer, the support layer and the protective layer forming a cavity for accommodating the device; achieving the effect of anti-leakage, protecting the front side of the device area in the device wafer from contamination, and improving the yield.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a wafer-level packaging method and a wafer-level packaging structure. background

[0002] With the continuous development of semiconductor packaging technology, wafer-level packaging has become the mainstream trend in the packaging industry due to its advantages such as good repeatability and short packaging cycle. After wafer-level packaging stacks the wafer and the protective layer / wafer, there will be a certain gap between them. In subsequent operations, especially wet processes and etching processes, due to capillary effects, the existence of these gaps will cause contamination inside the wafer, resulting in yield loss.

[0003] Existing methods to solve the above problems include: 1) using non-capillary bottom filling (NCF) to fill the gap between wafers during bonding; 2) hybrid bonding, etc. However, these methods have the disadvantages of being expensive and having a long process flow. In addition, they are not applicable to semiconductor devices that require a cavity on the front of the chip.

[0004] In view of this, it is necessary to provide a new wafer-level packaging method and a wafer-level packaging structure to solve the above problems. Summary of the invention

[0005] The object of the present invention is to provide a wafer-level packaging method and a wafer-level packaging structure.

[0006] To achieve the above-mentioned purpose, the present invention adopts the following technical solution: a wafer-level packaging method, comprising the following steps:

[0007] Forming at least one edge sealing layer on the bonding surface of the device wafer and / or the bonding surface of the protective layer in an area corresponding to the ineffective area at the edge of the device wafer;

[0008] Forming a support layer on a bonding surface of the device wafer and / or a bonding surface of the protective layer in an area corresponding to a peripheral area surrounding a chip functional area in the device wafer;

[0009] The device wafer is bonded to the protective layer by using a support layer and an edge sealing layer, and the support layer and the protective layer form a cavity for accommodating the device.

[0010] As a further improved technical solution of the present invention, each circle of the edge sealing layer is formed by a plurality of connected circular rings.

[0011] As a further improved technical solution of the present invention, the thickness of the circular ring is T, and along the radial direction of the device wafer, the length of the connection between two adjacent circular rings is greater than 2T.

[0012] As a further improved technical solution of the present invention, the thickness T of the ring is not less than 1 μm.

[0013] As a further improved technical solution of the present invention, the height of the edge sealing layer is not less than the height of the supporting layer.

[0014] As a further improved technical solution of the present invention, the edge sealing layer and the support layer are formed by dispensing or photolithography process.

[0015] As a further improved technical solution of the present invention, while forming the edge sealing layer and the support layer, the wafer-level packaging method also includes: forming reinforcing ribs in an area corresponding to a cutting area in the device wafer on a bonding surface of the device wafer or a bonding surface of the protective layer.

[0016] As a further improved technical solution of the present invention, the protective layer is a cap wafer arranged on the front side of the device wafer.

[0017] As a further improved technical solution of the present invention, there is no chip functional area on the cap wafer; the device in the chip functional area of ​​the device wafer is a filter, or the device in the chip functional area of ​​the device wafer is a Hall device and an alloy containing at least one element of iron, cobalt, and nickel located above the Hall device.

[0018] As a further improved technical solution of the present invention, the cap wafer has a chip functional area; the device in the chip functional area of ​​the device wafer is a Hall device, and the chip functional area on the cap wafer corresponding to the Hall device is provided with an alloy containing at least one element of iron, cobalt and nickel.

[0019] As a further improved technical solution of the present invention, the protective layer is a supporting wafer arranged on the back side of the device wafer.

[0020] As a further improved technical solution of the present invention, the edge sealing layer and the support layer are both bonding adhesives.

[0021] As a further improved technical solution of the present invention, the peripheral area of ​​the device wafer has a bonding pad, and the bonding pad is exposed on a side of the support layer away from the chip functional area.

[0022] To achieve the above-mentioned object of the invention, the present invention further provides a wafer-level packaging structure, comprising:

[0023] A device wafer, wherein the device wafer comprises a device region and an ineffective region located at the edge of the device region, wherein the device region comprises a plurality of chip functional regions and a peripheral region surrounding the chip functional regions;

[0024] A protective layer, disposed on the front side of the device wafer or located on the front side of the device wafer and the back side of the device wafer;

[0025] A support layer, the support layer is located in the peripheral area and connected between the device wafer and the protective layer, the support layer and the protective layer forming a cavity for accommodating the device;

[0026] At least one circle of edge sealing layer, the at least one circle of edge sealing layer is located in the ineffective area, and the edge sealing layer is connected between the device wafer and the protective layer.

[0027] As a further improved technical solution of the present invention, the edge sealing layer is formed by a plurality of connected circular rings.

[0028] As a further improved technical solution of the present invention, the thickness T of the circular ring is not less than 1 μm, and along the radial direction of the device wafer, the length of the connection between two adjacent circular rings is greater than 2T.

[0029] As a further improved technical solution of the present invention, the protective layer is a cap wafer arranged on the front side of the device wafer.

[0030] As a further improved technical solution of the present invention, there is no chip functional area on the cap wafer; the device in the chip functional area of ​​the device wafer is a filter, or the device in the chip functional area of ​​the device wafer is a Hall device and an alloy containing at least one element of iron, cobalt, and nickel located above the Hall device.

[0031] As a further improved technical solution of the present invention, the cap wafer has a chip functional area; the device in the chip functional area of ​​the device wafer is a Hall device, and the chip functional area on the cap wafer corresponding to the Hall device is provided with an alloy containing at least one element of iron, cobalt and nickel.

[0032] As a further improved technical solution of the present invention, the peripheral area of ​​the device wafer has a bonding pad, and the bonding pad is exposed on a side of the support layer away from the chip functional area.

[0033] The beneficial effects of the present invention are as follows: in the wafer-level packaging method of the present invention, by forming an edge sealing layer to seal the gap between the protective layer and the invalid area at the edge of the device wafer while bonding the device wafer to the protective layer, the effect of preventing leakage is achieved, and the front of the device area in the device wafer can be protected from contamination, thereby improving the yield rate; at the same time, a space can be left on the bonding surface of the device wafer, which can avoid glue overflow around the wafer after extrusion, and there is no need to fill glue after bonding, thereby reducing process costs. In addition, a cavity for accommodating a device can be formed, which can form a product structure that protects the device in the chip functional area on the front of the device wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1Schematic diagram of the structure of a cap wafer in a specific implementation manner (wafer-level packaging method in the first implementation manner of the present invention);

[0035] Figure 2 is a schematic structural diagram of a cap wafer in another specific implementation manner (a wafer-level packaging method in the first implementation manner of the present invention);

[0036] Figure 3(a) to Figure 3(e) FIG. 3( a) is a schematic diagram of the structure corresponding to each step in the wafer-level packaging method in the first embodiment of the present invention, wherein FIG. 3( a) is Figure 1 Sectional view along AA direction;

[0037] Figure 4(a) to Figure 4(e) It is a schematic structural diagram corresponding to each step in the wafer-level packaging method in the second embodiment of the present invention.

[0038] Figure 5(a) to Figure 5(e) It is a schematic structural diagram corresponding to each step in the wafer-level packaging method in the third embodiment of the present invention.

[0039] Figure 6 is a schematic structural diagram of a cap wafer in a wafer-level packaging method in a fourth embodiment of the present invention;

[0040] Figure 7(a) to Figure 7(e) FIG. 7( a) is a schematic diagram of the structure corresponding to each step in the wafer-level packaging method in the fourth embodiment of the present invention, wherein FIG. 7( a) is Figure 6 Cross-sectional view along the BB axis. DETAILED DESCRIPTION

[0041] The present invention will be described in detail below in conjunction with the various embodiments shown in the accompanying drawings. Figure 1 - As shown in FIG7 , a preferred embodiment of the present invention is shown. However, it should be noted that these embodiments are not limitations of the present invention, and any equivalent transformation or replacement of functions, methods, or structures made by ordinary technicians in the field according to these embodiments shall fall within the protection scope of the present invention.

[0042] Meanwhile, the drawings are all in a very simplified form and in an inaccurate proportion, and are only used to conveniently and clearly assist in explaining the various embodiments of the present invention.

[0043] It should be noted that the wafer-level packaging method described in this article includes a series of steps, and the order of these steps presented in this article is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted, or some other steps not described in this article may be added to the wafer-level packaging method.

[0044] Please refer to Figure 3(a) to Figure 3(e)FIG. 1 is a schematic diagram of the structure corresponding to each step in the wafer-level packaging method in the first embodiment of the present invention. The wafer-level packaging method comprises the following steps:

[0045] Combined with Figure 3(a), Figure 3(b) and Figure 1 As shown, at least one circle of edge sealing layer 3 is formed on the bonding surface of the device wafer 1 and / or the bonding surface of the protective layer in an area corresponding to the ineffective area 11 at the edge of the device wafer 1;

[0046] Forming a support layer 4 on the bonding surface of the device wafer 1 and / or the bonding surface of the protective layer in an area corresponding to the peripheral area 122 surrounding the chip functional area 121 in the device wafer 1;

[0047] As shown in FIG. 3( c ), the device wafer 1 is bonded to the protective layer by using a support layer 4 and an edge sealing layer 3 , and the support layer 4 and the protective layer form a cavity 5 for accommodating the device.

[0048] In the wafer-level packaging method of the present invention, a sealing layer 3 can be formed to seal the gap between the protective layer and the invalid area 11 at the edge of the device wafer 1 while bonding the device wafer 1 to the protective layer, thereby achieving the effect of preventing leakage, protecting the front of the device area in the device wafer 1 from contamination, and improving the yield rate; at the same time, a space can be left on the bonding surface of the device wafer 1, which can avoid glue overflow around the wafer after extrusion, and there is no need to fill glue after bonding, thereby reducing process costs. In addition, a cavity 5 for accommodating a device can be formed, which can form a product structure for protecting the device in the chip functional area 121 on the front of the device wafer 1.

[0049] Specifically, as shown in FIG3( b ), the device wafer 1 has a device area and an ineffective area 11 located at the edge of the device area. The device area has a plurality of chip functional areas 121 and a peripheral area 122 surrounding the chip functional areas 121. The device in the chip functional area 121 may be a filter, such as a MEMS filter.

[0050] In this embodiment, the surface of the device wafer 1 in the peripheral area 122 has a pad 13, and the pad 13 is exposed on the side of the support layer 4 away from the chip functional area 121. In the present invention, by forming an edge sealing layer 3 to seal the gap between the protective layer and the invalid area 11 at the edge of the device wafer 1, the effect of preventing leakage is achieved, and the pad 13 in the device wafer 1 can be protected from contamination, thereby improving the yield.

[0051] Furthermore, the device wafer 1 also has a cutting area 123, and the cutting area 123 is the area of ​​the cutting path.

[0052] Specifically, the substrate of the device wafer 1 can be selected from third generation semiconductor materials such as gallium nitride (GaN), silicon carbide (SiC), zinc oxide (ZnO), diamond, etc. Of course, it is not limited to this.

[0053] Furthermore, in this embodiment, the protective layer is a cap wafer 2 disposed on the front of the device wafer 1. Of course, this is not limiting, the protective layer may also be a non-wafer material protective cover disposed on the front of the device wafer 1, and its base material may be a ceramic substrate such as alumina, a quartz substrate or a glass substrate, etc.; or the protective layer may also include a supporting wafer disposed on the back of the device wafer 1. It is known that when the protective layer includes the cap wafer 2 and the supporting wafer, it is equivalent to stacking three wafers.

[0054] The following briefly describes the specific packaging method between the device wafer 1 and the cap wafer 2, taking the protective layer as the cap wafer 2 disposed on the front of the device wafer 1 as an example. It can be seen that the packaging method between the device wafer 1 and the cap wafer 2 is also applicable to the packaging method between the device wafer 1 and the support wafer.

[0055] The cap wafer 2 and the support wafer can be made of any suitable substrate known to those skilled in the art, such as at least one of the following materials: lithium tantalate (LiTaO3), lithium niobate (LiNbO3), silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP).

[0056] In a specific implementation, the cap wafer 2 is a common silicon wafer to reduce costs.

[0057] refer to Figure 1As shown in FIG. 3( a ), in this embodiment, in order to process the cap wafer 2, the edge sealing layer 3 and the support layer 4 are formed on the bonding surface of the cap wafer 2, and the edge sealing layer 3 and the support layer 4 are formed at the same time, which simplifies the process flow of the wafer-level packaging method and facilitates the subsequent downward movement of the cap wafer 2 to achieve the bonding between the cap wafer 2 and the device wafer 1. That is, the edge sealing layer 3 is formed on the bonding surface of the cap wafer 2 in the area corresponding to the invalid area 11 at the edge of the device wafer 1, and at the same time, the support layer 4 is formed on the bonding surface of the cap wafer 2 in the area corresponding to the peripheral area 122 surrounding the chip functional area 121 in the device wafer 1. Of course, this is not limited to this. In other embodiments, the edge sealing layer 3 and the support layer 4 can also be formed on the bonding surface of the device wafer 1, or one of them is formed on the cap wafer 2 and the other is formed on the device wafer 1.

[0058] For the sake of convenience of explanation, the area on the bonding surface of the cap wafer 2 corresponding to the invalid area 11 at the edge of the device wafer 1 is defined as the first area 21, the area on the bonding surface of the cap wafer 2 corresponding to the peripheral area 122 surrounding the chip functional area 121 in the device wafer 1 is defined as the second area 22, the area on the bonding surface of the cap wafer 2 corresponding to the cutting area in the device wafer 1 is defined as the third area 23, and the area on the bonding surface of the cap wafer 2 corresponding to the chip functional area 121 in the device wafer 1 is defined as the fourth area 24.

[0059] In a specific embodiment, the method for processing the cap wafer 2 is: using bonding glue in the first area 21 and the second area 22 to respectively form the edge sealing layer 3 and the support layer 4 through a wiring dispensing process.

[0060] In another specific embodiment, the method for processing the cap wafer 2 is: forming the edge sealing layer 3 and the support layer 4 on the bonding surface of the cap wafer 2 by a photolithography process. Specifically, a bonding adhesive layer is first formed on the bonding surface of the cap wafer 2 by means of glue coating or film printing, and then a photoresist is spin-coated on the bonding adhesive layer to form a photoresist layer, and then the photoresist layer is sequentially exposed and developed according to the pattern to be formed, and after development, the bonding adhesive layer in the third area 23, the fourth area 24, and the area corresponding to the pad 13 in the second area 22 is removed by an etching process, and finally the photoresist layer is washed off to form the required pattern, that is, the edge sealing layer 3 and the support layer 4 are formed.

[0061] In this embodiment, the cap wafer 2 is only used to protect the device wafer 1 . Therefore, the processing of the cap wafer 2 is only to form the edge sealing layer 3 and the support layer 4 on the bonding surface of the cap wafer 2 .

[0062] Furthermore, combined with Figure 1 As shown, the edge sealing layer 3 is formed by a plurality of connected circular rings 31. It can provide sufficient support force for the device wafer 1 and the cap wafer 2, thereby preventing the device wafer 1 and the cap wafer 2 from being broken or damaged due to uneven force in the subsequent thinning process, thereby improving the yield of the product.

[0063] Furthermore, the thickness of the circular ring 31 is T, and along the radial direction of the device wafer 1, the length of the connection between two adjacent circular rings 31 is greater than 2T, thereby increasing the leakage path and improving the anti-leakage effect.

[0064] Please refer to Figure 1 As shown, in a specific embodiment, two adjacent rings 31 are approximately tangent to each other, that is, the two rings 31 overlap at the edge. At this time, the length L of the overlapping portion of the two rings 31 is greater than 2T.

[0065] Please refer to Figure 2 As shown, in another specific embodiment, two adjacent circular rings 31 intersect each other. At this time, the length of the connection between the two adjacent circular rings 31 must be greater than 2T, which increases the leakage path and thus improves the anti-leakage effect.

[0066] Specifically, the thickness T of the ring 31 is not less than 1 μm, which is conducive to forming the edge sealing layer 3 by a dispensing process or a photolithography process.

[0067] It should be noted that, in this document, the circular ring 31 is not limited to a circular ring 31 with uniform thickness, as long as the thickness T of the narrowest part of the circular ring 31 is not less than 1 μm.

[0068] Of course, this is not limited to the above. It can be understood that in other embodiments, the edge sealing layer can also be set as a circular ring structure located in the invalid area 11 and surrounding the device area 12, and further, the inner circle and outer circle of the circular ring structure can be set to a wavy shape to enhance its supporting effect.

[0069] For further information, see Figure 1 As shown in FIG3(a), in this embodiment, the first region 21 of the cap wafer 2 has only one circle of the edge sealing layer 3. Of course, this is not limiting, and in other embodiments, multiple circles of the edge sealing layer 3 may be provided on the first region 21. When there are multiple circles of the edge sealing layer 3, the multiple circles of the edge sealing layer 3 are arranged in sequence in concentric circles along the radial direction of the device wafer 1, so as to further improve the anti-leakage effect and improve the product yield.

[0070] Furthermore, the height of the edge sealing layer 3 after molding is not less than the height of the support layer 4. After hot pressing bonding, the bonding effect between the upper and lower ends of the edge sealing layer 3 and the cap wafer 2 and the device wafer 1 can be ensured, the anti-leakage effect of the edge sealing layer 3 is improved, and the yield of the product is improved.

[0071] For further information, see Figure 3(d) to Figure 3(e) As shown, after the device wafer 1 is bonded to the protective layer, the wafer-level packaging method further includes the following steps:

[0072] Thinning the device wafer 1 and / or the cap wafer 2 to form a wafer-level packaging structure 10;

[0073] The wafer-level packaging structure 10 is cut along the cutting area 123 to form a single chip unit 20 .

[0074] Furthermore, as shown in Figure 3(d), the present invention also provides a wafer-level packaging structure 10 corresponding to the wafer-level packaging method in the first embodiment, wherein the wafer-level packaging structure 10 includes a device wafer 1, a protective layer arranged on the front side of the device wafer 1 or the front side and back side of the device wafer 1, a support layer 4 and an edge sealing layer 3.

[0075] As shown in FIG. 3( b ), the device wafer 1 has a device area and an invalid area 11 located at the edge of the device area. The device area has a plurality of chip functional areas 121 and a peripheral area 122 surrounding the chip functional area 121. The support layer 4 is located in the peripheral area 122 and is connected between the device wafer 1 and the protective layer. The support layer 4 and the protective layer form a cavity 5 for accommodating the device. The edge sealing layer 3 is located in the invalid area 11 and is connected between the device wafer 1 and the protective layer. The effect of preventing leakage can be achieved, and the front of the device area in the device wafer 1 can be protected from contamination, thereby improving the yield; at the same time, a cavity 5 for accommodating the device on the device wafer 1 can be formed, and a product structure for protecting the device in the chip functional area 121 on the front of the device wafer 1 can be formed.

[0076] In this embodiment, the protective layer is a cap wafer 2 disposed on the front of the device wafer 1. Of course, this is not limiting, the protective layer may also be a non-wafer material protective cover disposed on the front of the device wafer 1, and its base material may be a ceramic substrate such as alumina, a quartz substrate or a glass substrate, etc.; or the protective layer may also include a supporting wafer disposed on the back of the device wafer 1. It is known that when the protective layer includes the cap wafer 2 and the supporting wafer, it is equivalent to stacking three wafers.

[0077] In a specific embodiment, the cap wafer 2 is a common silicon wafer to reduce costs. Of course, it is not limited to this. It is known that the cap wafer 2 and the support wafer can be selected from any suitable substrate known to those skilled in the art, such as at least one of the following materials: lithium tantalate (LiTaO3), lithium niobate (LiNbO3), silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-sided polished silicon wafers (Double Side Polished Wafers, DSP).

[0078] The cap wafer 2 in this embodiment is only used to protect the device wafer 1 , so the cap wafer 2 does not have a chip functional area.

[0079] Furthermore, combined with Figure 1 As shown, the edge sealing layer 3 is formed by a plurality of connected circular rings 31. It can provide sufficient support force for the device wafer 1 and the cap wafer 2, so as to prevent the device wafer 1 and the cap wafer 2 from being broken and damaged due to uneven force in the subsequent thinning process after bonding, thereby improving the yield of the product.

[0080] Furthermore, the thickness of the circular ring 31 is T, and along the radial direction of the device wafer 1, the length of the connection between two adjacent circular rings 31 is greater than 2T, thereby increasing the leakage path and improving the anti-leakage effect.

[0081] Please refer to Figure 1 As shown, in a specific embodiment, two adjacent rings 31 are approximately tangent to each other, that is, the two rings 31 overlap at the edge. At this time, the length L of the overlapping portion of the two rings 31 is greater than 2T.

[0082] Please refer to Figure 2 As shown, in another specific embodiment, two adjacent circular rings 31 intersect each other. At this time, the length of the connection between the two adjacent circular rings 31 must be greater than 2T, which increases the leakage path and thus improves the anti-leakage effect.

[0083] Specifically, the thickness T of the ring 31 is not less than 1 μm, which is beneficial to the molding of the edge sealing layer 3 .

[0084] Of course, this is not limited to the above. It can be understood that in other embodiments, the edge sealing layer can also be set as a circular ring structure located in the invalid area 11 and surrounding the device area 12, and further, the inner circle and outer circle of the circular ring structure can be set to a wavy shape to enhance its supporting effect.

[0085] For further information, see Figure 1 As shown, in this embodiment, the ineffective area 11 has only one circle of the edge sealing layer 3. Of course, this is not limited to this. In other embodiments, the ineffective area 11 can also be provided with multiple circles of the edge sealing layer 3. When there are multiple circles of the edge sealing layer 3, along the radial direction of the device wafer 1, the multiple circles of the edge sealing layer 3 are arranged in sequence in concentric circles to further improve the anti-leakage effect and improve the yield of the product.

[0086] Furthermore, the peripheral area 122 of the device wafer 1 has a pad 13, and the pad 13 is exposed on the side of the support layer 4 away from the chip functional area 121. In the present invention, by forming an edge sealing layer 3 to seal the gap between the protective layer and the invalid area 11 at the edge of the device wafer 1, the effect of preventing leakage is achieved, and the pad 13 in the device wafer 1 can be protected from contamination, thereby improving the yield.

[0087] Furthermore, the device wafer 1 also has a cutting area 123, which is the area of ​​the cutting path. The wafer-level packaging structure 10 also includes a reinforcing rib 6 disposed in the cutting area 123 and connected between the cap wafer 2 and the device wafer 1, which can enhance the strength of the device wafer 1 and the cap wafer 2 after bonding, and prevent the device wafer 1 and the cap wafer 2 from being broken and damaged due to uneven force in the subsequent thinning process, thereby improving the yield of the product.

[0088] Please refer to Figure 4(a) to Figure 4(e) As shown, it is a wafer-level packaging method in the second embodiment of the present invention. The difference between the wafer-level packaging method in the second embodiment of the present invention and the wafer-level packaging method in the first embodiment is that: in the second embodiment of the present invention, the cap wafer 2a not only protects the device wafer 1, but also has a chip functional area. At this time, the device in the chip functional area 121 of the device wafer 1 is a Hall device, and the chip functional area corresponding to the Hall device on the cap wafer 2a is provided with an alloy 25 containing at least one element of iron, cobalt, and nickel. That is, when processing the cap wafer 2a, in addition to forming the support layer 4 and the edge sealing layer 3 on the cap wafer 2a, an alloy 25 containing at least one element of iron, cobalt, and nickel is also provided on the chip functional area of ​​the cap wafer 2a.

[0089] It is known that the alloy 25 containing at least one element of iron, cobalt, and nickel is a material that is easily magnetized, and thus can achieve communication interconnection with the Hall device on the device wafer 1 .

[0090] After the wafer-level packaging structure 10 a is formed, it is finally cut into individual chip units 20 a .

[0091] The second embodiment of the present invention is the same as the first embodiment except for the above differences; details will not be repeated here.

[0092] Correspondingly, please refer to Figure 4(d), the present invention also provides a wafer-level packaging structure 10a corresponding to the wafer-level packaging method in the second embodiment, and the difference between the wafer-level packaging structure 10a and the wafer-level packaging structure 10 corresponding to the wafer-level packaging method in the first embodiment is that the cap wafer 2a in the wafer-level packaging structure 10a in the second embodiment has a chip functional area. For example, when the device in the chip functional area 121 of the device wafer 1 is a Hall device, the chip functional area on the cap wafer 2a is provided with an alloy 25 containing at least one element of iron, cobalt, and nickel.

[0093] The wafer-level packaging structure 10a corresponding to the wafer-level packaging method in the second embodiment of the present invention is the same as the wafer-level packaging structure 10 corresponding to the first embodiment except for the above-mentioned differences; details will not be repeated here.

[0094] Please refer to Figure 5(a) to Figure 5(e) As shown, it is a wafer-level packaging method in the third embodiment of the present invention. The difference between the wafer-level packaging method in the third embodiment of the present invention and the wafer-level packaging method in the first embodiment is that: in the third embodiment of the present invention, the device in the chip functional area 121 in the device wafer 1 is a Hall device and an alloy containing at least one element of iron, cobalt, and nickel located above the Hall device. That is, when processing the device wafer 1, after forming the Hall device in the chip functional area 121, it also includes the following steps: forming a polymer layer, such as a PI layer, in the chip functional area 121, and then forming an alloy 25 containing at least one element of iron, cobalt, and nickel on the polymer layer.

[0095] It is known that the alloy 25 containing at least one element of iron, cobalt and nickel is a material that is easily magnetized, thereby enabling communication and interconnection with the Hall device.

[0096] After the wafer-level packaging structure 10b is formed, it is finally cut into individual chip units 20b.

[0097] The third embodiment of the present invention is the same as the first embodiment except for the above differences; details will not be repeated here.

[0098] Correspondingly, please refer to Figure 5(d), the present invention also provides a wafer-level packaging structure 10b corresponding to the wafer-level packaging method in the third embodiment, and the difference between the wafer-level packaging structure 10b and the wafer-level packaging structure 10 corresponding to the wafer-level packaging method in the first embodiment is that the device in the chip functional area 121 in the device wafer 1 in the wafer-level packaging structure 10b in the third embodiment is a Hall device and an alloy containing at least one element of iron, cobalt, and nickel located above the Hall device.

[0099] The wafer-level packaging structure 10 b corresponding to the wafer-level packaging method in the third embodiment of the present invention is the same as the wafer-level packaging structure 10 corresponding to the first embodiment except for the above-mentioned differences; details will not be repeated here.

[0100] Please refer to Figure 6 as well as Figure 7(a) to Figure 7(e) As shown, it is a wafer-level packaging method in the fourth embodiment of the present invention. The difference between the wafer-level packaging method in the fourth embodiment of the present invention and the wafer-level packaging method in the first embodiment is that: while forming the edge sealing layer 3 and the support layer 4, the wafer-level packaging method further includes: forming a reinforcing rib 6 on the bonding surface of the device wafer 1 or the bonding surface of the protective layer in an area corresponding to the cutting area 123 in the device wafer 1, that is, forming a reinforcing rib 6 on the cutting area 123 in the bonding surface of the device wafer 1 or on the third area 23 in the cap wafer 2c. It can enhance the strength of the bonded device wafer 1 and the cap wafer 2c, avoid the device wafer 1 and the cap wafer 2c from being broken and damaged due to uneven force in the subsequent thinning process, and improve the yield of the product.

[0101] It can be understood that the reinforcing ribs 6 only need to be provided in the areas where the strength needs to be enhanced, and do not need to be provided in other areas.

[0102] Specifically, the reinforcing ribs 6 can be formed synchronously with the edge sealing layer 3 and the supporting layer 4. The forming method of the reinforcing ribs 6 can be the same as the forming method of the edge sealing layer 3 and the supporting layer 4, which will not be described in detail.

[0103] After the wafer-level packaging structure 10c is formed, it is finally cut into individual chip units 20c.

[0104] It can be known that in the structural schematic diagram corresponding to each step of the wafer-level packaging method in the fourth embodiment of the present invention, in order to clearly show the reinforcing rib 6, the welding pad is not shown, wherein the setting position of the reinforcing rib 6 is staggered with the welding pad, and the setting position of the welding pad is consistent with that in the first embodiment, which will not be repeated here.

[0105] The fourth embodiment of the present invention is the same as the first embodiment except for the above differences; details will not be repeated here.

[0106] Correspondingly, please refer to Figure 7(d), the present invention also provides a wafer-level packaging structure 10c corresponding to the wafer-level packaging method in the fourth embodiment, and the difference between the wafer-level packaging structure 10c and the wafer-level packaging structure 10 corresponding to the wafer-level packaging method in the first embodiment is that: the cutting area 123 in the device wafer 1 in the wafer-level packaging structure 10c in the fourth embodiment has a reinforcing rib 6 connecting the device wafer 1 and the cap wafer 2c.

[0107] The wafer-level packaging structure 10c corresponding to the wafer-level packaging method in the fourth embodiment of the present invention is the same as the wafer-level packaging structure 10 corresponding to the first embodiment except for the above-mentioned differences; no further description is given here. Compared with the prior art, in the wafer-level packaging method of the present invention, an edge sealing layer 3 is formed to seal the gap between the protective layer and the invalid area 11 at the edge of the device wafer 1 while bonding the device wafer 1 to the protective layer, so as to achieve the effect of anti-leakage, and can protect the front of the device area in the device wafer 1 from contamination, thereby improving the yield; at the same time, a space can be left on the bonding surface of the device wafer 1, so as to avoid glue overflow around the wafer after extrusion, and there is no need to fill glue after bonding, thereby reducing the process cost. In addition, a cavity 5 for accommodating a device can be formed, so as to form a product structure for protecting the device in the chip functional area 121 on the front of the device wafer 1.

[0108] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0109] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wafer-level packaging method, characterized in that: The steps include: A device wafer is provided, wherein the device wafer has a device area and an invalid area located at the edge of the device area, wherein the device area has a plurality of chip functional areas and a peripheral area surrounding the chip functional areas; Forming at least one edge sealing layer on the bonding surface of the device wafer and / or the bonding surface of the protective layer in an area corresponding to the ineffective area at the edge of the device wafer; Forming a support layer on a bonding surface of the device wafer and / or a bonding surface of the protective layer in an area corresponding to a peripheral area of ​​the device wafer; The device wafer is bonded to the protective layer by using a support layer and an edge sealing layer. The support layer and the protective layer form a cavity for accommodating the device. The edge sealing layer seals the gap between the protective layer and the ineffective area at the edge of the device wafer.

2. The wafer-level packaging method according to claim 1, wherein: Each circle of the edge sealing layer is formed by a plurality of connected circular rings.

3. The wafer-level packaging method according to claim 2, wherein: The thickness of the circular ring is T, and along the radial direction of the device wafer, the length of the connection between two adjacent circular rings is greater than 2T.

4. The wafer level packaging method according to claim 2, wherein: The thickness T of the ring is not less than 1 μm.

5. The wafer level packaging method according to claim 1, wherein: The height of the edge sealing layer is not less than the height of the supporting layer.

6. The wafer-level packaging method according to any one of claims 1 to 5, characterized in that: The edge sealing layer and the support layer are formed by dispensing or photolithography process.

7. The wafer level packaging method according to claim 1, wherein: While forming the edge sealing layer and the support layer, the wafer-level packaging method further includes: forming reinforcing ribs on the bonding surface of the device wafer or the bonding surface of the protective layer in an area corresponding to the cutting area in the device wafer.

8. The wafer level packaging method according to claim 1, wherein: The protection layer is a cap wafer arranged on the front side of the device wafer.

9. The wafer level packaging method according to claim 8, wherein: There is no chip functional area on the cap wafer; the device in the chip functional area of ​​the device wafer is a filter, or the device in the chip functional area of ​​the device wafer is a Hall device and an alloy containing at least one element of iron, cobalt and nickel located above the Hall device.

10. The wafer level packaging method according to claim 8, wherein: The cap wafer has a chip functional area; the device in the chip functional area of ​​the device wafer is a Hall device, and the chip functional area on the cap wafer corresponding to the Hall device is provided with an alloy containing at least one element of iron, cobalt and nickel.

11. The wafer level packaging method according to claim 1, wherein: The protection layer is a support wafer arranged on the back side of the device wafer.

12. The wafer level packaging method according to claim 1, wherein: The edge sealing layer and the support layer are both bonding adhesives.

13. The wafer level packaging method according to claim 1, wherein: The peripheral area of ​​the device wafer has a bonding pad, and the bonding pad is exposed on a side of the support layer away from the chip functional area.

14. A wafer-level packaging structure, characterized in that: include: A device wafer, wherein the device wafer comprises a device region and an ineffective region located at the edge of the device region, wherein the device region comprises a plurality of chip functional regions and a peripheral region surrounding the chip functional regions; A protective layer, disposed on the front side of the device wafer or located on the front side of the device wafer and the back side of the device wafer; A support layer, the support layer is located in the peripheral area and connected between the device wafer and the protective layer, the support layer and the protective layer forming a cavity for accommodating the device; At least one circle of edge sealing layer, the at least one circle of edge sealing layer is located in the ineffective area, and the edge sealing layer is connected between the device wafer and the protective layer.

15. The wafer-level packaging structure according to claim 14, wherein: The edge sealing layer is formed by a plurality of connected circular rings.

16. The wafer-level packaging structure according to claim 15, wherein: The thickness T of the circular ring is not less than 1 μm, and along the radial direction of the device wafer, the length of the connection between two adjacent circular rings is greater than 2T.

17. The wafer-level packaging structure according to claim 14, wherein: The protection layer is a cap wafer arranged on the front side of the device wafer.

18. The wafer-level packaging structure according to claim 17, wherein: There is no chip functional area on the cap wafer; the device in the chip functional area of ​​the device wafer is a filter, or the device in the chip functional area of ​​the device wafer is a Hall device and an alloy containing at least one element of iron, cobalt and nickel located above the Hall device.

19. The wafer-level packaging structure according to claim 17, wherein: The cap wafer has a chip functional area; the device in the chip functional area of ​​the device wafer is a Hall device, and the chip functional area on the cap wafer corresponding to the Hall device is provided with an alloy containing at least one element of iron, cobalt and nickel.

20. The wafer-level packaging structure according to claim 14, wherein: The peripheral area of ​​the device wafer has a bonding pad, and the bonding pad is exposed on a side of the support layer away from the chip functional area.

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