Method for processing a bonded substrate, layout structure and packaging method

Abstract

The application provides a processing method of a bonding substrate, a layout structure and a packaging method. A pattern structure of an alignment mark and a pattern structure of a bonding limiting piece are simultaneously formed in a first mask layer, and the alignment mark and the bonding limiting piece are simultaneously formed by using a same etching process, which is equivalent to omitting a processing flow of the bonding limiting piece, reduces process steps and is beneficial to reducing processing cost. Moreover, the bonding limiting piece is arranged in a cutting path area, and does not need to additionally occupy space of a chip area, so that effective reduction of a chip area is realized. In addition, when bonding packaging is performed, the existence of the bonding limiting piece can effectively control the extrusion degree of the substrate, avoids the situation that the bonding material is largely extruded due to over-extrusion, and guarantees the reliability of chip packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for processing, layout structure and packaging of a bonding substrate. Background Technology

[0002] Semiconductor manufacturing typically includes front-end chip fabrication and back-end packaging. Traditional packaging methods usually employ wire bonding, but with the development of very large-scale integrated circuits (VLSI), wire bonding can no longer meet the process requirements. Therefore, wafer-level bonding packaging technology has been proposed, which can meet the market's increasing demand for thinner and lighter microelectronic products, and has thus gradually replaced wire bonding packaging as a more important packaging method. For example, in microelectromechanical systems (MEMS), chip packaging can be achieved through wafer-to-wafer bonding.

[0003] Figure 1 The diagram illustrates a first type of bonding structure for chip bonding and packaging, which typically involves forming corresponding bonding pads (i.e., ...) within the chip regions of two substrates. Figure 1 The bonding pads 10 and 20 (as indicated in the diagram) are used to achieve chip packaging by applying relative pressure to the two substrates, causing the bonding pads at corresponding positions within the chip area to press against each other and form a fusion bond. However, Figure 1 The bonding structure shown often exhibits fluctuations in bonding effectiveness due to the magnitude of the applied pressure. For example, excessive pressure can cause a large amount of bonding material to be extruded, resulting in less bonding material remaining at the bonding interface, affecting reliability. Furthermore, the extruded bonding material can also cause adhesion risks.

[0004] Figure 2 The diagram illustrates a second bonding structure for chip bonding and packaging. Specifically, an overflow groove 30 is provided on the side of the bonding pad. This allows the extruded bonding material to be guided into the overflow groove 30 when pressure is applied to the two substrates for bonding, effectively avoiding the risk of adhesion. However, Figure 2 The structure shown still suffers from insufficient bonding material at the bonding interface due to the extrusion of bonding material during bonding, which affects reliability.

[0005] Figure 3 The diagram illustrates a third bonding structure for chip bonding and packaging. Specifically, a baffle 40 is provided on the side of the bonding pad. During the bonding process, the baffle 40 can effectively resist the applied pressure, limit the degree of mutual compression between the two substrates, and prevent a large amount of bonding material from being squeezed out.

[0006] Although Figure 3 The bonding structure shown can effectively improve the problem of excessive extrusion of bonding materials, but this bonding method requires the formation of additional retaining walls 40, which inevitably increases the preparation process and increases the processing cost. Summary of the Invention

[0007] The purpose of this invention is to provide a method for processing a bonding substrate, which simplifies the processing procedure of the bonding substrate.

[0008] To this end, the present invention provides a method for processing a bonding substrate, comprising: providing a bonding substrate, wherein the bonding substrate defines an alignment mark area, a plurality of chip areas, and a dicing channel area located between adjacent chip areas; forming a first mask layer on the surface of the bonding substrate, wherein the first mask layer forms a first pattern structure in the alignment mark area and a second pattern structure in the dicing channel area, and the first mask layer exposes the chip areas; using the first mask layer as a mask, etching the chip areas of the bonding substrate, and copying the first pattern structure to the alignment mark area to form alignment marks, while copying the second pattern structure to the dicing channel area to form bonding limiting members; and forming a first bonding pad in the chip areas.

[0009] Optionally, the method for fabricating the first mask layer includes: forming a mask material layer on the bonding substrate; and performing a photolithography process based on a mask to form the first patterned structure and the second patterned structure in the mask material layer. The mask has an alignment mark pattern and a limiting member pattern formed thereon, the alignment mark pattern defining the first patterned structure and the limiting member pattern defining the second patterned structure.

[0010] Optionally, the second graphic structure includes an extension line that extends continuously along the cutting channel area; or, the second graphic structure includes a plurality of strip segments arranged sequentially along the cutting channel area.

[0011] Optionally, the top surface of the first bonding pad is lower than the top surface of the bonding stop.

[0012] Optionally, the method for fabricating the first bonding pad includes: forming a second mask layer, the second mask layer covering the alignment mark and the bonding limiting member, and forming a third patterned structure in the chip region; performing an etching process using the second mask layer as a mask to replicate the third patterned structure into the chip region to form a bottom support pad protruding from the top surface of the chip region; and removing the second mask layer and forming a bonding material layer on the bottom support pad to constitute the first bonding pad.

[0013] Optionally, the chip region of the bonding substrate is etched using the first mask layer as a mask, so that the top surface of the chip region is sunk by 0.5μm-2.0μm.

[0014] The present invention also provides a layout structure for a photomask, the photomask having an alignment mark area, a plurality of chip areas, and a dicing channel area located between adjacent chip areas. Furthermore, an alignment mark pattern and a limiting member pattern are formed on the photomask, the alignment mark pattern being located within the alignment mark area and the limiting member pattern being located within the dicing channel area.

[0015] Optionally, the limiting member pattern is an extension line that extends continuously along the cutting channel area; or, the limiting member pattern includes a plurality of strip segments arranged sequentially along the cutting channel area.

[0016] The present invention also provides a packaging method, comprising: processing a bonding substrate using the processing method described above to form a first bonding pad in a chip region of the bonding substrate and forming a bonding limiting member in a dicing region of the bonding substrate; and bonding the bonding substrate and a device substrate, wherein a second bonding pad is formed in a chip region of the device substrate, and the second bonding pad and the first bonding pad are bonded to each other.

[0017] Optionally, the method of bonding the bonding substrate and the device substrate includes: placing the bonding substrate and the device substrate opposite to each other, and applying pressure to the bonding substrate and / or the device substrate to fuse the second bonding pad and the first bonding pad together until the bonding limiting member on the bonding substrate abuts against the device substrate.

[0018] In the bonding substrate processing method provided by this invention, a patterned structure of alignment marks and a patterned structure of bonding limiting members are simultaneously formed within the first mask layer. The alignment marks and bonding limiting members are formed simultaneously through an etching process, allowing the fabrication process of the bonding limiting members to be integrated into the fabrication process of the alignment marks. This eliminates the need for a separate bonding limiting member fabrication process, significantly reducing process steps and lowering processing costs. Furthermore, the bonding limiting members are positioned within the dicing area, eliminating the need for additional space in the chip area and effectively reducing the chip area. Simultaneously, the size of the bonding limiting members can be maximized within the dicing area to ensure high strength to withstand subsequent bonding pressure. Moreover, during bonding and packaging, the presence of the bonding limiting members effectively controls the degree of compression on the substrate, preventing overpressure and excessive extrusion of bonding material, thus ensuring the reliability of the chip packaging. Attached Figure Description

[0019] Figure 1 This is the first bonding structure for bonding packaging.

[0020] Figure 2 This is the second type of bonding structure for bonding packaging.

[0021] Figure 3 This is the third type of bonding structure for bonding packaging.

[0022] Figure 4 This is a schematic flowchart of a bonding substrate processing method according to an embodiment of the present invention.

[0023] Figure 5 This is a top view of the first mask layer in the bonding substrate processing method according to an embodiment of the present invention.

[0024] Figures 6-10 This is a cross-sectional schematic diagram of the bonding substrate in one embodiment of the present invention during its processing.

[0025] Figures 11-12 This is a schematic diagram of the bonding process of the encapsulation method in one embodiment of the present invention.

[0026] The reference numerals in the attached figures are as follows:

[0027] 10 / 20-bonding pad;

[0028] 30 - Overflow channel;

[0029] 40- Retaining wall;

[0030] 100-bonded substrate;

[0031] 100A - Chip Area;

[0032] 110A - First Chip Area;

[0033] 120A - Second chip area;

[0034] 100B - Cutting track area;

[0035] 100C - Alignment Mark Area;

[0036] 210 - First mask layer;

[0037] 210C - First graphic structure;

[0038] 210B - Second graphic structure;

[0039] 220 - Second mask layer;

[0040] 220C - First Cover Section;

[0041] 220B - Second Cover Section;

[0042] 220A - Third graphic structure;

[0043] 300C - Alignment Mark;

[0044] 300B - Bonding limit component;

[0045] 400 - First bonding pad;

[0046] 410 - Bottom support pad;

[0047] 420 - Bonding material layer;

[0048] 500 - Device substrate;

[0049] 600 - Second bonding pad. Detailed Implementation

[0050] The core concept of this invention lies in providing a method for processing a bonding substrate, which can be found in the following reference. Figure 4 As shown, the processing method for bonding substrates may include the following steps.

[0051] Step S100: A bonding substrate is provided, wherein an alignment mark area, a plurality of chip areas and a dicing channel area located between adjacent chip areas are defined on the bonding substrate.

[0052] In step S200, a first mask layer is formed on the surface of the bonding substrate. The first mask layer has a first pattern structure in the alignment mark area and a second pattern structure in the dicing area, and the first mask layer exposes the chip area.

[0053] In step S300, using the first mask layer as a mask, the chip area of ​​the bonding substrate is etched, and the first pattern structure is copied into the alignment mark area to form an alignment mark. At the same time, the second pattern structure is copied into the dicing area to form a bonding limiting member, which protrudes from the top surface of the chip area.

[0054] Step S400: A first bonding pad is formed in the chip region.

[0055] In other words, this invention integrates the fabrication process of the bonding limiting member and the fabrication process of the alignment mark, thereby eliminating the need for an additional bonding limiting member fabrication process, significantly reducing process steps and lowering processing costs. Furthermore, since the bonding limiting member in the formed bonding substrate is located within the dicing area, it does not require additional chip area, facilitating effective chip area reduction. In addition, during bonding and packaging using this bonding substrate, the limiting member effectively resists bonding pressure, controls the degree of compression between substrates, prevents excessive extrusion of bonding material, and ensures the reliability of chip packaging.

[0056] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the processing method, layout structure, and packaging method of the bonding substrate proposed in this invention. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the invention. It should be understood that relative terms such as "above," "below," "top," "bottom," and "upper" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described, for example, as being "above" another element will now be below that element.

[0057] In step S100 of preparing the bonding substrate, please refer to the following for details. Figure 5 and Figure 6 As shown, a bonding substrate 100 is provided, on which alignment mark areas 100C, a plurality of chip areas 100A, and dicing channels 100B located between adjacent chip areas are defined. The bonding substrate 100 is, for example, a wafer.

[0058] In this embodiment, the bonding substrate 100 can be used to bond with another device substrate (not shown in the figure) after processing. The device substrate has multiple chip regions arranged in a one-to-one correspondence, and device structures can also be formed in the chip regions. By bonding the bonding substrate 100 to the device substrate, the chip region 100A of the bonding substrate 100 covers the chip region of the device substrate, thereby realizing chip packaging of each chip in the device substrate.

[0059] Furthermore, the plurality of chip regions 100A on the bonding substrate 100 may be arranged in an array. The plurality of chip regions 100A on the bonding substrate 100 may include a first chip region for encapsulating a functional chip (i.e., Figure 5 The first chip area 110A shown and the second chip area for sealing the test chip (i.e., Figure 5 The second chip area 120A shown is an example of a functional chip with a device structure formed on a device substrate, and the test chip is an example of a chip with a test structure or a marking structure formed on a device substrate. In this embodiment, the alignment marking area 100C is disposed in the second chip area (i.e., for sealing the test chip) used for sealing the test chip. Figure 5 The second chip area 120A is shown.

[0060] Continue to refer to Figure 5 and Figure 6As shown, adjacent chip regions 100A are separated by a dicing channel region 100B. In subsequent processes, the dicing channel region 100B is diced to separate multiple chips on the substrate. Additionally, an alignment mark region 100C on the bonding substrate 100 is used to prepare alignment marks. The formed alignment marks can serve as alignment targets for subsequent photolithography processes, and also as alignment targets between two substrates during subsequent bonding processes.

[0061] In step S200 of preparing the bonding substrate, continue to refer to Figure 5 and Figure 6 As shown, a first mask layer 210 is formed on the surface of the bonding substrate 100. The first mask layer 210 exposes the chip region 100A and forms a first pattern structure 210C in the alignment mark region 100C and a second pattern structure 210B in the dicing channel region 100B. The first pattern structure 210C corresponds to the alignment mark pattern structure, and the second pattern structure 210B corresponds to the bonding limiting member pattern structure. That is, the first mask layer 210 simultaneously defines both the alignment mark pattern structure and the bonding limiting member pattern structure.

[0062] Furthermore, the pattern structure of the alignment mark (i.e., the first pattern structure 210C) and the pattern structure of the bonding limiting member (i.e., the second pattern structure 210B) within the first mask layer 210 can also be defined simultaneously by the same mask, so that the preparation step of the bonding limiting member can be completely integrated into the preparation step of the alignment mark, omitting the additional preparation step of the bonding limiting member, effectively bonding the preparation process, and reducing processing costs.

[0063] Specifically, the method for fabricating the first mask layer 210 includes, for example,: 1) forming a mask material layer on a bonding substrate 100, the mask material layer being, for example, a photoresist layer; 2) performing a photolithography process using a mask to form the first patterned structure 210C and the second patterned structure 210B in the mask material layer. The mask has an alignment mark pattern and a limiting member pattern formed thereon. The alignment mark pattern is formed in the alignment mark area to define the first patterned structure 210C, and the limiting member pattern is formed in the dicing area to define the second patterned structure 210B.

[0064] In a specific example, the graphic structure of the bonding limiting member (i.e., the second graphic structure 210B) can be adjusted according to the specific conditions within the dicing zone 100C. For example, when no other components are provided within the dicing zone 100C, the second graphic structure 210B can extend continuously along the dicing zone 100C. For instance, the second graphic structure 210B can be an extension line that extends continuously around the periphery of the chip region 100A, or the second graphic structure 210B includes multiple strip segments arranged sequentially along the dicing zone 100C.

[0065] In step S300 of preparing the bonding substrate, specifically combined Figure 5 and Figure 7 As shown, using the first mask layer 210 as a mask, the bonding substrate 100 is etched to copy the first pattern structure 210C into the alignment mark area 100C to form an alignment mark 300C, and simultaneously copy the second pattern structure 210B into the dicing area 100B to form a bonding limiting member 300B. Afterwards, the first mask layer 210 can be removed.

[0066] In this embodiment, under the masking effect of the first mask layer 210, the exposed chip region 100A is etched, causing the top surface of the chip region 100A to sink, thereby forming a protruding bonding limiting member 300B in the dicing area 100B and a protruding alignment mark 300C in the alignment mark area 100C. Specifically, the chip region 100A can be etched to a thickness of approximately 0.5μm-2.0μm, correspondingly making the protrusion height H1 of the bonding limiting member 300B relative to the top surface of the chip region 0.5μm-2.0μm, or more specifically, the bonding limiting member 300B can protrude 1μm-1.5μm relative to the top surface of the chip region.

[0067] It should be noted that in this embodiment, by placing the bonding limiting member 300B within the dicing channel region 100B, it is not necessary to occupy additional space in the chip region 100A. This facilitates chip area reduction and allows for maximizing the size of the bonding limiting member 300B within the dicing channel region 100B, ensuring that the bonding limiting member 300B has high strength to withstand subsequent bonding pressure. Figure 3 Taking the bonding structure shown as an example, its barrier 40 is located within the chip area and needs to occupy a certain space within the chip area. For example, if the width of the barrier 40 is 15μm and the distance between the barrier 40 and the bonding pad 10 is 30μm, then it is equivalent to needing an additional 45μm on one side of the chip. However, compared with Figure 3Compared to the bonding structure shown, in this embodiment, the bonding limiting member 300B is set in the dicing channel area 100B, which does not require occupying the space of the chip area 100A, thus greatly reducing the size of the chip area 100A.

[0068] In step S400 of preparing the bonding substrate, please refer to the following for details. Figures 8-10 As shown, a first bonding pad 400 is formed within the chip region 100A. In this embodiment, the top surface of the first bonding pad 400 is lower than the top surface of the bonding limiting member 300B.

[0069] Furthermore, the first bonding pad 400 may include a bottom support pad 410 and a bonding material layer 420. The bottom support pad 410 may be a block-shaped structure protruding from the surface of the chip region, and the bonding material layer 420 is formed on the bottom support pad 410, thereby improving the overall strength of the first bonding pad 400. In this embodiment, the bonding material layer 420 is formed on the top surface of the bottom support pad 410 and also covers the sidewalls of the bottom support pad 410.

[0070] In a specific example, the preparation method of the first bonding pad 400 includes the following steps.

[0071] First refer to Figure 8 As shown, a second mask layer is formed, covering the alignment mark 300C and the bonding limiter 300B, and a third pattern structure 220A is formed within the chip region 100A, the third pattern structure 220A corresponding to the pattern structure of the bonding pad. For example... Figure 8 As shown, the second mask layer includes a first cover portion 220C covering the alignment mark 300C, a second cover portion 220B covering the bonding limit member 300B, and a third pattern structure 220A formed in the chip area.

[0072] Continue to refer to Figure 8 As shown, using the second mask layer as a mask, an etching process is performed to replicate the third pattern structure 220A into the chip region 100A, thereby forming a bottom support pad 410 protruding from the top surface of the chip region 100A. In this embodiment, the chip region 100A can be etched to a thickness of approximately 1.5μm-2.5μm, correspondingly making the protrusion height H2 of the formed bottom support pad 410 relative to the top surface of the chip region 1.5μm-2.5μm. It should be understood that the height of the bonding limiting member 300B relative to the top surface of the chip region at this time is the sum of the first protrusion height H1 and the second protrusion height H2.

[0073] Next, refer to Figures 9-10As shown, the second mask layer is removed, and a bonding material layer 420 is formed on the bottom support pad 410 to constitute the first bonding pad 400. The bonding material layer 420 is, for example, a metal material layer, which may further be an aluminum layer, a germanium layer, etc. The thickness of the bonding material layer 420 above the bottom support pad 410 is, for example, 0.4 μm-1.2 μm.

[0074] In the bonding substrate processing method described above, the pattern of alignment mark 300C and the pattern of bonding limiting member 300B can be defined simultaneously using the same mask, and the pattern of alignment mark and bonding limiting member can be copied into bonding substrate 100 simultaneously in the same etching process. This allows bonding limiting member 300B to be formed simultaneously in the preparation process of alignment mark 300C, saving the preparation process of limiting member.

[0075] Specifically, the layout structure of the mask used includes an alignment mark area, multiple chip areas, and dicing channels located between adjacent chip areas. Furthermore, the mask has an alignment mark pattern and a locating member pattern formed thereon. The alignment mark pattern is located within the alignment mark area, and the locating member pattern is located within the dicing channel area. The locating member pattern may be, for example, an extension line continuously extending along the dicing channel area; or, the locating member pattern may include multiple strip segments arranged sequentially along the dicing channel area.

[0076] Based on the bonding substrate described above, a further packaging method is described below. The packaging method includes: processing the bonding substrate using the processing method described above, and bonding the processed bonding substrate and a device substrate together.

[0077] For details, please refer to [link / reference]. Figures 11-12 As shown, the bonding substrate 100 is processed to form a first bonding pad 400 in the chip region of the bonding substrate 100, a bonding limiting member 300B in the dicing region of the bonding substrate 100, and an alignment mark 300C in the alignment mark region. In this embodiment, the bonding limiting member 300B and the alignment mark 300C are formed simultaneously in the same fabrication process, and both protrude from the top surface of the chip region and have the same height.

[0078] Furthermore, a second bonding pad 600 is formed in the chip region of the device substrate 500. When the bonding substrate 100 and the device substrate 500 are bonded together, the second bonding pad 600 and the first bonding pad 400 are bonded together. The second bonding pad 600 is, for example, a metal pad, and the material of the metal pad includes, for example, aluminum or germanium.

[0079] In this embodiment, the sum of the heights of the first bonding pad 400 and the second bonding pad 600 is greater than the height of the bonding limiting member 300B, so that the first bonding pad 400 and the second bonding pad 600 have sufficient mutual fusion allowance to ensure sufficient bonding. For example, the height of the first bonding pad 400 (including the bottom support pad 410 and the bonding material layer 420) is 2μm-3.5μm, and the height of the second bonding pad 600 is 0.5μm-1.5μm. The sum of the heights of the first bonding pad 400 and the second bonding pad 600 is approximately 2.5μm-5μm. Then, the height of the bonding limiting member 300B (corresponding to the sum of the first protrusion height H1 and the second protrusion height H2) can be 2μm-4.5μm.

[0080] For details, please refer to the following: Figures 11-12 As shown, the process of bonding the bonding substrate 100 and the device substrate 500 together includes, for example, setting the bonding substrate 100 and the device substrate 500 opposite to each other, and applying pressure to the bonding substrate 100 and / or the device substrate 500 to bring the second bonding pad 600 and the first bonding pad 400 into contact with each other, and pressing them together under pressure to fuse the second bonding pad 600 and the first bonding pad 400 together, and correspondingly bringing the bonding substrate 100 and the device substrate 500 closer to each other until the top surface of the bonding limiting member 300B on the bonding substrate 100 abuts against the surface of the device substrate 500.

[0081] In the packaging method described above, the presence of the bonding limiting member 300B effectively controls the degree of compression on the substrate, preventing the bonding material from being squeezed out in large quantities under overpressure conditions, thus ensuring the reliability of the chip packaging.

[0082] While the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.

[0083] It should also be noted that references to "an embodiment," "an embodiment," "a specific embodiment," "some embodiments," etc., in the specification only indicate that the described embodiment may include a particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0084] It should be understood that, unless otherwise specified or indicated, the terms "first," "second," "third," etc., in the specification are used only to distinguish the various components, elements, steps, etc., in the specification, and not to indicate the logical or sequential relationships between the various components, elements, steps, etc. Furthermore, the word "or" should be understood as having the definition of logical "or," not the definition of logical "exclusive or," unless the context clearly indicates the opposite meaning. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for processing a bonding substrate, characterized in that, include: A bonding substrate is provided, wherein an alignment mark area, a plurality of chip areas and a dicing track area located between adjacent chip areas are defined on the bonding substrate; A first mask layer is formed on the surface of the bonding substrate. The first mask layer has a first pattern structure formed in the alignment mark area and a second pattern structure formed in the dicing area. The first mask layer exposes the chip area. Using the first mask layer as a mask, the chip area of ​​the bonding substrate is etched so that the top surface of the chip area sinks down, and the first pattern structure is copied into the alignment mark area to form an alignment mark protruding from the top surface of the chip area. At the same time, the second pattern structure is copied into the dicing area to form a bonding limiting member protruding from the top surface of the chip area. as well as, A first bonding pad is formed within the chip region; The method for preparing the first bonding pad includes: A second mask layer is formed, which covers the alignment mark and the bonding limiter, and a third pattern structure is formed in the chip area; An etching process is performed using the second mask layer as a mask to replicate the third patterned structure into the chip region, forming a bottom support pad protruding from the top surface of the chip region, such that the height of the bonding limiting member relative to the top surface of the chip region is the same as the height of the bottom support pad; and, The second mask layer is removed, and a bonding material layer is formed on the bottom support pad to form the first bonding pad.

2. The method for processing a bonding substrate as described in claim 1, characterized in that, The method for preparing the first mask layer includes: A mask material layer is formed on the bonding substrate; and, A photolithography process is performed on a mask to form the first patterned structure and the second patterned structure in the mask material layer; wherein, an alignment mark pattern and a limiting member pattern are formed on the mask, the alignment mark pattern being used to define the first patterned structure and the limiting member pattern being used to define the second patterned structure.

3. The method for processing a bonding substrate as described in claim 1, characterized in that, The second graphic structure includes an extension line that extends continuously along the cutting channel area; or, the second graphic structure includes a plurality of strip segments arranged sequentially along the cutting channel area.

4. The method for processing a bonding substrate as described in claim 1, characterized in that, The top surface of the first bonding pad is lower than the top surface of the bonding stop.

5. The method for processing a bonding substrate as described in claim 1, characterized in that, The chip region of the bonding substrate is etched using the first mask layer as a mask, so that the top surface of the chip region is sunk by 0.5μm-2.0μm.

6. A packaging method, characterized in that, include: The bonding substrate is processed using the processing method described in any one of claims 1-5 to form a first bonding pad in the chip region of the bonding substrate and a bonding limiting member in the dicing region of the bonding substrate; and, The bonding substrate and a device substrate are bonded together. A second bonding pad is formed in the chip region of the device substrate, and the second bonding pad and the first bonding pad are bonded to each other.

7. The packaging method as described in claim 6, characterized in that, The method for bonding the bonding substrate and the device substrate includes: The bonding substrate and the device substrate are positioned opposite each other, and pressure is applied to the bonding substrate and / or the device substrate to fuse the second bonding pad and the first bonding pad together until the bonding limiting member on the bonding substrate abuts against the device substrate.

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