A method for manufacturing an array substrate for avoiding over-engraving of a touch metal layer opening

Abstract

The present invention discloses a manufacturing method of an array substrate for avoiding over-etching of a touch metal layer opening, and relates to the technical field of array substrate processing. The method of the present invention uses a CH mask after the PV insulation layer is formed to expose and etch the thickness of the PV insulation layer at the CH hole position in the AA area and the deep hole position of the Fanout without increasing the number of masks, thereby avoiding over-etching damage to the touch metal layer due to the inconsistent hole depths of the deep and shallow holes when etching the CH deep and shallow holes, thereby ensuring the stability of the TFT device and the product yield. By leaving a Metal III touch metal layer at the PV hole, damage to the Metal II source and drain metal layer during etching is prevented, and at the same time, the Metal III touch metal layer will not affect the SD-PE lap conduction.

Description

Technical Field

[0001] The present invention relates to the technical field of array substrate processing, and in particular to a method for manufacturing an array substrate which can avoid over-engraving of a touch metal layer opening. Background Art

[0002] The film layer structure of the AA area in the existing TIC ArrayTFT substrate surface is usually that a Metal I gate metal layer, a gate insulating layer, an active layer, a Metal II source and drain metal layer, and a PV insulating layer are arranged on the substrate glass in sequence; an organic flat layer, a touch metal layer Metal III, and a VA insulating layer are arranged on the PV insulating layer in sequence; a common electrode layer is arranged on the VA insulating layer, a CH insulating layer is formed on the common electrode layer by CVD, and a pixel electrode layer is arranged on the CH insulating layer. A CH deep and shallow hole is designed in the fanout area, and the Metal III touch metal layer contacts the pixel electrode layer through the CH shallow hole, and the pixel electrode layer contacts the Metal II source and drain metal layer through the CH deep hole. The Metal II source and drain metal layer is connected to Vcom OPT through TFT to conduct static electricity. There is no Metal I gate metal layer, active layer, or common electrode layer at the deep and shallow hole position in the fanout area.

[0003] In the actual production process, the CH holes in the AA area and the CH deep and shallow holes in the Fanout area are opened by exposure etching after the CH film is formed. The etching of the insulating layer usually uses charged ions formed by CF4 / SF6 gas under high voltage to bombard the film layer and react to etch. Because the CH holes in the AA area and the CH deep holes in the Fanout area need to etch three layers of PV / VA / CH, while the CH shallow holes in the Fanout area only need to etch two layers of VA / CH, the film thicknesses to be etched for the deep and shallow holes are different, which makes it easier for the touch metal layer of the shallow hole to be damaged by ion bombardment and over-etching. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a manufacturing method for an array substrate that avoids over-etching of the touch metal layer openings. Without adding a mask, a CH mask is used for exposure and etching after the PV insulating layer is formed, thereby avoiding over-etching damage to the touch metal layer due to inconsistent hole depths of deep holes and shallow holes when etching CH deep holes, thereby ensuring the stability of TFT devices and product yield.

[0005] The present invention is achieved in that:

[0006] A method for manufacturing an array substrate for avoiding over-engraving of a touch metal layer opening, which is used to manufacture an array substrate including both an AA area and a Fanout area, wherein the AA area is provided with a CH hole, and the Fanout area is provided with a CH deep hole and a CH shallow hole;

[0007] The method comprises the following steps:

[0008] Step 1, sequentially forming a Metal I gate metal layer, a gate insulating layer, an active layer, a Metal II source and drain metal layer, and a PV insulating layer on a substrate glass; wherein, in the Fanout region, the Metal I gate metal layer and the active layer are formed only at non-CH deep holes and non-CH shallow holes;

[0009] Step 2: Based on step 1, a PV hole is etched by using a CH mask for exposure;

[0010] Step 3: Based on step 2, an organic planarization layer is formed;

[0011] Step 4: Based on step 3, a Metal III touch metal layer is formed; at the same time, a Metal III touch metal layer is left at the PV hole to prevent damage to the Metal II source and drain metal layer during etching;

[0012] Step 5: Based on step 4, a VA insulating layer is formed, and then a VA hole is etched;

[0013] Step 6: Based on step 5, a common electrode layer is formed in the touch control area;

[0014] Step 7: Based on step 6, a CH insulating layer is formed;

[0015] Step 8, based on step 7, using the CH mask to perform exposure etching at the CH hole position in the AA area, the CH deep hole position in the Fanout area, and the CH shallow hole position, to form a CH hole, a CH deep hole, and a CH shallow hole respectively;

[0016] Step 8: Based on step 7, a pixel electrode layer is formed.

[0017] Furthermore, in the step 2, a CH mask is used for exposure to etch out the PV hole, and the number of etching layers is one layer.

[0018] Furthermore, in step 7, the CH mask is used to perform exposure etching at the CH hole position in the AA area, the CH deep hole position in the Fanout area, and the CH shallow hole position, and the number of etching layers is two.

[0019] Furthermore, the Metal I gate metal layer is Mo / Al / Mo or Ti / Al / Ti, the Metal II source and drain metal layer is Mo / Al / Mo or Ti / Al / Ti; and the Metal III touch metal layer is Mo / Al / Mo or Ti / Al / Ti.

[0020] Furthermore, the gate insulating layer is made of SiOx material; and the active layer is made of a-Si, MOx, LTPS or IGZO.

[0021] Furthermore, the PV insulating layer is a SiOx insulating layer; and the VA insulating layer and the CH insulating layer are SiOx and SiNx insulating layers.

[0022] Furthermore, the common electrode layer and the pixel electrode layer are made of ITO thin film material.

[0023] The present invention has the following advantages:

[0024] The method of the present invention uses a CH mask after the PV insulating layer is formed to expose and etch away the thickness of the PV insulating layer at the CH hole position of the AA area and the deep hole position of the Fanout without adding a mask, thereby avoiding over-etching damage to the touch metal layer due to inconsistent hole depths of the deep hole and the shallow hole when etching the CH deep and shallow holes, thereby ensuring the stability of the TFT device and the product yield; by leaving the Metal III touch metal layer at the PV hole, damage to the Metal II source and drain metal layer during etching is prevented, and the Metal III touch metal layer will not affect the SD-PE overlap conductivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0026] Figure 1a A schematic diagram of the structure of the AA area of ​​the array substrate for preventing over-engraving of the touch metal layer opening in the present invention;

[0027] Figure 1b A schematic diagram of the structure of the Fanout area of ​​the array substrate for preventing over-engraving of the touch metal layer opening in the present invention;

[0028] Figure 2 1 is a structural schematic diagram of step 1 in the manufacturing process of an array substrate according to an embodiment of the present invention;

[0029] Figure 3 Schematic diagram of the structure of step 2 in the manufacturing process of the array substrate according to an embodiment of the present invention;

[0030] Figure 4 Schematic diagram of the structure of step 3 in the manufacturing process of the array substrate according to an embodiment of the present invention;

[0031] Figure 5 is a structural schematic diagram of step 4 in the manufacturing process of the array substrate according to an embodiment of the present invention;

[0032] Figure 6 is a structural schematic diagram of step 5 in the manufacturing process of the array substrate according to an embodiment of the present invention;

[0033] Figure 7 is a structural schematic diagram of step 6 in the manufacturing process of the array substrate according to an embodiment of the present invention;

[0034] Figure 8 is a structural schematic diagram of step 7 in the manufacturing process of the array substrate according to an embodiment of the present invention;

[0035] Fig. 9 is a structural schematic diagram of step 8 in the manufacturing process of the array substrate according to an embodiment of the present invention;

[0036] Fig.10 Schematic diagram of the structure of step 9 in the manufacturing process of the array substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0038] In order to solve the problem of damage caused by over-etching of the touch metal layer of the CH shallow hole in the Fanout area, the solution of the present invention uses a CH mask after PV film formation to expose and etch away the PV film thickness of the CH hole position in the AA area (Active Area) and the deep hole position of the Fanout without increasing the mask, thereby avoiding damage to the touch metal layer caused by over-etching due to inconsistent hole depths of the deep and shallow holes when etching the CH deep and shallow holes, thereby ensuring the stability of the TFT device and the product yield.

[0039] The embodiment of the present invention provides a method for manufacturing an array substrate for avoiding over-engraving of a touch metal layer opening as shown in FIG. 1 , wherein the array substrate also includes an AA area (such as Figure 1a ) and the array substrate of the Fanout region (such as Figure 1b ), the AA area is provided with CH holes, and the Fanout area is provided with CH deep holes and CH shallow holes. The array substrate manufacturing process is as follows Figure 2-Figure 10 As shown, specifically including:

[0040] Step 1, sequentially forming a Metal I gate metal layer (GE), a gate insulating layer (GI), an active layer (SE), a Metal II source and drain metal layer (SD) and a PV insulating layer (PV) on a substrate glass (Glass); wherein, in the Fanout region, the Metal I gate metal layer (GE) and the active layer (SE) are only formed at non-CH deep holes and non-CH shallow holes, and there is no GE or SE at the CH deep and shallow holes, such as Figure 2 shown.

[0041] Step 2: Based on step 1, use CH mask exposure to etch out PV holes; the number of etching layers is one PV layer, such as Figure 3After PV film formation, a CH mask is used to expose and etch away the PV film thickness at the CH hole position of the AA area (Active Area) and the deep hole position of the Fanout, thereby avoiding over-etching damage to the touch metal layer due to inconsistent hole depths of the deep and shallow holes when etching CH deep and shallow holes.

[0042] Step 3: Based on step 2, an organic planarization layer (OC) is formed, such as Figure 4 As shown; the organic planarization layer (OC) is mainly an organic material, covering the insulating layer, and is used to planarize the surface of the TFT device.

[0043] Step 4: Based on step 3, a Metal III touch metal layer (CM) is formed; at the same time, a Metal III touch metal layer (CM) is left at the PV hole, such as Figure 5 As shown in the figure, when the Metal III touch metal layer (CM) is formed and etched, the PV hole is not etched, thereby preventing the Metal II source and drain metal layer (SD) from being damaged during etching.

[0044] Step 5: Based on step 4, a VA insulating layer (VA) is formed, and then a VA hole is etched, such as Figure 6 shown.

[0045] Step 6: Based on step 5, a common electrode layer (BC) is formed in the touch area, such as Figure 7 shown.

[0046] Step 7: Based on step 6, a CH insulating layer (CH) is formed, such as Figure 8 shown.

[0047] Step 8: Based on step 7, the CH mask is used to perform exposure etching at the CH hole position in the AA area, the CH deep hole position in the Fanout area, and the CH shallow hole position to form a CH hole, a CH deep hole, and a CH shallow hole, respectively. The etching layers are two layers of VA insulating layer / CH insulating layer (VA / CH), such as Fig. 9 shown.

[0048] Step 8: Based on step 7, a pixel electrode layer (PE) is formed. Fig.10 shown.

[0049] In a possible implementation, the Metal I gate metal layer (GE) is Mo / Al / Mo or Ti / Al / Ti, the Metal II source and drain metal layer is Mo / Al / Mo or Ti / Al / Ti; and the Metal III touch metal layer is Mo / Al / Mo or Ti / Al / Ti.

[0050] In a possible implementation, the gate insulating layer (GI) is an insulating layer with a relatively large dielectric constant, and may be made of SiOx material; the active layer (SE) is made of a-Si, MOx, LTPS or IGZO.

[0051] In a possible implementation, the PV insulating layer is an insulating layer with a large dielectric constant, which is used to isolate the influence of water and oxygen on the semiconductor, and a SiOx insulating layer can be selected; the VA insulating layer and the CH insulating layer are SiOx and SiNx insulating layers. The etching gas for the SiOx insulating layer is CF4, and the etching gas for the SiNx insulating layer is SF6.

[0052] In a possible implementation, the common electrode layer (BC) and the pixel electrode layer (PE) are made of ITO thin film material.

[0053] The method of the present invention uses a CH mask after the PV insulating layer is formed to expose and etch away the thickness of the PV insulating layer at the CH hole position of the AA area and the deep hole position of the Fanout without adding a mask, thereby avoiding over-etching damage to the touch metal layer due to inconsistent hole depths of the deep hole and the shallow hole when etching the CH deep and shallow holes, thereby ensuring the stability of the TFT device and the product yield; by leaving the Metal III touch metal layer at the PV hole, damage to the Metal II source and drain metal layer during etching is prevented, and the Metal III touch metal layer will not affect the SD-PE overlap conductivity.

[0054] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing an array substrate to avoid over-engraving of a touch metal layer opening, characterized in that: Used to manufacture an array substrate including both an AA area and a Fanout area, wherein the AA area is provided with a CH hole, and the Fanout area is provided with a CH deep hole and a CH shallow hole; The method comprises the following steps: Step 1, sequentially forming a Metal I gate metal layer, a gate insulating layer, an active layer, a Metal II source and drain metal layer, and a PV insulating layer on a substrate glass; wherein, in the Fanout region, the Metal I gate metal layer and the active layer are formed only at non-CH deep holes and non-CH shallow holes; Step 2: Based on step 1, a PV hole is etched by using a CH mask for exposure; Step 3: Based on step 2, an organic planarization layer is formed; Step 4: Based on step 3, a Metal III touch metal layer is formed; at the same time, a Metal III touch metal layer is left at the PV hole to prevent damage to the Metal II source and drain metal layer during etching; Step 5: Based on step 4, a VA insulating layer is formed, and then a VA hole is etched; Step 6: Based on step 5, a common electrode layer is formed in the touch control area; Step 7: Based on step 6, a CH insulating layer is formed; Step 8, based on step 7, using the CH mask to perform exposure etching at the CH hole position in the AA area, the CH deep hole position in the Fanout area, and the CH shallow hole position, to form a CH hole, a CH deep hole, and a CH shallow hole respectively; Step 9: Based on step 8, a pixel electrode layer is formed.

2. The method according to claim 1, characterized in that: In the step 2, a CH mask is used for exposure and etching of a PV hole, and the number of etching layers is one layer.

3. The method according to claim 1, characterized in that: In step 7, the CH mask is used to perform exposure etching at the CH hole position in the AA area, the CH deep hole position in the Fanout area, and the CH shallow hole position, and the number of etching layers is two.

4. The method according to claim 1, characterized in that: The Metal I gate metal layer is Mo / Al / Mo or Ti / Al / Ti, the Metal II source and drain metal layer is Mo / Al / Mo or Ti / Al / Ti; the Metal III touch metal layer is Mo / Al / Mo or Ti / Al / Ti.

5. The method according to claim 1, characterized in that: The gate insulating layer is made of SiOx material; the active layer is made of a-Si, MOx, LTPS or IGZO.

6. The method according to claim 1, characterized in that: The PV insulating layer is a SiOx insulating layer; the VA insulating layer and the CH insulating layer are SiOx and SiNx insulating layers.

7. The method according to claim 1, characterized in that: The common electrode layer and the pixel electrode layer are made of ITO thin film material.

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