Semiconductor structure, semiconductor device and method of manufacturing the same

Abstract

Disclosed herein are epitaxial source / drain structures for enhancing performance of multi-gate devices such as fin field effect transistors (FETs) or gate-all-around (GAA) FETs and methods of fabricating the epitaxial source / drain structures. An exemplary source / drain structure extends from a topmost channel layer to a depth in a semiconductor substrate. The source / drain structure includes an undoped epitaxial layer having a trough-shaped top surface, a first doped epitaxial layer above the undoped epitaxial layer, a second doped epitaxial layer above the first doped epitaxial layer, and a third doped epitaxial layer above the second doped epitaxial layer. The thickness of the undoped epitaxial layer is less than the depth of the epitaxial source / drain structure into the semiconductor substrate. The thickness and the depth are adjusted based on the dimensions of the active region to which the epitaxial source / drain structure belongs, such that the epitaxial source / drain structure mitigates short channel effects while optimizing performance. Embodiments of the present application also relate to semiconductor structures, semiconductor devices, and methods of fabricating the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures, semiconductor devices, and methods of manufacturing the same. Background Technology

[0002] In recent years, multi-gate devices have been introduced, featuring gates that extend partially or completely around the channel to provide access to the channel on at least both sides, thereby improving gate control. Multi-gate devices can significantly reduce IC technology, maintain gate control, and mitigate short-channel effects (SCE), while seamlessly integrating with traditional IC manufacturing processes. However, as multi-gate devices continue to proliferate, advanced technologies are needed to optimize their reliability. Therefore, while existing multi-gate devices and the methods used to manufacture them are generally sufficient to meet their intended purposes, they are not entirely satisfactory in all aspects. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor structure, including: a semiconductor substrate; a first channel layer, a first gate, and a first epitaxial source / drain structure, wherein the first gate is located above the first channel layer, and the first epitaxial source / drain structure is adjacent to the first channel layer, wherein the first channel layer, the first gate, and the first epitaxial source / drain structure are located above the semiconductor substrate, and further wherein the first epitaxial source / drain structure includes: a first undoped semiconductor layer and a first doped semiconductor layer located above the first undoped semiconductor layer, wherein the first undoped semiconductor layer is located between the first doped semiconductor layer and the semiconductor substrate; a second channel layer, a second gate, and a second epitaxial source / drain structure, wherein the second gate is located above the second channel layer, and the second epitaxial source / drain structure is located above the second channel layer. The drain structure is adjacent to the second channel layer, wherein the second channel layer, the second gate, and the second epitaxial source / drain structure are located above the semiconductor substrate, and further wherein the second epitaxial source / drain structure includes: a second undoped semiconductor layer and a second doped semiconductor layer located above the second undoped semiconductor layer, wherein the second undoped semiconductor layer is located between the second doped semiconductor layer and the semiconductor substrate; wherein the first undoped semiconductor layer extends to a first depth in the semiconductor substrate, the second undoped semiconductor layer extends to a second depth in the semiconductor substrate, and the second depth is different from the first depth; and wherein the first channel layer has a first channel length, the second channel layer has a second channel length, and the second channel length is different from the first channel length.

[0004] Some other embodiments of this application provide a semiconductor device, including: a first transistor having a first channel layer, a first gate surrounding the first channel layer, and a first epitaxial source / drain structure disposed adjacent to the first channel layer, wherein the first channel layer, the first gate, and the first epitaxial source / drain structure are disposed above a semiconductor substrate, and the first epitaxial source / drain structure includes: a first undoped epitaxial layer having a first groove-shaped top surface, and a first doped epitaxial layer having a first internal portion and a first external portion, the first internal portion having a first dopant concentration and the first external portion having a second dopant concentration, wherein the second dopant concentration is less than the first dopant concentration, and the first external portion of the first doped epitaxial layer is disposed between the first undoped epitaxial layer and the first doped epitaxial layer. Between the first internal portions of the epitaxial layer, a second transistor has a second channel layer, a second gate surrounding the second channel layer, and a second epitaxial source / drain structure disposed adjacent to the second channel layer. The second channel layer, the second gate, and the second epitaxial source / drain structure are disposed above the semiconductor substrate. The second epitaxial source / drain structure includes: a second undoped epitaxial layer having a second trench top surface configured differently from the first trench top surface, and a second doped epitaxial layer having a second internal portion and a second external portion. The second internal portion has a first dopant concentration, and the second external portion has a second dopant concentration. The second external portion of the second doped epitaxial layer is disposed between the second undoped epitaxial layer and the second internal portion of the second doped epitaxial layer.

[0005] Further embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a first source / drain trench extending through a first semiconductor layer to a first depth in a semiconductor substrate and a second source / drain trench extending through a second semiconductor layer to a second depth in a semiconductor substrate, wherein the first depth is different from the second depth, the first source / drain trench is located in a first active region of a first size, and the second source / drain trench is located in a second active region of a second size different from the first size; forming a first undoped epitaxial layer in the first source / drain trench and forming a second undoped epitaxial layer in the second source / drain trench, wherein a first thickness of the first undoped epitaxial layer is less than the first depth, and a second thickness of the second undoped epitaxial layer is less than the second depth; and forming a first doped epitaxial layer in the first source / drain trench and over the first undoped epitaxial layer, and forming a second doped epitaxial layer in the second source / drain trench and over the second undoped epitaxial layer. Attached Figure Description

[0006] The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a flowchart of a method for manufacturing a multi-gate device with an enhanced epitaxial source / drain structure according to various aspects of the present invention.

[0008] Figures 2A to 2H It is according to various aspects of the present invention in relation to Figure 1 Partial cross-sectional views of multi-gate devices with enhanced epitaxial source / drain structures in some or all of the various manufacturing stages related to the method described in the article.

[0009] Figures 3A to 3I It is according to various aspects of the present invention in relation to Figure 1 Partial three-dimensional view of a multi-gate device with enhanced epitaxial source / drain structure in part or all of the various manufacturing stages related to the method described in the article.

[0010] Figures 4A to 4C It is according to various aspects of the present invention in relation to Figure 1 Partial cross-sectional views of multi-gate devices with different active region sizes in some or all of the various manufacturing stages related to the method.

[0011] Figure 5 It is possible to use various aspects of the present invention. Figure 1 A partial cross-sectional view of another multi-gate device with an enhanced epitaxial source / drain structure, fabricated by the method described in the article. Detailed Implementation

[0012] The present invention generally relates to epitaxial source / drain structures and methods thereof for enhancing the performance of multi-gate devices such as fin field-effect transistors (FETs) or gate all-around (GAA) FETs.

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one component and another in the invention. Spatially relative terms are intended to cover different orientations of the device including the components. Furthermore, when numerical values ​​or ranges are described using terms such as “about,” “approximately,” etc., as will be understood by those skilled in the art, the term is intended to cover values ​​within a reasonable range that takes into account inherent variations during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having numerically related characteristics, the numerical value or range of numerical values ​​encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer with a thickness of "about 5 nm" can cover a size range from 4.5 nm to 5.5 nm, where the manufacturing tolerances associated with the deposited material layer are + / - 10%, as known to those skilled in the art. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Figure 1 This is a flowchart of a method 10 for manufacturing a multi-gate device with an enhanced epitaxial source / drain structure according to various aspects of the present invention. Figures 2A to 2H It is according to various aspects of the present invention in relation to Figure 1 A partial cross-sectional view of a multi-gate device 100 having an enhanced epitaxial source / drain structure in part or all of the various manufacturing stages related to method 10. Figures 3A to 3I It is according to various aspects of the present invention in relation to Figure 1 A partial perspective view of a portion or all of the multi-gate device 100 at various manufacturing stages related to the method described in the paper. Figure 3A and Figure 3B and Figure 2A The manufacturing stage corresponds to (where Figure 2A It is along Figure 3B (The line A-A' is intercepted). Figure 3C and Figure 2B The manufacturing stage corresponds to (where Figure 2B It is along Figure 3C (The line A-A' is intercepted). Figure 3D and Figure 2C The manufacturing stage corresponds to (where Figure 2C It is along Figure 3D (The line A-A' is intercepted). Figure 3E and Figure 2D The manufacturing stage corresponds to (where Figure 2D It is along Figure 3E (The line A-A' is intercepted). Figure 3F and Figure 2E The manufacturing stage corresponds to (where Figure 2E It is along Figure 3F (The line A-A' is intercepted). Figure 3G and Figure 2F The manufacturing stage corresponds to (where Figure 2F It is along Figure 3G (The line A-A' is intercepted). Figure 3H and Figure 2G The manufacturing stage corresponds to (where Figure 2G It is along Figure 3H (The line A-A' is intercepted), and Figure 3I and Figure 2H The manufacturing stage corresponds to (where Figure 2H It is along Figure 3I (The line A-A' is intercepted). Figures 4A to 4C It is according to various aspects of the invention at various manufacturing stages (e.g., with) Figure 1 Partial cross-sectional views of multi-gate devices with different active region sizes (related to the methods described). In some embodiments, Figure 4A and Figure 2C Corresponding to the manufacturing stage, Figure 4B and Figure 2E Corresponding to the manufacturing stage, and Figure 4C and Figure 2G The corresponding manufacturing stage.

[0015] The multi-gate device 100 includes at least one GAA transistor (i.e., a transistor having a gate surrounding at least one floating channel (e.g., nanowire, nanosheet, nanorod, etc.), wherein the at least one floating channel extends between an epitaxial source / drain). In some embodiments, the multi-gate device 100 is configured with at least one p-type GAA transistor and at least one n-type GAA transistor. The multi-gate device 100 may be included in a microprocessor, memory, and / or other IC device. In some embodiments, the multi-gate device 100 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which includes a variety of passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. For ease of description and understanding, this document also discusses... Figure 1 , Figures 2A to 2G , Figures 3A to 3I and Figures 4A to 4C For clarity, it has been simplified. Figure 1 , Figures 2A to 2G , Figures 3A to 3I and Figures 4A to 4C To better understand the inventive concept of the present invention. Additional steps may be provided before, during, and after method 10, and for additional embodiments of method 10, some of the described steps may be moved, replaced, or eliminated. Additional components may be added to the multi-gate device 100, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 100.

[0016] Transfer to Figure 1 and Figure 2A (and corresponding) Figure 3A and Figure 3B Method 10 begins by receiving a multi-gate device precursor for the multi-gate device 100 in block 15. Figure 2A In the middle, the multi-gate device 100 has undergone with Figure 3A and Figure 3B The associated process, and the multi-gate device precursor, includes a semiconductor substrate (wafer) 105, a semiconductor layer stack 110 (having semiconductor layers 115, 120, and fin portions 105' of the semiconductor substrate 105 (i.e., patterned, protruding portions of the semiconductor substrate 105)), an isolation component 125, and dummy gates 130A-130C (typically referred to as dummy gates 130). For example, the semiconductor layer stack 110 is constructed by depositing semiconductor layers 115 and 120 (e.g., fins 105' of the semiconductor substrate 105) over the substrate 105. Figure 3A(as depicted in the image) and patterning semiconductor layer 115, semiconductor layer 120 and substrate 105 to form a semiconductor layer stack 110 extending from substrate 105 (as shown in the image). Figure 3B The substrate 105 is formed as depicted in the illustration. The substrate 105 includes: elemental semiconductors, such as silicon and / or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In the depicted embodiment, the substrate 105 includes silicon. The substrate 105 (including fin portion 105') may include various doped regions, such as p-type doped regions (referred to as p-wells), n-type doped regions (referred to as n-wells), or combinations thereof. In some embodiments, fin portion 105' includes p-wells (such as where an n-type transistor is formed in transistor region 106A) and n-wells (such as where a p-type transistor is formed in transistor region 106B), or vice versa. n-wells include n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. p-wells include p-type dopants, such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, the doped regions in the substrate 105 (and fin portion 105') include a combination of p-type and n-type dopants. The individual doped regions can be formed directly on and / or in the substrate 105 (and fin portion 105'), for example, providing p-well structures, n-well structures, double-well structures, bump structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be implemented to form the individual doped regions.

[0017] exist Figure 3AIn this configuration, semiconductor layers 115 and 120 are stacked vertically (e.g., along the z-direction) from the top surface of substrate 105 in a staggered or alternating arrangement. In some embodiments, deposition includes epitaxially growing semiconductor layers 115 and 120 in the depicted staggered and alternating arrangement. For example, a first of semiconductor layers 115 is epitaxially grown on substrate 105, a first of semiconductor layers 120 is epitaxially grown on the first of semiconductor layers 115, a second of semiconductor layers 115 is epitaxially grown on the first of semiconductor layers 120, and so on, until the semiconductor layer stack 110 has a desired number of semiconductor layers 115 and 120. In such embodiments, semiconductor layers 115 and 120 may be referred to as epitaxial layers. In some embodiments, the epitaxial growth of semiconductor layers 115 and 120 is achieved by molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), other suitable epitaxial growth processes, or combinations thereof. Semiconductor layer 115 has a different composition than semiconductor layer 120 to achieve different etch selectivity and / or different oxidation rates during subsequent processes. Semiconductor layers 115 and 120 include different materials, atomic percentages of components, weight percentages of components, thicknesses, and / or properties to achieve desired etch selectivity during etching processes, such as etching processes implemented to form a floating channel layer in the channel region of a multi-gate device. For example, in the case where semiconductor layer 115 comprises silicon-germanium and semiconductor layer 120 comprises silicon, for a given etchant, the silicon etch rate of semiconductor layer 120 is less than the silicon-germanium etch rate of semiconductor layer 115. In some embodiments, semiconductor layers 115 and 120 comprise the same materials but have different atomic percentages of components to achieve etch selectivity and / or different oxidation rates. For example, semiconductor layers 115 and 120 may comprise silicon-germanium, wherein semiconductor layers 115 and 120 have different silicon atomic percentages and / or different germanium atomic percentages. Semiconductor layer 115 and semiconductor layer 120 include any combination of semiconductor materials that provide desired etch selectivity, desired oxidation rate difference and / or desired performance characteristics (e.g., materials that maximize current), including any semiconductor materials disclosed herein.

[0018] exist Figure 2A and Figure 3BIn the process, after patterning, the semiconductor layer stack 110 includes a fin portion 105' of the substrate 105 (also referred to as a substrate extension portion, substrate fin portion, fin portion, etched substrate portion, etc.) and a semiconductor layer stack portion disposed above the fin portion 105' (i.e., the portion of the semiconductor layer stack 110 including semiconductor layers 115 and 120). The semiconductor layer stack 110 extends substantially along the x-direction and has a length along the x-direction, a width along the y-direction, and a height along the z-direction. In some embodiments, photolithography and / or etching processes are performed to pattern the semiconductor layers 115, 120, and substrate 105 to form the semiconductor layer stack 110. The photolithography process may include forming a resist layer (e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (such as ultraviolet (UV), deep UV (DUV), or extreme UV (EUV) light), where the mask blocks, transmits, and / or reflects radiation to the resist layer, depending on the mask pattern and / or mask type (e.g., binary mask, phase-shift mask, or EUV mask), thereby projecting an image onto the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiant energy, the exposed portions of the resist layer undergo chemical changes, and the exposed (or unexposed) portions of the resist layer dissolve during the development process, depending on the properties of the resist layer and the properties of the developer used in the development process. After development, the patterned resist layer comprises a resist pattern corresponding to the mask. The etching process uses the patterned resist layer as an etching mask to remove portions of semiconductor layer 120, semiconductor layer 115, and substrate 105. In some embodiments, a patterned resist layer is formed over a mask layer disposed above the semiconductor layer stack 110. A first etching process removes a portion of the mask layer to form the patterned layer (i.e., a patterned hard mask layer), and a second etching process uses the patterned layer as an etching mask to remove a portion of the semiconductor layer stack 110. The etching process may include dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process is a reactive ion etching (RIE) process. After the etching process, the patterned resist layer is removed, for example, by a resist stripping process or other suitable process.Optionally, the semiconductor layer stack 110 is formed using multiple patterning processes, such as dual patterning lithography (DPL) processes (e.g., lithography-etch-lithography-etch (LELE) process, self-aligned dual patterning (SADP) process, spacer-dielectric (SID) process, other dual patterning processes, or combinations thereof), triple patterning processes (e.g., lithography-etch-lithography-etch-lithography-etch (LELELE) process, self-aligned triple patterning (SATP) process, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some embodiments, directional self-assembly (DSA) technology is performed concurrently with the formation of the semiconductor layer stack 110. Furthermore, in some embodiments, the exposure process may perform maskless lithography, electron beam (e-beam) writing, and / or ion beam writing for patterning the resist layer. In some embodiments, the semiconductor layer stack 110 is formed by a fin manufacturing process, and the semiconductor layer stack 110 may be referred to as a fin, fin structure, fin element, active fin region, active region, etc.

[0019] In some embodiments, after patterning, trenches surround the semiconductor layer stack 110, thereby separating the semiconductor layer stack 110 from other active regions of the multi-gate device 100. In such embodiments (e.g., Figure 3BThe isolation member 125 can be formed in the trench by depositing an insulating material filling the trench over the substrate 105 (e.g., using a CVD process or a spin-coating glass process) and performing a chemical mechanical polishing (CMP) process to remove excess insulating material and / or planarize the top surface of the isolation member 125. The deposition process can be a flowable CVD (FCVD) process, a high aspect ratio deposition (HARP) process, a high density plasma CVD (HDPCVD) process, other suitable deposition processes, or combinations thereof. In some embodiments, the CMP process removes the insulating material over the top surface of the semiconductor layer stack 110. In some embodiments, the insulating material is etched back, such that a portion of the semiconductor layer stack 110 extends from the isolation member 125 (i.e., the top surface of the semiconductor layer stack 110 is higher than the top surface of the isolation member 125). In some embodiments, the isolation member 125 has a multilayer structure, such as an oxide layer disposed over a silicon nitride pad. In some embodiments, the isolation component 125 includes a dielectric layer disposed above a doped pad (including, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG)). In some embodiments, the isolation component 125 includes a bulk dielectric layer disposed above the dielectric pad. The isolation component 125 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components) or combinations thereof. The isolation component 125 may be configured as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a localized oxidation of silicon (LOCOS) structure, and / or other suitable isolation structures.

[0020] exist Figure 2A and Figure 3B In this process, dummy gates 130A-130C are formed above the channel region of the semiconductor layer stack 110, such that the dummy gates 130A-130C are disposed between the source / drain regions of the semiconductor layer stack 110. The dummy gates 130A-130C extend longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the semiconductor layer stack 110. For example, the dummy gates 130A-130C extend substantially parallel to each other in the y-direction, having a length in the y-direction, a width in the x-direction, and a height in the z-direction. In the XZ plane (… Figure 2A In the YZ plane, as depicted, dummy gates 130A-130C are disposed on the top surface of the semiconductor layer stack 110. Figure 3BIn this configuration, dummy gates 130A-130C can be disposed above the top and sidewall surfaces of the semiconductor layer stack 110, thereby enclosing the semiconductor layer stack 110. Each of the dummy gates 130A-130C includes a dummy gate dielectric, a dummy gate electrode, and a hard mask. The dummy gate dielectric includes a dielectric material. In some embodiments, the dummy gate dielectric includes an interface layer (including, for example, silicon oxide) and a dielectric layer disposed above the interface layer. The dummy gate electrode includes a suitable dummy gate material, and the hard mask includes a suitable hard mask material. In some embodiments, the dummy gate electrode includes a polysilicon layer, and the hard mask includes a silicon nitride layer. The dummy gates 130A-130C may include other layers, such as a capping layer, an interface layer, a diffusion layer, a barrier layer, or a combination thereof.

[0021] The dummy gates 130A-130C are formed by deposition, photolithography, etching, other suitable processes, or combinations thereof. For example, a first deposition process is performed to form a dummy gate dielectric layer over the multi-gate device 100, a second deposition process is performed to form a dummy gate electrode layer over the dummy gate dielectric layer, and a third deposition process is performed to form a hard mask layer over the dummy gate electrode layer. Deposition processes include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), MOCVD, remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), HDPCVD, FCVD, HARP, low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), subatmospheric pressure CVD (SACVD), other suitable deposition processes, or combinations thereof. Photolithographic patterning and etching processes are then performed to pattern the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer to form the dummy gates 130A-130C, including the dummy gate dielectric, the dummy gate electrode, and the hard mask. Photolithography patterning processes may include resist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, resist development, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Etching processes may include dry etching, wet etching, other etching processes, or combinations thereof.

[0022] Transfer to Figure 2B (and corresponding) Figure 3C )and Figure 2C (and corresponding) Figure 3D ), forming with pseudo-gate 130A-130C ( Figure 2B ( Figure 3C )and Figure 2C ( Figure 3D Adjacent (i.e., along its sidewalls) gate spacers 132, and in the source / drain regions of the semiconductor layer stack 110 ( Figure 2C ( Figure 3DThis forms source / drain grooves (trenches) 140. Figure 2B ( Figure 3C In this configuration, a spacer layer 132' is formed over the multi-gate device 100. For example, a dielectric layer is formed over the semiconductor layer stack 110, the isolation component 125, and the dummy gates 130A-130C by a deposition process such as CVD, PECVD, ALD, PEALD, PVD, other suitable deposition processes, or combinations thereof. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable spacer components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, silicon carbonitride boron, etc.). In some embodiments, the spacer layer 132' is a single layer, such as a dielectric layer comprising silicon and nitrogen (which may be referred to as a silicon nitride layer). In some embodiments, the spacer layer 132' comprises multiple layers, such as a first dielectric layer (e.g., a silicon carbonitride layer) formed by a first deposition process and a second dielectric layer (e.g., a silicon nitride layer) formed over the first dielectric layer by a second deposition process. In some embodiments, the spacer layer 132' has a substantially uniform thickness along the top surface and sidewalls of the dummy gates 130A-130C and the semiconductor layer stack 110. For example, the thickness of the spacer layer 132' along the top surface of the semiconductor layer stack 110, the top surface of the dummy gates 130A-130C, the sidewalls of the semiconductor layer stack 110, and the sidewalls of the dummy gates 130A-130C is substantially the same. In some embodiments, the spacer layer 132' is formed by a conformal deposition process, such that the spacer layer 132' conforms to the surface of the multi-gate device 100 on which the spacer layer 132' is deposited (and thus can be referred to as a conformal spacer layer).

[0023] exist Figure 2C ( Figure 3DIn this process, spacer etching is performed on spacer layer 132' to form gate spacers 132 along the sidewalls of dummy gates 130A-130C, and source / drain etching is performed (e.g., in block 20 of method 10) to form source / drain recesses 140 in the source / drain regions of semiconductor layer stack 110 in transistor regions 106A and 106B, respectively. Spacer etching substantially removes spacer layer 132' from horizontal (lateral) surfaces of multi-gate device 100, such as the top surface of semiconductor layer stack 110, the top surface of isolation member 125, and the top surface of dummy gates 130A-130C, thereby forming corresponding gate spacers 132 along the sidewalls of dummy gates 130A-130C. In some embodiments, spacer etching may remove a portion of semiconductor layer stack 110, thereby initiating the formation of source / drain recesses 140 in semiconductor layer stack 110. In some embodiments, spacer etching selectively removes spacer layer 132' relative to dummy gates 130A-130C, isolation member 125, and / or semiconductor layer stack 110. In other words, spacer etching substantially removes spacer layer 132', but does not remove or substantially does not remove dummy gates 130A-130C, isolation member 125, and / or semiconductor layer stack 110. In some embodiments, gate spacer 132 includes more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers. For example, in the case where spacer layer 132' includes a first dielectric layer and a second dielectric layer, gate spacer 132 may include a spacer liner (e.g., an L-shaped liner) formed of the first dielectric layer and a main spacer formed of the second dielectric layer. Implantation, diffusion, and / or annealing processes can be performed to form lightly doped source and drain (LDD) components and / or heavily doped source and drain (HDD) components in the source / drain regions of the semiconductor layer stack 110 before and / or after the formation of the gate spacer 132.

[0024] Source / drain etching removes exposed portions of the semiconductor layer stack 110 (i.e., source / drain regions of the semiconductor layer stack 110 not covered by dummy gates 130A-130C and gate spacers 132) to form source / drain grooves 140 extending through the semiconductor layer stack 110 to a depth in the substrate 105 (e.g., depth in the fin portion 105'). Figure 2CIn the process, the etching process completely removes semiconductor layers 115 and 120 in the source / drain regions of the semiconductor layer stack 110, as well as some, but not all, of the fin portions 105' in the source / drain regions of the semiconductor layer stack 110, such that the source / drain groove 140 extends into the fin portion 105' but does not penetrate the fin portion 105'. When the source / drain groove 140 extends into the fin portion 105' and / or the substrate 105, as depicted, the channel region of the semiconductor layer stack 110 has a protrusion formed by the fin portion 105' and / or the substrate 105 in the XZ plane (hereinafter referred to as semiconductor mesa 105P'), and the source / drain regions of the semiconductor layer stack 110 have a recess formed by the fin portion 105' and / or the substrate 105 in the XZ plane. Therefore, the source / drain recess 140 is formed by the sidewalls of the adjacent channel regions of the semiconductor layer stack 110 and the top of the remaining, recessed portions of the fin portions 105' and / or the substrate 105 in the source / drain regions of the semiconductor layer stack 110. In some embodiments, the source / drain recess 140 has a U-shaped cross-sectional profile, wherein the substantially linear, sidewall, and / or vertical portions of the U-shaped cross-sectional profile are formed by the adjacent channel regions of the semiconductor layer stack 110, and the substantially curved, bottom, and / or horizontal portions of the U-shaped cross-sectional profile are formed by the fin portions 105' and / or the substrate 105 (e.g., the adjacent semiconductor mesa 105P' in the channel regions of the semiconductor layer stack 110 and the remaining, recessed portions of the fin portions 105' and / or the substrate 105 in the source / drain regions of the semiconductor layer stack 110 extending between the adjacent semiconductor mesa 105P').

[0025] The source / drain recess 140 has a width W in the x-direction between the sidewalls of adjacent channel regions of the semiconductor layer stack 110 and a depth D in the z-direction between the top surface of the semiconductor layer stack 110 and the bottommost portion of the source / drain recess 140. The depth D is the sum of the height h of the semiconductor layer stack 110 and the depth d of the source / drain recess 140 to the substrate 105. The depth d corresponds to the height of the semiconductor mesa 105P', which lies between the top surface of the semiconductor mesa 105P' and the bottommost portion of the source / drain recess 140. In embodiments where the depth d is less than the fin portion 105', the semiconductor mesa 105P' is formed by the fin portion 105'. In embodiments where the depth d is greater than the fin portion 105', the semiconductor mesa 105P' is formed by the fin portion 105' and the substrate 105. In some embodiments, the depth d is about 20 nm to about 100 nm. The height h can be configured to optimize the performance and / or fabrication of multi-gate devices. For example, after source / drain etching, the remaining portion of the semiconductor layer stack 110 (i.e., the channel region) has a finned structure. If the fins are too high, they are prone to bending and / or collapse, which can affect manufacturing reliability and / or device reliability. On the other hand, because higher fins contribute to higher drive currents, fins that are too short cannot provide a multi-gate device with the desired performance characteristics. For example, shorter fins will have fewer semiconductor layers and thus limit the number of channels in a multi-gate device, which correspondingly limits the drive current of the multi-gate device. In the depicted embodiment, the height h is from about 30 nm to about 80 nm, where a height h greater than about 80 nm may cause undesirable bending and / or collapse of the remaining portion of the semiconductor layer stack 110, and a height h less than about 30 nm will not provide a multi-gate device with sufficiently high drive currents and / or other optimal performance characteristics manufactured from the semiconductor layer stack 110.

[0026] Source / drain etching includes dry etching, wet etching, other suitable etching processes, or combinations thereof. Various etching parameters can be adjusted to selectively etch the semiconductor layer stack 110 (i.e., semiconductor layer 120, semiconductor layer 115, and fin portion 105') while minimally (or not at all) etching the dummy gates 130A-130C, gate spacers 132, and / or isolation portions 125. These parameters include etching gas composition, carrier gas composition, etching gas flow rate, carrier gas flow rate, etching time, etching pressure, etching temperature, source power, radio frequency (RF) bias voltage, direct current (DC) bias voltage, RF bias power, DC bias power, other suitable etching parameters, or combinations thereof. For example, an etchant is selected for source / drain etching that can remove the material of the semiconductor layer stack 110 (e.g., semiconductor materials such as silicon germanium and silicon) at a higher rate than the material of the dummy gates 130A-130C and / or the gate spacer 132 (e.g., dielectric materials such as silicon oxide and / or polycrystalline silicon materials) (i.e., the etchant has high etch selectivity relative to the material of the semiconductor layer stack 110). In some embodiments, the etch gas for source / drain etching includes CH4, CHF3, O2, HBr, SiCl4, SO2, SF6, He, H2, other suitable etch gas components, or combinations thereof. In some embodiments, source / drain etching is dry etching performed using a fluorine-containing etch gas (e.g., CHF3 and / or SF6) and an oxygen-containing etch gas (e.g., O2). In some embodiments, source / drain etching is performed at an etching temperature of about 25°C to about 152°C. In some embodiments, source / drain etching is performed at an etch pressure of about 5 mTorr to about 100 mTorr. In some embodiments, source / drain etching is a multi-step etching process. For example, source / drain etching may use alternating etchants to remove semiconductor layers 115 and 120 individually and alternately. In some embodiments, photolithography processes, such as those described herein, are performed to form a patterned mask layer covering dummy gates 130A-130C and / or isolation member 125, and source / drain etching uses the patterned mask layer as an etching mask. In some embodiments, source / drain etching removes all fin portions 105' of the source / drain regions of the semiconductor layer stack 110, such that the source / drain recess 140 extends to or below the bottom surface of the isolation member 125. In some embodiments, spacer etching and source / drain etching are single etching processes. In some embodiments, spacer etching and source / drain etching are separate, sequential etching processes.

[0027] Short-channel effects (SCE) impact the reliability and predictability of transistor performance, such as threshold voltage, leakage current, current-voltage behavior, and / or other performance characteristics. Because SCE is highly dependent on channel length, devices with small active regions are therefore more sensitive to SCE than those with large active regions. The epitaxial source / drain fabrication techniques described herein, relative to a height h and a configuration depth d, to minimize and / or mitigate SCE depend on the size of the active region of a multi-gate device (for transistors, for the purposes of this invention, typically includes a channel region disposed between the source and drain regions). For example, turn to... Figure 4A Multi-gate devices S with small active regions and L with large active regions are configured to have different heights relative to height h to minimize SCE, as further described below. For the purposes of this invention, a small active region device generally refers to an active region having a width W1 of less than or equal to about 30 nm (and / or a channel length (i.e., the length of semiconductor layer 120 along the x-direction) of less than or equal to about 20 nm), and a large active region refers to an active region having a width W2 of greater than about 30 nm (and / or a channel length (i.e., the length of semiconductor layer 120 along the x-direction) of greater than about 20 nm). In some embodiments, multi-gate device S is a transistor of a memory, such as static random access memory (SRAM). In some embodiments, multi-gate device L is a transistor of an input / output (I / O) device. In some embodiments, multi-gate device S and / or multi-gate device L is a transistor of a ring oscillator (RO) device. This invention contemplates multi-gate device S and / or multi-gate device L as transistors of other types of integrated circuit (IC) devices.

[0028] exist Figure 4AIn it, the multi-gate device S (i.e., the small active region device) has a semiconductor mesa 105P' (with a height H1 less than the height h (H1 < h)), and the multi-gate device L (i.e., the large active region device) has a semiconductor mesa 105P' (with a height H2 greater than the height h (i.e., H2 > h)). In other words, the depth d of the source / drain groove 140 in the multi-gate device S is less than the depth d of the source / drain groove 140 in the multi-gate device L, the depth d of the source / drain groove 140 in the multi-gate device S is less than the height h, and the depth d of the source / drain groove 140 in the multi-gate device L is greater than the height h. In some embodiments, the height H1 is less than the thickness of the fin portion 105', and the height H2 is greater than the thickness of the fin portion 105'. In some embodiments, the ratio of the height h to the height H1 (i.e., h / H1) is greater than 1, and the ratio of the height h to the height H2 (i.e., h / H2) is less than 1. For example, the ratio of the height h to the height H1 is from about 1 to about 4 and / or the ratio of the height h to the height H2 is from about 0.5 to about 0.9. In some embodiments, the difference between the height h and the height H1 (i.e., Δheight-S = │h – H1│) is from about 5 nm to about 30 nm. In some embodiments, the difference between the height h and the height H2 (i.e., Δheight-L = │h - H2│) is from about 10 nm to about 50 nm. In some embodiments, H1 is from about 20 nm to about 30 nm, where H1 less than 20 nm cannot provide sufficient volume in the substrate 105 for the subsequently formed undoped epitaxial source / drain layer to mitigate SCE for the small active region device, and H1 greater than 30 nm unnecessarily increases the manufacturing / production time and / or cost, while mitigating minimal additional SCE for the small active region device. In some embodiments, H2 is from about 35 nm to about 100 nm, where H2 less than 35 nm cannot provide sufficient volume in the substrate 105 for the subsequently formed undoped epitaxial source / drain layer to mitigate SCE for the large active region device, and H2 greater than 100 nm unnecessarily increases the manufacturing / production time and / or cost, while mitigating minimal additional SCE for the large active region device.

[0029] The small active region device is configured to have a shallower source / drain recess 140 (e.g., H1 < H2) than the large active region device, recognizing that the small active region device and the large active region device have different sensitivities to SCE. For example, since SCE can increase as the depth d of the source / drain recess 140 increases (e.g., because an increase in the source / drain depth results in an increase in the depth and / or volume of the epitaxial source / drain structure in the substrate 105), as the depth d of the source / drain recess 140 increases, the small active region device (i.e., shorter channel length) may be more sensitive to SCE. However, since the large active region device (i.e., longer channel length) is less sensitive to SCE than the small active region device, the large active region device is less sensitive to an increase in the depth of the source / drain recess. Thus, configuring the large active region device to have the same source / drain depth as the small active region device unnecessarily limits the operating flexibility of the large active region device. For example, since the source / drain depth affects the depth and / or volume of the epitaxial source / drain structure, a shallower source / drain depth results in a smaller epitaxial source / drain structure and thus a smaller strain applied to the channel region, which may limit the drive current of the transistor. Limiting the source / drain depth of the large active region device to the source / drain depth that optimizes the performance of the small active region device (e.g., by mitigating SCE) thus limits the performance improvement that can be achieved by the larger epitaxial source / drain structure provided by the deeper source / drain recess, even though the large active region device is insensitive to SCE at such a depth. Thus, the source / drain etching of the epitaxial source / drain manufacturing techniques described herein is adjusted based on the active region size to optimize the source / drain profile of the source / drain recess 140 (e.g., to provide different source / drain depths and / or different height ratios for the small active region device and the large active region device to mitigate SCE while optimizing performance). In some embodiments, the source / drain profile can be such that the simultaneously formed undoped epitaxial layer 152 has different profiles based on the active region size, where the different profiles can specifically enhance performance and / or mitigate the short channel effect of the active region of its corresponding size.

[0030] In some embodiments, source / drain etching is a cyclic photolithography / etching process. For example, source / drain etching may include: performing a first photolithography process to form a first masking layer covering a small active region device (e.g., including a multi-gate device S) and exposing a large active region device (e.g., including a multi-gate device L); performing the first source / drain etching to form a source / drain groove of height H2 in the source / drain region of the large active region device, wherein height H2 is greater than height h; removing the first masking layer; performing a second photolithography process to form a second masking layer exposing the small active region device (e.g., including a multi-gate device S) and covering the large active region device (e.g., including a multi-gate device L); performing the second source / drain etching to form a source / drain groove of height H1 in the source / drain region of the small active region device, wherein height H1 is less than height h; and removing the second masking layer.

[0031] Transfer to Figures 2D to 2F (and its corresponding Figures 3E to 3G An internal spacer 148' is formed below the gate spacer 132, between the semiconductor layers 120, and along the sidewall of the semiconductor layer 115. The internal spacer 148' separates the semiconductor layers 120 from each other and separates the bottommost semiconductor layer 120 from the fin portion 105'. Figure 2D ( Figure 3E In this process, an etching process is performed that selectively etches the semiconductor layer 115 exposed by the source / drain trench 140, while at least (or not at all) etching the semiconductor layer 120, fin portions 105', dummy gates 130A-130C, gate spacers 132, and / or isolation portions 125. The etching process forms gaps 145 between the semiconductor layers 120 and between the fin portions 105' and the semiconductor layers 120. The gaps 145 are disposed below the gate spacers 132, such that the semiconductor layers 120 are suspended below the gate spacers 132 and separated from each other by the gaps 145. In some embodiments, the gaps 145 extend at least partially below the dummy gates 130A-130C. The etching process is configured to etch the semiconductor layer 115 laterally (e.g., along the x-direction and / or y-direction). In the depicted embodiment, the etching process reduces the length of the semiconductor layer 115 along the x-direction. The etching process is dry etching, wet etching, other suitable etching processes, or combinations thereof.

[0032] exist Figure 2E ( Figure 3FIn the deposition process, a spacer layer 148 is then formed over the multi-gate device 100, including over the components of the multi-gate device 100 that form source / drain trenches 140 (e.g., semiconductor layers 115, 120, and fin portions 105'), such as by CVD, PVD, ALD, RPCVD, PECVD, HDPCVD, FCVD, HARP, LPCVD, ALCVD, APCVD, SACVD, MOCVD, plating, other suitable methods, or combinations thereof. The spacer layer 148 partially fills the source / drain trenches 140. In the depicted embodiment, the deposition process is configured to ensure that the spacer layer 148 fills the gaps 145. Figure 2F (and its corresponding Figure 3F In the process, an internal spacer etching is then performed, selectively etching the spacer layer 148 to form internal spacers 148' filling the gaps 145, while at least (or not at all) etching the semiconductor layer 120, fin portions 105', dummy gates 130A-130C, gate spacers 132, and / or isolation members 125. The spacer layer 148 (and therefore the internal spacers 148') comprises a material different from the material of the semiconductor layer 120, the fin portions 105', the isolation members 125, the dummy gates 130A-130C, and / or the gate spacers 132, to achieve desired etch selectivity during the internal spacer etching. In some embodiments, the spacer layer 148 comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and / or silicon carbonitride). In some embodiments, the spacer layer 148 comprises a low-k dielectric material, such as those described herein. In some embodiments, dopants (e.g., p-type dopants and / or n-type dopants) are introduced into the dielectric material, such that the spacer layer 148 comprises the doped dielectric material. The internal spacer etching is dry etching, wet etching, other suitable etching processes, or a combination thereof.

[0033] Transfer to Figure 2F ( Figure 3G )and Figure 2G ( Figure 3H Method 10 continues to form an epitaxial source / drain structure 150 in the source / drain trench 140. For example, method 10 includes: epitaxially growing an undoped semiconductor layer, such as an undoped epitaxial layer 152 located in the source / drain trench 140, in block 25 within the source / drain trench 140. Figure 2F and Figure 3G In block 30, a first doped semiconductor layer is epitaxially grown over an undoped semiconductor layer in the source / drain trench, such as epitaxial layer 154A and epitaxial layer 154B located over the undoped epitaxial layer 152 in the source / drain trench 140. Figure 2G and Figure 3H ); and in frame 35, a second doped semiconductor layer is epitaxially grown over the first doped semiconductor layer in the source / drain trench, such as located in the source / drain trench 140 ( Figure 2G and Figure 3H The method 10 further includes epitaxially growing epitaxial layers 156A and 156B above epitaxial layers 154A and 154B in the first doped semiconductor layer, such as epitaxial layers 154A and 154B, having a first dopant concentration, and a second doped semiconductor layer, such as epitaxial layers 156A and 156B, having a second dopant concentration greater than the first dopant concentration. The method 10 may also include epitaxially growing a third doped semiconductor layer above the second doped semiconductor layer, such as epitaxial layers 158A and 158B respectively located above epitaxial layers 156A and 156B. Figure 2G and Figure 3H The epitaxial growth of undoped epitaxial layers 152, 154A and 154B, 156A and 156B, and / or 158A and 158B is controlled (adjusted) to enhance the performance of the multi-gate device 100. In some embodiments, the epitaxial growth of each layer of the epitaxial source / drain structure 150 is controlled to maximize the strain applied to the channel region (here, semiconductor layer 120) of the multi-gate device 100 by the epitaxial source / drain structure 150. In some embodiments, maximizing the volume of epitaxial layers 156A and 156B in the epitaxial source / drain structure 150 and / or maximizing the dopant concentration of epitaxial layers 156A and 156B in the epitaxial source / drain structure 150 increases the strain applied to the channel region of the multi-gate device 100. In some embodiments, the interface between the undoped epitaxial layer 152 and the epitaxial source / drain structure 150 has fewer defects (and in some embodiments, none) than the interface between the doped epitaxial layer and the semiconductor substrate of the epitaxial source / drain structure. Therefore, the undoped epitaxial layer 152 provides a buffer between the doped epitaxial layer (e.g., epitaxial layers 154A, 154B, 156B, and / or 156B) and the semiconductor substrate 105, which can reduce short-channel effects in the multi-gate device 100. In some embodiments, as described herein, the profiles of the undoped epitaxial layer 152 and / or the epitaxial source / drain structure 150 are adjusted based on the active region size to mitigate short-channel effects while optimizing performance (e.g., drive current).

[0034] exist Figure 2F ( Figure 3GIn the source / drain trench 140, an undoped or unintentionally doped (UID) epitaxial layer 152 is formed in the bottom portion. The undoped epitaxial layer 152 is substantially free of dopant. The undoped epitaxial layer 152 comprises silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In the depicted embodiment, the undoped epitaxial layer 152 comprises silicon substantially free of n-type and p-type dopant or silicon-germanium substantially free of n-type and p-type dopant. For the purposes of this invention, a layer with a size less than about 5 × 10⁻⁶ is preferred. 18 cm -3 Semiconductor materials with a dopant concentration of [specific value] are considered undoped and / or have a UID. In some embodiments, the undoped epitaxial layer 152 has approximately 1 × 10⁻⁶ [value]. 18 cm -3 Approximately 5×10 18 cm -3 The dopant concentration. The undoped epitaxial layer 152 has a trench-shaped structure and physically contacts the semiconductor mesa 105P', fin portion 105', and / or substrate 105. For example, the undoped epitaxial layer 152 has a central, substrate region 152A extending laterally and / or horizontally between opposing sidewall regions 152B, wherein the sidewall regions 152B extend vertically and / or project upward relative to the central, substrate region 152A, thereby forming a trench 152'. In some embodiments, the trench 152' has a trapezoidal cross-sectional profile, wherein the trench 152' has a substantially flat, linear, and / or horizontally oriented bottom (e.g., formed by the central, substrate region 152A of the undoped epitaxial layer 152), which extends between opposing substantially tapered, inclined, and / or vertically oriented sidewalls (e.g., formed by the sidewall regions 152B of the undoped epitaxial layer 152). In some embodiments, the channel structure is a U-shaped structure, wherein the sidewall region 152B is a substantially linear and / or substantially vertically extending portion of the U-shaped structure, and the center, base region 152A is a substantially curved and / or substantially horizontally extending portion of the U-shaped structure. In some embodiments, the channel structure is a V-shaped structure, wherein the sidewall region 152B is a substantially inclined and / or substantially vertically extending portion of the V-shaped structure, and the center, base region 152A is a substantially pointed portion of the V-shaped structure.

[0035] Therefore, the bottom portion of the source / drain trench 140 formed by the semiconductor mesa 105P', fin portion 105', and / or substrate 105 has a portion partially filled by the undoped epitaxial layer 152 ("partially filled bottom portion") and a portion filled by the undoped epitaxial layer 152 ("filled bottom portion"). The partially filled bottom portion has a height h1 along the z-direction, and the filled bottom portion has a height h2 along the z-direction. The height h1 corresponds to the depth d1 in the trench 152' to the fin portion 105' and / or substrate 105, wherein the depth d1 is between the lowest point of the top surface of the semiconductor mesa 105P' and the top surface of the undoped epitaxial layer 152 relative to the top surface of the semiconductor mesa 105P'. The height h1 / depth d1 also corresponds to the remaining depth (d) in the source / drain trench 140 to the fin portion 105' and / or substrate 105. 剩余 Correspondingly, for example, the remaining depth from the source / drain recess 140 to the fin portion 105' and / or the substrate 105 is given by the difference between the depth d and the height h1 (i.e., d 剩余 =d-h1). In some embodiments, the minimum thickness of the undoped epitaxial layer 152 along the z-direction is given by the height h2, and the maximum thickness of the undoped epitaxial layer 152 along the z-direction is given by the sum of the heights h1 and h2. In some embodiments, the undoped epitaxial layer 152 has a central portion disposed between the end portions, wherein the central portion has the minimum thickness and the end portions have the maximum thickness. In some embodiments, the central portion and / or the end portions have varying thicknesses. For example, moving along the x-direction from the semiconductor mesa 105P' toward the central portion, the end portions may have a thickness along the z-direction that decreases from the maximum thickness to the minimum thickness or is greater than the minimum thickness but less than the maximum thickness. In another example, moving along the x-direction from the first end portion to the second end portion, the central portion may have a thickness along the z-direction that decreases from a thickness greater than the minimum thickness but less than the maximum thickness at the first end portion to the minimum thickness at the midpoint and then increases from the minimum thickness at the midpoint to a thickness greater than the minimum thickness but less than the maximum thickness at the second end portion. In such embodiments, the central portion may have a curved top surface. In some embodiments, the central portion has a substantially uniform thickness along the z-direction, moving from the first end portion to the second end portion along the x-direction. In such embodiments, the central portion may have a substantially flat, linear top surface.

[0036] The height h1 / depth d1 and height h2 are controlled to maximize the volume of the undoped epitaxial layer 152 below the top surface of the semiconductor mesa 105P', while maximizing the volume of the subsequently formed doped epitaxial layers (i.e., epitaxial layers 156A and / or 156B) of the epitaxial source / drain structure 150 above the top surface of the semiconductor mesa 105P'. If the height h1 / depth d1 is too small (e.g., less than or equal to 0 nm), the undoped epitaxial layer 152 may protrude above the top surface of the semiconductor mesa 105P' and into the portion of the epitaxial source / drain structure 150 intended to apply strain to the channel region (i.e., semiconductor layer 120), thereby undesirably reducing such strain. If the height h1 / depth d1 is too large (e.g., greater than about 30 nm), the volume of the undoped epitaxial layer 152 may be too small below the top surface of the semiconductor mesa 105P' and / or the thickness of the undoped epitaxial layer 152 along the sidewalls of the semiconductor mesa 105P' may be too thin, resulting in insufficient buffering between the semiconductor mesa 105P' and the doped epitaxial layer of the epitaxial source / drain structure 150, thereby offsetting the SCE reduction function of the undoped epitaxial layer 152. In some embodiments, the height h1 / depth d1 is about 0 nm to about 30 nm. A height h1 / depth d1 less than about 0 nm may cause the undoped epitaxial layer 152 to protrude above the top surface of the semiconductor mesa 105P' and into the portion of the epitaxial source / drain structure 150 intended to apply strain to the channel region (i.e., semiconductor layer 120), thereby reducing such strain. A height h1 / depth d1 greater than approximately 30 nm may result in the undoped epitaxial layer 152 being too thin along the sidewall of the semiconductor mesa 105P', thus providing insufficient buffering between the semiconductor mesa 105P' and the doped epitaxial layer of the epitaxial source / drain structure 150, thereby offsetting the SCE reduction function of the undoped epitaxial layer 152.

[0037] The epitaxial source / drain fabrication techniques described herein adjust heights h1 and h2 based on the active region size. Adjusting heights h1 and h2 based on the active region size can reduce (and in some embodiments, eliminate) the surface area coefficient (SCE) experienced by small and / or large active region devices, while optimizing the performance of both. In some embodiments, heights h1 and h2 are adjusted by a process for forming the undoped epitaxial layer 152. In some embodiments, heights h1 and h2 are adjusted due to the contour of the source / drain recesses 140 obtained by adjusting the source / drain etching. For example, see [link to documentation]. Figure 4B, for the multi-gate device S (i.e., the small active region device), the height h1 is equal to the height H3 and the height h2 is equal to the height H4. For the multi-gate device L (i.e., the large active region device), the height h1 is equal to the height H5, and the height h2 is equal to the height H6. The height H3 is less than the height H4 (H3 < H4), the height H5 is less than the height H6 (H5 < H6), and the height H3 is less than the height H5 (H3 < H5). In other words, the remaining depth of the fin portion 105' and / or the source / drain recess 140 in the substrate 105 in the multi-gate device S is less than the remaining depth of the fin portion 105' and / or the source / drain recess 140 in the substrate 105 in the multi-gate device L. Therefore, by adjusting the source / drain profile of the source / drain recess 140 based on the active region size as done in Figure 4A (e.g., providing different source / drain depths and / or different height ratios) and / or by adjusting the profile of the undoped epitaxial layer 152 based on the active region size as done in Figure 4B (e.g., providing an undoped epitaxial layer 152 with different height / depth and / or height ratios), the disclosed epitaxial source / drain manufacturing method optimizes the undoped epitaxial layer 152 based on the active region size (i.e., a smaller depth for small active region devices and a larger depth for large active region devices).

[0038] In some embodiments, the height H3 is from about 0 nm to about 10 nm. In some embodiments, the ratio of the height H3 to the height H4 is from about 0.05 to about 0.3. A height H3 less than 0 nm and / or a ratio of the height H3 to the height H4 less than 0.05 may cause the undoped epitaxial layer 152 to protrude above the top surface of the semiconductor mesa 105P' and into the portion (i.e., the semiconductor layer 120) of the epitaxial source / drain structure 150 that is intended to apply strain to the channel region, and thus undesirably reduce such strain. A height H3 greater than 10 nm and / or a ratio of the height H3 to the height H4 greater than 0.03 may result in minimal deposition of the undoped epitaxial material in the source / drain recess 140 and / or a thickness of the undoped epitaxial layer 152 along the sidewalls of the semiconductor mesa 105P' that is too thin, such that the undoped epitaxial layer 152 provides insufficient buffering between the semiconductor mesa 105P' and the doped epitaxial layer of the epitaxial source / drain structure 150, thus offsetting the SCE reduction function of the undoped epitaxial layer 152.

[0039] In some embodiments, the height H5 is from about 10 nm to about 30 nm. In some embodiments, the ratio of height H5 to height H6 is from about 0.1 to about 0.5. A height H5 of less than 10 nm and / or a height H5 to height H6 ratio of less than 0.1 may cause the undoped epitaxial layer 152 to protrude above the top surface of the semiconductor mesa 105P' and into the portion of the epitaxial source / drain structure 150 intended to apply strain to the channel region (i.e., the semiconductor layer 120), thereby undesirably reducing such strain. A height H5 greater than 30 nm and / or a height H5 to height H6 ratio greater than 0.5 may result in minimal deposition of undoped epitaxial material in the source / drain trench 140 and / or an undoped epitaxial layer 152 that is too thin along the sidewall of the semiconductor mesa 105P'. This would cause the undoped epitaxial layer 152 to provide insufficient buffering between the semiconductor mesa 105P' and the doped epitaxial layer of the epitaxial source / drain structure 150, thereby offsetting the SCE reduction function of the undoped epitaxial layer 152.

[0040] In some embodiments, the undoped epitaxial layer 152 is formed by a selective epitaxial growth (SEG) process, which selectively deposits (grows) semiconductor material (e.g., silicon or silicon-germanium) from a semiconductor surface (e.g., semiconductor mesa 105P', fin portion 105', substrate 105, and / or semiconductor layer 120) while restricting (or preventing) the growth of semiconductor material from dielectric surfaces and / or non-semiconductor surfaces (e.g., internal spacers 148', dummy gates 130A-130C, gate spacers 132', and / or isolation components 125). For example, silicon and / or germanium are grown from semiconductor layer 120 but not from semiconductor mesa 105P', fin portion 105', substrate 105, and / or semiconductor layer 120. In some embodiments, the SEG process is a selective CVD process that introduces a silicon-containing precursor and / or a germanium-containing precursor and a carrier gas into the process chamber, wherein the silicon-containing precursor and / or the germanium-containing precursor interacts with the semiconductor mesa 105P', fin portion 105', substrate 105, and / or semiconductor layer 120 to form an undoped epitaxial layer 152. Silicon-containing precursors include silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2) (DCS), trichlorosilane (SiHCl3), silicon tetrachloride (SiCl4), other suitable silicon-containing precursors, or combinations thereof. Germanium-containing precursors include germanane (GeH4), digermanane (Ge2H6), germanium tetrachloride (GeCl4), germanium dichloride (GeCl2), other suitable germanium-containing precursors, or combinations thereof. The carrier gas can be an inert gas, such as a hydrogen-containing gas (e.g., H2), an argon-containing gas (e.g., Ar), a helium-containing gas (e.g., He), a nitrogen-containing gas (e.g., N2), a xenon-containing gas, other suitable inert gases, or combinations thereof. While the various parameters of the selective CVD process can be tuned to ensure that silicon-containing and / or germanium-containing precursors nucleate and selectively grow from and / or grow faster from semiconductor surfaces, some silicon and / or germanium materials may nucleate and grow on dielectric and / or non-semiconductor surfaces. To prevent or limit such growth, the selective CVD process may further introduce an etchant-containing precursor into the process chamber, which may interact with the dielectric and / or non-semiconductor surfaces of the multi-gate device 100 (e.g., isolation components 125, dummy gates 130A-130C, gate spacers 132, and / or internal spacers 148'). Etching precursors include chlorine (Cl2), hydrogen chloride (HCl), other etchant precursors that can selectively promote the growth of desired semiconductor materials (e.g., silicon and / or germanium), or combinations thereof.Because growing silicon and / or germanium (if any) on and from dielectric and / or non-semiconductor surfaces is largely discontinuous and discrete compared to growing silicon and / or germanium (which is likely continuous and coalesced) on and from semiconductor surfaces, an etchant-containing precursor can remove any silicon and / or germanium from dielectric and / or non-semiconductor surfaces faster than removing silicon and / or germanium from semiconductor surfaces. Therefore, the selective CVD process simultaneously deposits and etches semiconductor material, but is configured to have a deposition rate greater than the etch rate to ensure net deposition of semiconductor material. In some embodiments, the etchant-containing precursor prevents any nucleation of semiconductor material on dielectric and / or non-semiconductor surfaces. Because the epitaxial layer 152 is undoped, no doped precursor is introduced into the process chamber during the selective CVD process and / or other SEG processes.

[0041] Various deposition parameters can be adjusted to selectively deposit semiconductor materials on the semiconductor surface, such as deposition gas composition, carrier gas composition, deposition gas flow rate, carrier gas flow rate, deposition time, deposition pressure, deposition temperature, source power, RF bias voltage, DC bias voltage, RF bias power, DC bias power, other suitable deposition parameters, or combinations thereof. In some embodiments, when forming the undoped epitaxial layer 152, the multi-gate device 100 is exposed to a deposition mixture comprising DCS and / or SiH4 (silicon-containing precursor), H2 (carrier precursor), and HCl (etchant-containing precursor). In some embodiments, the selective CVD process is performed at a deposition temperature of about 600°C to about 750°C. In some embodiments, the selective CVD process is performed at a deposition pressure of about 10 Torr to about 100 Torr. In some embodiments, the selective CVD process is configured as a bottom-up deposition process (i.e., from the bottom to the top of the source / drain trench 140), such that the undoped epitaxial layer 152 grows from the semiconductor mesa 105P', fin portion 105', and / or substrate 105, but not from the semiconductor layer 120. In some embodiments, an etching process is performed after the selective CVD process to remove semiconductor material (e.g., silicon and / or germanium) that may have been formed on the semiconductor layer 120. Post-deposition etching includes dry etching, wet etching, other suitable etching processes, or combinations thereof. Various etching parameters can be adjusted to selectively etch semiconductor material while at least (or not at all) etching the internal spacers 148', dummy gates 130A-130C, gate spacers 132, and / or isolation components 125, such as etching gas composition, carrier gas composition, etching gas flow rate, carrier gas flow rate, etching time, etching pressure, etching temperature, source power, RF bias voltage, DC bias voltage, RF bias power, DC bias power, other suitable etching parameters, or combinations thereof. For example, an etchant is selected for post-deposition etching that can remove semiconductor materials, such as silicon and / or germanium, at a higher rate than the materials of the internal spacers 148', dummy gates 130A-130C, gate spacers 132, and / or isolation components 125 (e.g., dielectric materials, such as silicon oxide and / or polycrystalline silicon materials), i.e., the etchant has high etch selectivity relative to the semiconductor material. In some embodiments, post-deposition etching is a dry etching performed with a chlorine-containing etching gas (e.g., HCl) and a hydrogen-containing carrier gas (e.g., H2). In some embodiments, post-deposition etching is performed with an HCl flow rate of about 200 standard cubic centimeters per minute (sccm) to about 500 sccm.

[0042] Selective CVD processes and post-deposition etching are performed "in situ." For example, selective CVD processes and post-deposition etching are performed in the same process chamber, such as the process chamber of a CVD tool, so that the workpiece (wafer) on which multi-gate devices 100 are fabricated remains under vacuum conditions. Therefore, "in situ" also generally refers to performing various processes on the workpiece without exposing the wafer to external environments such as oxygen (e.g., outside of an IC processing system). Thus, performing selective CVD processes and post-deposition etching can minimize (or eliminate) exposure to oxygen and / or other external environments during the process.

[0043] Conversely, the selective CVD process for forming the undoped epitaxial layer 152 and the epitaxial growth process for forming the doped epitaxial layers (i.e., epitaxial layers 154A, 154B, 156A, 156B, 158A, and / or 158B) of the epitaxial source / drain structure 150 are performed "out of place." For example, the undoped epitaxial layer 152 and the doped epitaxial layer of the epitaxial source / drain structure 150 are performed in different process chambers, such as different process chambers of a CVD tool, so that the workpiece (wafer) on which the multi-gate device 100 is fabricated is not maintained under vacuum conditions between the formation of the undoped epitaxial layer 152 and the doped epitaxial layer. For example, the vacuum conditions may be disrupted when the workpiece is transferred from one process chamber (e.g., for depositing the undoped epitaxial layer 152) to another process chamber (e.g., for depositing the doped epitaxial layer). Therefore, "external" also often refers to the various processes performed on a workpiece, where the wafer may be exposed to external environments such as oxygen between processes (e.g., outside of an IC processing system).

[0044] exist Figure 2G ( Figure 3HIn this embodiment, epitaxial layers 154A and 154B are formed above an undoped epitaxial layer 152. Epitaxial layers 154A and 154B are disposed along the sidewalls and bottom of the source / drain recess 140 and partially fill the source / drain recess 140. Epitaxial layers 154A and 154B physically contact epitaxial layer 152, semiconductor mesa 105P', semiconductor layer 120, and / or internal spacer 148'. Epitaxial layers 154A and 154B are discontinuous epitaxial layers having discrete and separated sidewall epitaxial portions and bottom epitaxial portions. The sidewall epitaxial portions are disposed on the sidewalls of semiconductor layer 120, and the sidewall epitaxial portions on adjacent semiconductor layers 120 are not connected to each other. In some embodiments, as depicted, the sidewall epitaxial portions wrap around the respective semiconductor layer 120 and extend above the top and / or bottom of the respective semiconductor layer 120. The bottom epitaxial portion is disposed on top of the undoped epitaxial layer 152 and is not connected to the sidewall epitaxial portion. In some embodiments, as depicted, the bottom epitaxial portion physically contacts the portion of the top surface of the semiconductor mesa 105P' not covered by the undoped epitaxial layer 152, such as the portion of the top surface of the semiconductor mesa 105P' extending between the bottommost inner spacer 148' and the undoped epitaxial layer 152.

[0045] The bottom epitaxial portion has a thickness t1 along the z-direction (i.e., the bottom thickness), and the sidewall epitaxial portion has a thickness t2 along the x-direction (i.e., the sidewall thickness). Thickness t1 is less than the height h2 of the undoped epitaxial layer 152. In the depicted embodiment, thickness t1 is greater than height h1, the bottom epitaxial portion fills the trench 150', and the bottom epitaxial portion protrudes above the top surface of the semiconductor mesa 105P'. In some embodiments, thickness t1 is less than height h1, the bottom epitaxial portion does not fill the trench 150', and the source / drain recess 140 still extends below the top surface of the semiconductor mesa 105P'. In some embodiments, thickness t1 is approximately equal to height h1, and the bottom epitaxial portion fills the trench 150' but does not protrude above the top surface of the semiconductor mesa 105P'. In some embodiments, thickness t1 is approximately 10 nm to approximately 20 nm. In some embodiments, thickness t2 is approximately 2 nm to approximately 10 nm. Thicknesses t1 and t2 are controlled to maximize the volume of epitaxial layers 156A and 156B subsequently formed in the epitaxial source / drain structure 150. If thicknesses t1 and / or t2 are too thick (e.g., greater than about 20 nm and / or greater than about 10 nm, respectively), the volume of epitaxial layers 156A and / or 156B in the epitaxial source / drain structure 150 may be too small and provide insufficient strain to the channel region (i.e., semiconductor layer 120) of the multi-gate device 100. If thicknesses t1 and / or t2 are too thin (e.g., less than about 10 nm and / or less than about 2 nm, respectively), epitaxial layers 154A and / or 154B may provide insufficient growth surfaces for the subsequent formation of epitaxial layers 156A and 156B, respectively. In some embodiments, when the undoped epitaxial layer 152 has a different lattice constant and / or a different lattice structure than epitaxial layers 156A and / or 156B, epitaxial layers 154A and / or 154B can be used as buffer layers. For example, the lattice constant and / or lattice structure of epitaxial layer 154A can gradually change from a lattice constant and / or lattice structure similar to that of undoped epitaxial layer 152 to a lattice constant and / or lattice structure similar to that of epitaxial layer 156A, and / or the lattice constant and / or lattice structure of epitaxial layer 154B can gradually change from a lattice constant and / or lattice structure similar to that of undoped epitaxial layer 152 to a lattice constant and / or lattice structure similar to that of epitaxial layer 156B.

[0046] Epitaxial layers 156A and 156B are formed over epitaxial layers 154A and 154B, respectively, to fill the source / drain recess 140. Epitaxial layers 156A and 156B are separated from the semiconductor layer 120 but not from the internal spacer 148' by sidewall epitaxial portions of epitaxial layers 154A and 154B, respectively. In the depicted embodiment, epitaxial layers 156A and 156B respectively enclose epitaxial layers 154A and 154B and physically contact the internal spacer 148'. In some embodiments, the sidewall epitaxial portions of epitaxial layers 154A and / or 154B extend at least partially over the internal spacer 148', such that epitaxial layers 154A and 154B respectively separate portions of epitaxial layers 156A and 156B from the internal spacer 148'. Epitaxial layers 156A and 156B are further separated from the undoped epitaxial layer 152 by the bottom epitaxial portions of epitaxial layers 154A and 154B, respectively. Epitaxial layers 156A and 156B have a thickness t3 along the z-direction and a thickness t4 along the x-direction. The thickness t3 is greater than the thickness t1 of the bottom epitaxial portions of epitaxial layers 154A and 154B and greater than the height h2 of the undoped epitaxial layer 152. In some embodiments, the thickness t3 is about 40 nm to about 100 nm. In some embodiments, the thickness t4 is about 20 nm to about 60 nm. In the depicted embodiment, with epitaxial layers 154A and 154B filling trench 150', epitaxial layers 156A and 156B are disposed on the top surface of semiconductor mesa 105P'. In some embodiments, when epitaxial layers 154A and 154B do not fill trench 150', epitaxial layers 156A and 156B fill the remaining portion of trench 150' and extend below the top surface of semiconductor mesa 105P'. In some embodiments, when the thickness t1 of epitaxial layers 154A and 154B is approximately equal to the height h1, epitaxial layers 156A and 156B may extend to the top surface of approximately semiconductor mesa 105P'.

[0047] Epitaxial layers 158A and 158B are formed over epitaxial layers 156A and 156B, respectively. Epitaxial layers 158A and 158B may be referred to as capping layers. In some embodiments, epitaxial layers 158A and 158B serve as capping layers to protect epitaxial layers 156A and 156B (i.e., heavily doped portions of the epitaxial source / drain structure 150) during subsequent processes (such as processes associated with fabricating source / drain contacts). Epitaxial layers 158A and 158B physically contact epitaxial layers 156A and 156B, respectively, and in the depicted embodiment, respectively cap the top surfaces of layers 156A and 156B. Epitaxial layers 158A and 158B further extend between and physically contact the gate spacers 132 of adjacent dummy gates 130A-130C. In some embodiments, epitaxial layers 158A and 158B further physically contact portions of the topmost semiconductor layer 120 not covered by epitaxial layers 154A and / or 156A and 154B and / or 156B, respectively. Epitaxial layers 158A and 158B have a thickness t5 along the z-direction and a thickness t6 along the x-direction. In some embodiments, the thickness t5 is about 10 nm to about 30 nm. In the depicted embodiment, because epitaxial layers 156A and 156B have recessed top surfaces and therefore do not fill the source / drain trench 140, epitaxial layers 158A and 158B fill the remaining portion of the source / drain trench 140 and extend below the top surface of the topmost semiconductor layer 120. In such an embodiment, the thickness t5 is given by the sum of the thickness t7 along the z-direction (which corresponds to the thickness of the bottom epitaxial portion of epitaxial layers 158A and 158B located below the top surface of the topmost semiconductor layer 120) and the thickness t8 along the z-direction (which corresponds to the thickness of the top epitaxial portion of epitaxial layers 158A and 158B located above the top surface of the topmost semiconductor layer 120). In some embodiments, the thickness t8 is about 1 nm to about 15 nm. In the depicted embodiment, the thickness t6 is approximately the same as the thickness t4 of epitaxial layers 156A and 156B, respectively. In some embodiments, the thickness t6 is from about 20 nm to about 60 nm. In some embodiments, the thickness t6 varies as the substrate 105 is moved along the z-direction. For example, the thickness t6 decreases from a maximum thickness to a minimum thickness. In some embodiments, the thickness t6 of the top epitaxial portion is substantially uniform and is the maximum thickness, and the thickness t6 of the bottom epitaxial portion decreases from a thickness less than the maximum thickness to a minimum thickness. In some embodiments, the thickness t6 of the top epitaxial portion increases from a thickness less than the maximum thickness to the maximum thickness.

[0048] The thickness t8 corresponds to the height of the epitaxial layers 158A and 158B above the top surface of the topmost semiconductor layer 120, which may be referred to as the raised height of the epitaxial source / drain structure 150. Go to Figure 4C , the present invention contemplates adjusting the thickness t8 (i.e., the raised height of the epitaxial source / drain structure 150) based on the active region size. In some embodiments, the thickness t8 is adjusted by the process for forming the epitaxial layers 158A and 158B (collectively referred to as epitaxial layer 158 in Figure 4C ). In some embodiments, the thickness t8 is adjusted due to the profile of the source / drain recess 140 by adjusting the source / drain etching and / or adjusting the epitaxial growth of the epitaxial layers 156A and 156B (collectively referred to as epitaxial layer 156 in Figure 4C ), the epitaxial layers 154A and 154B (collectively referred to as epitaxial layer 154 in Figure 4C ) and / or the undoped epitaxial layer 152. It should be noted that, in contrast to Figure 2G , when deposited, the epitaxial layer 154 extends continuously (i.e., without interruption) along the sidewalls and bottom of the source / drain recess 140. In such an embodiment, the epitaxial layer 154 separates the epitaxial layer 156 from the semiconductor layer 120, the inner spacer 148' and the undoped epitaxial layer 152, such that the epitaxial layer 156 does not physically contact the semiconductor layer 120, the inner spacer 148' or the undoped epitaxial layer 152.

[0049] In Figure 4C , for the multi-gate device S (i.e., the small active region device), the thickness t8 is equal to the height H7, and for the multi-gate device L (i.e., the large active region device), the thickness t8 is equal to the height H8, and the height H7 is less than the height H8 (H7 < H8). In other words, the raised height of the epitaxial source / drain structure 150 in the multi-gate device S is less than the raised height of the epitaxial source / drain structure 150 in the multi-gate device L. In some embodiments, the height H7 is from about 1 nm to about 5 nm. In some embodiments, the height H8 is from about 5 nm to about 15 nm. The ratio of the height H7 to the height H8 (i.e., the raised height ratio = H7 / H8) is less than about 1. In some embodiments, the raised height ratio is from about 0.2 to about 0.7, where a raised height ratio less than 0.2 can provide a large active region device with an epitaxial source / drain structure 150 having a raised height less than the desired raised height, and thus prevent the performance optimization of the large active region device, while a raised height ratio greater than 0.7 can provide a small active region device with an epitaxial source / drain structure 150 having a raised height greater than the desired raised height, and thus prevent the performance optimization of the small active region device. Therefore, by based on as Figure 4AModifications to the active region size, source / drain profiles of the source / drain recess 140 (e.g., providing different source / drain depths and / or different height ratios in small and large active regions) and / or as... Figure 4B The undoped epitaxial layer 152 is formed as described in the above. The disclosed epitaxial source / drain fabrication method can optimize the bump height for the epitaxial source / drain structure 150 based on the active region size (i.e., a smaller bump height for small active region devices and a larger bump height for large active region devices).

[0050] return Figure 2G ( Figure 3H Epitaxial layers 154A and 156A comprise the same semiconductor material but with different concentrations. The semiconductor material may include silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In the depicted embodiment, where transistor region 106A is a p-type transistor region, epitaxial layers 154A and 156A comprise p-doped silicon-germanium but with different p-type concentrations. For example, the p-type dopant concentration of epitaxial layer 154A is less than that of epitaxial layer 156A. In some embodiments, epitaxial layer 154A has approximately 1 × 10⁻⁶ ppm. 20 cm -3 Approximately 5×10 20 cm -3 The p-type dopant concentration (e.g., boron concentration), and the epitaxial layer 156A has approximately 5 × 10⁻⁶ p-type dopant concentrations. 20 cm -3 Approximately 2×10 21 cm -3 The p-type dopant concentration (e.g., boron concentration). In some embodiments, epitaxial layer 154A has a p-type dopant concentration of about 0.2 at% to about 1 at%, and epitaxial layer 156A has a p-type dopant concentration of about 1 at% to about 4 at%. In some embodiments, epitaxial layer 154A and epitaxial layer 156A also have different germanium concentrations. For example, the germanium concentration of epitaxial layer 156A is greater than that of epitaxial layer 154A. In a further described embodiment, semiconductor layer 120 may include germanium in transistor region 106A, and the germanium concentration in epitaxial layer 154A is approximately the same as the germanium concentration in semiconductor layer 120. For example, epitaxial layer 154A and semiconductor layer 120 in transistor region 106A may have a germanium concentration of about 25 at%. The present invention contemplates embodiments of different semiconductor materials in which epitaxial layers 154A and 156A have the same or different dopant concentrations.

[0051] Epitaxial layers 154B and 156B comprise the same semiconductor material but with different concentrations. The semiconductor material may include silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In the depicted embodiment, where transistor region 106B is an n-type transistor region, epitaxial layers 154B and 156B comprise n-doped silicon but with different n-type concentrations. For example, the n-type dopant concentration of epitaxial layer 154B is less than that of epitaxial layer 156B. In some embodiments, epitaxial layer 154B has approximately 1 × 10⁻⁶ ppm. 20 cm -3 Approximately 5×10 20 cm -3 The n-type dopant concentration (e.g., phosphorus or arsenic concentration), and the epitaxial layer 156B has approximately 5 × 10⁻⁶ ppm. 20 cm -3 Approximately 2×10 21 cm -3 The n-type dopant concentration (e.g., phosphorus or arsenic concentration). In some embodiments, epitaxial layer 154B has an n-type dopant concentration of about 0.2 at% to about 1 at%, and epitaxial layer 156B has an n-type dopant concentration of about 1 at% to about 4 at%. In some embodiments, epitaxial layer 154B and epitaxial layer 156B also have different silicon concentrations. In some embodiments, epitaxial layer 154B and / or epitaxial layer 156B are substantially free of germanium (i.e., the germanium concentration is about 0 at%). The present invention contemplates embodiments of different semiconductor materials in which epitaxial layer 154B and epitaxial layer 156B have the same or different dopant concentrations.

[0052] Epitaxial layers 158A and 158B comprise semiconductor materials such as silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In the depicted embodiments, where transistor region 106A is a p-type transistor region and transistor region 106B is an n-type transistor region, epitaxial layer 158A comprises p-doped silicon-germanium and epitaxial layer 158B comprises n-doped silicon. In some embodiments, epitaxial layer 158A has approximately 1 × 10⁻⁶ Ω·cm. 21 cm -3 Approximately 3×10 21 cm -3 The p-type dopant concentration (e.g., boron concentration), and the epitaxial layer 158B has approximately 1 × 10⁻⁶ p-type dopant concentration. 21 cm -3 Approximately 3×10 21 cm -3The n-type dopant concentration (e.g., phosphorus or arsenic concentration). In some embodiments, epitaxial layer 158A has a p-type dopant concentration of about 1 at% to about 6 at% and epitaxial layer 158B has an n-type dopant concentration of about 1 at% to about 6 at%. Doping epitaxial layers 158A and 158B (such as those provided herein) can reduce the source / drain contact resistance (R0). CSD (That is, the resistance to current flow between the epitaxial source / drain structure 150 and the subsequently formed source / drain contacts). In some embodiments, the dopant concentrations of epitaxial layers 158A and 158B are greater than the dopant concentrations of epitaxial layers 156A and 156B, respectively. In some embodiments, the dopant concentrations of epitaxial layers 158A and / or 158B are equal to the dopant concentrations of epitaxial layers 156A and 156B, respectively. In some embodiments, as depicted, the dopant concentrations of epitaxial layers 158A and / or 158B are less than the dopant concentrations of epitaxial layers 156A and 156B, respectively. In some embodiments, epitaxial layers 158A and / or 158B are substantially dopant-free (e.g., undoped and / or UID).

[0053] Epitaxial layers 154A and 154B can be grown from semiconductor layer 120 and undoped epitaxial layer 152; epitaxial layers 156A and 156B can be grown from epitaxial layers 154A and 154B, respectively; and epitaxial layers 158A and 158B can be grown from epitaxial layers 156A and 156B, respectively. Epitaxial layers 154A, 154B, 156A, 156B, 158A, and / or 158B can be formed by performing CVD deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the components of the substrate 105, fin portion 105', semiconductor layer 120, undoped epitaxial layer 152, epitaxial layer 154A, epitaxial layer 154B, epitaxial layer 156A and / or epitaxial layer 156B. In some embodiments, epitaxial growth conditions, such as epitaxial growth precursors, epitaxial growth temperature, epitaxial growth time, epitaxial growth pressure and / or other suitable epitaxial growth parameters, are adjusted to achieve epitaxial growth on a semiconductor surface, while minimal (or no) growth is performed on a dielectric surface and / or non-semiconductor surface. In some embodiments, epitaxial layers 154A, 154B, 156A, 156B, 158A and / or 158B are doped during deposition by adding dopants to the source material of the epitaxial process. In some embodiments, epitaxial layers 154A, 154B, 156A, 156B, 158A, and / or 158B are doped by ion implantation after the deposition process. In some embodiments, an annealing process is performed to activate the dopants in the epitaxial layers 154A, 154B, 156A, 156B, 158A, 158B, and / or other source / drain regions (such as HDD regions and / or LDD regions) of the multi-gate device 100.

[0054] In the depicted embodiments, epitaxial layers 154A, 154B, 156A, 156B, 158A, and 158B are formed using corresponding SEG processes. In some embodiments, the SEG process is a selective CVD process, such as remote plasma CVD (RPCVD), which introduces silicon-containing and / or germanium-containing precursors and a carrier gas into a process chamber, wherein the silicon-containing and / or germanium-containing precursors interact with the semiconductor surface of the multi-gate device 100 to form epitaxial layers 154A, 154B, 156A, 156B, 158A, and 158B, respectively. Silicon-containing precursors include SiH4, Si2H6, DCS, SiHCl3, SiCl4, other suitable silicon-containing precursors, or combinations thereof. Germanium-containing precursors include GeH4, Ge2H6, GeCl4, GeCl2, other suitable germanium-containing precursors, or combinations thereof. The carrier gas can be an inert gas, such as H2. In some embodiments, the selective CVD process introduces a dopant-containing precursor into the process chamber to promote in-situ doping of epitaxial layers 154A, 154B, 156A, 156B, 158A, and / or 158B. Dopant-containing precursors include boron (e.g., B2H6), phosphorus (e.g., PH3), arsenic (e.g., AsH3), other suitable dopant-containing precursors, or combinations thereof. In some embodiments, the selective CVD process introduces an etchant-containing precursor into the process chamber to prevent or limit the growth of silicon and / or germanium materials on dielectric and / or non-semiconductor surfaces, as described herein. In such embodiments, the parameters of the selective CVD process are adjusted to ensure net deposition of semiconductor material on the semiconductor surface. Etching precursors include Cl2, HCl, other etchant-containing precursors, or combinations thereof that can selectively promote the growth of the desired semiconductor material (e.g., silicon and / or germanium).

[0055] In some embodiments, when epitaxial layers 154A, 156A, and / or 158A are formed, the multi-gate device 100 is exposed to a deposition gas comprising GeH4 (germanium-containing precursor), DCS (silicon-containing precursor), H2 (carrier precursor), B2H6 (dopant-containing precursor), and HCl (etchant precursor). In some embodiments, when epitaxial layers 154B, 156B, and / or 158B are formed, the multi-gate device 100 is exposed to a deposition gas comprising DCS (silicon-containing precursor), H2 (carrier precursor), PH3 and / or AsH3 (dopant-containing precursor) and HCl (etchant precursor). In some embodiments, when epitaxial layers 154A, 156A, and / or 158A are formed, the multi-gate device 100 is exposed to a deposition gas comprising GeH4 (a germanium-containing precursor), H2 (a carrier precursor), B2H6 (a dopant-containing precursor), and HCl (an etchant precursor). In some embodiments, when epitaxial layers 154B, 156B, and / or 158B are formed, the multi-gate device 100 is exposed to a deposition gas comprising SiH4 (a silicon-containing precursor), H2 (a carrier precursor), PH3 and / or AsH3 (a dopant-containing precursor) and HCl (an etchant precursor). In some embodiments, when forming epitaxial layers 156A and / or 156B (which have the highest volume and highest dopant concentration in the epitaxial source / drain structure 150), the etch rate and deposition rate are adjusted to provide at least partial removal (etching) of the doped semiconductor material from the top surface of the topmost semiconductor layer 120, particularly the portion of the top surface of the topmost semiconductor layer 120 directly adjacent to the gate structure of the multi-gate device 100 (i.e., the gate spacer 132 and the dummy gate 130). In such embodiments, removing the heavily doped semiconductor material from the portion of the top surface of the topmost semiconductor layer 120 directly adjacent to the gate structure of the multi-gate device 100 can reduce dopant diffusion from the epitaxial source / drain structure 150 into the subsequently formed metal gate. In a further embodiment, epitaxial layers 158A and 158B (which may have lower dopant concentrations than epitaxial layers 156A and 156B, respectively) physically contact the portion of the top surface of the topmost semiconductor layer 120 that is directly adjacent to the gate structure of the multi-gate device 100.

[0056] The doped epitaxial layers for the epitaxial source / drain structures 150 used for different types of transistors (e.g., NMOS and PMOS) can be formed in different process chambers. In some embodiments, epitaxial layers 154A, 156A, and / or 158A of the epitaxial source / drain structures 150 in transistor region 106A (e.g., where a p-type transistor of the multi-gate device 100 is formed) are formed in a first CVD process chamber (or tool), and epitaxial layers 154B, 156B, and / or 158B of the epitaxial source / drain structures 150 in transistor region 106B (e.g., where an n-type transistor of the multi-gate device 100 is formed) are formed in a second CVD process chamber. In some embodiments, the formation of the doped epitaxial source / drain is a cyclic lithography / deposition process. For example, forming a doped epitaxial source / drain may include: performing a first photolithography process to form a first masking layer covering transistor region 106A and exposing transistor region 106B; performing a first deposition sequence to form epitaxial layer 154A, epitaxial layer 156A and / or epitaxial layer 158A; removing the first masking layer; performing a second photolithography process to form a second masking layer exposing transistor region 106A and covering transistor region 106B; performing a second deposition sequence to form epitaxial layer 154B, epitaxial layer 156B and / or epitaxial layer 158B; and removing the second masking layer.

[0057] In some embodiments, the first deposition sequence is three separate deposition steps performed sequentially to form epitaxial layer 154A, epitaxial layer 156A, and / or epitaxial layer 158A, and / or the second deposition sequence is three separate deposition steps performed sequentially to form epitaxial layer 154B, epitaxial layer 156B, and / or epitaxial layer 158B. In such embodiments, deposition may be paused between each deposition step, for example, by stopping the flow of deposition gas into the process chamber between deposition steps. In some embodiments, a purge process is performed between each deposition step before performing subsequent deposition steps, the purge process removing deposition gas and any byproducts of the previous deposition step from the process chamber. In some embodiments, the first deposition sequence is a continuous deposition process having three sets of different deposition conditions for forming epitaxial layer 154A, epitaxial layer 156A, and / or epitaxial layer 158A, and / or the second deposition sequence is a continuous deposition process having three sets of different deposition conditions for forming epitaxial layer 154B, epitaxial layer 156B, and / or epitaxial layer 158B. Deposition conditions may include silicon precursor flow rate and / or concentration, germanium precursor flow rate and / or concentration, dopant precursor flow rate and / or concentration, etchant precursor flow rate and / or concentration, deposition pressure, deposition time, deposition temperature, other deposition parameters, and / or combinations thereof. For example, silicon precursors, germanium precursors, dopant precursors, and / or etchant precursors may flow continuously into the process chamber during the etching sequence, but the concentrations and / or flow rates of the silicon precursors, germanium precursors, dopant precursors, and / or etchant precursors may differ for each deposition stage (i.e., deposition of epitaxial layers 154A / 154B, 156A / 156B, and 158A / 158B, respectively). For each deposition stage, the deposition pressure, deposition time, deposition temperature, and / or other deposition parameters may also differ.

[0058] This invention considers epitaxial source / drain structures 150 with different configurations and / or different cross-sectional profiles in transistor regions 106A and 106B. For example, the thickness t1 of the bottom epitaxial portion of epitaxial layer 154A may be different from (e.g., greater than) the thickness t1 of the bottom epitaxial portion of epitaxial layer 154B and / or the thickness t2 of the sidewall epitaxial portion of epitaxial layer 154A may be different from (e.g., greater than) the thickness t2 of the sidewall epitaxial portion of epitaxial layer 154B. In another example, in transistor region 106A, the bottom epitaxial portion of epitaxial layer 154A is connected to the bottommost sidewall epitaxial portion of epitaxial layer 154A, while in transistor region 106B, the bottom epitaxial portion of epitaxial layer 154B is not connected to the bottommost sidewall epitaxial portion of epitaxial layer 154B. In such an embodiment, epitaxial layer 156A physically contacts the bottommost internal spacer 148', while epitaxial layer 156B does not physically contact the bottommost internal spacer 148'. In another embodiment, the sidewall epitaxial portion of epitaxial layer 154A may be larger than the sidewall epitaxial portion of epitaxial layer 154B, such that the gap between adjacent sidewall epitaxial portions of epitaxial layer 154A is smaller than the gap between adjacent sidewall epitaxial portions of epitaxial layer 154B. In yet another embodiment, epitaxial layers 154A and 154B have different shapes and / or epitaxial layers 156A and 156B have different shapes. In yet another embodiment, the thickness t3 and / or thickness t4 of epitaxial layer 156A may be different from the thickness t3 and / or thickness t4 of epitaxial layer 156B. In yet another embodiment, epitaxial layers 156A and 156B have different top surface configurations. For example, the recessed top surface of epitaxial layer 156A may be shallower than the recessed top surface of epitaxial layer 156B, such that after the formation of epitaxial layers 156A and 156B, the remaining depth of the source / drain trench 140 in transistor region 106A is less than the remaining depth of the source / drain trench 140 in transistor region 106B. In such an embodiment, epitaxial layer 158B extends further below the top surface of the topmost semiconductor layer 120 than epitaxial layer 158A, such that the thickness t7 of epitaxial layer 158B is greater than the thickness t7 of epitaxial layer 158A. In yet another example, the thicknesses t5, t6, t7, and / or t8 of epitaxial layer 158A may differ from the thicknesses t5, t6, t7, and / or t8 of epitaxial layer 158B. In yet another example, epitaxial layers 158A and 158B have different shapes.

[0059] Transfer to Figure 2H (and its corresponding Figure 3IThe multi-gate device 100 may undergo further processing. For example, a dielectric layer 170 (e.g., a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer) may be formed over the multi-gate device 100, and CMP and / or other planarization processes may be performed until the top (or top surface) of the dummy gates 130A-130C is reached (exposed). The dielectric layer 170 is disposed over the epitaxial source / drain structure 150 and between adjacent gate spacers 132. The dielectric layer 170 may be formed by CVD, PVD, ALD, RPCVD, PECVD, HDPCVD, FCVD, HARP, LPCVD, ALCVD, APCVD, SACVD, MOCVD, other suitable methods, or combinations thereof. In some embodiments, the ILD layer may be formed by FCVD, HARP, HDPCVD, or combinations thereof. In some embodiments, a planarization process removes the hard mask of the dummy gates 130A-130C to expose the underlying dummy gate electrode, such as a polysilicon gate electrode, of the dummy gates 130A-130C. The ILD layer includes a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BSG, BPSG, FSG, etc. (Applied Materials, Santa Clara, California), degel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric materials, filaments (Dow Chemical Company, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer comprises a dielectric material having a dielectric constant smaller than that of silicon dioxide (e.g., k < 3.9). In some embodiments, the ILD layer comprises a dielectric material having a dielectric constant less than about 2.5 (i.e., very low k (ELK) dielectric material), such as SiO2 (e.g., porous silicon dioxide), silicon carbide (SiC), and / or carbon-doped oxides (e.g., SiCOH-based materials (having, for example, Si-CH3 bonds)), each of which is tuned / configured to exhibit a dielectric constant less than about 2.5. The ILD layer may comprise a multilayer structure having a variety of dielectric materials. CESL comprises materials different from those of the ILD layer, such as dielectric materials different from those of the ILD layer. For example, in the case where the ILD layer includes a dielectric material comprising silicon and oxygen and having a dielectric constant approximately less than that of silicon dioxide, the CESL may include silicon and nitrogen, such as silicon nitride or silicon oxynitride.

[0060] A gate replacement process is then performed to replace dummy gates 130A-130C with gate stacks 160A, 160B, and 160C, respectively. For example, dummy gates 130A-130C are removed to form gate openings (formed between gate spacers 132 and / or internal spacers 148') that expose channel regions of semiconductor layer stacks 110 (e.g., semiconductor layers 120 and 115). In some embodiments, an etching process is performed that selectively removes dummy gates 130A-130C relative to dielectric layer 170, gate spacers 132, internal spacers 148', semiconductor layer 115, and / or semiconductor layer 120. In other words, the etching process substantially removes dummy gates 130A-130C, but does not remove or substantially does not remove dielectric layer 170, gate spacers 132, internal spacers 148', semiconductor layer 115, and / or semiconductor layer 120. The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric layer 170 and / or the gate spacer 132, but has openings therein that expose dummy gates 130A-130C.

[0061] During the gate replacement process, prior to forming the gate stacks 160A-160C in the gate openings, a channel release process is performed to form a floating channel layer. For example, the semiconductor layer 115 exposed by the gate openings is selectively removed to form air gaps between semiconductor layers 120 and between semiconductor layers 120 and semiconductor mesa 105P', thereby suspending the semiconductor layers 120 in the channel region of the multi-gate device 100. In the depicted embodiment, each transistor region 106A and transistor region 106B has three suspended semiconductor layers 120 stacked vertically along the z-direction, hereinafter referred to as channel layers 120', to provide three channels through which current can flow between the respective epitaxial source / drain structures 150 during transistor operation of the multi-gate device 100. In some embodiments, an etching process is performed to selectively etch semiconductor layer 115 while at least (or not at all) etching semiconductor layer 120, semiconductor mesa 105P', gate spacer 132, internal spacer 148', and / or dielectric layer 170. In some embodiments, an etchant is selected for the etching process that etches silicon germanium (i.e., semiconductor layer 115) at a higher rate than silicon (i.e., semiconductor layer 120 and semiconductor mesa 105P') and dielectric material (i.e., gate spacer 132, internal spacer 148', and / or dielectric layer 170) (i.e., the etchant has high etch selectivity relative to silicon germanium). The etching process is dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, an oxidation process may be performed prior to the etching process to convert semiconductor layer 115 into a silicon germanium oxide part, wherein the etching process then removes the silicon germanium oxide part. In some embodiments, during and / or after the removal of semiconductor layer 115, an etching process is performed to modify the contour of semiconductor layer 120 to achieve a target size and / or target shape for channel layer 120.

[0062] Gate stacks 160A-160C (also referred to as high-k / metal gates) are then formed in the gate openings. Gate stacks 160A-160C are disposed between corresponding gate spacers 132. Gate stacks 160A-160C are also disposed between corresponding internal spacers 148'. Gate stacks 160A-160C are also disposed between channel layers 120' and between channel layers 120' and semiconductor mesa 105P'. In the depicted embodiment, when the multi-gate device 100 is a GAA transistor, the gate stacks 160A-160C, for example, surround the channel layers 120' in the YZ plane. In some embodiments, forming gate stacks 160A-160C includes: depositing a gate dielectric layer partially filling a gate opening over a multi-gate device 100; depositing a gate electrode layer partially filling the gate opening over the gate dielectric layer; depositing a hard mask layer filling the remaining portion of the gate opening over the gate electrode layer; and performing a planarization process, such as CMP, on the hard mask layer, the gate electrode layer, and / or the hard mask layer to form the gate stacks 160A-160C. Deposition processes may include CVD, PVD, ALD, RPCVD, PECVD, HDPCVD, FCVD, HARP, LPCVD, ALCVD, APCVD, SACVD, MOCVD, plating, other suitable methods, or combinations thereof. While the depicted embodiments fabricate metal gate stacks according to a post-gate process, embodiments of fabricating metal gate stacks according to a gate-before process or a hybrid post-gate / gate-before process are contemplated in this invention.

[0063] Gate stacks 160A-160C are configured to achieve desired functionality according to the design requirements of the multi-gate device 100, such that gate stacks 160A-160C may include the same or different layers and / or materials. In some embodiments, gate stacks 160A-160C include gate dielectrics (e.g., gate dielectrics 162A, 162B, and 162C, each of which may include a gate dielectric layer) and gate electrodes (e.g., gate electrodes 164A, 164B, and 164C, each of which may include a work function layer and a bulk (or filled) conductive layer). Gate stacks 160A-160C may include a number of other layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some embodiments, gate dielectrics 162A-162C include a gate dielectric layer disposed above an interface layer (including a dielectric material, such as silicon oxide), and gate electrodes 164A-164C are respectively disposed above gate dielectrics 162A-162C. The gate dielectric layer includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. Examples of high-k dielectric materials include hafnium dioxide (HfO2), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials having a high dielectric constant (k value) relative to the dielectric constant of silicon dioxide (k≈3.9). For example, a high-k dielectric material has a dielectric constant greater than about 3.9. In some embodiments, the gate dielectric layer is a high-k dielectric layer. The gate electrodes 164A-164C comprise conductive materials such as polysilicon, Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the work function layer is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function), and a bulk conductive layer is a conductive layer formed on top of the work function layer. In some embodiments, the work function layer comprises an n-type work function material such as Ti, Ag, Mn, Zr, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer comprises a p-type work function material such as Ru, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Bulk conductive layers include suitable conductive materials such as Al, W, Cu, Ti, Ta, polycrystalline silicon, metal alloys, other suitable materials, or combinations thereof.Hard mask 134 includes any suitable hard mask material, such as any material (e.g., silicon nitride or silicon carbonitride) that can protect the gate stacks 160A-160C during subsequent processes (such as those associated with forming gate contacts and / or source / drain contacts).

[0064] The process can then proceed to form device-level contacts (such as metal-to-polysilicon (MP) contacts, which typically refer to contacts to gate stacks 160A-160C) and metal-to-device (MD) contacts (typically refer to contacts to electrically active regions of the multiple gate devices 100, such as epitaxial source / drain structures 150). Device-level contacts electrically and physically connect IC device components to local contacts (interconnects), which will be further described below. For example, source / drain contacts are formed by performing photolithography and etching processes (such as those described herein) to form contact openings extending through dielectric layer 170 to expose epitaxial source / drain structures 150; performing a first deposition process to form a contact barrier material over dielectric layer 170 that partially fills the contact openings; and performing a second deposition process to form a contact bulk material over the contact barrier material, wherein the contact bulk material fills the remaining portion of the contact openings. In such an embodiment, the contact barrier material and the contact bulk material are disposed in the contact openings and over the top surface of dielectric layer 170. The first and second deposition processes may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. In some embodiments, a silicide layer is formed over the epitaxial source / drain structure 150 prior to the formation of the contact barrier material (e.g., by depositing a metal layer over epitaxial layers 158A and / or 158B and heating the multi-gate device 100 such that the composition of epitaxial layers 158A and / or 158B reacts with the metal composition of the metal layer). In some embodiments, the silicide layer includes a metal composition (e.g., nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof) and the composition of epitaxial layers 158A and / or 158B (e.g., silicon and / or germanium). CMP and / or other planarization processes are performed to remove, for example, excess contact bulk material and contact barrier material from above the top surface of dielectric layer 170, thereby creating source / drain contacts (i.e., contact barrier layers and contact bulk layers filling contact openings). The CMP process planarizes the top surface of the source / drain contacts, thereby forming a substantially flat surface between the top surface of dielectric layer 170 and the top surface of the source / drain contacts.

[0065] The process can continue to form additional components of the MLI component, such as intermediate process layers (e.g., CESL, ILD layers, vias, gate contacts, and / or source / drain contacts) and BEOL structures. The BEOL structure can include additional metallization layers (layers) of the MLI component, such as a first metallization layer (i.e., metal layer 1 (M1) and via layer 0 (V0)), a second metallization layer above the first metallization layer (i.e., metal layer 2 (M2) and via layer 1 (V1))... up to the topmost metallization layer (i.e., metal layer X (MX) and via layer Y (VY), where X is the total number of patterned metalline layers of the MLI component, and Y is the total number of patterned via layers of the MLI component). Each metallization layer includes a patterned metalline layer and a patterned via layer configured to provide at least one BEOL interconnect structure disposed in an insulating layer. The patterned metalline layer and the patterned metal via layer are formed by any suitable process (including by various dual damascene processes) and include any suitable materials and / or layers.

[0066] Figure 5 These are partial or complete cross-sectional views of the multi-gate device 200 according to various aspects of the present invention. For clarity and simplicity, Figure 1 Multi-gate device 100 and Figure 5 The same components of the multi-gate device 200 are designated by the same reference numerals. The multi-gate device 200 is similar to the multi-gate device 100 in many respects, except that the undoped epitaxial layer 152 has a substantially flat, substantially linear top surface. In such embodiments, the thickness of the undoped epitaxial layer 152 along the z-direction is substantially uniform. The multi-gate device 200 can be included in a microprocessor, memory, and / or other IC device. In some embodiments, the multi-gate device 200 is part of an IC chip, a SoC, or thereof, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. For clarity, simplified representations have been provided. Figure 5 To better understand the inventive concept of the present invention. Additional components may be added to the multi-gate device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 200.

[0067] This document discloses epitaxial source / drain structures and methods for fabricating epitaxial source / drain structures to enhance the performance of multi-gate devices such as fin field-effect transistors (FETs) or gate-all-around (GAA) FETs. Numerous different embodiments are provided. An exemplary semiconductor structure includes a first channel layer, a first gate above the first channel layer, a first epitaxial source / drain structure adjacent to the first channel layer, a second channel layer, a second gate above the second channel layer, and a second epitaxial source / drain structure adjacent to the second channel layer. The first channel layer, the first gate, the first epitaxial source / drain structure, the second channel layer, the second gate, and the second epitaxial source / drain structure are located above a semiconductor substrate. The first epitaxial source / drain structure includes a first undoped semiconductor layer and a first doped semiconductor layer above the first undoped semiconductor layer, and the second epitaxial source / drain structure includes a second undoped semiconductor layer and a second doped semiconductor layer above the second undoped semiconductor layer. The first undoped semiconductor layer is located between the first doped semiconductor layer and the semiconductor substrate. The second undoped semiconductor layer is located between the second doped semiconductor layer and the semiconductor substrate. A first undoped semiconductor layer extends to a first depth in the semiconductor substrate, and a second undoped semiconductor layer extends to a second depth in the semiconductor substrate, wherein the second depth is different from the first depth. A first channel layer has a first channel length, and a second channel layer has a second channel length, wherein the second channel length is different from the first channel length.

[0068] In some embodiments, the first depth is greater than the second depth, and the first channel length is greater than the second channel length. In some embodiments, the first configuration of the first undoped semiconductor layer and the first doped semiconductor layer in the first epitaxial source / drain structure differs from the second configuration of the second undoped semiconductor layer and the second doped semiconductor layer in the second epitaxial source / drain structure. In some embodiments, the first doped semiconductor layer extends a first distance below the top surface of the semiconductor substrate, and the second doped semiconductor layer extends a second distance below the top surface of the semiconductor substrate, which is different from the first distance. In some embodiments, the first epitaxial source / drain structure has a first width, the second epitaxial source / drain structure has a second width, and the first width and the second width are different.

[0069] In some embodiments, a first channel layer is disposed above a first semiconductor mesa of a semiconductor substrate, and a second channel layer is disposed above a second semiconductor mesa of the semiconductor substrate. A first undoped semiconductor layer is adjacent to the first semiconductor mesa, and a second undoped semiconductor layer is adjacent to the second semiconductor mesa. The top surface of the first undoped semiconductor layer is a first height above the top surface of the first semiconductor mesa, and the top surface of the second undoped semiconductor layer is a second height above the top surface of the second semiconductor mesa, wherein the first height is equal to the second height. In some embodiments, the first semiconductor mesa has a third height greater than the first height, and the second semiconductor mesa has a fourth height less than the second height. In some embodiments, the first undoped semiconductor layer has a fifth height less than the third height, and the second undoped semiconductor layer has a sixth height less than the fourth height.

[0070] In some embodiments, the first epitaxial source / drain structure further includes a third doped semiconductor layer and a fourth doped semiconductor layer located above the first doped semiconductor layer, and the second epitaxial source / drain structure further includes a fifth doped semiconductor layer and a sixth doped semiconductor layer located above the second doped semiconductor layer. The first doped semiconductor layer is located between the first channel layer and the third doped semiconductor layer. The second doped semiconductor layer is located between the second channel layer and the fifth doped semiconductor layer.

[0071] An exemplary device includes a first transistor and a second transistor. The first transistor has a first channel layer, a first gate surrounding the first channel layer, and a first epitaxial source / drain structure disposed adjacent to the first channel layer. The second transistor has a second channel layer, a second gate surrounding the second channel layer, and a second epitaxial source / drain structure disposed adjacent to the second channel layer. The first channel layer, the first gate, the first epitaxial source / drain structure, the second channel layer, the second gate, and the second epitaxial source / drain structure are disposed above a semiconductor substrate. The first epitaxial source / drain structure includes: a first undoped epitaxial layer having a first trench-shaped top surface; and a first doped epitaxial layer having a first internal portion having a first dopant concentration and a first external portion having a second dopant concentration. The second dopant concentration is less than the first dopant concentration, and the first external portion of the first doped epitaxial layer is disposed between the first undoped epitaxial layer and the first internal portion of the first doped epitaxial layer. The second epitaxial source / drain structure includes: a second undoped epitaxial layer having a second trench-shaped top surface; and a second doped epitaxial layer having a second internal portion having a first dopant concentration and a second external portion having a second dopant concentration. The second trench-shaped top surface is configured differently from the first trench-shaped top surface. The second external portion of the second doped epitaxial layer is disposed between the second undoped epitaxial layer and the second internal portion of the second doped epitaxial layer.

[0072] In some embodiments, the first lowest point of the first trench top surface of the first undoped epitaxial layer relative to the topmost surface of the semiconductor substrate is different from the second lowest point of the second trench top surface of the second undoped epitaxial layer relative to the topmost surface of the semiconductor substrate. In some embodiments, the first undoped epitaxial layer and the second undoped epitaxial layer are each positioned below the topmost surface of the semiconductor substrate. In some embodiments, the first channel layer has a first length, the second channel layer has a second length, and the second length is different from the first length. In some embodiments, the first undoped epitaxial layer has a first central portion disposed between first end portions, the second undoped epitaxial layer has a second central portion disposed between second end portions, the first central portion and the second central portion have different profiles, and the first end portion and the second end portion have different profiles. In some embodiments, the first distance between the bottommost point of the first outer portion of the first doped epitaxial layer and the bottommost surface of the first epitaxial source / drain structure is different from the second distance between the bottommost point of the second outer portion of the second doped epitaxial layer and the bottommost surface of the second epitaxial source / drain structure. In some embodiments, the first epitaxial source / drain structure further includes a third doped epitaxial layer disposed above a first outer portion of the first doped epitaxial layer, and the second epitaxial source / drain structure further includes a fourth doped epitaxial layer disposed above a second outer portion of the second doped epitaxial layer. The third doped epitaxial layer has a first thickness, and the fourth doped epitaxial layer has a second thickness different from the first thickness.

[0073] An exemplary method includes forming a first source / drain trench extending through a first semiconductor layer to a first depth in a semiconductor substrate and a second source / drain trench extending through a second semiconductor layer to a second depth in the semiconductor substrate. The first depth differs from the second depth. The first source / drain trench is located in a first active region of a first size, and the second source / drain trench is located in a second active region of a second size different from the first size. The method further includes forming a first undoped epitaxial layer in the first source / drain trench and forming a second undoped epitaxial layer in the second source / drain trench. A first thickness of the first undoped epitaxial layer is less than the first depth, and a second thickness of the second undoped epitaxial layer is less than the second depth. The method further includes forming a first doped epitaxial layer in the first source / drain trench and over the first undoped epitaxial layer, and forming a second doped epitaxial layer in the second source / drain trench and over the second undoped epitaxial layer.

[0074] In some embodiments, the first undoped epitaxial layer and the second undoped epitaxial layer, as well as the first doped epitaxial layer and the second doped epitaxial layer, are formed in anatomical locations. In some embodiments, forming the first undoped epitaxial layer and the second undoped epitaxial layer includes performing a selective chemical vapor deposition (SCCVD) process and an etching process after the SCCVD process. In some embodiments, the SCCVD process and the etching process are performed in situ. In some embodiments, a first depth is greater than a first distance between the top surface of the first semiconductor layer and the top surface of the semiconductor substrate, and a second depth is less than a second distance between the top surface of the second semiconductor layer and the top surface of the semiconductor substrate.

[0075] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising: Semiconductor substrate; The system comprises a first channel layer, a first gate, and a first epitaxial source / drain structure, wherein the first gate is located above the first channel layer and the first epitaxial source / drain structure is adjacent to the first channel layer, wherein the first channel layer, the first gate, and the first epitaxial source / drain structure are located above the semiconductor substrate, and further wherein the first epitaxial source / drain structure includes: a first undoped semiconductor layer and a first doped semiconductor layer located above the first undoped semiconductor layer, wherein the first undoped semiconductor layer is located between the first doped semiconductor layer and the semiconductor substrate; The second channel layer, the second gate, and the second epitaxial source / drain structure are provided. The second gate is located above the second channel layer, and the second epitaxial source / drain structure is adjacent to the second channel layer. The second channel layer, the second gate, and the second epitaxial source / drain structure are located above the semiconductor substrate. Furthermore, the second epitaxial source / drain structure includes a second undoped semiconductor layer and a second doped semiconductor layer located above the second undoped semiconductor layer. The second undoped semiconductor layer is located between the second doped semiconductor layer and the semiconductor substrate. Wherein, the first undoped semiconductor layer extends to a first depth in the semiconductor substrate, the second undoped semiconductor layer extends to a second depth in the semiconductor substrate, and the second depth is different from the first depth; and The first channel layer has a first channel length, the second channel layer has a second channel length, and the second channel length is different from the first channel length. The first depth is greater than the second depth, and the first channel length is greater than the second channel length.

2. The semiconductor structure according to claim 1, wherein, The length of the first channel is greater than 20 nm, and the length of the second channel is less than or equal to 20 nm.

3. The semiconductor structure according to claim 1, wherein, The first configuration of the first undoped semiconductor layer and the first doped semiconductor layer in the first epitaxial source / drain structure is different from the second configuration of the second undoped semiconductor layer and the second doped semiconductor layer in the second epitaxial source / drain structure.

4. The semiconductor structure according to claim 3, wherein, The first doped semiconductor layer extends to a first distance below the top surface of the semiconductor substrate, and the second doped semiconductor layer extends to a second distance below the top surface of the semiconductor substrate, which is different from the first distance.

5. The semiconductor structure according to claim 1, wherein, The first epitaxial source / drain structure has a first width, the second epitaxial source / drain structure has a second width, and the first width is different from the second width.

6. The semiconductor structure according to claim 1, wherein: The first channel layer is disposed above the first semiconductor mesa of the semiconductor substrate, and the second channel layer is disposed above the second semiconductor mesa of the semiconductor substrate; The first undoped semiconductor layer is adjacent to the first semiconductor mesa, and the second undoped semiconductor layer is adjacent to the second semiconductor mesa; The top surface of the first undoped semiconductor layer is the first height above the top surface of the first semiconductor mesa; The top surface of the second undoped semiconductor layer is a second height above the top surface of the second semiconductor mesa; as well as The first height is equal to the second height.

7. The semiconductor structure according to claim 6, wherein, The first semiconductor mesa has a third height that is greater than the first height, and the second semiconductor mesa has a fourth height that is less than the second height.

8. The semiconductor structure according to claim 1, wherein: The first epitaxial source / drain structure further includes a third doped semiconductor layer located above the first doped semiconductor layer and a fourth doped semiconductor layer located above the third doped semiconductor layer, wherein the first doped semiconductor layer is located between the first channel layer and the third doped semiconductor layer; and The second epitaxial source / drain structure further includes a fifth doped semiconductor layer located above the second doped semiconductor layer and a sixth doped semiconductor layer located above the fifth doped semiconductor layer, wherein the second doped semiconductor layer is located between the second channel layer and the fifth doped semiconductor layer.

9. A semiconductor device, comprising: A first transistor has a first channel layer, a first gate surrounding the first channel layer, and a first epitaxial source / drain structure disposed adjacent to the first channel layer. The first channel layer, the first gate, and the first epitaxial source / drain structure are disposed above a semiconductor substrate. The first epitaxial source / drain structure includes: a first undoped epitaxial layer having a first groove-shaped top surface, and a first doped epitaxial layer having a first internal portion and a first external portion. The first internal portion has a first dopant concentration, and the first external portion has a second dopant concentration, wherein the second dopant concentration is less than the first dopant concentration. The first external portion of the first doped epitaxial layer is disposed between the first undoped epitaxial layer and the first internal portion of the first doped epitaxial layer. The second transistor has a second channel layer, a second gate surrounding the second channel layer, and a second epitaxial source / drain structure disposed adjacent to the second channel layer. The second channel layer, the second gate, and the second epitaxial source / drain structure are disposed above the semiconductor substrate. The second epitaxial source / drain structure includes: a second undoped epitaxial layer having a second trench top surface configured differently from the first trench top surface; and a second doped epitaxial layer having a second inner portion and a second outer portion. The second inner portion has a first dopant concentration, and the second outer portion has a second dopant concentration. The second outer portion of the second doped epitaxial layer is disposed between the second undoped epitaxial layer and the second inner portion of the second doped epitaxial layer.

10. The device according to claim 9, wherein, The first lowest point of the first groove top surface of the first undoped epitaxial layer relative to the top surface of the semiconductor substrate is different from the second lowest point of the second groove top surface of the second undoped epitaxial layer relative to the top surface of the semiconductor substrate.

11. The device according to claim 9, wherein, The first undoped epitaxial layer and the second undoped epitaxial layer are each positioned below the top surface of the semiconductor substrate.

12. The device according to claim 9, wherein, The first channel layer has a first length, the second channel layer has a second length, and the second length is different from the first length.

13. The device according to claim 9, wherein, The first undoped epitaxial layer has a first central portion disposed between the first end portions, and the second undoped epitaxial layer has a second central portion disposed between the second end portions. The first central portion and the second central portion have different contours, and the first end portions and the second end portions have different contours.

14. The device according to claim 9, wherein, The first distance between the bottom point of the first outer portion of the first doped epitaxial layer and the bottom surface of the first epitaxial source / drain structure is different from the second distance between the bottom point of the second outer portion of the second doped epitaxial layer and the bottom surface of the second epitaxial source / drain structure.

15. The device according to claim 9, wherein: The first epitaxial source / drain structure further includes a third doped epitaxial layer disposed above the first external portion of the first doped epitaxial layer; The second epitaxial source / drain structure further includes a fourth doped epitaxial layer disposed above the second outer portion of the second doped epitaxial layer; and The third doped epitaxial layer has a first thickness, and the fourth doped epitaxial layer has a second thickness that is different from the first thickness.

16. A method for manufacturing a semiconductor device, comprising: A first source / drain trench extending through a first semiconductor layer to a first depth in a semiconductor substrate and a second source / drain trench extending through a second semiconductor layer to a second depth in a semiconductor substrate are formed, wherein the first depth is different from the second depth, the first source / drain trench is located in a first active region of a first channel length, and the second source / drain trench is located in a second active region of a second channel length different from the first channel length, wherein the first channel length is greater than the second channel length, and the first depth is greater than the second depth; A first undoped epitaxial layer is formed in the first source / drain trench, and a second undoped epitaxial layer is formed in the second source / drain trench, wherein a first thickness of the first undoped epitaxial layer is less than the first depth, and a second thickness of the second undoped epitaxial layer is less than the second depth; and A first doped epitaxial layer is formed in the first source / drain trench and above the first undoped epitaxial layer, and a second doped epitaxial layer is formed in the second source / drain trench and above the second undoped epitaxial layer.

17. The method according to claim 16, wherein, The formation of the first undoped epitaxial layer and the second undoped epitaxial layer, as well as the formation of the first doped epitaxial layer and the second doped epitaxial layer in different locations, are implemented.

18. The method according to claim 16, wherein, Forming the first undoped epitaxial layer and the second undoped epitaxial layer includes performing a selective chemical vapor deposition (SCCVD) process and then performing an etching process after the SCCVD process.

19. The method according to claim 18, wherein, The selective chemical vapor deposition process and the etching process are carried out in situ.

20. The method of claim 16, wherein: The first depth is greater than the first distance between the topmost surface of the first semiconductor layer and the topmost surface of the semiconductor substrate; as well as The second depth is less than the second distance between the top surface of the second semiconductor layer and the top surface of the semiconductor substrate.

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