Disposable programmable memory array and method of making the same

Abstract

The present disclosure provides a one-time programmable memory array and a method of fabricating the same. The memory array has a plurality of active regions, a plurality of pairs of programming word lines and reading word lines, and a plurality of dummy word lines. The active regions extend along a first direction in a semiconductor substrate and are separately arranged along a second direction. The programming word lines, the reading word lines, and the dummy word lines extend along the second direction on the semiconductor substrate. A cell is defined in the memory array in a region where one of the active regions intersects with one pair of the programming word lines and the reading word lines. The dummy word lines are respectively arranged between adjacent pairs of the programming word lines and the reading word lines. An isolation transistor is defined in a region where one of the active regions intersects with one of the dummy word lines.

Description

Technical Field

[0001] This disclosure claims priority and benefits to U.S. Official Application No. 17 / 214,494, filed March 26, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a memory element and a method for fabricating the same. In particular, it relates to a semiconductor element having a one-time programmable (OTP) memory array and a method for fabricating the semiconductor element. Background Technology

[0003] Non-volatile memory elements retain data even when the power is off. Based on the number of programmable cycles, these non-volatile memory elements can be further classified into multiple-programmable (MTP) memory elements and one-time-programmable (OTP) memory elements. A user can program an MTP memory element multiple times to modify the data stored in it. On the other hand, an OTP memory element can only be programmed once, and the data stored in it cannot be modified.

[0004] Furthermore, the OTP memory element can be classified into a fuse type and an anti-fuse type based on its programming state. Before programming, the fuse type OTP memory element is short-circuited, and after programming, it becomes open. Conversely, before programming, the anti-fuse type OTP memory element is open-circuited, and after programming, it becomes short-circuited. Compared to the fuse type OTP memory element, the anti-fuse type OTP memory element is also compatible with complementary metal-oxide-semiconductor (CMOS) manufacturing processes.

[0005] In an antifuse OTP memory array, insulation between these cell units is important for blocking crosstalk between them. However, the insulation structure that extends between these cell units to achieve this insulation may pose an obstacle to miniaturizing the antifuse OTP memory array.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides an antifuse OTP memory array. The antifuse OTP memory array includes multiple active regions extending along a first direction and separately arranged along a second direction in a semiconductor substrate; multiple pairs of programmable word lines and read word lines extending along the second direction on the semiconductor substrate, wherein a region where one of the active regions intersects with one pair of programmable word lines and one pair of read word lines defines a cell in the antifuse one-time programmable memory array; and multiple dummy word lines extending along the second direction on the semiconductor substrate and respectively disposed between adjacent pairs of programmable word lines and read word lines, wherein a region where one of the active regions intersects with one of the dummy word lines defines an insulating transistor.

[0008] Another embodiment of this disclosure provides an antifuse OTP memory array. The antifuse OTP memory array includes a plurality of cell units arranged along a plurality of rows and columns, and each cell unit includes an access transistor and an antifuse storage element electrically coupled to a source / drain terminal of the access transistor; and a plurality of insulating transistors, each electrically coupled to an adjacent cell unit in the same column and configured to remain in an off state so that adjacent cell units are electrically insulated from each other.

[0009] Another embodiment of this disclosure provides an antifuse OTP memory array. The antifuse OTP memory array includes an active region extending laterally in a semiconductor substrate; a first read word line and a first programmable word line extending on and intersecting the active region, and separated from each other, wherein a first cell of the antifuse one-time programmable memory array is defined in a region where the active region intersects with the first read word line and the first programmable word line; a pair of first source / drain structures disposed in the active region and within the first cell, wherein the first read word line is disposed between the pair of first source / drain structures, and the first programmable word line overlaps with one of the first source / drain structures; a second read word line and a second programmable word line... A word line extends over and intersects the active region, and is separated from each other, wherein a second cell of the antifuse one-time programmable memory array is defined in a region where the active region intersects with the second read word line and the second programmable word line; a pair of second source / drain structures are disposed in the active region and within the second cell, wherein the second read word line is disposed between the pair of second source / drain structures, and the first programmable word line overlaps with one of the second source / drain structures; and a dummy word line extends over the active region and is located between the first and second cells, wherein an insulated transistor is defined in a region where the active region intersects with the dummy word line.

[0010] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0011] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0012] Figure 1A This is a wiring diagram illustrating an antifuse OTP memory array according to an embodiment of the present disclosure.

[0013] Figure 1B This is a circuit diagram illustrating an embodiment of the present disclosure. Figure 1A The adjacent cells in the antifuse OTP memory array shown.

[0014] Figure 2 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure, for example. Figure 1A The adjacent cell arrangement shown is along the row direction.

[0015] Figure 3 This is a flowchart illustrating an embodiment of this disclosure, for example. Figure 2 The method for preparing the structure shown.

[0016] Figures 4A to 4M This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure as follows: Figure 3 The intermediate structures at different stages during the preparation method shown.

[0017] Figure 5 This is a cross-sectional schematic diagram illustrating adjacent unit cells arranged along the column direction in other embodiments of this disclosure.

[0018] Figure 6A and Figure 6B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation of... Figure 5 The structures shown are the various structures during the structural period.

[0019] Explanation of reference numerals in the attached figures:

[0020] 10: Antifuse OTP memory array

[0021] 100: Unit cell

[0022] 100': Unit cell

[0023] 102: Insulation structure

[0024] 200: Semiconductor substrate

[0025] 204: Gate dielectric layer

[0026] 206: Gate spacer

[0027] 208: Source / Drain Structure

[0028] 210: Capacitor dielectric layer

[0029] 210': Capacitor dielectric layer

[0030] 212: Gate dielectric layer

[0031] 214: Gate spacer

[0032] 216: Isolation layer

[0033] 216a: Isolation layer

[0034] 216b: Isolation layer

[0035] 216c: Isolation layer

[0036] 218: Wiring Components

[0037] 218a: Conductive via

[0038] 218b: Conductive trace / pad

[0039] 400: Gate dielectric material layer

[0040] 402: Gate material layer

[0041] 404: Spacer material layer

[0042] 406: Dielectric material layer

[0043] 408: Conductive material layer

[0044] 600: Dielectric material layer

[0045] 602: Conductive material layer

[0046] AA: Active Zone

[0047] AF: Anti-fuse storage element

[0048] AT: Access Transistor

[0049] BL: Bitline

[0050] CN: Common Node

[0051] DT: Insulating Transistor

[0052] DW: Virtual Character Line

[0053] H: Opening

[0054] S11: Steps

[0055] S13: Steps

[0056] S15: Steps

[0057] S17: Steps

[0058] S19: Steps

[0059] S21: Steps

[0060] S23: Steps

[0061] S25: Steps

[0062] S27: Steps

[0063] S29: Steps

[0064] S31: Steps

[0065] S33: Steps

[0066] S35: Steps

[0067] S37: Steps

[0068] S39: Steps

[0069] WP: Programmatic Character Line

[0070] WR: Read character line

[0071] X: Direction

[0072] Y: direction Detailed Implementation

[0073] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0074] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0075] Figure 1A This is a wiring diagram illustrating an antifuse OTP memory array 10 according to an embodiment of the present disclosure. Figure 1B This is a circuit diagram illustrating an embodiment of the present disclosure. Figure 1A Adjacent cell 100 in the antifuse OTP memory array 10 shown.

[0076] Please refer to Figure 1A The antifuse OTP memory array 10 includes a plurality of cell cells 100 arranged along a plurality of columns and a plurality of rows. Cell cells 100 in the same column are arranged along direction X, while cell cells 100 in the same row can be arranged along direction Y, which intersects direction X. Each cell cell 100 is coupled to a programmable word line WP, a read word line WR, and a bit line BL, and is defined in an active region AA that intersects the programmable word line WP and the read word line WR. Further reference will be made to... Figure 2 As described, the active region AA can be a doped region in a semiconductor substrate, while the programmable word line WP, read word line WR, and bit line BL can be conductive lines on the semiconductor substrate. In some embodiments, the cell cells 100 in the same column can share the same active region AA and the same bit line BL, and the cell cells 100 in the same row can share one of the programmable word lines WP and one of the read word lines WR. In these embodiments, the multiple bit lines BL and multiple active regions AA can extend along the X direction, while the multiple programmable word lines WP and multiple read word lines WR can extend along the Y direction.

[0077] Please refer to Figure 1A and Figure 1BEach cell 100 includes an access transistor AT and an antifuse storage element AF, wherein the antifuse storage element AF is coupled to the access transistor AT. In some embodiments, the access transistor AT is a three-terminal element, while the antifuse storage element AF is a two-terminal element. For example, the access transistor AT may be a field-effect transistor (e.g., an N-type field-effect transistor), and the antifuse storage element AF may be a capacitor. One of the read word lines WR coupled to the cell 100 serves as a gate terminal of the access transistor AT in the cell 100. One source / drain terminal of the access transistor AT is coupled to one of the bit lines BL. The other source / drain terminals of the access transistor AT are coupled to a terminal of the antifuse storage element AF and may be represented as a common node CN (e.g., ...). Figure 1B (As shown). Furthermore, one of the programmed character lines WP is used as another terminal of the antifuse storage element AF.

[0078] Accordingly, a voltage bias across the antifuse memory element AF is determined by a voltage supplied to the programming word line WP and a voltage at the common node CN. If a cell 100 is selected for programming, the access transistor AT of the selected cell 100 is turned on, and the voltage at the common node CB of the selected cell 100 is pushed to a voltage (e.g., a ground voltage), which is received by a bit line BL coupled to the selected cell 100. Furthermore, the programming word line WP coupled to the selected cell 100 can receive a sufficiently high programming voltage, and a difference between this programming voltage and the selected bit line BL may cause the antifuse memory element AF to break down in order to program the antifuse memory element AF. Once the antifuse memory element AF is programmed, the two terminals of the antifuse memory element AF are short-circuited, and a resistive state of the antifuse memory element AF changes from a high-resistance state to a low-resistance state. This change in resistance is the opposite of the change in resistance of an electronic fuse, and this may be the origin of the term "anti-fuse".

[0079] On the other hand, during programmed operation, the antifuse storage element AF in a non-selected cell 100 may not be programmed. The access transistor AT in the non-selected cell 100 remains in an off state, and therefore the source / drain terminals of this access transistor AT at the common node CN are electrically floated. Therefore, the difference between a voltage supplied to the programmed word line WP coupled to the non-selected cell 100 and a voltage at the common node CN is not sufficient to break the antifuse storage element AF in the non-selected cell 100. Therefore, the antifuse storage element AF in the non-selected cell 100 may remain in an open state (e.g., a high-resistance state).

[0080] During a read operation, the access transistor AT in a selected cell 100 is turned on. Furthermore, the programming word line WP coupled to the selected cell 100 receives a read voltage lower than the programming voltage used in a programming operation, and the bit line BL coupled to the selected cell 100 can be grounded. If the antifuse memory element AF in the selected cell 100 has been programmed (e.g., short-circuited), the difference between the read voltage supplied to the programming word line WP and the ground voltage on the bit line BL may result in a read current flowing through the antifuse memory element AF. On the other hand, if the antifuse memory element AF is in an open state, almost no current flows through it. By sensing the presence of this read current on the bit line BL, a resistive state of the antifuse memory element AF (e.g., a bit of metadata stored in the antifuse memory element AF) can be confirmed.

[0081] In some embodiments, each active region AA extends through a column of cells 100 and is shared by these cells 100 in the same column. To block crosstalk between adjacent cells 100 passing through the shared active region A, insulated transistors DT are respectively disposed between adjacent cells 100 arranged along a column direction (e.g., direction X). These insulated transistors DT may be parasitic field-effect transistors, each of which is formed by a virtual word line DW, an overlapping portion of a lower active region AA, and access transistors AT on opposite sides of the virtual word line DW and connected to multiple source / drain terminals of the active region AA. Figure 1A and Figure 1BIn one example, the overlapping portions of the virtual word lines DW, the lower active region AA, and the source / drain terminals of the access transistor AT on opposite sides of the virtual word lines DW and coupled to the bit line BL can form the insulated transistors DT. By controlling a voltage on the virtual word lines DW, the insulated transistors DT can be maintained in a closed state. Therefore, multiple current paths may not form in the overlapping portions of the active region AA and the virtual word lines DW. In other words, crosstalk between adjacent cells 100 passing through these portions of the active regions A can be blocked. For example, the insulated transistors DT are N-type field-effect transistors, and the virtual word lines DW are coupled to a negative voltage to ensure that the insulated transistors DT are in a closed state. Alternatively, the virtual word lines DW of the N-type insulated transistors DT can be grounded, and the N-type insulated transistors DT can also be maintained in a closed state.

[0082] In some embodiments, the access transistors AT and the antifuse memory elements AF in adjacent cell cells 100 on opposite sides of a virtual character line DW are symmetrically arranged with respect to the virtual character line DW. For example... Figure 1A In the example shown, the read word lines WR of the access transistors AT and the programmable word lines WP of the antifuse memory elements AF are symmetrically arranged relative to the virtual word lines DW, and each read word line WR extends between the virtual word line DW and one of the programmable word lines WP. In these embodiments, although not shown, other virtual word lines DW may extend between two programmable word lines WP (e.g., as shown in the figure). Figure 1A The rightmost programmed character line WP and an additional programmed character line (not shown) to the right of this programmed character line WP are respectively positioned between this virtual character line DW and a read character line WR. In this way, the source and drain terminals of an access transistor AT can be used as the source / drain terminals of one of the insulated transistors DT.

[0083] Compared to dividing each active region AA into separate segments using an insulating structure to block crosstalk between adjacent cell cells 100, using insulated transistors DT to achieve insulation between adjacent cell cells 100 can reduce the overall footprint or increase the memory density of the antifuse one-time programmable memory array 10, because the virtual character line DW can be formed with a width (e.g., 20 nm), which is much smaller than the width of the isolation structure between adjacent cell cells 100 (e.g., 50 nm). Furthermore, by avoiding the use of an insulating structure that blocks crosstalk between adjacent cell cells 100 arranged along the column direction (e.g., direction X), a possible stress effect on these cell cells 100 (caused during the formation of the insulating structure) can be effectively reduced.

[0084] On the other hand, according to the embodiments of this disclosure, the active regions AA arranged along the row direction (e.g., direction Y) are insulated from and separated from each other by an insulating structure 102 (in the blank area of ​​FIG. 1). The insulating structure 102 may laterally surround the active regions AA, but does not extend between adjacent cell cells 100 arranged along the column direction (e.g., direction X). As described above, the insulation between adjacent cell cells 100 arranged along the column direction is achieved by insulating transistors DT.

[0085] Figure 2 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure, for example. Figure 1A The adjacent unit cells 100 are arranged along the column direction (e.g., direction X).

[0086] Please refer to Figure 2 Two adjacent unit cells 100 formed at an edge of an active region AA are schematically described. The active region AA may be a well region in the semiconductor substrate 200 and may extend from an upper surface of the semiconductor substrate 200 into the semiconductor substrate 200. Furthermore, the active region AA is laterally surrounded by an insulating structure 102. The insulating structure 102 may be a trench isolation structure and extends from the upper surface of the semiconductor substrate 200 into the semiconductor substrate 200, with a depth greater than, equal to, or less than a depth of the active region AA. Please refer to... Figure 1A The insulating structure 102 may not extend into the spaces between adjacent unit cells 100 arranged along the column direction. In some embodiments, the semiconductor substrate 200 is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer), and the insulating structure 102 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof.

[0087] In each unit cell 100, the access transistor AT includes a read word line WR disposed on the active region AA. The read word line WR contacts the active region AA via a gate dielectric layer 204 for capacitive coupling to the active region AA. In some embodiments, a stacked structure including the read word line WR and the gate dielectric layer 204 is laterally surrounded by a gate spacer 206. According to some embodiments, the read word line WR comprises polysilicon, while the gate dielectric layer 204 comprises silicon oxide. Furthermore, the gate spacer 206 may be a single layer or a multilayer structure comprising silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. However, other suitable materials may be used to form the read word line WR, the gate dielectric layer 204, and the gate spacer 206, and this disclosure is not limited to the materials of these elements.

[0088] Each access transistor AT also includes a plurality of source / drain structures 208 disposed on opposite sides of the read word line WR. These source / drain structures 208 serve as the source and drain terminals of the access transistor AT. In some embodiments, the source / drain structures 208 are multiple doped regions in the semiconductor substrate 200 and extend from the upper surface of the semiconductor substrate 200 into the active region AA. In other embodiments, the source / drain structures 208 are multiple epitaxial structures formed in multiple recesses at the upper surface of the semiconductor substrate 200. The source / drain structures 208 may or may not extend into the region below the gate spacer 206. A conductivity type of the source / drain structures 208 may be complementary to a conductivity type of the active region AA. For example, the active region AA is P-type, while the source / drain structures 208 are N-type. Furthermore, the dimensions of the source / drain structures may be the same or different from each other.

[0089] One of the source / drain structures 208 of each access transistor AT can be considered as a terminal of the antifuse storage element AF in the same unit cell 100, and is described as follows (see reference). Figure 1B The common node CN. A programmed word line WP disposed above the source / drain structure 208 serves as another terminal of the antifuse memory element AF. The programmed word line WP contacts this source / drain structure 208 via a capacitor dielectric layer 210 for capacitive coupling to this source / drain structure 208. When an antifuse memory element AF is selected for programming, a breakdown may occur in the capacitor dielectric layer 210 due to a large bias voltage between the two terminals of the antifuse memory element AF. As a result of the breakdown, the two terminals of the antifuse memory element AF may be short-circuited, and the antifuse memory element AF may be considered to be programmed into a low-resistance state. The programmed word line WP contains a conductive material, which may be the same as or different from the conductive material forming the read word line WR. For example, in embodiments where the read word line WR contains polysilicon, the programmed word line WP may contain tungsten. Furthermore, the capacitor dielectric layer 210 may comprise a dielectric material that is the same as or different from the dielectric material forming the gate dielectric layer 204. For example, in embodiments where the gate dielectric layer 204 comprises silicon oxide, the capacitor dielectric layer 210 may comprise silicon oxide or a dielectric material with a high dielectric constant. Furthermore, the thicknesses of the programmable word line WP and the capacitor dielectric layer 210 may be the same as or different from the thicknesses of the read word line WR and the gate dielectric layer 204, respectively. However, the total thickness of the programmable word line WP and the capacitor dielectric layer 210 may be substantially the same as the total thickness of the read word line WR and the gate dielectric layer 204.

[0090] The insulated transistor ST between adjacent cell cells 100 includes a virtual word line DW, which serves as a gate terminal. The source / drain structures 208 of the virtual word lines DW located on opposite sides of the access transistors AT in the adjacent cell cell 100 can be used as the source and drain terminals of the insulated transistor DT. Figure 1A As shown, although not shown in the figure, some insulated transistors DT can be respectively disposed between two antifuse storage elements AF of adjacent cell 100, and the source / drain structures 208 that serve as terminals of these antifuse storage elements SF can serve as source and drain terminals of these insulated transistors DT. The virtual character line DW contacts the active region AA via a gate dielectric layer 212 for capacitive coupling to the active region AA. In addition, a stacked structure including the virtual character line DW and the gate dielectric layer 212 can be laterally surrounded by a gate spacer 214. The source / drain structures 208 that serve as source and drain terminals of the insulated transistors DT may or may not extend into the region below the gate spacer 214. According to some embodiments, the virtual character line DW includes a conductive material (e.g., polysilicon) for forming the read character line WR; the gate dielectric layer 212 includes a dielectric material (e.g., silicon oxide) for forming the gate dielectric layer 204; and the gate spacer 214 includes an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof) for forming the gate spacer 206. However, this disclosure is not limited to the materials used to form the virtual character line DW, the gate dielectric layer 212, and the gate spacer 214. Furthermore, according to some embodiments of this disclosure, the virtual character line DW, the gate dielectric layer 212, and the gate spacer 214 are structurally identical to the read character line WR, the gate dielectric layer 204, and the gate spacer 206, respectively. However, the virtual character line DW and the gate spacer 214 may differ in size and / or shape from the read character line WR, the gate dielectric layer 204, and the gate spacer 206.

[0091] In some embodiments, a channel length (measured from one of the source / drain structures 208 of the insulated transistor DT to the other) is ensured to be sufficiently long so that the insulated transistor DT is prevented from being accidentally turned on. The channel length of the insulated transistor DT can be adjusted by modifying a width of the virtual character line DW and / or modifying a thickness of the gate spacer 214 used to define the source / drain structures 208 of the insulated transistor DT.

[0092] A stack of multiple isolation layers 216 may be disposed on a semiconductor substrate 200. The access transistors AT, antifuse memory elements AF, and isolating transistors DT, located above the upper surface of the semiconductor substrate 200, may be laterally surrounded by the lowest isolation layer 216 and covered by the other isolation layers 216. For example, the isolation layers 216 may include an isolation layer 216a, an isolation layer 216b, and an isolation layer 216c. The read word lines WR and the gate spacers AT surrounding the underlying gate dielectric layers 204 and the access transistors AT; the programmable word lines WP and the capacitor dielectric layers 210 surrounding the underlying antifuse memory elements AF; and the virtual word lines DW and the gate spacers 214 surrounding the underlying gate dielectric layers 212 and the isolating transistors DT may be laterally surrounded by isolation layer 216a. Furthermore, an isolation layer 216b is stacked on isolation layer 216a and covered by isolation layer 216c. Each of these isolation layers 216 contains an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like. In some embodiments, a contact etch stop layer (not shown) is disposed along a lower surface of the lowest isolation layer 216 (e.g., isolation layer 216a) and has sufficient etch selectivity relative to these isolation layers 216. Additionally, additional etch stop layers may be disposed between adjacent isolation layers 216 and also have sufficient etch selectivity relative to these isolation layers 216.

[0093] Multiple routing elements 218 are formed in the stack of isolation layers 216 and configured to out-rout the access transistors AT, the antifuse memory elements AF, and the insulating transistors DT. The routing elements 218 may include multiple conductive vias 218a and multiple conductive traces / pads 218b. Each conductive via 218a may pass through one or more isolation layers 216 along a stacking direction of the isolation layers 216 to provide a vertical conductive path within the isolation layers 216. Conversely, each conductive trace / pad 218b may extend laterally within one of the isolation layers 216 to provide a horizontal conductive path. Figure 2 As shown, the read character lines WR, the programmed character lines WP, and the virtual character lines DW are wired through the conductive vias 218a and the conductive traces / pads 218b. Although not shown in the figure, it is as follows... Figure 1A As shown, the access transistors AT are not shared by the source / drain structure 208 of the antifuse access elements AF, and can be routed to multiple bit lines BL through some wiring elements 218.

[0094] It should be understood that, although not shown in the figures, a complete back-end (BEOL) structure may include multiple isolation layers 216 and multiple wiring elements 218 stacked along a vertical direction. Furthermore, in addition to the antifuse one-time programmable memory array 10, other integrated circuits may also be formed in / on the semiconductor substrate 200, but occupying different areas.

[0095] As described above, each active region AA can extend continuously along the column direction (e.g., direction X) by a column of cell cells 100 without interruption by the insulating structure 102. Instead of using the isolation structure 102 to block crosstalk between adjacent cell cells 100 arranged along the column direction, these isolation transistors DT are disposed between these adjacent cell cells 100 to ensure insulation between them. Therefore, this insulation between adjacent cell cells 100 can be achieved by using a smaller footprint area, thereby increasing memory density. Furthermore, by avoiding dividing each active region AA into segments by the insulating structure 102, a possible stress effect on these cell cells 100 (caused during the formation of the insulating structure 1023) can be effectively reduced.

[0096] On the other hand, insulation between these unit cells 100 arranged along the row direction (e.g., direction Y) can still be achieved by the insulation structure 102. In other words, these active regions AA arranged along the row direction (e.g., direction Y) are separated from each other by the insulation structure 102.

[0097] Figure 3 This is a flowchart illustrating an embodiment of this disclosure, for example. Figure 2 The method for preparing the structure shown. Figures 4A to 4M This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure as follows: Figure 3 The intermediate structures at different stages during the preparation method shown.

[0098] Please refer to Figure 3 and Figure 4AStep S11 is performed, and an insulating structure 102 is formed in the semiconductor substrate 200. As described above, the insulating structure 102 defines the boundaries of the active regions AA formed in subsequent steps. In some embodiments, the method of fabricating the insulating structure 102 includes forming a recess on the upper surface of the semiconductor substrate 200 by a photolithography process and an etching process (e.g., an anisotropic etching process). Next, an isolation material is formed on the recessed semiconductor substrate 200 by a deposition process, such as a chemical vapor deposition (CVD) process. Furthermore, the portions of the isolation material on the upper surface of the semiconductor substrate 200 can be removed by a planarization process, and the remaining portions of the isolation material form the insulating structure 102. For example, the planarization process may include a polishing process, an etching process, or a combination thereof.

[0099] Subsequently, step S13 is performed, and a plurality of active regions AA are formed in the regions of the semiconductor substrate 200 that are laterally surrounded by the insulating structure 102. In some embodiments, the method for fabricating the active regions AA may include an ion implantation process. During the ion implantation process, the insulating structure 102 may be used as a mask pattern.

[0100] In other embodiments, the ion implantation process is performed prior to the formation of the insulating structure 102. In these other embodiments, a well region is formed by the ion implantation process, and then the insulating structure 102 is formed in this well region. The portions of the well region laterally surrounded by the insulating structure 102 may form the active regions AA.

[0101] refer to Figure 3 and Figure 4B Step S15 is executed, and a gate dielectric material layer 400 and a gate material layer 402 are sequentially formed on the semiconductor substrate 200. The gate dielectric material layer 400 is patterned to form gate dielectric layers 204 and 212, while the gate material layer 402 is patterned to form read word lines WR and virtual word lines DW. In some embodiments, the fabrication technique of the gate dielectric material layer 400 includes an oxidation process or a deposition process (e.g., a CVD process), and the fabrication method of the gate material layer 402 includes a deposition process (e.g., a CVD process).

[0102] Please refer to Figure 3 and Figure 4CStep S17 is performed to pattern the gate dielectric material layer 400 to form gate dielectric layers 204 and 212, and to pattern the gate material layer 402 to form the read character lines WR and the virtual character lines DW. In some embodiments, the patterning method of the gate dielectric material layer 400 and the gate material layer 402 includes a photolithography process and at least one etching process (e.g., at least one anisotropic etching process). In other processes, a plurality of hard mask patterns (not shown) are formed on the gate material layer 402, and then the gate material layer 402 and the gate dielectric material layer 400 are etched using the hard mask patterns as shadow masks to form the gate dielectric layers 204 and 212, the read character lines WR, and the virtual character lines DW. In these other embodiments, after the patterning process, the read character lines WR and the virtual character lines DW may remain covered by the hard mask patterns.

[0103] Please refer to Figure 3 and Figure 4D Step S19 is executed, and a spacer material layer 404 is formed on the current structure. The spacer material layer 404 will be patterned to form a plurality of gate spacers 206, 214. Currently, the spacer material layer 404 can fully and conformally cover as shown in the figure. Figure 4C The structure. In some embodiments, the method for preparing the spacer material layer 404 includes a deposition process, such as a CVD process.

[0104] Please refer to Figure 3 and Figure 4E Step S21 is performed, and the spacer material layer 404 is patterned to form the gate spacers 206 and 214. In some embodiments, portions of the spacer material layer 404 lining the upper surface of the semiconductor substrate 200, an upper surface of the insulating structure 102, the upper surfaces of the read word lines WR, and the upper surfaces of the virtual word lines DW are removed by an etching process, such as an anisotropic etching process. The remaining portions of the spacer material layer 404 form the gate spacers 206 and 214. Since a lithography process may not be used during this patterning, the formation of the gate spacers 206 and 214 can be considered a self-aligned process.

[0105] Please refer to Figure 3 and Figure 4FStep S23 is executed, and the source / drain structures 208 are formed in the active regions AA. In some embodiments, the method of fabricating the source / drain structures 208 includes an ion implantation process. During the ion implantation process, the read word lines WR, the virtual word lines DW, and the gate spacers 206, 214 can be used as shielding masks. In those embodiments where the read word lines WR and the virtual word lines DW remain covered by the hard masking patterns, these hard masking patterns can shield multiple incident ions together with the gate spacers 206, 214 during the ion implantation process. Furthermore, in some embodiments, a thermal treatment, such as a drive-in process, can continue the ion implantation process. Since a photolithography process may not be used to form the source / drain structures 208, the source / drain structures 208 can be considered a self-aligned process.

[0106] Please refer to Figure 3 and Figure 4G Step S25 is performed, and an isolation layer 216a is formed on the semiconductor substrate 200. In some embodiments, the method for preparing the isolation layer 216a includes forming an isolation material layer by a deposition process to fully cover the semiconductor substrate 200. Figure 4F The structure, for example, is a CVD process. Next, a planarization process (e.g., a polishing process, an etching process, or a combination thereof) can be used to remove portions of the isolation material layer above the read character lines WR and the virtual character lines DW, and the remaining portions of the isolation material layer form isolation layer 216a. In embodiments where the read character lines WR and the virtual character lines WR are covered by the hard mask patterns, the hard mask patterns can be removed along with portions of the isolation material layer during the planarization process. Alternatively, the hard mask patterns can be retained, and the upper surfaces of the hard mask patterns can be substantially coplanar with an upper surface of isolation layer 216a.

[0107] Please refer to Figure 3 and Figure 4H Step S27 is executed, and a plurality of openings H are formed in the isolation layer 216a. These openings H are configured to accommodate the capacitor dielectric layers 210 and the programmed character lines WP formed in subsequent steps, and pass through the isolation layer 216a to reach... Figure 1A and Figure 1B The source / drain structure 208 of the common node CN is described. According to some embodiments, the fabrication method of the openings H includes a photolithography process and an etching process (e.g., an anisotropic etching process).

[0108] Please refer to Figure 3 and Figure 4IStep S29 is performed, and a dielectric material layer 406 is formed on the current structure. The dielectric material layer 406 will be patterned to form the capacitor dielectric layer 210 in a subsequent step. Currently, the dielectric material layer 406 may extend along the upper surface of the isolation layer 216a and may fill the openings H. In some embodiments, the method of preparing the dielectric material layer 406 includes a deposition process, such as a CVD process.

[0109] Please refer to Figure 3 and Figure 4J Step S31 is performed, and the dielectric material layer 406 is patterned to form the capacitor dielectric layer 210. During patterning, portions of the dielectric material layer 406 above the isolation layer 216a can be removed by a planarization process, for example, a polishing process, an etching process, or a combination thereof. Furthermore, portions of the dielectric material layer 406 in the openings H are recessed by an etching process, for example, an anisotropic etching process. These resulting portions of the dielectric material layer 406 form the capacitor dielectric layer 210.

[0110] Please refer to Figure 3 and Figure 4K Step S33 is executed, and a conductive material layer 408 is formed on the current structure. The conductive material layer 408 will be patterned to form the programmed character lines WP in subsequent steps. Currently, the conductive material layer 408 may extend along the upper surface of the isolation layer 216a and may fill the openings H. Accordingly, the capacitor dielectric layers 210 may be covered by the conductive material layer 408. In some embodiments, the method of preparing the conductive material layer 408 includes a deposition process (e.g., a physical vapor deposition (PVD) process), a plating process, or a combination thereof.

[0111] Please refer to Figure 3 and Figure 4L Step S35 is performed, and the conductive material layer 408 is patterned to form the programmed character lines WP. This patterning may include the removal of portions of the conductive material layer 408 above the upper surface of the insulating layer 216a. In some embodiments, this removal is achieved by a planarization process. For example, the planarization process may include a polishing process, an etching process, or a combination thereof.

[0112] Please refer to Figure 3 and Figure 4M Step S37 is executed, and the isolation layers 216B and 216c are formed on the isolation layer 216a. In some embodiments, the preparation method of each isolation layer 216b and 216c includes a deposition process, such as a CVD process.

[0113] In some embodiments, although not shown in the figures, some conductive vias (or represented as multiple contact plugs) may be formed in the isolation layer 216a prior to the formation of the isolation layers 216b, 216c, to wire some source / drain structures 208.

[0114] Please refer to Figure 3 and Figure 2 Step S39 is performed after the isolation layers 216b and 216c are formed, and a plurality of wiring elements 218 are formed in the isolation layers 216b and 216c. In some embodiments, at least one damascene process is used to form the wiring elements 218.

[0115] Up to this point, it has been formed as follows Figure 2 The structure shown is further illustrated. Furthermore, a BEOL process can be performed on this structure to form a device wafer. Additionally, this device wafer can undergo a packaging process to form multiple device dies.

[0116] Figure 5 This is a cross-sectional schematic diagram illustrating adjacent unit cells 100' arranged along a column direction (e.g., direction X) in other embodiments of this disclosure. These unit cells 100' are similar to... Figure 2 The unit cells 100 shown will only be described in terms of their differences. Identical or similar parts in the unit cells 100 and 100' will not be described again.

[0117] Please refer to Figure 5 In some embodiments, a plurality of capacitor dielectric layers 210' extend further along the programmed character lines WP, such that the programmed character lines WP laterally contact the isolation layer 216a via portions of the further extension of the capacitor dielectric layers 210'. In these embodiments, the programmed character lines WP can be considered to be disposed within the recesses defined by the capacitor dielectric layers 210'. Furthermore, the uppermost surface of the capacitor dielectric layers 210' can be substantially coplanar with the upper surfaces of the programmed character lines WP.

[0118] Figure 6A and Figure 6B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation of... Figure 5 The structures shown are the various structures during the structural period.

[0119] Please refer to Figure 6A Regarding Figure 5 The method for fabricating the capacitor dielectric layer 210' and the programmed character lines WP shown is as follows: Figure 4HAs shown, after forming the openings H in the isolation layer 216a, a dielectric material layer 600 may be conformally formed on the resulting structure. The dielectric material layer 600 will be patterned to form the capacitor dielectric layer 210'. Currently, the dielectric material layer 600 may define a plurality of recesses in the corresponding openings H. In some embodiments, the method of fabricating the dielectric material layer 600 includes a deposition process, such as a CVD process.

[0120] Next, a conductive material layer 602 is formed on the dielectric material layer 600. The conductive material layer 602 may fill the recesses defined by the dielectric material layer 600 and will be patterned to form the programmed character lines WP. In some embodiments, the method of preparing the conductive material layer 602 includes a deposition process (e.g., a PVD process), a plating process, or a combination thereof.

[0121] Please refer to Figure 6B The dielectric material layer 600 and the conductive material layer 602 above the upper surface of the isolation layer 216a are removed. The remaining portions of the dielectric material layer 600 form the capacitor dielectric layers 210', while the remaining portions of the conductive material layer 602 form the programmed character lines WP. In some embodiments, a planarization process is performed to remove the portions of the dielectric material layer 600 and the conductive material layer 602 above the upper surface of the isolation layer 216a. For example, the planarization process may include a polishing process, an etching process, or a combination thereof.

[0122] Executable Figure 3 , Figure 4M and Figure 2 More processes are shown to form such Figure 5 The structure shown.

[0123] As described above, an antifuse one-time programmable memory array is provided. In this antifuse one-time programmable memory array, multiple active regions extend continuously along a column of cells without being interrupted by an insulating structure. Instead of using an insulating structure to block crosstalk between adjacent cells arranged along the column direction, multiple insulated transistors are disposed between these adjacent cells to ensure insulation between them. Therefore, insulation between these adjacent cells can be achieved using a smaller footprint, thereby increasing the memory density of the antifuse one-time programmable memory array. Furthermore, by avoiding dividing each active region into multiple segments through the insulating structure, a possible stress effect on these cells (caused during the formation of the insulating structure) can be effectively reduced.

[0124] One embodiment of this disclosure provides an antifuse OTP memory array. The antifuse OTP memory array includes multiple active regions extending along a first direction and separately arranged along a second direction in a semiconductor substrate; multiple pairs of programmable word lines and read word lines extending along the second direction on the semiconductor substrate, wherein a region where one of the active regions intersects with one pair of programmable word lines and one pair of read word lines defines a cell in the antifuse one-time programmable memory array; and multiple dummy word lines extending along the second direction on the semiconductor substrate and respectively disposed between adjacent pairs of programmable word lines and read word lines, wherein a region where one of the active regions intersects with one of the dummy word lines defines an insulating transistor.

[0125] Another embodiment of this disclosure provides an antifuse OTP memory array. The antifuse OTP memory array includes a plurality of cell units arranged along a plurality of rows and columns, and each cell unit includes an access transistor and an antifuse storage element electrically coupled to a source / drain terminal of the access transistor; and a plurality of insulating transistors, each electrically coupled to an adjacent cell unit in the same column and configured to remain in an off state so that adjacent cell units are electrically insulated from each other.

[0126] Another embodiment of this disclosure provides an antifuse OTP memory array. The antifuse OTP memory array includes an active region extending laterally in a semiconductor substrate; a first read word line and a first programmable word line extending on and intersecting the active region, and separated from each other, wherein a first cell of the antifuse one-time programmable memory array is defined in a region where the active region intersects with the first read word line and the first programmable word line; a pair of first source / drain structures disposed in the active region and within the first cell, wherein the first read word line is disposed between the pair of first source / drain structures, and the first programmable word line overlaps with one of the first source / drain structures; a second read word line and a second programmable word line... A word line extends over and intersects the active region, and is separated from each other, wherein a second cell of the antifuse one-time programmable memory array is defined in a region where the active region intersects with the second read word line and the second programmable word line; a pair of second source / drain structures are disposed in the active region and within the second cell, wherein the second read word line is disposed between the pair of second source / drain structures, and the first programmable word line overlaps with one of the second source / drain structures; and a dummy word line extends over the active region and is located between the first and second cells, wherein an insulated transistor is defined in a region where the active region intersects with the dummy word line.

[0127] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0128] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this publication.

Claims

1. An antifuse one-time programmable memory array, comprising: Multiple cell units are arranged along multiple rows and multiple columns, and each cell unit includes an access transistor and an antifuse memory element electrically coupled to a source / drain terminal of the access transistor. as well as Multiple insulated transistors, each electrically coupled to an adjacent cell in the same column, are configured to remain in a closed state such that adjacent cells are electrically insulated from each other. A source / drain terminal of the access transistor in a first cell and a source / drain terminal of the access transistor in a second cell are considered as the source / drain terminals of one of the insulating transistors coupled between the first and second cells.

2. The antifuse one-time programmable memory array as claimed in claim 1, wherein the insulating transistors are N-type field-effect transistors.

3. The antifuse one-time programmable memory array as claimed in claim 2, wherein the gate terminals of the isobaric transistors are configured to receive a negative voltage.

4. The antifuse one-time programmable memory array as claimed in claim 1, wherein the antifuse memory elements are two-terminal elements.

5. The antifuse one-time programmable memory array as claimed in claim 4, wherein the antifuse storage element is a capacitor.

6. An antifuse one-time programmable memory array, comprising: An active region extends laterally within a semiconductor substrate; A first read character line and a first programmable character line extend over and intersect the active region, and are separated from each other, wherein a first cell of the antifuse one-time programmable memory array is defined in a region where the active region intersects with the first read character line and the first programmable character line; A pair of first source / drain structures are disposed in the active region and within the first cell, wherein the first read word line is disposed between the pair of first source / drain structures, and the first programmable word line overlaps with one of the first source / drain structures; A second read character line and a second programmable character line extend over and intersect the active region, and are separated from each other, wherein a second cell of the antifuse one-time programmable memory array is defined in a region where the active region intersects with the second read character line and the second programmable character line; A pair of second source / drain structures are disposed in the active region and within the second cell, wherein the second read word line is disposed between the pair of second source / drain structures, and the first programmable word line overlaps with one of the second source / drain structures; and A virtual character line extends over the active region and between the first and second cell cells, wherein an insulated transistor is defined in a region where the active region intersects with the virtual character line. One of the first source / drain structures and one of the second source / drain structures are used as the source / drain terminals of the insulated transistor.

7. The antifuse one-time programmable memory array of claim 6, wherein the active region connection extends through the first cell, the second cell, and the insulating transistor between the first and second cells.

8. The antifuse one-time programmable memory array as claimed in claim 6 further includes a plurality of gate spacers, which are laterally positioned around the first read word line, the second read word line, and the virtual word line, respectively.

9. The antifuse one-time programmable memory array as described in claim 6, further comprising: Multiple gate dielectric layers separate the first read character line, the second read character line, and the virtual character line from the semiconductor substrate, respectively; as well as Multiple capacitor dielectric layers separate the first and second programmed character lines from the semiconductor substrate.

10. The antifuse one-time programmable memory array of claim 6, wherein the first and second read character lines and the virtual character line comprise a first conductive material that is different from a second conductive material forming the first and second programmable character lines.

11. The antifuse one-time programmable memory array of claim 10, wherein the first conductive material comprises polysilicon and the second conductive material comprises a metal.

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