Semiconductor device array

Abstract

The present disclosure relates to the technical field of semiconductor, and particularly relates to a semiconductor device array. The semiconductor device array comprises: a plurality of branches, each branch in the plurality of branches extending along a row direction of the semiconductor device array, each branch comprising a plurality of semiconductor devices in parallel; a plurality of source lines, the plurality of source lines extending along a first direction and connected with sources of the semiconductor devices; and a plurality of word lines, the plurality of word lines extending along a second direction and connected with gates of the semiconductor devices, wherein the second direction is different from the first direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device array. BACKGROUND

[0002] A semiconductor device array composed of multiple semiconductor devices can realize analog signal conversion and vector-matrix arithmetic calculation, and thus is widely applied in the fields of artificial intelligence, data processing, model calculation, etc. The design of different semiconductor device arrays will have a direct impact on their performance, accuracy and robustness.

[0003] The methods described in this section can not be the methods previously conceived or employed. Unless otherwise indicated, nothing in this section should be assumed to be prior art merely because of its inclusion in this section. Similarly, unless otherwise indicated, matters discussed in this section should not be assumed to be prior to their mention in this section. SUMMARY

[0004] According to an aspect of the present disclosure, a semiconductor device array is provided, comprising: a plurality of branches, each branch of the plurality of branches extending along a row direction of the semiconductor device array, the each branch comprising a plurality of semiconductor devices in parallel; a plurality of source lines extending along a first direction and connected to sources of the semiconductor devices; a plurality of word lines extending along a second direction and connected to gates of the semiconductor devices, wherein the second direction is different from the first direction.

[0005] According to one or more embodiments of the present disclosure, the accuracy and robustness of the output parameters of the semiconductor device array can be improved, while the adjustment of individual semiconductor devices is realized to adapt to the application requirements.

[0006] These and other aspects of the present disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0007] In the following description of the example embodiments in conjunction with the attached drawings, further details, features and advantages of the present disclosure are disclosed, in which:

[0008] Figure 1 is a circuit schematic diagram of a semiconductor device array according to some embodiments of the present disclosure;

[0009] Figure 2 is a circuit schematic diagram of a semiconductor device array according to some embodiments of the present disclosure;

[0010] Figure 3 is a top plan view of a semiconductor device array according to some embodiments of the present disclosure;

[0011] Figure 4 is a top plan view of an array of semiconductor devices according to some embodiments of the present disclosure;

[0012] Figures 5a to 5d is a cross-sectional schematic view of a semiconductor device according to some embodiments of the present disclosure;

[0013] Figures 6a to 6d is a cross-sectional schematic view of a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 7 is a circuit schematic of an array of semiconductor devices and an arithmetic circuit according to some embodiments of the present disclosure;

[0015] Figure 8 is a circuit schematic of an array of semiconductor devices and an arithmetic circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0017] Spatially relative terms such as "beneath", "below", "lower", "under", "above", "upper" and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The terms such as "before" or "after" and "leading to" or "following" can be similarly interpreted, for example, to indicate the order of light passing through elements, as appropriate. A device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items and the phrase "at least one of A and B" means A alone, B alone, or both A and B.

[0019] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "adjacent to" another element or layer, it can be directly on, connected, coupled or adjacent to the other element or layer, or there can be one or more intermediate elements or layers. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly coupled to" or "directly adjacent to" another element or layer, there are no intermediate elements or layers. It will also be understood that when an element is referred to as being "between" two other elements or layers, it can be directly between, or there can be one or more intermediate elements or layers. In contrast, when an element is referred to as being "directly between" two other elements or layers, there are no intermediate elements or layers.

[0020] Embodiments of the present disclosure are described herein with reference to schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] As used herein, the term "substrate" can refer to a substrate of a diced wafer, or can indicate a substrate of an undiced wafer. Similarly, the terms chip and die can be used interchangeably unless such interchange would be contradictory.

[0023] In the field of existing semiconductor devices, due to the limitation of manufacturing process, there can be deviations in the working parameters of the semiconductor devices, such as deviations in device size, e.g. gate size, surface defects of wafer substrate, deviations caused by implanting devices on wafer substrate, and the like. The parameter deviations can cause the working reference of multiple semiconductor devices in a semiconductor device array to be inconsistent with each other, thereby affecting the accuracy and robustness of the final output signal. Therefore, how to improve the performance, accuracy and robustness of the semiconductor device array has been the focus of attention.

[0024] According to an aspect of the present disclosure, a semiconductor device array is provided, comprising: a plurality of branches, each branch of the plurality of branches extending along a row direction of the semiconductor device array, each branch comprising a plurality of semiconductor devices connected in parallel; a plurality of source lines extending along a first direction and connected to sources of the semiconductor devices; a plurality of word lines extending along a second direction and connected to gates of the semiconductor devices, wherein the second direction is different from the first direction.

[0025] In the above semiconductor device array, by arranging the plurality of semiconductor devices in parallel in the plurality of branches, deviations caused by manufacturing process and the like during semiconductor manufacturing can be suppressed, and the accuracy and robustness of the output parameters of the semiconductor device array can be improved.

[0026] In addition, in the case of parallel connection of the plurality of semiconductor devices, by arranging the plurality of source lines and the plurality of word lines along different directions, adjustment of each semiconductor device in the semiconductor device array can be realized via different source lines and word lines to adapt to the application requirements (e.g. for converting between analog voltage signals and analog current signals, etc.).

[0027] Specifically, according to the present embodiment, the first direction is a column direction of the semiconductor device array, and the second direction is a row direction of the semiconductor device array. In other words, the plurality of word lines of the semiconductor device array are arranged along the row direction which is the same as the extending direction of the plurality of branches, while the plurality of source lines of the semiconductor device array are arranged along the column direction which is different from the extending direction of the plurality of branches. The arrangement will be described in detail below. Figure 1 The arrangement will be described in detail below.

[0028] Figure 1 is a circuit schematic diagram of a semiconductor device array 100 according to some embodiments of the present disclosure.

[0029] As Figure 1As shown, the semiconductor device array 100 includes a first leg 110 and a second leg 120, where the first leg 110 and the second leg 120 extend in a row direction of the semiconductor device array. The first leg 110 and the second leg 120 each include three semiconductor devices arranged in parallel, exemplarily, the first leg 110 includes a first semiconductor device 111, a second semiconductor device 112, and a third semiconductor device 113, and the second leg 120 includes a fourth semiconductor device 121, a fifth semiconductor device 122, and a sixth semiconductor device 123.

[0030] As shown, the semiconductor device array 100 further includes a first word line WLn-1 and a second word line WLn, which extend in the row direction of the semiconductor device array in the same direction as the first leg 110 and the second leg 120 to connect to the gates of the plurality of semiconductor devices in each row. Specifically, in the first leg 110, the gates of the first semiconductor device 111, the second semiconductor device 112, and the third semiconductor device 113 are connected to the same first word line WLn-1. Similarly, the gates of the fourth semiconductor device 121, the fifth semiconductor device 122, and the sixth semiconductor device 123 in the second leg 120 are connected to the same second word line WLn. Figure 1 As shown, the semiconductor device array 100 further includes a first source line SLn-1, a second source line SLn, and a third source line SLn+1, which extend in the row direction of the semiconductor device array in a direction different from the first leg 110 and the second leg 120 to connect to the sources of the plurality of semiconductor devices in each column. Specifically, the sources of the first semiconductor device 111 and the fourth semiconductor device 121 are connected to the same first source line SLn-1, the sources of the second semiconductor device 112 and the fifth semiconductor device 122 are connected to the same second source line SLn, and the sources of the third semiconductor device 113 and the sixth semiconductor device 123 are connected to the same third source line SLn+1.

[0031] Figure 1 Thus, each semiconductor device in the semiconductor device array 100 can be regulated by a certain source line and / or a certain word line. For example, when it is desired to regulate the second semiconductor device 112, a signal can be input to the source of the second semiconductor device 112 through the second source line SLn, and a signal can be input to the gate of the second semiconductor device 112 through the first word line WLn-1. Other semiconductor devices (111, 113, 121, 122, 123) in the semiconductor device array 100 are not affected because at least one of their sources and gates does not receive the input signal.

[0032] Thus, each semiconductor device in the semiconductor device array 100 can be regulated by a certain source line and / or a certain word line. For example, when it is desired to regulate the second semiconductor device 112, a signal can be input to the source of the second semiconductor device 112 through the second source line SLn, and a signal can be input to the gate of the second semiconductor device 112 through the first word line WLn-1. Other semiconductor devices (111, 113, 121, 122, 123) in the semiconductor device array 100 are not affected because at least one of their sources and gates does not receive the input signal.

[0033] ​According to some embodiments, each branch of the plurality of branches further comprises a bit line extending in a row direction of the array of semiconductor devices connected to the drain of the semiconductor devices in the branch.

[0034] In particular, as shown, the array of semiconductor devices 100 further comprises a first bit line BLm-1 and a second bit line BLm extending in the same direction as the first branch 110, the second branch 120, in a row direction of the array of semiconductor devices to be connected to the drain of the plurality of semiconductor devices in each row. In particular, in the first branch 110, the drain of the first semiconductor device 111, the second semiconductor device 112, and the third semiconductor device 113 are connected to the same first bit line BLm-1. Similarly, the drain of the fourth semiconductor device 121, the fifth semiconductor device 122, and the sixth semiconductor device 123 in the second branch 120 are connected to the same second bit line BLm. Figure 1

[0035] Thus, a signal can be input to the drain of each semiconductor device in the array of semiconductor devices via the bit line to enable regulation of each semiconductor device.

[0036] In some embodiments, the semiconductor device in the array of semiconductor devices (e.g., the array of semiconductor devices 100) can be a variety of forms of semiconductor devices. For example, according to some embodiments, the semiconductor device is a NOR flash memory. In some embodiments, the semiconductor device can be a NOR flash memory applied to Computing in Memory (CIM). In some embodiments, the semiconductor device comprises a storage portion for storing information, which can be a split gate - floating gate, 1.5T MONOS / SONOS, 2T flash, etc.

[0037] In particular, according to some embodiments, the semiconductor device further comprises a storage portion, the gate of the semiconductor device comprises a select gate, and wherein the plurality of word lines extend in a second direction connected to the select gate of the semiconductor device.

[0038] In some embodiments, the storage portion included in the semiconductor device can be a charge-trap based storage layer (e.g., a nitride storage layer), exemplarily, the material of the storage layer can be silicon nitride (SiN), or a high-K material such as HfO2, HfSiON, Ta2O5, Al2O3, TiO2, ZrO2, etc.

[0039] In some embodiments, the storage portion included in the semiconductor device can be a floating gate, exemplarily, the floating gate can be formed by deposition of a polysilicon material.

[0040] ​In the following exemplary embodiments, a semiconductor device and a semiconductor device array including a plurality of semiconductor devices are shown with a floating gate as the storage portion. It is to be understood that other storage structures, such as a charge-trap based storage layer, can also be used to replace (or at least partially replace) the floating gate as the storage portion.

[0041] As shown in FIG. 1, each semiconductor device (e.g., the first semiconductor device 111) includes a selection transistor and a floating transistor connected in series, where the drain of the selection transistor is connected to a bit line as the drain of the semiconductor device, and the source of the floating transistor is connected to a source line as the source of the semiconductor device. The selection gate of the selection transistor and the floating gate of the floating transistor serve as the gate of the semiconductor device, where the selection gate can be used to select the semiconductor device of a fixed address for operation, and the floating gate can be used to store information. Figure 1 As shown in FIG. 1, the first word line WLn-1 of the semiconductor device array 100 is connected to the selection gates of the semiconductor devices 111, 112, and 113 in the first branch 110, and the second word line WLn is connected to the selection gates of the semiconductor devices 121, 122, and 123 in the second branch 120. The semiconductor devices in the first branch 110 and the second branch 120 can be selected for operation by the first word line WLn-1 and the second word line WLn, respectively.

[0042] Figure 1 As shown in FIG. 1, the first word line WLn-1 of the semiconductor device array 100 is connected to the selection gates of the semiconductor devices 111, 112, and 113 in the first branch 110, and the second word line WLn is connected to the selection gates of the semiconductor devices 121, 122, and 123 in the second branch 120. The semiconductor devices in the first branch 110 and the second branch 120 can be selected for operation by the first word line WLn-1 and the second word line WLn, respectively.

[0043] According to some embodiments, the gate of the semiconductor device further includes a control gate, each branch of the plurality of branches further includes a control line, and wherein the control line extends along a row direction of the semiconductor device array to connect to the control gate of the semiconductor devices in the branch.

[0044] In particular, in some embodiments, the control gate is disposed above the floating gate to form a gate stack. The control gate is connected to the control line to enable regulation of the floating transistor.

[0045] As shown in FIG. 1, the first word line WLn-1 of the semiconductor device array 100 is connected to the selection gates of the semiconductor devices 111, 112, and 113 in the first branch 110, and the second word line WLn is connected to the selection gates of the semiconductor devices 121, 122, and 123 in the second branch 120. The semiconductor devices in the first branch 110 and the second branch 120 can be selected for operation by the first word line WLn-1 and the second word line WLn, respectively. Figure 1 As shown in FIG. 1, the semiconductor device array 100 further includes a first control line CGn-1 and a second control line CGn, which extend along the same direction as the first branch 110 and the second branch 120, along a row direction of the semiconductor device array to connect to the control gates of the plurality of semiconductor devices in each row. In particular, in the first branch 110, the control gates of the first semiconductor device 111, the second semiconductor device 112, and the third semiconductor device 113 are connected to the same first control line CGn-1. Similarly, the control gates of the fourth semiconductor device 121, the fifth semiconductor device 122, and the sixth semiconductor device 123 in the second branch 120 are connected to the same second control line CGn. ​

[0046] Thus, a signal can be input to the control gate of each semiconductor device in the semiconductor array via the control line to enable regulation of each semiconductor device.

[0047] In addition to the control gate and the select gate described above, the semiconductor device can further include more gates to enable different operations. For example, according to some embodiments, the gates of the semiconductor device further include an erase gate, each branch of the plurality of branches further includes an erase line, and wherein the erase line extends along the row direction of the semiconductor device array and is connected to the erase gate of the semiconductor device in the branch.

[0048] Similar to the control line, the erase line can extend along the row direction of the semiconductor device array to be connected to the control gate of the plurality of semiconductor devices in each row. For example, a first erase line is connected to the erase gates of the first semiconductor device 111, the second semiconductor device 112, and the third semiconductor device 113 in the first branch 110, a second erase line is connected to the control gates of the fourth semiconductor device 121, the fifth semiconductor device 122, and the sixth semiconductor device 123 in the second branch 120, and so on.

[0049] It can be understood that, Figure 1 The number of rows and columns of semiconductor devices in the semiconductor device array 100 shown in FIG. 1 is only illustrative, and in actual use, more or fewer rows or columns of semiconductor devices can also be included, and one or more of the source lines, the word lines, the bit lines, the control lines, and the erase lines can be arranged accordingly. For example, when the semiconductor device array includes m x n semiconductor devices arranged in m rows and n columns, m word lines (e.g., WL1, WL2, … WLm) and n source lines (e.g., SL1, SL2, … SLn) can be arranged accordingly, where m is a positive integer greater than zero, n is a positive integer greater than zero, and m and n can be the same or different. When it is desired to regulate the semiconductor device in the i-th row and the j-th column of the m x n semiconductor device array, the regulation of the semiconductor device can be achieved by operating the i-th word line WL1 to input a signal to the gate of the semiconductor device, and operating the j-th source line SLj to input a signal to the source of the semiconductor device. In addition, more or fewer bit lines, control lines, and erase lines can be arranged by the same or similar methods described above to enable regulation of a single semiconductor device.

[0050] As Figure 1As can be seen, according to the present embodiment, each of the plurality of source lines is connected to the source of one column of semiconductor devices along the column direction of the array of semiconductor devices, and the sources of the semiconductor devices in different columns are connected to different source lines. This results in the source lines of semiconductor devices that are physically adjacent in a row being disconnected. When a signal is input to the source of a semiconductor device through a source line, other cells in the same row are not affected by the source line (e.g., due to leakage of the source line).

[0051] In the process of semiconductor device fabrication, the above-mentioned source lines can be active regions formed on the substrate of the array of semiconductor devices, the active regions being connected to the sources of the plurality of semiconductor devices through the source regions of the plurality of semiconductor devices on the substrate. In some fabrication scenarios, the active regions are formed on the substrate of the array of semiconductor devices in a direction parallel to the branches. Therefore, the array of semiconductor devices needs to be processed to disconnect the active regions between different columns of semiconductor devices, and further connect the disconnected active regions along the column direction of the semiconductor devices. The specific method will be described in detail below in conjunction with the detailed description. Figure 3 Detailed description.

[0052] In some embodiments, the above-mentioned semiconductor devices are programmable semiconductor devices. In other words, the threshold voltage of the above-mentioned semiconductor devices can be adjusted by applying a bias voltage to its source, drain, and gate (e.g., control gate, select gate, and erase gate). The bias voltage can be applied by an external programming circuit.

[0053] According to some embodiments, the plurality of source lines and the plurality of word lines are connected to a programming circuit, the programming circuit being configured to: apply a first bias voltage to the source of the semiconductor device via the plurality of source lines; and apply a second bias voltage to the select gate of the semiconductor device via the plurality of word lines; wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage and the second bias voltage of the semiconductor device.

[0054] Thus, the adjustment of individual semiconductor devices in the array of semiconductor devices can be achieved. According to some embodiments, when a programming operation is performed on a certain semiconductor device, a positive voltage higher than the threshold voltage of the semiconductor device, i.e., the second bias voltage (e.g., 0.8V-1.6V), is applied on the select gate of the semiconductor device; a positive voltage, i.e., the first bias voltage (e.g., 4.5V), is applied on the source of the semiconductor device to provide a strong lateral electric field; and a negative current (e.g., -1 μA) is injected into the drain of the semiconductor device, or alternatively, in some embodiments, a third bias voltage (e.g., 0.5V) can also be applied on the drain of the semiconductor device, in which case, due to electron source injection effect, a portion of hot electrons is injected into the floating gate of the semiconductor device, while another portion of hot electrons migrates to the source of the semiconductor device.

[0055] According to some embodiments, when a certain semiconductor device in the array of semiconductor devices is not selected for writing, the first bias voltage of the semiconductor device is 0. According to yet some embodiments, when a certain semiconductor device in the array of semiconductor devices is not selected for writing, the second bias voltage of the semiconductor device is 0.

[0056] In particular, when a certain semiconductor device in the array of semiconductor devices is selected for operation (e.g., the programming operation described above), the first bias voltage and the second bias voltage of the semiconductor device are set to non-zero voltages. For semiconductor devices that are not selected for operation, the first bias voltage and / or the second bias voltage of the semiconductor devices are 0.

[0057] According to some embodiments, the plurality of branches are connected to a programming circuit, and the programming circuit is further configured to: access, via the bit line, the third bias voltage to the drain of the semiconductor devices in the branch, wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage, the second bias voltage, and the third bias voltage of the semiconductor device.

[0058] According to some embodiments, the programming circuit is further configured to: access, via the control line, the fourth bias voltage to the control gate of the semiconductor devices in the branch, wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage of the semiconductor device.

[0059] In some embodiments, when a programming operation is performed on a certain semiconductor device, a higher voltage (e.g., 11V) is applied on the control gate of the semiconductor device to couple a voltage on the floating gate to turn on the floating gate and provide a strong vertical electric field, thereby improving the programming efficiency.

[0060] Thus, each semiconductor device in the array of semiconductor devices can have a bias voltage applied to the source, gate (control gate, select gate), and drain to adjust the threshold voltage of the semiconductor device in a programmed manner (e.g., hot electron injection HCI manner).

[0061] The state of each semiconductor device can be determined by a read operation. Specifically, according to some embodiments, when a read operation is performed on a semiconductor device, a positive voltage (e.g., 1.8V) is applied to the control gate of the semiconductor device, a positive voltage (e.g., 1.8V) is applied to the select gate of the semiconductor device, a lower positive voltage (e.g., 0.6V) is applied to the drain of the semiconductor device, and the source of the semiconductor device is set to 0V. At this time, the state of the semiconductor device is determined by the magnitude of the current between the source and the drain of the semiconductor device.

[0062] For example, Table 1 shows the programming circuit configuration used by the array of semiconductor devices 100 shown in FIG. 1 when performing programming and read operations on the fifth semiconductor device 122. Figure 1

[0063] Table 1 Programming Circuit Configuration

[0064]

[0065] where Vcc is a predetermined positive voltage, e.g., 1.8V, and Vblr is a predetermined lower positive voltage, e.g., 0.6V. It should be understood that the configurations and numerical ranges given in Table 1 for programming and read operations are merely illustrative. In actual use, other types of programming circuit configurations and other numerical ranges can be used to perform programming and read operations on the semiconductor devices, depending on the manufacturing process of the semiconductor devices.

[0066] In addition to the programming and read operations described above, an erase operation can also be performed. Specifically, according to some embodiments, the programming circuit is further configured to apply a fifth bias voltage to the erase gate of the semiconductor devices in the branch via the erase line, wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage, the second bias voltage, the third bias voltage, the fourth bias voltage, and the fifth bias voltage of the semiconductor device.

[0067] The erase operation can be implemented using FN (Fowler-Nordheim) tunneling effect or BTBT (Band to Band Tunneling) effect, depending on the structure and material of the semiconductor devices.

[0068] ​In some embodiments, when performing an erase operation on a certain semiconductor device, a high positive voltage (e.g., 11V) is applied to the erase gate of the semiconductor device, while the select gate, the drain and the source of the semiconductor device are all set to 0V. At this time, due to the FN tunneling effect, the electrons in the floating gate of the semiconductor device are pulled to the erase gate under the action of the voltage difference between the erase gate and the floating gate of the semiconductor device.

[0069] In other embodiments, when performing an erase operation on a certain semiconductor device, a high negative voltage (e.g., -5V-10V) is applied to the control gate of the semiconductor device, a high positive voltage (e.g., 5V-10V) is applied to the source of the semiconductor device to form a voltage difference between the control gate and the source, while the drain of the semiconductor device is set to 0V. At this time, due to the BTBT effect, holes are injected into the floating gate of the semiconductor device.

[0070] The above describes a manner in which the plurality of word lines of the semiconductor device array are arranged along the same row direction as the plurality of branch extension directions, while the plurality of source lines of the semiconductor device array are arranged along the different column direction from the plurality of branch extension directions. In actual use, more possible arrangement manners can be used for the purpose of simplifying the manufacturing process and avoiding changing the supporting equipment. The following will combine Figure 2 The following will combine

[0071] Figure 2 is a circuit schematic diagram of a semiconductor device array 200 according to some embodiments of the present disclosure. According to the present embodiment, the first direction is the row direction of the semiconductor device array, and the second direction is the column direction of the semiconductor device array.

[0072] As shown in Figure 2 The semiconductor device array 200 includes a first branch 210 and a second branch 220, where the first branch 210 and the second branch 220 extend along the row direction of the semiconductor device array. The first branch 210 and the second branch 220 each include 3 semiconductor devices arranged in parallel. For example, the first branch 210 includes a first semiconductor device 211, a second semiconductor device 212 and a third semiconductor device 213, and the second branch 220 includes a fourth semiconductor device 221, a fifth semiconductor device 222 and a sixth semiconductor device 223.

[0073] As shown in Figure 2As shown, the semiconductor device array 200 also includes a first word line WLn-1, a second word line WLn, and a third word line WLn+1, which extend along the row direction of the semiconductor device array in a different direction from the first branch 210 and the second branch 220 to connect to the gates of the plurality of semiconductor devices in each column. Specifically, the gates of the first semiconductor device 211 and the fourth semiconductor device 221 are connected to the same first word line WLn-1, the gates of the second semiconductor device 212 and the fifth semiconductor device 222 are connected to the same second word line WLn, and the gates of the third semiconductor device 213 and the sixth semiconductor device 223 are connected to the same third word line WLn+1.

[0074] According to this embodiment, the source of a semiconductor device is connected to the source of the semiconductor device above it or the source of the semiconductor device below it in the same column via the same source line. In other words, the sources of every two rows of semiconductor devices can be connected to a single source line to share a single source line.

[0075] Specifically, such as Figure 2 As shown, the semiconductor device array 200 also includes a first source line SLn, which extends in the same direction as the first branch 210 and the second branch 220, along the row direction of the semiconductor device array to connect to the sources of multiple semiconductor devices in adjacent rows. Specifically, in the first branch 210, the sources of the first semiconductor device 211, the second semiconductor device 212, and the third semiconductor device 213 are connected to the same first source line SLn, while the sources of the fourth semiconductor device 221, the fifth semiconductor device 222, and the sixth semiconductor device 223 in the second branch 220 are also connected to the same first source line SLn.

[0076] Therefore, when operating on a semiconductor device in a semiconductor device array, by arranging the word line to extend along the column direction of the semiconductor device array, other semiconductor devices in the same row can be unaffected by the word line input signal.

[0077] and Figure 1 Similarly, each of the multiple branches also includes a bit line that extends along the row direction of the semiconductor device array and is connected to the drain of the semiconductor device in that branch.

[0078] Specifically, such as Figure 2As shown, the semiconductor device array 200 also includes a first bit line BLm-1 and a second bit line BLm, which extend in the same direction as the first branch 210 and the second branch 220, along the row direction of the semiconductor device array to connect to the drains of multiple semiconductor devices in each row. Specifically, in the first branch 210, the drains of the first semiconductor device 211, the second semiconductor device 212, and the third semiconductor device 213 are connected to the same first bit line BLm-1. Similarly, the drains of the fourth semiconductor device 221, the fifth semiconductor device 222, and the sixth semiconductor device 223 in the second branch 220 are connected to the same second bit line BLm.

[0079] In some embodiments, the semiconductor devices in the semiconductor device array 200 include a storage portion for storing information, which may be a floating gate or a charge trap-based storage layer (e.g., a memory using SONOS technology). Exemplarily, the material of the storage layer may be silicon nitride (SiN), or a high-K material such as HfO2, HfSiON, Ta2O5, Al2O3, TiO2, ZrO2, etc.

[0080] In the exemplary embodiments described below, a semiconductor device and an array of semiconductor devices comprising multiple semiconductor devices are illustrated, with a floating gate as an example of a storage portion. It will be understood that other storage structures, such as charge-trap-based storage layers, may also be used to replace (or at least partially replace) the floating gate as a storage portion.

[0081] For example, such as Figure 2 As shown, the semiconductor devices in the semiconductor device array 200 include a select transistor and a floating transistor connected in series. The drain of the select transistor is connected to a bit line, serving as the drain of the semiconductor device, and the source of the floating transistor is connected to a source line, serving as the source of the semiconductor device. The select gate of the select transistor and the floating gate of the floating transistor serve as the gate of the semiconductor device. Specifically, the first word line WLn-1 of the semiconductor device array 200 is connected to the select gate of the first column of semiconductor devices 211 and 221, the second word line WLn is connected to the select gate of the second column of semiconductor devices 212 and 222, and the third word line WLn+1 is connected to the select gate of the third column of semiconductor devices 213 and 223.

[0082] also, Figure 2The semiconductor devices in the semiconductor device array 200 shown in FIG. 2 also include control gates above the floating gates. The semiconductor device array 200 includes a first control line CGn-1 and a second control line CGn, which extend in the same direction as the first branch 210, the second branch 220, along the row direction of the semiconductor device array to connect to the control gates of the plurality of semiconductor devices in each row. Specifically, in the first branch 210, the control gates of the first semiconductor device 211, the second semiconductor device 212, and the third semiconductor device 213 are connected to the same first control line CGn-1. Similarly, the control gates of the fourth semiconductor device 221, the fifth semiconductor device 222, and the sixth semiconductor device 223 in the second branch 220 are connected to the same second control line CGn.

[0083] Similar to the semiconductor device array 100, in some embodiments, Figure 2 The gates of the semiconductor devices in the semiconductor device array 200 shown in FIG. 2 also include erase gates, and each branch of the plurality of branches also includes an erase line, and wherein the erase line extends in the row direction of the semiconductor device array to connect to the erase gates of the semiconductor devices in the branch. The erase line can extend in the row direction of the semiconductor device array to connect to the control gates of the plurality of semiconductor devices in each row. For example, a first erase line connects to the erase gates of the first semiconductor device 211, the second semiconductor device 212, and the third semiconductor device 213 in the first branch 210, a second erase line connects to the control gates of the fourth semiconductor device 221, the fifth semiconductor device 222, and the sixth semiconductor device 223 in the second branch 220, and so on.

[0084] It can be understood that, Figure 2 The number of rows and columns of semiconductor devices in the semiconductor device array 200 shown in FIG. 2 is only illustrative, and in actual use, more or fewer rows or columns of semiconductor devices can also be included, and one or more of the source lines, word lines, bit lines, control lines, and erase lines can be arranged accordingly, which will not be described here.

[0085] From Figure 2 As can be seen from FIG. 1, according to the present embodiment, each of the plurality of word lines is connected to the gates of a column of semiconductor devices in the column direction of the semiconductor device array, and the gates of the semiconductor devices in different columns are connected to different word lines. Thus, the word lines of the semiconductor devices adjacent to each other in a row are physically disconnected. When a signal is input to the gate of a certain semiconductor device (for example, the select gate in FIG. 1) through the word line, other cells in the same row will not be affected by the word line. Figure 2

[0086] ​In the process of semiconductor device fabrication, the word lines can be polysilicon gates or metal gates. In some fabrication scenarios, the polysilicon gates or metal gates are implanted on the substrate of the semiconductor device in a direction parallel to the branches. Therefore, it is necessary to process the semiconductor device array to disconnect different column gates and further connect the disconnected gates along the column direction of the semiconductor device. The specific method will be described below in conjunction with Figure 4 DETAILED DESCRIPTION.

[0087] In addition, Figure 2 The semiconductor device shown in Figure 1 may be a programmable semiconductor device described above in conjunction with Figure 1 The bias voltage can also be set for the source, gate (control gate, select gate), and drain of the semiconductor device by the method described above in conjunction with Figure 1 to perform read operations, erase operations (e.g., through FN tunneling effect or BTBT effect), etc., which will not be described here.

[0088] Exemplarily, Table 2 shows the programming circuit configuration used by the semiconductor device array 200 shown in Figure 2 when performing programming operations and read operations on the fifth semiconductor device 222.

[0089] Table 2 Programming Circuit Configuration

[0090]

[0091] wherein Vcc is a preset positive voltage, for example 1.8V, and Vblr is a preset lower positive voltage, for example 0.6V. It should be understood that the configurations and numerical intervals given in Table 2 for programming operations and read operations are only illustrative. In actual use, more other types of programming circuit configurations and other numerical intervals can be used to achieve the programming and read operations of the semiconductor device according to different semiconductor device fabrication processes.

[0092] The following will describe in detail how to make the source line or the word line extend along the column direction of the semiconductor device array in conjunction with Figure 3 and Figure 4 .

[0093] Figure 3 is a top-down plan view of a semiconductor device array 300 according to some embodiments of the present disclosure.

[0094] As Figure 3As shown, the semiconductor device array 300 includes a plurality of bit lines BLm-1, BLm, a plurality of word lines WLn-1 and WLn, a plurality of source lines SLn-1 and SL. As can be appreciated, the floating gates are disposed below the control gates CGn-1 and CGn.

[0095] wherein the semiconductor devices of each row correspond to the same word line, e.g., as shown in Figure 3 As shown, the four semiconductor devices of the upper row all correspond to the word line WLn-1. According to some embodiments, as shown in Figure 3 As shown, each word line extends through a plurality of semiconductor devices in the same row.

[0096] The source lines extending in the row direction of the semiconductor device array are broken to form a plurality of source lines in different columns. Specifically, according to some embodiments, the semiconductor device array is disposed on a substrate, wherein the substrate includes: active regions, the active regions between different columns of semiconductor devices are broken, and wherein each of the plurality of source lines is disposed to include: a plurality of active regions in the column direction of the semiconductor device array; and a metal line connecting the plurality of active regions.

[0097] In the present embodiment, the source lines in the semiconductor device array 300 are disposed as active regions (i.e., white areas) on the substrate. Figure 3 The active regions between the second column of semiconductor devices and the third column of semiconductor devices, starting from the left, shown in FIG. 2B have been broken, such that the source of the semiconductor devices of the second column are connected to the source line SLn-1, while the source of the semiconductor devices of the third column are connected to the source line SLn, with no connection between the source line SLn-1 and the source line SLn. To further ensure that the source regions of the semiconductor devices of the first column and the second column, the third column and the fourth column, starting from the left, are also connected to different source lines, the active regions in between can also be broken, such that the sources of the semiconductor devices in different columns of the semiconductor device array 300 are connected to different source lines. Thus, the source lines of the semiconductor devices that are left and right adjacent within a row are physically broken. When a signal is input to the source of a semiconductor device through a source line, other semiconductor devices within the same row will not be affected by the source line (e.g., due to interference caused by leakage of the source line).

[0098] Further, the broken active regions in the same column can be connected via a metal line to form a source line extending in the column direction of the semiconductor device array. Specifically, a corresponding tungsten plug can be disposed on the broken active regions in the same column, and the tungsten plugs are connected by a metal line to connect the broken active regions in the same column to form a source line extending in the column direction of the semiconductor device array.

[0099] Figure 4is a top plan view of a semiconductor device array 400 according to some embodiments of the present disclosure.

[0100] As shown in Figure 4 , the semiconductor device array 400 includes a plurality of bit lines BLm-1, BLm, a plurality of word lines WLn-1 and WLn, and a source line SLn. It can be understood that the floating gates are arranged below the control gates CGn-1 and CGn.

[0101] wherein the semiconductor devices in the upper and lower rows correspond to the same source line SLn. The word lines extending along the row direction of the semiconductor device array are disconnected to form a plurality of word lines in different columns. Specifically, according to some embodiments, the gates of the semiconductor devices are polysilicon gates or metal gates, the gates between the semiconductor devices in different columns are disconnected, and wherein each of the plurality of word lines includes: a plurality of gates along the column direction of the semiconductor device array, and a metal line connecting the plurality of gates.

[0102] In the present embodiment, the word lines in the semiconductor device array 400 are arranged as polysilicon gates or metal gates (i.e., diagonal line areas). Figure 4 The gates between the two columns of semiconductor devices shown inare disconnected, so that the gates (e.g., select gates) of the semiconductor devices in different columns of the semiconductor device array 400 are connected to different word lines. Thus, the word lines of the semiconductor devices adjacent to each other within a row are physically disconnected. When a signal is input to the gate of a certain semiconductor device through a word line, other semiconductor devices within the same row will not be affected by the word line.

[0103] According to some embodiments, the gates are disconnected via at least one of a photolithography and etching process.

[0104] Further, the gates in the same column, which are disconnected into multiple segments, can be connected via a metal line to form a word line extending along the column direction of the semiconductor device array. Specifically, corresponding tungsten plugs can be provided on the multiple segments of gates in the same column, and the tungsten plugs are connected by a metal line to connect the multiple segments of gates in the same column to form a word line extending along the column direction of the semiconductor device array.

[0105] The structure of a semiconductor device according to some embodiments of the present disclosure will be described in detail below. Figures 5a to 5d , Figures 6a to 6d

[0106] Figures 5a to 5d is a cross-sectional view of a semiconductor device 500 according to some embodiments of the present disclosure.

[0107] As shown in 5a, the semiconductor device 500 includes a substrate 510 and a gate structure formed on the substrate. The substrate 510 includes a drain region 511 and a source region 512, and the gate structure includes a floating gate 521, a control gate 522, and a select gate 524.

[0108] Specifically, the floating gate 521 is located above the first portion between the drain region 511 and the source region 512, and the selection gate 524 is located above the second portion between the drain region 511 and the source region 512, and on the side of the floating gate 521 opposite to the source region 512.

[0109] Semiconductor device 500 includes a first programming channel 531a and a second programming channel 531b, wherein the first programming channel 531a extends from the drain region 511 to the edge of the floating gate 521 facing the select gate 524, and the second programming channel 531 extends from the drain region 111 to the source region 112.

[0110] like Figure 5b As shown, according to some embodiments, when programming the semiconductor device 500, a positive voltage higher than the threshold voltage (e.g., 0.8-1.6V) is applied to the select gate 524, while a positive voltage (e.g., 4.5V) is applied to the source region 512 to provide a strong lateral electric field, and a negative current (e.g., -1μA) is injected into the drain region 511. Alternatively, in some embodiments, a voltage (e.g., 0.5V) may also be applied to the drain of the semiconductor device. In this case, due to the electron source injection effect, a portion of the hot electrons are injected into the floating gate 521 through the first programming channel 531a, while a portion of the hot electrons migrate to the source region 512 through the second programming channel 531b.

[0111] According to other embodiments, when programming the semiconductor device 500, programming efficiency is improved by applying a higher voltage (e.g., 8-12V) to the control gate 522, which couples a voltage onto the floating gate 521 to turn on the floating gate and provide a strong electric field in the vertical direction.

[0112] In some embodiments, the semiconductor device 500 can be applied to a semiconductor device array in which multiple word lines are arranged along a row direction that is the same as the extension direction of multiple branches, and multiple source lines are arranged along a column direction that is different from the extension direction of multiple branches (e.g., Figure 1 (Semiconductor device array 100 in the middle).

[0113] For example, when programming a semiconductor device 500 in the semiconductor device array, a positive voltage higher than the threshold voltage (e.g., 0.8-1.6V) is applied to the word line corresponding to its row, a positive voltage (e.g., 4-6V) is applied to the source line corresponding to its column, and a voltage of, for example, 0.5V is applied to the bit line of its row, so that hot electrons can pass through the first programming channel 531a and the second programming channel 531b. In addition, a higher voltage (e.g., 8-12V) can be applied to the control line corresponding to its row.

[0114] For other semiconductor devices in the same row as this semiconductor device, since these other semiconductor devices are in different columns, such as... Figure 5c As shown, the source regions of other semiconductor devices are connected to different source lines and kept at 0V (not subject to the aforementioned positive voltage) or floating, in which case no hot electrons pass through the first programming channel and the second programming channel.

[0115] In some embodiments, the semiconductor device 500 can be applied to a semiconductor device array in which multiple source lines are arranged in a row direction that is the same as the extension direction of multiple branches, and multiple word lines are arranged in a column direction that is different from the extension direction of multiple branches (e.g., Figure 2 (Semiconductor device array 200 in the middle).

[0116] Similarly, in this arrangement, the following can also be used: Figure 5b Perform programming operations as shown.

[0117] For other semiconductor devices in the same row as this semiconductor device, since these other semiconductor devices are in different columns, such as... Figure 5d As shown, the select gates of other semiconductor devices are connected to different word lines and kept at 0V (not subjected to the aforementioned positive voltage higher than the threshold voltage). At this time, the first programming channel and the second programming channel are closed, and no hot electrons pass through them.

[0118] This allows for the operation of each semiconductor device in the semiconductor device array.

[0119] Figures 6a to 6d This is a schematic cross-sectional view of a semiconductor device 600 according to some embodiments of the present disclosure.

[0120] As shown in 6a, the semiconductor device 600 includes a substrate 610 and a gate structure formed on the substrate. The substrate 610 includes a drain region 611 and a source region 612, and the gate structure includes a floating gate 621, a control gate 622, an erase gate 623, and a select gate 624.

[0121] Specifically, the floating gate 621 is located over a first portion between the drain region 611 and the source region 612, the select gate 624 is located over a second portion between the drain region 611 and the source region 612, and on an opposite side of the floating gate 621 from the source region 612, and the erase gate 623 is located over the source region 612.

[0122] As shown in FIG. 6B, the semiconductor device 600 includes a first programming path 631a extending from the drain region 611 to an edge portion of the floating gate 621 facing the select gate 624, a second programming path 631b extending from the drain region 611 to the source region 612, and an erase path 632 extending from an edge portion of the floating gate 621 facing the erase gate 623 to the erase gate 623. Figure 6a

[0123] Similarly, the semiconductor device 600 can be accessed with bias voltages or currents as shown in FIG. 6B to perform programming operations on the semiconductor device 600. Figure 5b Figure 6b In some embodiments, the semiconductor device 600 can be applied to a semiconductor device array (e.g., the semiconductor device array 100 in FIG. 1) in which a plurality of word lines are arranged along a row direction that is the same as a direction in which a plurality of branches extend, and a plurality of source lines are arranged along a column direction that is different from the direction in which the plurality of branches extend. When a programming operation is performed on a certain semiconductor device 600 in the semiconductor device array, other semiconductor devices in the same row do not have a hot electron pass through the first programming path and the second programming path because the source region is not applied with a positive voltage (as shown in FIG. 6B) due to being connected to different source lines.

[0124] In some embodiments, the semiconductor device 600 can be applied to a semiconductor device array (e.g., the semiconductor device array 200 in FIG. 2) in which a plurality of source lines are arranged along a row direction that is the same as a direction in which a plurality of branches extend, and a plurality of word lines are arranged along a column direction that is different from the direction in which the plurality of branches extend. When a programming operation is performed on a certain semiconductor device 600 in the semiconductor device array, other semiconductor devices in the same row do not have a hot electron pass through the first programming path and the second programming path because the select gate is not applied with a positive voltage higher than a threshold voltage (as shown in FIG. 6B) due to being connected to different word lines. Figure 1 Figure 6c In some embodiments, the semiconductor device 600 can be applied to a semiconductor device array (e.g., the semiconductor device array 200 in FIG. 2) in which a plurality of source lines are arranged along a row direction that is the same as a direction in which a plurality of branches extend, and a plurality of word lines are arranged along a column direction that is different from the direction in which the plurality of branches extend. When a programming operation is performed on a certain semiconductor device 600 in the semiconductor device array, other semiconductor devices in the same row do not have a hot electron pass through the first programming path and the second programming path because the select gate is not applied with a positive voltage higher than a threshold voltage (as shown in FIG. 6B) due to being connected to different word lines.

[0125] In some embodiments, the semiconductor device 600 can be applied to a semiconductor device array (e.g., the semiconductor device array 200 in FIG. 2) in which a plurality of source lines are arranged along a row direction that is the same as a direction in which a plurality of branches extend, and a plurality of word lines are arranged along a column direction that is different from the direction in which the plurality of branches extend. When a programming operation is performed on a certain semiconductor device 600 in the semiconductor device array, other semiconductor devices in the same row do not have a hot electron pass through the first programming path and the second programming path because the select gate is not applied with a positive voltage higher than a threshold voltage (as shown in FIG. 6B) due to being connected to different word lines. Figure 2 Figure 6d In some embodiments, the semiconductor device 600 can be applied to a semiconductor device array (e.g., the semiconductor device array 200 in FIG. 2) in which a plurality of source lines are arranged along a row direction that is the same as a direction in which a plurality of branches extend, and a plurality of word lines are arranged along a column direction that is different from the direction in which the plurality of branches extend. When a programming operation is performed on a certain semiconductor device 600 in the semiconductor device array, other semiconductor devices in the same row do not have a hot electron pass through the first programming path and the second programming path because the select gate is not applied with a positive voltage higher than a threshold voltage (as shown in FIG. 6B) due to being connected to different word lines.

[0126] ​​​​Furthermore, in some embodiments, when an erase operation is performed on the semiconductor device 600, a high positive voltage (e.g., 11V) is applied on the erase gate 623, while the select gate 624, the drain region 611 and the source region 612 are all set to 0V, at this time, due to the FN tunneling effect, the electrons in the floating gate 621 are pulled to the erase gate 623 under the action of the voltage difference between the erase gate 623 and the floating gate 621.

[0127] As mentioned before, the semiconductor device array provided by the present disclosure can be used to implement the conversion between analog voltage signals and analog current signals, and to perform vector-matrix arithmetic calculations, etc. Exemplarily, the following will be described in combination with Figure 7 and Figure 8 The detailed description of the semiconductor device array as a conversion circuit, and the connection with other operation circuits.

[0128] Specifically, according to some embodiments, each branch in the plurality of branches further comprises: an analog current input end connected to the gate and the drain of each semiconductor device in the branch for inputting an analog current signal; and an analog voltage output end connected to the gate and the drain of each semiconductor device in the branch for outputting an analog voltage signal, the analog voltage signal being determined based on at least the analog current signal and the threshold voltage of each semiconductor device in the branch.

[0129] Wherein, the programming operation on the semiconductor device array can be performed by the above-mentioned programming circuit to adjust the threshold voltage of each semiconductor in the semiconductor device array. The semiconductor device with a specific threshold voltage can be regarded as having an equivalent analog weight W.

[0130] Figure 7 The circuit schematic diagram of the semiconductor device array and the operation circuit according to some embodiments of the present disclosure.

[0131] In some embodiments, Figure 7 The left semiconductor device array 710 in FIG. 7 can be equivalent to Figure 1 The equivalent representation of the plurality of parallel semiconductor devices in a branch in the semiconductor device array 100 shown in FIG. 6, wherein the gate and the drain of the plurality of parallel semiconductor devices are connected to the input end Iin of the analog current to generate a corresponding analog voltage signal, and output the analog voltage signal to the right operation circuit 720.

[0132] In the present embodiment, the plurality of semiconductor devices of the right operation circuit 720 can be programmed via the above-mentioned similar method. For example, by accessing a bias voltage at the source, gate and drain of the semiconductor device, to adjust the threshold voltage and the corresponding equivalent weight W of the plurality of semiconductor devices in the operation circuit.

[0133] As shown in Figure 7 , the outputted analog voltage signal is applied to the gates of the plurality of semiconductor devices of the operation circuit 720. Based on the equivalent analog weight W and the gate voltage applied to the gate, the output current Iout1 and Iout2 of the drain output of the plurality of semiconductor devices of the operation circuit can be obtained, which can be obtained via the following formula:

[0134] Output current = Gate voltage x Equivalent analog weight W

[0135] For example, the output current Iout1 is equal to the gate voltage multiplied by the equivalent weight W1 of the semiconductor device on the left side of the operation circuit 720, while the output current Iout2 is equal to the gate voltage multiplied by the equivalent weight W2 of the semiconductor device on the right side of the operation circuit 720.

[0136] Figure 8 is a circuit schematic diagram of a semiconductor device array and an operation circuit according to some embodiments of the present disclosure.

[0137] In some embodiments, Figure 8 The semiconductor device array 810 on the left side in Figure 2 may correspond to the equivalent representation of a plurality of parallel semiconductor devices of one branch in the semiconductor device array 200 shown in , wherein the gates and drains of the plurality of parallel semiconductor devices are connected to the input end Iin of the analog current to generate a corresponding analog voltage signal and output the analog voltage signal to the operation circuit 820 on the right side.

[0138] The outputted analog voltage signal is applied to the gates of the plurality of semiconductor devices of the operation circuit 820, and similar calculations described above in connection with Figure 7 may be performed, which will not be described herein again.

[0139] In addition, the operation circuit described above in connection with Figure 7 and Figure 8 may be a matrix multiplication operation circuit. Specifically, according to some embodiments, the semiconductor device array is connected to a matrix multiplication operation circuit, which is configured to perform a matrix multiplication operation based on the analog voltage signal outputted by the analog voltage output end.

[0140] Specifically, when, for example, Figure 7 or Figure 8 the circuit schematic diagram shown in, the semiconductor device array on the left side includes a plurality of branches (for example, Figure 1 and Figure 2When the semiconductor device array includes two branches (as shown in FIG. 2), the semiconductor device array can accordingly convert multiple analog current input signals to multiple analog voltage output signals. The operation circuit can accordingly include multiple rows of semiconductor devices to receive the multiple analog voltage output signals and compute output currents based on the multiple analog voltage output signals. Illustratively, when the semiconductor device array includes n branches, the semiconductor device array can receive n analog current input signals (e.g., Iin1, Iin2,... Iin n) and convert them to n analog voltage output signals (e.g., V1, V2,... Vn). The operation circuit can be arranged with n x m semiconductor devices, where n and m are positive integers greater than zero, and the equivalent analog weight of the semiconductor device in the i-th row and j-th column can be denoted by Wij, according to the required output current dimension m (e.g., required output currents Iout1, Iout2,... Iout m). Thus, each column output current is the summation of the currents generated by multiplying the equivalent weight of all n semiconductor devices in the column by the n analog voltage output signals, thereby implementing a matrix multiplication operation.

[0141] Some example aspects of the present disclosure are described below.

[0142] Aspect 1. A semiconductor device array, comprising:

[0143] a plurality of branches, each branch of the plurality of branches extending along a row direction of the semiconductor device array, the each branch including a plurality of semiconductor devices in parallel;

[0144] a plurality of source lines extending along a first direction to connect to sources of the semiconductor devices;

[0145] a plurality of word lines extending along a second direction to connect to gates of the semiconductor devices, wherein the second direction is different from the first direction.

[0146] Aspect 2. The semiconductor device array of Aspect 1, wherein the first direction is a column direction of the semiconductor device array, and the second direction is a row direction of the semiconductor device array.

[0147] Aspect 3. The semiconductor device array of Aspect 2, wherein each source line of the plurality of source lines connects to sources of a column of semiconductor devices along the column direction of the semiconductor device array, and sources of semiconductor devices in different columns are connected to different source lines.

[0148] Aspect 4. The semiconductor device array of Aspect 3, arranged on a substrate, wherein the substrate includes: active regions, the active regions between different columns of semiconductor devices are partitioned,

[0149] and wherein each source line of the plurality of source lines is arranged to include:

[0150] a plurality of active regions along a column direction of the array of semiconductor devices; and

[0151] a metal line connecting the plurality of active regions.

[0152] Aspect 5. The array of semiconductor devices of Aspect 1, wherein the first direction is a row direction of the array of semiconductor devices, and the second direction is a column direction of the array of semiconductor devices.

[0153] Aspect 6. The array of semiconductor devices of Aspect 5, wherein each word line of the plurality of word lines is connected to gates of a column of semiconductor devices along a column direction of the array of semiconductor devices, and gates of semiconductor devices in different columns are connected to different word lines.

[0154] Aspect 7. The array of semiconductor devices of Aspect 6, wherein a source of the semiconductor device is connected to a same source line as a source of an above neighboring semiconductor device or a source of a below neighboring semiconductor device of the semiconductor device in a same column.

[0155] Aspect 8. The array of semiconductor devices of Aspect 6 or 7, wherein the gates of the semiconductor devices are poly-si gates or metal gates, and the gates between different column semiconductor devices are isolated,

[0156] and wherein each word line of the plurality of word lines includes:

[0157] a plurality of gates along a column direction of the array of semiconductor devices, and

[0158] a metal line connecting the plurality of gates.

[0159] Aspect 9. The array of semiconductor devices of Aspect 8, wherein the gates between different column semiconductor devices are isolated via at least one of a photolithography and etching process.

[0160] Aspect 10. The array of semiconductor devices of any one of Aspects 1-9, wherein each branch of the plurality of branches further includes a bit line extending along a row direction of the array of semiconductor devices connected to a drain of the semiconductor device in the branch.

[0161] Aspect 11. The array of semiconductor devices of Aspect 10, wherein the semiconductor device further includes a storage portion, the gate of the semiconductor device includes a select gate, and wherein the plurality of word lines extend along a second direction connected to the select gate of the semiconductor device.

[0162] Aspect 12. The array of semiconductor devices of aspect 11, wherein the gates of the semiconductor devices further comprise control gates, each branch of the plurality of branches further comprises a control line, and wherein,

[0163] the control line extends along a row direction of the array of semiconductor devices in connection with the control gates of the semiconductor devices in that branch.

[0164] Aspect 13. The array of semiconductor devices of aspect 11 or 12, wherein the gates of the semiconductor devices further comprise erase gates, each branch of the plurality of branches further comprises an erase line, and wherein,

[0165] the erase line extends along a row direction of the array of semiconductor devices in connection with the erase gates of the semiconductor devices in that branch.

[0166] Aspect 14. The array of semiconductor devices of aspect 13, wherein the plurality of source lines and the plurality of word lines are in connection with programming circuitry configured for:

[0167] accessing a first bias voltage to the source of the semiconductor devices via the plurality of source lines; and

[0168] accessing a second bias voltage to the select gate of the semiconductor devices via the plurality of word lines;

[0169] wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage and the second bias voltage of that semiconductor device.

[0170] Aspect 15. The array of semiconductor devices of aspect 14, wherein the first bias voltage of a certain one of the semiconductor devices is 0 when not selected for writing to.

[0171] Aspect 16. The array of semiconductor devices of aspect 14, wherein the second bias voltage of a certain one of the semiconductor devices is 0 when not selected for writing to.

[0172] Aspect 17. The array of semiconductor devices of any one of aspects 14 to 16, wherein the plurality of branches are in connection with the programming circuitry, the programming circuitry is further configured for:

[0173] accessing a third bias voltage to the drain of the semiconductor devices in that branch via the bit line,

[0174] wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage, the second bias voltage, and the third bias voltage of the semiconductor device.

[0175] Aspect 18. The array of semiconductor devices of any one of aspects 14-17, wherein the programming circuitry is further configured for:

[0176] accessing, via the control line, a fourth bias voltage to the control gate of the semiconductor device in the branch,

[0177] wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage of the semiconductor device.

[0178] Aspect 19. The array of semiconductor devices of any one of aspects 14-18, wherein the programming circuitry is further configured for:

[0179] accessing, via the erase line, a fifth bias voltage to the erase gate of the semiconductor device in the branch,

[0180] wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage, the second bias voltage, the third bias voltage, the fourth bias voltage, and the fifth bias voltage of the semiconductor device.

[0181] Aspect 20. The array of semiconductor devices of any one of aspects 1-19, wherein each of the plurality of branches further comprises:

[0182] an analog current input terminal connected to the gate and the drain of each of the semiconductor devices in the branch for inputting an analog current signal; and

[0183] an analog voltage output terminal connected to the gate and the drain of each of the semiconductor devices in the branch for outputting an analog voltage signal, the analog voltage signal determined based on at least the analog current signal and the threshold voltage of each of the semiconductor devices in the branch.

[0184] Aspect 21. The array of semiconductor devices of aspect 20, wherein the array of semiconductor devices is connected to a matrix multiplication circuitry, the matrix multiplication circuitry configured to:

[0185] perform a matrix multiplication operation based on the analog voltage signal outputted by the analog voltage output terminal.

[0186] Aspect 22. The array of semiconductor devices of any one of aspects 1 to 21, wherein the semiconductor devices are NOR flash memory.

[0187] While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered illustrative or exemplary and not restrictive; the disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps not listed in the claims, the word "a" or "an" does not exclude a plurality, and the term "multiple" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. An array of semiconductor devices, comprising: a plurality of legs, each leg of the plurality of legs extending in a row direction of the array of semiconductor devices, the each leg comprising a plurality of drain co-located semiconductor devices; a plurality of source lines extending in a first direction in connection with sources of the semiconductor devices; a plurality of word lines extending in a second direction in connection with select gates of the semiconductor devices, wherein the second direction is different from the first direction, wherein the source lines and the word lines are used to select one semiconductor device in the array of semiconductor devices; wherein each leg of the plurality of legs further comprises: an analog current input in connection with a control gate and a drain of each semiconductor device in the leg for inputting an analog current signal; and an analog voltage output in connection with the control gate and the drain of each semiconductor device in the leg for outputting an analog voltage signal determined based on at least the analog current signal and a threshold voltage of a selected semiconductor device in the leg; wherein the array of semiconductor devices is used in connection with a matrix multiplication circuit configured to: perform a matrix multiplication operation based on the analog voltage signal output by the analog voltage output.

2. The array of semiconductor devices of claim 1, wherein, the first direction is a column direction of the array of semiconductor devices, and the second direction is a row direction of the array of semiconductor devices.

3. The array of semiconductor devices of claim 2, wherein, each source line of the plurality of source lines is in connection with sources of a column of semiconductor devices in the column direction of the array of semiconductor devices, and sources of semiconductor devices in different columns are connected to different source lines.

4. The array of semiconductor devices of claim 3, arranged on a substrate, wherein, the substrate comprises: active regions, the active regions between different column semiconductor devices are partitioned, and wherein each source line of the plurality of source lines is arranged to comprise: a plurality of active regions in the column direction of the array of semiconductor devices; and a metal line connecting the plurality of active regions.

5. The array of semiconductor devices of claim 1, wherein, the first direction is a row direction of the array of semiconductor devices, and the second direction is a column direction of the array of semiconductor devices.

6. The array of semiconductor devices of claim 5, wherein, each word line of the plurality of word lines is in connection with select gates of a column of semiconductor devices in the column direction of the array of semiconductor devices, and select gates of semiconductor devices in different columns are connected to different word lines.

7. The array of semiconductor devices of claim 6, wherein, the source of the semiconductor device is connected to the source of an upper neighboring semiconductor device or a lower neighboring semiconductor device of the semiconductor device in the same column.

8. The array of semiconductor devices of claim 6, wherein, the select gate of the semiconductor device is a poly gate or a metal gate, the select gates between different column semiconductor devices are partitioned, and wherein each word line of the plurality of word lines comprises: a plurality of select gates in the column direction of the array of semiconductor devices, and a metal line connecting the plurality of select gates.

9. The array of semiconductor devices of claim 8, wherein, the select gates between different column semiconductor devices are partitioned via at least one of a photolithography and an etching process.

10. The array of semiconductor devices of any one of claims 1 to 9, wherein, each leg of the plurality of legs further comprises a bit line extending in the row direction of the array of semiconductor devices in connection with the drains of the semiconductor devices in the leg.

11. The array of semiconductor devices of claim 10, wherein, The semiconductor device further comprises a storage portion, and wherein the plurality of word lines extend in a second direction in connection with the select gates of the semiconductor device.

12. The array of semiconductor devices of claim 11, wherein, Each branch of the plurality of branches further comprises a control line, and wherein, The control line extends in a row direction of the array of semiconductor devices in connection with the control gates of the semiconductor devices of the branch.

13. The array of semiconductor devices of claim 12, wherein, The semiconductor device further comprises an erase gate, each branch of the plurality of branches further comprises an erase line, and wherein, The erase line extends in a row direction of the array of semiconductor devices in connection with the erase gates of the semiconductor devices of the branch.

14. The array of semiconductor devices of claim 13, wherein, The plurality of source lines and the plurality of word lines are in connection with a programming circuit, the programming circuit being configured for: accessing, via the plurality of source lines, a first bias voltage for the source of the semiconductor device; and accessing, via the plurality of word lines, a second bias voltage for the select gate of the semiconductor device; wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage and the second bias voltage of the semiconductor device.

15. The array of semiconductor devices of claim 14, wherein, The first bias voltage of a certain one of the semiconductor devices is 0 when write to that semiconductor device is not selected.

16. The array of semiconductor devices of claim 14, wherein, The second bias voltage of a certain one of the semiconductor devices is 0 when write to that semiconductor device is not selected.

17. The array of semiconductor devices of any one of claims 14 to 16, wherein, The plurality of branches are in connection with the programming circuit, the programming circuit being further configured for: accessing, via the bit line, a third bias voltage for the drain of the semiconductor device of the branch, wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage, the second bias voltage and the third bias voltage of the semiconductor device.

18. The array of semiconductor devices of claim 17, wherein, The programming circuit is further configured for: accessing, via the control line, a fourth bias voltage for the control gate of the semiconductor device of the branch, wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage, the second bias voltage, the third bias voltage and the fourth bias voltage of the semiconductor device.

19. The array of semiconductor devices of claim 18, wherein, The programming circuit is further configured for: accessing, via the erase line, a fifth bias voltage for the erase gate of the semiconductor device of the branch, wherein the threshold voltage of each of the semiconductor devices is determined based on at least one of the first bias voltage, the second bias voltage, the third bias voltage, the fourth bias voltage and the fifth bias voltage of the semiconductor device.

20. The array of semiconductor devices of any one of claims 1 to 9, wherein, The semiconductor device is a NOR flash memory.

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