Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a method of manufacturing the same are provided. The semiconductor memory device includes: a channel layer having a first portion and a second portion, the first portion and the second portion extending in a longitudinal direction; a gate stack structure surrounding the first portion of the channel layer; a first semiconductor layer of a first conductivity type in contact with the second portion of the channel layer; and a second semiconductor layer of a second conductivity type.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the three-dimensional semiconductor memory device. Background Art

[0002] A semiconductor memory device may include memory cells capable of storing data. A three-dimensional semiconductor memory device may include a three-dimensional memory cell array.

[0003] Various operations of the memory cells may be controlled by a peripheral circuit structure. A three-dimensional semiconductor memory device may include a peripheral circuit structure overlapping the three-dimensional memory cell array. In the three-dimensional semiconductor memory device as described above, due to structural constraints and manufacturing process constraints, an erase operation for erasing data stored in the memory cells may be limited to a gate-induced drain leakage (GIDL) method using a gate-induced drain leakage (GIDL) current. The erase operation according to the GIDL method may be performed based on minority carriers, and thus the reliability of the erase operation may deteriorate. Summary of the Invention

[0004] According to an embodiment, a semiconductor memory device may include: a channel layer having a first portion and a second portion extending in a longitudinal direction; a gate stack structure surrounding the first portion of the channel layer; a first semiconductor layer including a first impurity of a first conductivity type, the first semiconductor layer contacting sidewalls of the second portion of the channel layer; and a second semiconductor layer covering the first semiconductor layer and the channel layer, wherein the second semiconductor layer includes a source region doped with a second impurity of a second conductivity type opposite to the first conductivity type.

[0005] According to an embodiment, a semiconductor memory device may include: a three-dimensional memory cell array; a first semiconductor layer overlapping the three-dimensional memory cell array, the first semiconductor layer including a first impurity of a first conductivity type; and a second semiconductor layer disposed above the first semiconductor layer, the second semiconductor layer including a source region doped with a second impurity of a second conductivity type opposite to the first conductivity type, wherein the three-dimensional memory cell array includes a plurality of channel layers, each channel layer having a first contact surface contacting the first semiconductor layer and a second contact surface contacting the second semiconductor layer.

[0006] According to an embodiment, a method of manufacturing a semiconductor memory device may include the steps of: forming a plurality of channel layers, each channel layer including a first portion and a second portion, the first portion being surrounded by a gate stack structure and a memory layer being interposed between the first portion and the gate stack structure, the second portion extending from the first portion and being exposed to an area outside the gate stack structure; forming a first semiconductor layer contacting a part of the second portion of each channel layer, the first semiconductor layer including a first impurity of a first conductivity type; and forming a second semiconductor layer contacting a part of the second portion of each channel layer that is open through the first semiconductor layer, the second semiconductor layer including a second impurity of a second conductivity type opposite to the first conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor memory device according to an embodiment;

[0008] Figure 2 shows Figure 1 an embodiment of the arrangement of the memory cell array and the peripheral circuit structure shown;

[0009] Figure 3 shows Figure 2 a perspective view of an embodiment of the memory cell array shown;

[0010] Figure 4 shows Figure 3 a plan view of an embodiment of the second semiconductor layer shown;

[0011] Figure 5 is a cross-sectional view showing a first region and a second region of a semiconductor memory device taken along an X-Z plane according to an embodiment;

[0012] Figure 6 is a cross-sectional view showing a second region of a semiconductor memory device taken along a Y-Z plane according to an embodiment;

[0013] Figure 7 is a cross-sectional view showing a second region of a semiconductor memory device taken along a Y-Z plane according to an embodiment;

[0014] Figure 8 is an enlarged cross-sectional view showing a part of a semiconductor memory device according to an embodiment;

[0015] Figures 9A to 9C is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment;

[0016] Figures 10A to 10G shows Figure 9CCross-sectional view of an embodiment of a process subsequent to the process shown;

[0017] Figure 11 is a block diagram showing the configuration of a memory system according to an embodiment; and

[0018] Figure 12 is a block diagram showing the configuration of a computing system according to an embodiment. Detailed Description

[0019] To describe embodiments in accordance with concepts of the present disclosure, the specific structures and functional descriptions disclosed herein are merely illustrative. Embodiments in accordance with concepts of the present disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0020] It will be understood that although terms such as "first," "second," etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another, rather than to imply the number or order of the elements.

[0021] Various embodiments relate to a semiconductor memory device capable of improving operational reliability and a method of manufacturing the semiconductor memory device.

[0022] Figure 1 is a block diagram of a semiconductor memory device 100 according to an embodiment.

[0023] Referring to Figure 1 , the semiconductor memory device 100 may include a peripheral circuit structure 190 and a memory cell array 110.

[0024] The peripheral circuit structure 190 may be configured to perform a programming operation and a verification operation for storing data in the memory cell array 110, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. The peripheral circuit structure 190 may include an input / output circuit 180, a control circuit 150, a voltage generation circuit 130, a row decoder 120, a column decoder 170, a page buffer 160, and a source line driver 140.

[0025] The memory cell array 110 may include a plurality of memory cells storing data. According to an embodiment, the memory cell array 110 may include a three-dimensional memory cell array. The plurality of memory cells may store single-bit data or multi-bit data per cell. The plurality of memory cells may form a memory cell string. Each memory cell string may include memory cells connected in series with each other through a channel layer. The channel layer may be connected to the page buffer 160 through a bit line BL. The channel layer may include a portion connected to the first semiconductor layer of the memory cell array 110 and a portion connected to the source region of the memory cell array 110. The first semiconductor layer may be provided as a well region doped with a first impurity of a first conductivity type. The source region may be a region in the second semiconductor layer doped with a second impurity of a second conductivity type opposite to the first conductivity type. The first conductivity type may be p-type, and the second conductivity type may be n-type.

[0026] The input / output circuit 180 may transfer a command CMD and an address ADD received from an external device (e.g., a storage controller) of the semiconductor memory device 100 to the control circuit 150. The input / output circuit 180 may exchange data DATA with the external device and the column decoder 170.

[0027] The control circuit 150 may output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to the command CMD and the address ADD.

[0028] The voltage generation circuit 130 may generate various operation voltages Vop for performing a programming operation, a verification operation, a read operation, and an erase operation in response to the operation signal OP_S. The voltage generation circuit 130 may transfer an erase voltage Vers to the memory cell array 110 in response to the operation signal OP_S during the erase operation. During the erase operation, the erase voltage Vers may be transferred to the first semiconductor layer of the memory cell array 110. The first semiconductor layer may supply holes as majority carriers to the channel layer during the erase operation.

[0029] The row decoder 120 may be connected to the memory cell array 110 through a drain select line DSL, a word line WL, and a source select line SSL. The row decoder 120 may transfer the operation voltage Vop to the drain select line DSL, the word line WL, and the source select line SSL in response to the row address RADD.

[0030] The column decoder 170 may transfer the data DATA input from the input / output circuit 180 to the page buffer 160 or transfer the data DATA stored in the page buffer 160 to the input / output circuit 180 in response to the column address CADD. The column decoder 170 may exchange the data DATA with the input / output circuit 180 through the column lines CLL. The column decoder 170 may exchange the data DATA with the page buffer 160 through the data lines DTL.

[0031] The page buffer 160 may be connected to the memory cell array 110 through the bit lines BL. The page buffer 160 may temporarily store the data DATA received through the bit lines BL in response to the page buffer control signal PB_S. The page buffer 160 may sense the voltage or current of the bit lines BL during a read operation.

[0032] The source line driver 140 may transfer the source voltage Vsl to the memory cell array 110 in response to the source line control signal SL_S. According to an embodiment, the source line driver 140 may supply the source voltage Vsl for discharging to the source region of the memory cell array 110 during a read operation or a verify operation. According to an embodiment, the source voltage Vsl for discharging may be a ground voltage.

[0033] Figure 2 is a diagram showing Figure 1 an embodiment of the layout of the memory cell array 110 and the peripheral circuit structure 190 shown.

[0034] Referring to Figure 2 , the peripheral circuit structure 190 of the semiconductor memory device 100 may include a region overlapping with the memory cell array 110. The Z-axis direction in the XYZ coordinate system may be defined as the direction in which the peripheral circuit structure 190 faces the memory cell array 110. The peripheral circuit structure 190 may be connected to the first semiconductor layer, the second semiconductor layer, the bit lines, the drain selection lines, the word lines, and the source selection lines of the memory cell array 110 through a plurality of interconnects.

[0035] Figure 3 is a perspective view showing Figure 2 an embodiment of the memory cell array 110 shown.

[0036] Referring to Figure 3 , the memory cell array 110 may include memory cell strings defined along the cell plugs CPL, bit lines BL, a first semiconductor layer SEL1, and a second semiconductor layer SEL2.

[0037] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 may overlap with the bit lines BL, and the cell plugs CPL are inserted therebetween.

[0038] The cell plug CPL can be surrounded by conductive patterns which are stacked and spaced apart from each other in the Z-axis direction between the height at which the bit line BL is provided and the height at which the first semiconductor layer SEL1 is provided. As described above, a three-dimensional memory cell array can be defined by the cell plug CPL. The conductive patterns can be penetrated by the slit SI. At least one layer of the conductive patterns adjacent to the bit line BL among the conductive patterns can be penetrated by the drain separation slit DSI and the slit SI. The conductive patterns can be separated by the slit SI and the drain separation slit DSI into the drain select line DSL, the word line WL, and the source select line SSL. The drain select lines DSL provided at the same height between adjacent slits SI can be separated from each other by the drain separation slit DSI. The drain select line DSL can be used as the gate electrode of the drain select transistor. The word line WL can be used as the gate electrode of the memory cell. The source select line SSL can be used as the gate electrode of the source select transistor.

[0039] Each cell plug CPL can pass through at least one layer of the drain select line DSL, a plurality of word lines WL, and at least one layer of the source select line SSL. The plurality of word lines WL can be provided to be spaced apart from each other in the Z-axis direction between the bit line BL and the first semiconductor layer SEL1. At least one layer of the drain select line DSL can be provided between the plurality of word lines WL and the bit line BL. At least one layer of the source select line SSL can be provided between the plurality of word lines WL and the first semiconductor layer SEL1.

[0040] The bit line BL can extend in a direction intersecting with the word line WL. According to an embodiment, the word line WL can extend in the X-axis direction in the XYZ coordinate system, and the bit line BL can extend in the Y-axis direction in the XYZ coordinate system.

[0041] The first semiconductor layer SEL1 can be provided as a well region of the memory cell array 110 and can extend along the X-Y plane in the XYZ coordinate system. The second semiconductor layer SEL2 of the memory cell array 110 can include a source region and can extend along the X-Y plane in the XYZ coordinate system. The second semiconductor layer SEL2 can contact the upper surface of the first semiconductor layer SEL1.

[0042] Each of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 can extend from the first region AR1 of the semiconductor memory device to the second region AR2 of the semiconductor memory device. The drain select line DSL, the word line WL, and the source select line SSL can be penetrated by the cell plug CPL in the second region AR2. The first region AR1 of the semiconductor memory device can be an open region through the drain select line DSL, the word line WL, and the source select line SSL.

[0043] The first semiconductor layer SEL1 can include a first impurity of a first conductivity type. According to an embodiment, the first semiconductor layer SEL1 can be a doped silicon layer having p-type impurities.

[0044] The second semiconductor layer SEL2 may include a region doped with impurities of a first conductivity type and a region doped with impurities of a second conductivity type opposite to the first conductivity type. According to an embodiment, the second semiconductor layer SEL2 may include a well pick-up region doped with p-type impurities, a source region, and a source pick-up region doped with n-type impurities.

[0045] Figure 4 is a diagram showing Figure 3 a plan view of an embodiment of the second semiconductor layer SEL2 shown.

[0046] Referring to Figure 4 , the second semiconductor layer SEL2 may include a central region CER and an edge EG surrounding the central region CER. The edge EG may correspond to Figure 3 the first region AR1 shown, and the central region CER may correspond to Figure 3 the second region AR2 shown. The central region CER may overlap with Figure 3 the cell plug CPL forming the three-dimensional memory cell array shown.

[0047] The second semiconductor layer SEL2 may include a source region 215, a well pick-up region 213, and a source pick-up region 217. The source region 215 may be doped with a second impurity of a second conductivity type and may be defined in the central region CER. The well pick-up region 213 may be doped with a third impurity of a first conductivity type and may be defined in the edge EG. The concentration of the third impurity may be higher than Figure 3 the concentration of the first impurity of the first semiconductor layer SEL1 shown. The source pick-up region 217 may be defined in the source region 215. The source pick-up region 217 may be doped with a fourth impurity of a second conductivity type. The concentration of the fourth impurity may be higher than the concentration of the second impurity. The first conductivity type may be p-type, and the second conductivity type may be n-type.

[0048] The second semiconductor layer SEL2 may further include an additional region 211 surrounding the well pick-up region 213 in the edge EG. The additional region 211 may include a second impurity of a second conductivity type.

[0049] Similar to the second semiconductor layer SEL2, Figure 3 the first semiconductor layer SEL1 shown may include a central region and an edge surrounding the central region. The central region of the first semiconductor layer SEL1 may overlap with Figure 3 the cell plug CPL shown, and may correspond to Figure 3 the second region AR2 shown. The edge of the first semiconductor layer SEL1 may correspond to Figure 3 the first region AR1 shown.

[0050] Figure 5is a cross-sectional view showing a first region AR1 and a second region AR2 of a semiconductor memory device taken along the X-Z plane according to an embodiment. Figure 6 is a cross-sectional view showing a second region AR2 of a semiconductor memory device taken along the Y-Z plane according to an embodiment. Figure 7 is a cross-sectional view showing a second region AR2 of a semiconductor memory device taken along the Y-Z plane according to an embodiment. Figure 7 Shows Figure 6 a modification of the illustrated embodiment.

[0051] Referring to Figure 5 、 Figure 6 and Figure 7 ,the peripheral circuit structure of the semiconductor memory device may include a substrate 301 and transistors TR1, TR2, and TR3.

[0052] The substrate 301 may be a semiconductor substrate such as a silicon substrate or a germanium substrate. The substrate 301 may include active regions separated by an isolation layer 303.

[0053] The transistors TR1, TR2, and TR3 may form Figure 1 a part of the illustrated peripheral circuit structure 190. According to an embodiment, the transistors TR1, TR2, and TR3 may include a transistor TR1 forming Figure 1 the illustrated row decoder 120 and transistors TR2 and TR3 forming Figure 1 the illustrated page buffer 160.

[0054] Each of the transistors TR1, TR2, and TR3 may include a gate insulating layer 305, a gate electrode 307, and a junction 301J. The gate insulating layer 305 and the gate electrode 307 may be stacked over the substrate 301 in the active region. The junction 301J may be provided as a source region and a drain region. The junction 301J may be provided by doping at least one of an n-type impurity and a p-type impurity into the active region exposed on both sides of the gate electrode 307.

[0055] The semiconductor memory device may include a first interconnect 330 and a first conductive bonding pattern 331 connected to the peripheral circuit structure.

[0056] The first interconnect 330 may include a plurality of conductive patterns 311, 313, 315, 317, 319, 321, 323, and 325 connected to the transistors TR1, TR2, and TR3. The plurality of conductive patterns 311, 313, 315, 317, 319, 321, 323, and 325 may have various structures.

[0057] The first conductive bonding pattern 331 may be connected to the first interconnect 330. The first conductive bonding pattern 331 may be connected to transistors TR1, TR2, and TR3 via the first interconnect 330.

[0058] The substrate 301 may be covered by a first insulating structure 340. The transistors TR1, TR2, and TR3, the first interconnect 330, and the first conductive bonding pattern 331 may be embedded in the first insulating structure 340. The first insulating structure 340 may include two or more insulating layers.

[0059] The bit line BL of the memory cell array, the gate stack 350, the cell plug CPL, the first semiconductor layer SEL1, and the second semiconductor layer SEL2 may be disposed above the first insulating structure 340 and the first conductive bonding pattern 331.

[0060] The semiconductor memory device may include a metal lead 383 disposed at the same height as the bit line BL. The metal lead 383 may be spaced apart from the bit line BL. The conductive materials included in the metal lead 383 and the bit line BL may be various.

[0061] The cell plug CPL may be surrounded by the gate stack 350 disposed between the bit line BL and the first semiconductor layer SEL1. Each cell plug CPL may include a memory layer 361, a channel layer 363, and a core insulating layer 365.

[0062] The channel layer 363 may include a first portion P1 and a second portion P2 extending from the first portion P1 in the longitudinal direction of the channel layer 363. According to an embodiment, the longitudinal direction of the channel layer 363 may be the Z-axis direction. The channel layer 363 may include a drain stage DP extending from the first portion P1 in a direction opposite to the direction in which the second portion P2 extends. The channel layer 363 may serve as a channel region of a memory cell string and may include a semiconductor material. According to an embodiment, the channel layer 363 may include silicon.

[0063] The first portion P1 of the channel layer 363 may be surrounded by the gate stack 350. The second portion P2 of the channel layer 363 may protrude further than the gate stack 350 in the longitudinal direction of the channel layer 363 (e.g., in the Z-axis direction). The drain stage DP may be doped with impurities of a second conductivity type. The drain stage DP may include a portion surrounded by the gate stack 350. The length of the portion of the drain stage DP surrounded by the gate stack 350 may be controlled according to design rules.

[0064] The core insulating layer 365 may be disposed in the central region of each unit plug CPL. The memory layer 361 may be disposed between the first portion P1 of the channel layer 363 and the gate stack structure 350. The memory layer 361 may include a blocking insulating layer between the channel layer 363 and the gate stack structure 350, a data storage layer between the blocking insulating layer and the channel layer 363, and a tunnel insulating layer between the data storage layer and the channel layer 363. The data storage layer may include a material layer capable of storing data changed by Fowler-Nordheim tunneling. The material layer may include a nitride layer capable of capturing charges. The tunnel insulating layer may include an insulating material that allows charge tunneling. According to an embodiment, the tunnel insulating layer may include a silicon oxide layer.

[0065] Each gate stack structure 350 may include an interlayer insulating layer 351 and a conductive pattern 353 that are alternately disposed in the longitudinal direction of the channel layer 363. The stacked structure of the interlayer insulating layer 351 and the conductive pattern 353 may be penetrated by a slit SI.

[0066] As Figure 6 shown in the embodiment of, a conductive vertical contact 373 and a vertical insulating layer 371 may be disposed in the slit SI. The vertical insulating layer 371 may be disposed on the sidewalls of the conductive vertical contact 373. The conductive pattern 353 of each gate stack structure 350 may be insulated from the conductive vertical contact 373 through the vertical insulating layer 371.

[0067] As Figure 7 shown in the embodiment of, the slit SI may be filled with the vertical insulating layer 371'.

[0068] As Figure 5 、 Figure 6 and Figure 7 shown, the conductive pattern 353 of the gate stack structure 350 may be used as a drain select line DSL, a word line WL, and a source select line SSL. The drain separation slit DSI separating the drain select line DSL may be filled with a select isolation insulating layer 369.

[0069] Memory cells may be formed at the intersection of the channel layer 363 of the unit plug CPL and the word line WL. These memory cells may form a three-dimensional memory cell array. A drain select transistor may be formed at the intersection of the channel layer 363 of the unit plug CPL and the drain select line DSL. A source select transistor may be formed at the intersection of the channel layer 363 of the unit plug CPL and the source select line SSL. At least one drain select transistor, a plurality of memory cells, and at least one source select transistor may be serially connected through each channel layer 363.

[0070] Each gate stack structure 350 may have a stepped structure. The gate stack structure 350 and the cell plug CPL may be covered by a first insulating layer 370. The first insulating layer 370 may be formed between the height at which the bit line BL is provided and the gate stack structure 350. The slit SI and the drain separation slit DSI may penetrate through the first insulating layer 370.

[0071] The first insulating layer 370 may be penetrated by a gate vertical contact 375. The gate vertical contact 375 may overlap the stepped structure of the gate stack structure 350 in a one-to-one manner. The gate vertical contact 375 may contact the conductive pattern 353 in a one-to-one manner.

[0072] The semiconductor memory device may include a second insulating layer 380 between the height at which the bit line BL is provided and the first insulating layer 370, and a second insulating structure 390 between the second insulating layer 380 and the first insulating structure 340. The bit line BL and the metal lead 383 may be embedded in the second insulating structure 390. The second insulating structure 390 may include two or more insulating layers. The second insulating structure 390 may include a first height layer 390A between the height at which the bit line BL is provided and the second insulating layer 380, and a second height layer 390B between the height at which the bit line BL is provided and the first insulating structure 340.

[0073] The second insulating layer 380 and the first height layer 390A may be penetrated by inter-channel-bit connection structures 377A, 379A, and 381A, and inter-gate-wire connection structures 377B, 379B, and 381B. The inter-channel-bit connection structures 377A, 379A, and 381A and the inter-gate-wire connection structures 377B, 379B, and 381B may include conductive patterns having various structures.

[0074] According to an embodiment, the inter-channel-bit connection structures 377A, 379A, and 381A may include channel contacts 377A, first contact pads 379A, and bit line contacts 381A. The channel contacts 377A may extend from the channel layer 363 toward the bit line BL and may penetrate through the first insulating layer 370 and the second insulating layer 380. The first contact pads 379A may contact the channel contacts 377A and may be embedded in the first height layer 390A of the second insulating structure 390. The bit line contacts 381A may couple the first contact pads 379A to the bit line BL and may be embedded in the first height layer 390A of the second insulating structure 390.

[0075] According to an embodiment, the gate lead connection structures 377B, 379B, and 381B may include a gate contact 377B, a second contact pad 379B, and a lead contact 381B. The gate contact 377B may contact one of the gate vertical contacts 375 and may pass through the second insulating layer 380. The second contact pad 379B may contact the gate contact 377B and may be embedded in the first height layer 390A of the second insulating structure 390. The lead contact 381B may connect the second contact pad 379B to the metal lead 383 and may be embedded in the first height layer 390A of the second insulating structure 390.

[0076] The bit line BL and the metal lead 383 may be connected to the first conductive bonding pattern 331 via the second interconnect 385 and the second conductive bonding pattern 387. The second interconnect 385 and the second conductive bonding pattern 387 may be embedded in the second height layer 390B of the second insulating structure 390. The second conductive bonding pattern 387 may be bonded to the first conductive bonding pattern 331. The second interconnect 385 may include conductive patterns of various structures. The second interconnect 385 may connect the bit line BL and the metal lead 383 to the second conductive bonding pattern 387.

[0077] The first semiconductor layer SEL1 may extend in the X-Y plane from a first region AR1 to a second region AR2 of the semiconductor memory device. The first semiconductor layer SEL1 may contact the sidewalls of the second portion P2 of the channel layer 363. The first semiconductor layer SEL1 may surround the sidewalls of the second portion P2 of the channel layer 363 and may extend along the X-Y plane to overlap with the three-dimensional memory cell array defined by each of the gate stack structure 350 and the cell plug CPL.

[0078] As Figure 6 shown in the embodiment of, the first semiconductor layer SEL1 may surround the conductive vertical contact 373. The vertical insulating layer 371 may extend between the first semiconductor layer SEL1 and the conductive vertical contact 373.

[0079] As Figure 7 shown in the embodiment of, the first semiconductor layer SEL1 may surround the vertical insulating layer 371'.

[0080] Referring to Figure 5 , Figure 6 and Figure 7 , the second semiconductor layer SEL2 may cover the first semiconductor layer SEL1 and the channel layer 363 of the cell plug CPL. The second semiconductor layer SEL2 may extend in the X-Y plane from a first region AR1 to a second region AR2 of the semiconductor memory device. The second semiconductor layer SEL2 may include an edge EG provided in the first region AR1 and a central region CER provided in the second region AR2.

[0081] The additional region 211 and the well pick-up region 213 of the second semiconductor layer SEL2 may be disposed in the first region AR1 without overlapping the conductive pattern 353 and the cell plug CPL. The well pick-up region 213 may contact a region of the first semiconductor layer SEL1 that does not overlap the conductive pattern 353.

[0082] The conductive well contact 251 may be connected to the well pick-up region 213. The conductive well contact 251 may extend from the well pick-up region 213 in the Z direction.

[0083] The source region 215 of the second semiconductor layer SEL2 may be disposed in the second region AR2 to overlap the three-dimensional memory cell array. Each of the source region 215 of the second semiconductor layer SEL2 and the conductive vertical contact 373 may be used as a common source line.

[0084] The source pick-up region 217 of the second semiconductor layer SEL2 may be formed in the second semiconductor layer SEL2 in the second region AR2.

[0085] As Figure 6 shown in the embodiment of, the source pick-up region 217 of the second semiconductor layer SEL2 may be defined as a region doped with a fourth impurity of a second conductivity type in a portion of the source region 215 that does not overlap the conductive pattern 353 and the well pick-up region 213. According to the embodiment, the source pick-up region 217 may be formed in the second semiconductor layer SEL2 that overlaps the conductive vertical contact 373. The conductive vertical contact 373 may extend from the source pick-up region 217 in the same longitudinal direction as the channel layer 363. The source pick-up region 217 may be connected to the conductive source contact 253 that extends from the source pick-up region 217 in a direction opposite to the direction in which the conductive vertical contact 373 extends.

[0086] As Figure 7 shown in the embodiment of, the source pick-up region 217 of the second semiconductor layer SEL2 may be defined as a region doped with a fourth impurity of a second conductivity type in a portion of the source region 215 that overlaps the conductive pattern 353. The source pick-up region 217 may be formed to avoid overlapping the channel layer 363 of the cell plug CPL. According to the embodiment, the source pick-up region 217 may overlap the gate stack structure 350 between the source pick-up region 217 and the cell plug CPL. The source pick-up region 217 may be connected to the conductive source contact 253 that extends away from the gate stack structure 350.

[0087] Referring to Figure 5 、 Figure 6 and Figure 7, the conductive well contact 251 and the conductive source electrode contact 253 can pass through the upper insulating layer 250 disposed above the second semiconductor layer SEL2. The conductive well contact 251 and the conductive source electrode contact 253 can be connected to the upper leads 261 and 263 disposed above the upper insulating layer 250. The upper leads 261 and 263 can include a first upper lead 261 and a second upper lead 263.

[0088] The first upper lead 261 can be connected to the first semiconductor layer SEL1 serving as a well region via the conductive well contact 251. The first upper lead 261 can transmit an erase voltage during an erase operation.

[0089] The second upper lead 263 can be connected to the source region 215 of the second semiconductor layer SEL2 via the conductive source electrode contact 253. The second upper lead 263 can transmit a source voltage for discharging during a read operation or a verify operation.

[0090] The first semiconductor layer SEL1 can include a first impurity of a first conductivity type and can contact the channel layer 363. The first conductivity type can be p-type. Thus, during an erase operation, holes serving as majority carriers of the first semiconductor layer SEL1 can be supplied to the channel layer 363.

[0091] During a read operation or a verify operation, a read voltage or a verify voltage can be applied to the selected word line connected to the selected memory cell and a source voltage for discharging (e.g., a ground voltage) can be applied to the source region 215. The source region 215 of the second semiconductor layer SEL2 can include a second impurity of a second conductivity type and can contact the channel layer 363. The second conductivity type can be n-type. Thus, when the level of the threshold voltage of the selected memory cell is lower than the level of the read voltage or the verify voltage applied to the selected word line, the voltage pre-charged to the bit line BL can be discharged via the channel layer 363 through the source region 215 during a read operation or a verify operation.

[0092] Figure 8 is an enlarged cross-sectional view showing a part of the semiconductor memory device 100 according to an embodiment.

[0093] Referring to Figure 8 , the channel layer 363 can have a first contact surface SU1 contacting the first semiconductor layer SEL1 and a second contact surface SU2 contacting the second semiconductor layer SEL2. Holes from the first semiconductor layer SEL1 can be supplied to the channel layer 363 through the first contact surface SU1 of the channel layer 363. The second semiconductor layer SEL2 can provide a discharge path through the source region 215 connected to the second contact surface SU2.

[0094] The memory layer 361 can partially surround the sidewalls of the channel layer 363 such that the first contact surface SU1 and the second contact surface SU2 of the channel layer 363 are open.

[0095] Figures 9A to 9C is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0096] Reference Figure 9A , a circuit structure 410 may be formed, which forms the first region AR1 and the second region AR2 of the semiconductor memory device. The circuit structure 410 may include a peripheral circuit structure, a first interconnection 330 connected to the peripheral circuit structure, and a first conductive bonding pattern 331 connected to the first interconnection 330.

[0097] Forming the circuit structure 410 may include forming a peripheral circuit structure having a plurality of transistors TR1, TR2, and TR3. The plurality of transistors TR1, TR2, and TR3 may be formed in an active region of the substrate 301 divided by the isolation layer 303. The plurality of transistors TR1, TR2, and TR3 may be formed as described above with reference to FIG. Figure 5 , Figure 6 and Figure 7 Therefore, for the sake of brevity, the detailed description already described above will be omitted.

[0098] Forming the circuit structure 410 may also include forming a first interconnect 330 and a first conductive bonding pattern 331 embedded in the first insulating structure 340. The first interconnect 330 and the first conductive bonding pattern 331 may be formed as described above with reference to FIG. Figure 5 , Figure 6 and Figure 7 Therefore, for the sake of brevity, the detailed description already described above will be omitted.

[0099] Reference Figure 9B , a preliminary memory array 420 may be formed over a sacrificial substrate 421. The sacrificial substrate 421 may be a silicon layer. Figure 9B The cross-sectional view A in FIG. 1 is taken along the direction crossing the bit line BL. Figure 9B The cross-sectional view B in FIG. 1 is taken along a direction parallel to the bit line BL.

[0100] The preliminary memory array 420 may include a three-dimensional memory cell array, a gate vertical contact 375 and channel bit-to-bit connection structures 377A, 379A and 381A connected to the three-dimensional memory cell array, a gate lead connection structure 377B, 379B and 381B connected to the gate vertical contact 375, a metal lead 383 connected to the gate lead connection structure 377B, 379B and 381B, a bit line BL connected to the channel bit-to-bit connection structure 377A, 379A and 381A, a second interconnect 385 connected to the metal lead 383 and the bit line BL, and a second conductive bonding pattern 387 connected to the second interconnect 385.

[0101] The three-dimensional memory cell array may include a gate stack structure 350 disposed above a sacrificial substrate 421 and a channel layer 363 surrounded by the gate stack structure 350, and a memory layer 361 is interposed between the channel layer 363 and the gate stack structure 350. The three-dimensional memory cell array may be covered by a first insulating layer 370.

[0102] The gate stack structure 350 may include an interlayer insulating layer 351 and a conductive pattern 353 that are alternately stacked on top of each other above the sacrificial substrate 421. The interlayer insulating layer 351 and the conductive pattern 353 may be penetrated by a slit SI, and some of the conductive patterns 353 may be further penetrated by a drain separation slit DSI as well as the slit SI. The slit SI may be filled with a vertical insulating layer 371 and a conductive vertical contact 373 or may be filled with a vertical insulating layer 371’, as Figure 7 shown. The drain separation slit DSI may be filled with a select separation insulating layer 369.

[0103] The memory layer 361 may extend along the surface of a hole passing through the gate stack structure 350. The hole may extend into the sacrificial substrate 421. The channel layer 363 may extend along the inner wall of the memory layer 361. The channel layer 363 may extend into the sacrificial substrate 421 and the memory layer 361 may extend between the sacrificial substrate 421 and the channel layer 363. The central region of the hole may be filled with a core insulating layer 365. The channel layer 363 may include a drain stage DP having an n-type impurity. The drain stage DP may cover the upper end of the core insulating layer 365 facing in a direction opposite to the direction towards the sacrificial substrate 421.

[0104] Channel bit-to-bit connection structures 377A, 379A, and 381A, gate lead-to-lead connection structures 377B, 379B, and 381B, metal leads 383, bit lines BL, second interconnects 385, and second conductive bonding patterns 387 may be embedded in a second insulating layer 380 and a second insulating structure 390. The second insulating structure 390 may include a first height layer 390A between the bit line BL and the second insulating layer 380 and a second height layer 390B above the bit line BL. The channel bit-to-bit connection structures 377A, 379A, and 381A, gate lead-to-lead connection structures 377B, 379B, and 381B, metal leads 383, bit lines BL, second interconnects 385, second conductive bonding patterns 387, second insulating layer 380, and second insulating structure 390 may be configured in the same manner as described above with reference to Figure 5 , Figure 6 and Figure 7 described. Therefore, for the sake of brevity, the detailed description that has been described above will be omitted.

[0105] Refer to Figure 9C, the circuit structure 410 can be aligned with the preliminary memory array 420 such that the first insulating structure 340 of the circuit structure 410 faces the second height layer 390B of the preliminary memory array 420. Subsequently, the preliminary memory array 420 can be connected to the circuit structure 410. According to an embodiment, the preliminary memory array 420 can be connected to the circuit structure 410 by bonding the second conductive bonding pattern 387 of the preliminary memory array 420 to the first conductive bonding pattern 331 of the circuit structure 410.

[0106] can be provided by Figures 9A to 9C the process shown provides some structures for forming the first region AR1 and the second region AR2 of the semiconductor memory device in the X-Z plane and the Y-Z plane as shown.

[0107] Figures 10A to 10G is a cross-sectional view showing Figure 9C an embodiment of the process after the process shown. Figures 10A to 10G is Figure 9C an enlarged cross-sectional view of the region C shown.

[0108] Referring to Figure 10A , the sacrificial substrate 421 shown can be removed. Subsequently, the memory layer 361 can be partially removed to expose a portion of the channel layer 363. Thus, the channel layer 363 can be divided into a first portion P1 and a second portion P2. The first portion P1 is surrounded by the gate stack structure 350, and the memory layer 361 is interposed between the first portion P1 and the gate stack structure 350. The second portion P2 extends from the first portion P1 and is exposed to a region outside the gate stack structure 350. Figure 9C

[0109] Figure 10B Referring to Figure 10B , a preliminary first semiconductor layer 200 can be formed to cover the channel layer 363 and the gate stack structure 350. The preliminary first semiconductor layer 200 can extend along the X-Y plane. The preliminary first semiconductor layer 200 can be a doped semiconductor layer with first impurities of a first conductivity type. The first conductivity type can be p-type.

[0110] Referring to Figure 10C , by Figure 10B the preliminary first semiconductor layer 200 shown is planarized to define a first semiconductor layer SEL1 around the sidewall of the second portion P2 of the channel layer 363. The planarization of the preliminary first semiconductor layer 200 can be performed by a chemical mechanical polishing (CMP) method. According to an embodiment, a portion of the channel layer 363 can be removed and the core insulating layer 365 can be exposed by planarization. The first semiconductor layer SEL1 can include an edge 200EG that protrudes further than the conductive pattern 353 in a direction crossing the channel layer 363.

[0111] Subsequently, asFigure 10C As indicated in the region D shown, impurities 431 for controlling the threshold voltage can be implanted into a portion of the first part P1 of the channel layer 363 adjacent to the second part P2 of the channel layer 363. The impurities 431 for controlling the threshold voltage may include boron.

[0112] Referring to Figure 10D , a preliminary second semiconductor layer 210 can be formed over the first semiconductor layer SEL1. The preliminary second semiconductor layer 210 may include a second impurity of a second conductivity type opposite to the first conductivity type. The second conductivity type may be n-type. The preliminary second semiconductor layer 210 may contact an open portion of the second part P2 of the channel layer 363 through the first semiconductor layer SEL1 and may contact the first semiconductor layer SEL1. The preliminary second semiconductor layer 210 may contact the conductive vertical contact 373.

[0113] The preliminary second semiconductor layer 210 may extend along the X-Y plane. The preliminary second semiconductor layer 210 may include an edge 210EG that protrudes further than the conductive pattern 353 in a direction intersecting the channel layer 363. The preliminary second semiconductor layer 210 may include a central region 210CER surrounded by the edge 210EG.

[0114] Referring to Figure 10E , into Figure 10D the edge 210EG of the preliminary second semiconductor layer 210 shown, a third impurity 433 of the first conductivity type can be implanted. Thus, a well pick-up region 213 contacting the first semiconductor layer SEL1 can be formed.

[0115] An additional region 211 having the second impurity and a preliminary source region 215P having the second impurity can be divided by the well pick-up region 213. The preliminary source region 215P can be defined in Figure 10D the central region 210CER of the preliminary second semiconductor layer 210 shown. The concentration of the third impurity in the well pick-up region 213 can be higher than the concentration of the first impurity in the first semiconductor layer SEL1.

[0116] Referring to Figure 10F , into Figure 10D a portion of the central region 210CER of the preliminary second semiconductor layer 210 shown, a fourth impurity of the second conductivity type can be implanted. Thus, a source pick-up region 217 can be formed. The remaining portion of the central region 210CER of the preliminary second semiconductor layer 210 other than the portion implanted with the fourth impurity can be defined as the source region 215.

[0117] The concentration of the fourth impurity in the source pick-up region 217 can be higher than the concentration of the second impurity in the source region 215. As Figure 4 shown, the source region 215 can surround the source pick-up region 217.

[0118] The source pick-up region 217 may be defined in a region that does not overlap with the channel layer 363. According to an embodiment, the source pick-up region 217 may overlap with the conductive vertical contact 373. In another embodiment, the source pick-up region 217 may overlap with the gate stack structure 350 disposed between the channel layers 363, as Figure 7 shown.

[0119] The second semiconductor layer SEL2 having the source region 215, the source pick-up region 217, the additional region 211, and the well pick-up region 213 may be defined by the process described with reference to Figures 10A to 10F described.

[0120] With reference to Figure 10G , an upper insulating layer 250 may be formed over the second semiconductor layer SEL2. Subsequently, a conductive well contact 251 and a conductive source contact 253 passing through the upper insulating layer 250 may be formed. The conductive well contact 251 may be connected to the well pick-up region 213, and the conductive source contact 253 may be connected to the source pick-up region 217.

[0121] Subsequently, upper leads 261 and 263 respectively connected to the conductive well contact 251 and the conductive source contact 253 may be formed over the upper insulating layer 250.

[0122] Figure 11 is a block diagram showing the configuration of a memory system 1100 according to an embodiment.

[0123] With reference to Figure 11 , the memory system 1100 may include a memory device 1120 and a storage controller 1110.

[0124] The memory device 1120 may be a multi-chip package including a plurality of flash memory chips. The memory device 1120 may include a first impurity region of a first conductivity type and a second impurity region of a second conductivity type opposite to the first conductivity type. The first impurity region and the second impurity region may contact the channel layer of the memory cell array. The first impurity region may be used as a current path during an erase operation, and the second impurity region may be used as a current path during a read operation or a verify operation.

[0125] The storage controller 1110 may be configured to control the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as an operation memory for the CPU 1112. The CPU 1112 may perform general control operations on data exchanges of the storage controller 1110, and the host interface 1113 may include a data exchange protocol for a host accessing the memory system 1100. The error correction block 1114 may detect and correct errors included in data read from the memory device 1120. The memory interface 1115 may interface with the memory device 1120. The storage controller 1110 may further include a read-only memory (ROM) storing code data for the host interface.

[0126] The memory system 1100 having the above configuration may be a solid state drive (SSD) or a memory card in which the memory device 1120 and the storage controller 1110 are combined. For example, when the memory system 1100 is an SSD, the storage controller 1110 may communicate with an external device (e.g., a host) through one of various interface protocols including a universal serial bus (USB), a multimedia card (MMC), a high-speed peripheral component interconnect (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

[0127] Figure 12 is a block diagram showing a configuration of a computing system according to an embodiment.

[0128] Referring to Figure 12 , the computing system 1200 may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may further be included, and an application chipset, an image processor, a mobile DRAM, etc. may further be included.

[0129] The memory system 1210 may include a memory device 1212 and a storage controller 1211.

[0130] The memory device 1212 may include a first impurity region of a first conduction type and a second impurity region of a second conduction type opposite to the first conduction type. The first impurity region and the second impurity region may contact a channel layer of a memory cell array. The first impurity region may be used as a current path during an erase operation, and the second impurity region may be used as a current path during a read operation or a verify operation.

[0131] The storage controller 1211 may be configured in the same manner as the storage controller 1110 described above with reference to Figure 11 described.

[0132] According to an embodiment of the present disclosure, since an erasing operation based on majority carriers can be implemented, the operation reliability of the semiconductor memory device can be improved.

[0133] Cross - reference to related applications

[0134] This application claims priority to Korean Patent Application No. 10 - 2021 - 0038267, filed with the Korean Intellectual Property Office on March 24, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A channel layer having a first portion and a second portion, the first portion and the second portion extending in a longitudinal direction; A gate stack structure that surrounds the first portion of the channel layer; A first semiconductor layer, the first semiconductor layer including a well region doped with a first impurity of a first conductivity type, the first semiconductor layer contacting sidewalls of the second portion of the channel layer; And A second semiconductor layer that covers the first semiconductor layer and the channel layer, Wherein, the second semiconductor layer includes a source region doped with a second impurity of a second conductivity type opposite to the first conductivity type, and Wherein, the channel layer contacts both the well region of the first semiconductor layer and the source region of the second semiconductor layer.

2. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising a memory layer disposed between the first portion of the channel layer and the gate stack structure, Among them, The gate stack structure includes a plurality of conductive patterns and a plurality of interlayer insulating layers stacked alternately with each other in the longitudinal direction.

3. The semiconductor memory device according to claim 1, wherein, The second semiconductor layer further includes a well pick-up region doped with a third impurity of the first conductivity type, and Wherein, the concentration of the third impurity in the well pick-up region is higher than the concentration of the first impurity in the first semiconductor layer.

4. The semiconductor memory device according to claim 3, wherein, The well pick-up region contacts a part of the first semiconductor layer.

5. The semiconductor memory device according to claim 3, wherein, The second semiconductor layer further includes a source pick-up region doped with a fourth impurity of the second conductivity type in the source region, and Wherein, the concentration of the fourth impurity in the source pick-up region is higher than the concentration of the second impurity in the source region.

6. The semiconductor memory device according to claim 5, wherein, The source pick-up region is disposed in a portion of the source region that does not overlap with the channel layer and the well pick-up region.

7. The semiconductor memory device according to claim 5, the semiconductor memory device further comprising: A conductive vertical contact that extends from the source pick-up region in the same longitudinal direction as the channel layer; An insulating layer that is located between the conductive vertical contact and the gate stack structure; A conductive source contact that extends in a direction opposite to the direction in which the conductive vertical contact extends; And An upper lead that is connected to the conductive source contact and transmits a source voltage during a read operation or a verify operation.

8. The semiconductor memory device according to claim 5, wherein, The gate stack structure includes a plurality of conductive patterns stacked and spaced apart from each other in the longitudinal direction, and Wherein, the source pick-up region overlaps with the conductive patterns.

9. The semiconductor memory device according to claim 8, the semiconductor memory device further comprising: A conductive source contact that extends from the source pick-up region and extends away from the gate stack structure; And An upper lead that is connected to the conductive source contact and transmits a source voltage during a read operation or a verify operation.

10. The semiconductor memory device according to claim 3, the semiconductor memory device further comprising: A conductive well contact connected to the well pick-up region; and An upper lead connected to the conductive well contact and transmitting an erase voltage during an erase operation.

11. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising: A peripheral circuit structure overlapping with the gate stack structure; and A bit line disposed between the peripheral circuit structure and the gate stack structure.

12. A semiconductor memory device, the semiconductor memory device comprising: A three-dimensional memory cell array; A first semiconductor layer overlapping with the three-dimensional memory cell array, the first semiconductor layer including a well region doped with a first impurity of a first conductivity type; and A second semiconductor layer disposed above the first semiconductor layer, the second semiconductor layer including a source region doped with a second impurity of a second conductivity type opposite to the first conductivity type, wherein the three-dimensional memory cell array includes a plurality of channel layers, each of the channel layers having a first contact surface contacting the well region of the first semiconductor layer and a second contact surface contacting the source region of the second semiconductor layer.

13. The semiconductor memory device according to claim 12, wherein, The second semiconductor layer includes a central region overlapping with the three-dimensional memory cell array and an edge surrounding the central region, and wherein the source region of the second semiconductor layer is formed in the central region of the second semiconductor layer.

14. The semiconductor memory device according to claim 12, wherein, The second semiconductor layer further includes a well pick-up region doped with a third impurity of the first conductivity type, and wherein the concentration of the third impurity in the well pick-up region is higher than the concentration of the first impurity in the first semiconductor layer.

15. The semiconductor memory device according to claim 14, wherein, The second semiconductor layer further includes a central region overlapping with the three-dimensional memory cell array and an edge surrounding the central region, and wherein the well pick-up region is formed in the edge of the second semiconductor layer.

16. The semiconductor memory device according to claim 12, the semiconductor memory device further comprising a bit line spaced apart from the first semiconductor layer, and the channel layer is interposed between the bit line and the first semiconductor layer, the bit line being connected to the channel layer, Among them, The three-dimensional memory cell array further includes: A memory layer surrounding a part of the sidewall of each of the channel layers to expose the first contact surface and the second contact surface of each of the channel layers; and A plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked between the first semiconductor layer and the bit line, the plurality of interlayer insulating layers and the plurality of conductive patterns surrounding the memory layer.

17. The semiconductor memory device according to claim 16, the semiconductor memory device further comprising: A slit passing through the interlayer insulating layer and the conductive pattern; A conductive vertical contact located in the slit; An insulating layer located on the sidewall of the conductive vertical contact; and A source pickup region, which is doped with a fourth impurity of the second conductivity type and is located in a portion of the source region that overlaps with the conductive vertical contact. Wherein, the concentration of the fourth impurity in the source pickup region is higher than the concentration of the second impurity in the source region.

18. The semiconductor memory device according to claim 16, wherein, The second semiconductor layer further includes a source pickup region, which is doped with a fourth impurity of the second conductivity type and is located in a portion of the source region that overlaps with the conductive pattern but does not overlap with the channel layer, and Wherein, the concentration of the fourth impurity in the source pickup region is higher than the concentration of the second impurity in the source region.

19. The semiconductor memory device according to claim 12, the semiconductor memory device further includes a peripheral circuit structure overlapping with the first semiconductor layer, and the three-dimensional memory cell array is interposed between the first semiconductor layer and the peripheral circuit structure.

20. The semiconductor memory device according to claim 12, the semiconductor memory device further includes: A first upper lead, which is connected to the first semiconductor layer and transmits an erase voltage during an erase operation; And A second upper lead, which is connected to the source region and transmits a source voltage during a read operation or a verify operation.

21. A method of manufacturing a semiconductor memory device, the method includes the following steps: Forming a plurality of channel layers, each channel layer including a first portion and a second portion, the first portion being surrounded by a gate stack structure and a memory layer being interposed between the first portion and the gate stack structure, the second portion extending from the first portion and being exposed to an area outside the gate stack structure; Forming a first semiconductor layer that contacts a part of the second portion of each of the channel layers, the first semiconductor layer including a well region doped with a first impurity of a first conductivity type; And Forming a second semiconductor layer that contacts an open portion of the second portion of each of the channel layers through the first semiconductor layer, the second semiconductor layer including a source region doped with a second impurity of a second conductivity type opposite to the first conductivity type, Wherein, each of the channel layers includes a first contact surface contacting the well region of the first semiconductor layer and a second contact surface contacting the source region of the second semiconductor layer.

22. The method according to claim 21, the method further includes the following steps: Forming a peripheral circuit structure including a plurality of transistors; Forming a first conductive bonding pattern connected to the plurality of transistors; Forming a preliminary memory array, the preliminary memory array including the memory layer, the gate stack structure, the channel layer, and a bit line connected to the channel layer; Forming a second conductive bonding pattern connected to the preliminary memory array; And Bonding the second conductive bonding pattern to the first conductive bonding pattern.

23. The method according to claim 22, wherein, Forming the gate stack structure of the preliminary memory array above the substrate, and Wherein, the memory layer of the preliminary memory array extends between each of the channel layers and the substrate.

24. The method according to claim 23, the method further comprising the following steps: Removing the substrate; And Removing a part of the memory layer to expose the second part of each of the channel layers.

25. The method according to claim 21, the method further comprising the steps of: Forming a well pick-up region contacting the first semiconductor layer by implanting a third impurity of the first conductivity type into an edge of the second semiconductor layer, wherein the concentration of the third impurity in the well pick-up region is higher than the concentration of the first impurity in the first semiconductor layer.

26. The method according to claim 21, wherein, The second semiconductor layer includes a central region surrounded by an edge, and wherein the method further comprises forming a source pick-up region by implanting a fourth impurity of the second conductivity type into a part of the central region.

27. The method according to claim 26, wherein, The central region includes the source region doped with the second impurity, wherein the source region surrounds the source pick-up region, and wherein the concentration of the fourth impurity in the source pick-up region is higher than the concentration of the second impurity in the source region.

28. The method according to claim 26, wherein The source pick-up region does not overlap with the channel layer.

29. The method according to claim 26, wherein, The source pick-up region overlaps with the gate stack structure between the plurality of channel layers.

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