Array substrate, display panel and display device

Abstract

Embodiments of the present application provide an array substrate, a display panel and a display device. The present application relates to the technical field of display, and aims to solve the technical problem of a large number of wirings and high density in an array substrate. The array substrate comprises a plurality of driving circuit groups arranged side by side in a second direction; each driving circuit group comprises a plurality of pixel driving circuits arranged in a first direction, and each driving circuit group shares a group of signal lines for providing signals to the pixel driving circuits; the driving circuit groups comprise a first driving circuit group and a second driving circuit group arranged adjacently in the second direction, the first driving circuit group comprises a first sub-signal line, and the first sub-signal line is discontinuous in the same film layer; the second driving circuit group comprises a second sub-signal line for transmitting the same signals as the first sub-signal line, the second sub-signal line is continuous in the first direction, and the second sub-signal line shares transmission with the first sub-signal line. Through the arrangement, the number of signal line wirings can be effectively reduced, and the density of signal line wirings can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) display panel is a display device that utilizes the self-luminous principle of organic electroluminescent materials to realize display. Compared with liquid crystal display devices, the organic light emitting diode display panel has many advantages such as self-luminous, fast response speed, low-voltage driving, high brightness, thinness and the like, and thus gradually becomes the mainstream in the display field. In the display panel, each driving circuit group is provided with a signal line. The signal lines of each driving circuit group are independently provided, thereby resulting in a large number of signal line traces and a high density, and occupying a large space. SUMMARY

[0003] In view of the above problems, the embodiments of the present application provide an array substrate, a display panel and a display device, which can effectively reduce the number of signal line traces of the array substrate and reduce the density of the signal line traces.

[0004] In order to achieve the above-mentioned purpose, the embodiments of the present application provide the following technical solutions:

[0005] The first aspect of the embodiments of the present application provides an array substrate, comprising a plurality of driving circuit groups arranged side by side in a second direction; each driving circuit group comprises a plurality of pixel driving circuits arranged in a first direction, each driving circuit group shares a group of signal lines, and the signal lines are used to provide signals to the pixel driving circuits;

[0006] The driving circuit group comprises a first driving circuit group and a second driving circuit group arranged adjacent in the second direction, the first driving circuit group comprises a first sub-signal line, the first sub-signal line is discontinuous in the same film layer; the second driving circuit group comprises a second sub-signal line transmitting the same signal as the first sub-signal line, the second sub-signal line is continuous in the first direction, and shares transmission with the first sub-signal line.

[0007] The array substrate provided by the present application can effectively reduce the number and density of signal line traces due to the reuse of part of the second sub-signal line by the first sub-signal line, which is beneficial to save space.

[0008] In a possible implementation manner, the first sub-signal line and the second sub-signal line are electrically connected through a switching line.

[0009] In a possible implementation, the first sub-signal line comprises a connection end, and the second sub-signal line comprises a multiplexing part, in two adjacent groups of the signal lines, the connection end of one group of the first sub-signal lines is electrically connected to the multiplexing part of the second sub-signal line for transmitting the same signal in the other group through the adapter line.

[0010] In a possible implementation, the first direction is a row direction, and the second direction is a column direction.

[0011] In a possible implementation, the number of the second sub-signal lines is more than two, and the multiplexing parts of two adjacent second sub-signal lines are arranged on different metal layers. This is advantageous to reduce the resistance or capacitance deviation between the second sub-signal lines, thereby improving the display effect of the display panel.

[0012] In a possible implementation, the array substrate comprises a substrate, a first metal layer, and a second metal layer on the substrate, the first metal layer is insulated from the second metal layer, and the multiplexing parts of two adjacent second sub-signal lines are arranged on the first metal layer and the second metal layer in sequence.

[0013] In a possible implementation, the array substrate comprises a substrate, a first metal layer, a second metal layer, and a third metal layer on the substrate, the number of the second sub-signal lines is more than three, and the multiplexing parts of three adjacent second sub-signal lines are arranged on the first metal layer, the second metal layer, and the third metal layer in sequence. This can more effectively ensure that the second sub-signal lines do not easily interfere with each other while reducing the processing difficulty of the second sub-signal lines.

[0014] In a possible implementation, in two adjacent groups of the signal lines, the number of all the second sub-signal lines is more than two. This provides a possible implementation.

[0015] In a possible implementation, the pixel driving circuit is a 7T1C circuit.

[0016] In a possible implementation, in two adjacent groups of the signal lines, each second sub-signal line is a continuous and integral structure. This is advantageous to reduce the processing difficulty of the second sub-signal lines.

[0017] In a possible implementation, in two adjacent groups of the signal lines, each group of the signal lines comprises one light-emitting control line and three scan lines, in one group of the signal lines, the light-emitting control line and the three scan lines are all the second sub-signal lines, and in the other group of the signal lines, the light-emitting control line and two of the scan lines are the first sub-signal lines, and the other scan line is the second sub-signal line. This embodiment determines the specific number, form, and function of the signal lines.

[0018] In a possible implementation, in the two adjacent groups of the signal lines, at least part of the second sub-signal lines comprise a first part, a second part and a bridge, the connection end is connected to the first part, the multiplexing part comprises the second part, the first part and the second part are located in different metal layers, and the bridge electrically connects the first part and the second part. By flexibly adjusting the metal layers in which the first part and the second part of the second sub-signal line are located, it is easy to realize that the two adjacent multiplexing parts in each second sub-signal line are arranged in two different metal layers.

[0019] In a possible implementation, the first part and the second part are located in different metal layers from the bridge. This is advantageous for reducing the possibility of mutual interference between the first part, the second part and the bridge.

[0020] In a possible implementation, in the two adjacent groups of the signal lines, each second sub-signal line in one group is a continuous and integral structure, and at least part of the second sub-signal lines in the other group comprise the first part, the second part and the bridge.

[0021] In a possible implementation, in the two adjacent groups of the signal lines, each group of the signal lines comprises one light-emitting control line and three scan lines, in one group of the signal lines, the light-emitting control line and one scan line are the first sub-signal lines, and two scan lines are the second sub-signal lines, in the other group of the signal lines, one scan line is the first sub-signal line, the light-emitting control line and two scan lines are the second sub-signal lines, and the light-emitting control line comprises the first part, the second part and the bridge.

[0022] In a possible implementation, the signal lines and the switching lines are located in different metal layers. This is advantageous for reducing the possibility of mutual interference between the signal lines and the switching lines.

[0023] In a possible implementation, the array substrate comprises a fourth metal layer, and the switching line is arranged on the fourth metal layer. This is advantageous for reducing the processing difficulty of the switching line.

[0024] A second aspect of the embodiment of the present application provides a display panel comprising the array substrate in any of the above embodiments.

[0025] In a possible implementation, the display panel comprises a display area, an opening area and a non-display area; the non-display area is located between the opening area and the display area; the first sub-signal line is disconnected in the opening area; the connection end is located in the non-display area; the second sub-signal line is arranged to bypass the opening area; and the multiplexing unit is located in the non-display area and is arranged to bypass the opening area.

[0026] The multiplexing unit shared by the second sub-signal lines can be located in the non-display area outside the periphery of the opening area, so that the number and density of the wirings in the non-display area can be effectively reduced, thereby facilitating the reduction of the area of the non-display area, and accordingly the area of the display area can be increased, and the display effect of the display panel can be improved.

[0027] In a possible implementation, the display panel is an LTPO display panel.

[0028] A third aspect of the embodiments of the present application provides a display device comprising the display panel in any of the above embodiments.

[0029] In the array substrate, the display panel and the display device of the embodiments of the present application, the first sub-signal lines discontinuously and the second sub-signal lines continuously and conductively can share the transmission, so that at least part of the second sub-signal lines can be shared by the first sub-signal lines and the second sub-signal lines. In this way, the number and density of the signal lines can be effectively reduced, and the space can be saved. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative labor.

[0031] Figure 1 A structural schematic diagram of a pixel driving circuit of an embodiment of the present application;

[0032] Figure 2 A planar schematic diagram of peripheral wirings of an opening area of a display panel corresponding to an array substrate of an embodiment of the present application;

[0033] Figure 3 A planar schematic diagram of peripheral wirings of an opening area of a display panel corresponding to an array substrate of another embodiment of the present application;

[0034] Figure 4 A planar schematic diagram of peripheral wirings of an opening area of a display panel corresponding to an array substrate of still another embodiment of the present application;

[0035] Figure 5 A plan view of a peripheral wiring of an aperture region of a display panel corresponding to an array substrate of another embodiment of the present application;

[0036] Figure 6 A plan view of a peripheral wiring of an aperture region of a display panel corresponding to an array substrate of still another embodiment of the present application;

[0037] Figure 7 A schematic diagram of a connection state of a signal line and a pixel driving circuit of an embodiment of the present application;

[0038] Figure 8 A schematic diagram of a structure of a display panel of an embodiment of the present application;

[0039] Figure 9 A schematic diagram of a structure of a display panel of an embodiment of the present application; Figure 8 A schematic diagram of a structure of a display panel of an embodiment of the present application;

[0040] Explanation of reference signs:

[0041] 10, display panel;

[0042] 20, pixel driving circuit;

[0043] 30, first sub-signal line;

[0044] 40, second sub-signal line; 40a, multiplexing section; 401, first part; 402, second part; 403, cross bridge;

[0045] 50, switching line;

[0046] AA, display region;

[0047] NA, non-display region;

[0048] K, aperture region;

[0049] X, row direction;

[0050] Y, column direction. DETAILED DESCRIPTION

[0051] The inventor has found, through long-term research, that in the related art, a plurality of pixel driving circuits are provided in a display panel. The plurality of pixel driving circuits arranged in a first direction constitute a driving circuit group, and each driving circuit group shares a set of signal lines. The signal lines are used to input signals to the pixel driving circuits. Each set of signal lines is independently provided, resulting in a large number of signal line wirings, high density, and occupation of a large space.

[0052] It can be understood that the display panel can be an LTPO (Low Temperature Poly Oxide) display panel. Compared with an LTPS (Low Temperature Poly-Silicon) display panel, the LTPO (Low Temperature Poly Oxide) display panel has the characteristics of low power consumption and good low-frequency display effect.

[0053] It can be understood that the circuit structure of the pixel driving circuit in the LTPO display panel can be as shown in FIG. 2A, and the pixel driving circuit includes a capacitor Cst, a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, and a transistor T7, that is, a 7T1C circuit, wherein the transistor T1 serves as a driving transistor. Figure 1 Specifically, the first stage of the transistor T1 is connected to the first stage of the transistor T5, the second stage of the transistor T1 is connected to the first stage of the transistor T6, and the gate of the transistor T1 is connected to the first stage of the capacitor Cst; the second stage of the transistor T5 is connected to a voltage signal ELVDD, and the gate of the transistor T5 is connected to a light-emitting control signal EM; the second stage of the transistor T6 is connected to a first end of a light-emitting diode, and the gate of the transistor T6 is connected to the light-emitting control signal EM; the first stage of the transistor T2 is connected to the first stage of the transistor T1, the second stage of the transistor T2 is connected to a data line Vdata, and the gate of the transistor T2 is connected to a second scan line S2; the first stage of the transistor T3 is connected to the second stage of the transistor T1, the second stage of the transistor T3 is connected to the gate of the transistor T1, and the gate of the transistor T3 is connected to a third scan line S3; the first stage of the transistor T4 is connected to the first stage of the capacitor Cst, the second stage of the transistor T4 is connected to an initialization signal Vref1, and the gate of the transistor T4 is connected to a first scan line S1; the first stage of the transistor T7 is connected to the first end of the light-emitting diode, the second stage of the transistor T7 is connected to an initialization signal Vref2, and the gate of the transistor T7 is connected to the second scan line S2. The second stage of the capacitor Cst is connected to the voltage signal ELVDD; and the second end of the light-emitting diode is connected to a voltage signal ELVSS. Specifically, in the LTPO display panel, the materials of the semiconductor layers of the transistor T3 and the transistor T4 in the pixel driving circuit are indium gallium zinc oxide (IGZO), and the materials of the semiconductor layers of the remaining transistors T1, T2, T5, T6, and T7 are polysilicon.

[0054] In the technical solution, each of the driving circuit groups is correspondingly provided with a group of signal lines, in the adjacent two groups of the signal lines, the first sub-signal lines of one of the driving circuit groups are discontinuous in the same film layer, and the second sub-signal lines of the other of the driving circuit groups are continuous and share transmission with the first sub-signal lines transmitting the same signal. Thus, the signal lines for transmitting the same signal in the adjacent two driving circuit groups share a part, which is beneficial to reduce the number of signal lines and in turn reduce the signal line density.

[0055] To make the objectives, technical solutions, and superiorities of the embodiments of the present application clearer, the following further describes the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall into the scope of the present application.

[0056] In one aspect, the present application provides an array substrate, which can be seen from Figure 2 , Figure 2 The figure is a plane view of the peripheral wiring of the aperture region of the display panel corresponding to the array substrate of an embodiment of the present application. In the embodiment, a plurality of driving circuit groups are arranged side by side in the second direction; each of the driving circuit groups includes a plurality of pixel driving circuits 20 arranged in the first direction, each of the driving circuit groups shares a group of signal lines, and the signal lines are used to provide signals to the pixel driving circuits 20; the driving circuit groups include a first driving circuit group and a second driving circuit group arranged adjacent to each other in the second direction, the first driving circuit group includes first sub-signal lines 30, and the first sub-signal lines 30 are discontinuous in the same film layer, i.e., are arranged discontinuously; the second driving circuit group includes second sub-signal lines 40 transmitting the same signals as the first sub-signal lines 30, the second sub-signal lines 40 are continuous in the first direction, and share transmission with the first sub-signal lines 30.

[0057] It can be understood that the present application does not limit the order of the first driving circuit group and the second driving circuit group in the second direction.

[0058] It can be understood that the first driving circuit group can simultaneously include the first sub-signal lines 30 and the second sub-signal lines 40; and the second driving circuit group can also simultaneously include the first sub-signal lines 30 and the second sub-signal lines 40.

[0059] It can be understood that the pixel driving circuit 20 provided by the present application is of a 7T1C structure, which can be seen from the accompanying Figure 1 .

[0060] In the array substrate provided in this application, a non-continuous first sub-signal line 30 and a continuously conducting second sub-signal line 40 transmitting the same signal can share the transmission path, so that at least a portion of the second sub-signal line 40 can be shared by the first sub-signal line 30 and the second sub-signal line 40. This arrangement can effectively reduce the number and density of signal lines, which is beneficial for saving space.

[0061] In one possible implementation, the first sub-signal line 30 and the second sub-signal line 40 are electrically connected via an adapter cable 50.

[0062] In one specific embodiment, the first sub-signal line 30 includes a connecting terminal, and the second sub-signal line 40 includes a multiplexing portion 40a. In two adjacent sets of signal lines, the connecting terminal of one set of first sub-signal lines 30 is electrically connected to the multiplexing portion 40a of the other set of second sub-signal lines 40 used for transmitting the same signal via an adapter cable 50. The multiplexing portion 40a of the second sub-signal line 40 forms a shared portion between the first sub-signal line 30 and the second sub-signal line 40, thereby allowing the first sub-signal line 30 to multiplex a portion of the second sub-signal line 40 for signal transmission.

[0063] Specifically, the first direction is the row direction X, and the second direction is the column direction Y.

[0064] In the display panel 10 of this embodiment, the discontinuous first sub-signal line 30 and the continuous second sub-signal line 40 can be electrically connected by using an adapter cable 50, so that the multiplexing portion 40a on the second sub-signal line 40 can be shared by the first sub-signal line 30 and the second sub-signal line 40. The area of ​​the multiplexing portion 40a on the second sub-signal line 40 can effectively reduce the number and density of signal lines, which is beneficial for saving space.

[0065] See in some examples Figure 2 As shown, the first sub-signal line 30 corresponding to a drive circuit group located on the left side of the aperture area K is electrically connected to the second sub-signal line 40 via an adapter cable 50. The first sub-signal line 30 corresponding to a drive circuit group located on the right side of the aperture area K is electrically connected to the second sub-signal line 40 via another adapter cable 50.

[0066] In some embodiments, the signal line and the adapter 50 may be located on different metal layers, that is, the first sub-signal line 30 and the second sub-signal line 40 are both located on different metal layers from the adapter 50, which helps to reduce the possibility of mutual interference between the signal line and the adapter 50.

[0067] In some examples, the array substrate can include a substrate, a first metal layer (M1), and a second metal layer (M2). Preferably, the array substrate further includes a third metal layer (M3) and a fourth metal layer (M4). Among the first metal layer (M1), the second metal layer (M2), the third metal layer (M3), and the fourth metal layer (M4), an insulating layer can be arranged between any two adjacent metal layers.

[0068] In some examples, the third metal layer (M3) can be used to arrange a data signal line (not shown in the figure). The data signal line can extend along the column direction Y. The first sub-signal line 30 and the second sub-signal line 40 can be arranged to intersect the data signal line. The adapter line 50 of the embodiment of the present application can be arranged in the fourth metal layer (M4), which is conducive to reducing the processing difficulty of the adapter line 50.

[0069] In some embodiments, among all the signal lines, the number of the second sub-signal lines 40 is two or more. The multiplexing part 40a of the adjacent two second sub-signal lines 40 can be arranged in two different metal layers, thereby facilitating the reduction of the resistance or capacitance deviation formed between each second sub-signal line 40, so as to facilitate the improvement of the display effect of the display panel 10.

[0070] In some examples, the array substrate includes a substrate, a first metal layer (M1), and a second metal layer (M2). The first metal layer (M1) is insulated from the second metal layer (M2), and the multiplexing part 40a of the adjacent two second sub-signal lines 40 is arranged in the first metal layer (M1) and the second metal layer (M2) in turn, thereby ensuring that the processing difficulty of the second sub-signal line 40 is reduced without mutual interference between the second sub-signal lines 40.

[0071] In some examples, referring to Figure 2 As shown, one driving circuit group corresponds to a group of signal lines. Each group of driving circuit groups corresponds to one first sub-signal line 30 and one second sub-signal line 40. That is, the first driving circuit group includes one first sub-signal line 30, and the second driving circuit group includes one second sub-signal line 40 that transmits the same signal as the first sub-signal line 30. Among all the signal lines corresponding to the four groups of driving circuit groups, the number of the second sub-signal lines 40 is two. The multiplexing part 40a of the two second sub-signal lines 40 is arranged in two different metal layers. One of the two second sub-signal lines 40 is arranged in the first metal layer (M1), and the other is arranged in the second metal layer (M2).

[0072] In some embodiments, among the adjacent two groups of signal lines, the number of all the second sub-signal lines 40 is two or more. In some examples, Figure 3A plan view of the array substrate of the present application is shown schematically. The plan view shows the peripheral wiring of the aperture region K of the display panel. Referring to Figure 3 As shown, the number of second sub-signal lines 40 in the two adjacent groups of signal lines is two. The number of second sub-signal lines 40 in all the signal lines corresponding to the four adjacent groups of driving circuit groups is four. Exemplarily, the multiplexing portions 40a of the two adjacent second sub-signal lines 40 are disposed in the first metal layer (M1) and the second metal layer (M2), respectively. For example, Figure 3 The four multiplexing portions 40a shown in FIG. 4 can be disposed in the first metal layer (M1), the second metal layer (M2), the first metal layer (M1) and the second metal layer (M2), respectively.

[0073] In some examples, the number of all the second sub-signal lines 40 is three or more. The multiplexing portions 40a of the three adjacent second sub-signal lines 40 are disposed in the first metal layer (M1), the second metal layer (M2) and the third metal layer (M3), respectively, so as to ensure that the second sub-signal lines 40 do not easily interfere with each other while reducing the processing difficulty of the second sub-signal lines 40. Exemplarily, as shown in FIG. 5, Figure 3 The four multiplexing portions 40a shown in FIG. 5 can be disposed in the first metal layer (M1), the second metal layer (M2), the third metal layer (M3) and the first metal layer (M1), respectively. Understandably, Figure 3 The order of the metal layers in which the four multiplexing portions 40a are disposed is not limited to the above form, but can also be other forms, for example, the four multiplexing portions 40a can be disposed in the first metal layer (M1), the third metal layer (M3), the second metal layer (M2) and the first metal layer (M1), respectively, which is not specifically limited here.

[0074] In some embodiments, the number of all the second sub-signal lines 40 corresponding to the four adjacent groups of driving circuit groups is two or more, i.e., the number of all the second sub-signal lines 40 corresponding to the four adjacent groups of signal lines is two or more. In the four adjacent groups of driving circuit groups, each two groups of driving circuit groups correspond to at least one second sub-signal line 40. This embodiment can make the arrangement of the second sub-signal lines 40 more uniform.

[0075] In some embodiments, referring to Figure 3 As shown in FIG. 6, in the two adjacent groups of signal lines, two signal lines in one group of signal lines are both second sub-signal lines 40, and two signal lines in the other group of signal lines are both first sub-signal lines 30. That is, the first driving circuit group includes two first sub-signal lines 30, and the second driving circuit group includes two second sub-signal lines 40 that transmit the same signal as the first sub-signal lines 30. The two first sub-signal lines 30 are electrically connected to the two second sub-signal lines 40 for transmitting the same signal through the adapter lines 50.

[0076] In some embodiments, in the two adjacent groups of signal lines, each second sub-signal line 40 is a continuous structure, thereby facilitating the processing of the second sub-signal line 40. It should be noted that each second sub-signal line 40 is a continuous structure refers to that each part of the second sub-signal line 40 is not disconnected and is located in the same metal layer. The continuous second sub-signal line 40 can be formed by a patterning process.

[0077] In some embodiments, in the two adjacent groups of signal lines, one group of signal lines forms the second sub-signal line 40, and the other group of signal lines forms the first sub-signal line 30 and the second sub-signal line 40 respectively.

[0078] In some examples, Figure 4 The plan view of the peripheral wiring of the aperture area K of the display panel corresponding to the array substrate of the present application is schematically shown. Referring to Figure 4 As shown, each group of signal lines can include three signal lines. In the two adjacent groups of signal lines, the three signal lines of one group of signal lines can include two first sub-signal lines 30 and one second sub-signal line 40, and the three signal lines of the other group of signal lines can all be second sub-signal lines 40. That is, the first driving circuit group includes two first sub-signal lines 30 and one second sub-signal line 40, and the second driving circuit group includes three second sub-signal lines 40 which transmit the same signal as the first sub-signal line 30. Specifically, the two first sub-signal lines 30 in one group are respectively electrically connected to the two second sub-signal lines 40 in the other group which transmit the same signal through the adapter lines 50.

[0079] In some embodiments, Figure 5 The plan view of the peripheral wiring of the aperture area K of the display panel corresponding to the array substrate of the present application is schematically shown. Referring to Figure 5 As shown, each group of signal lines can include four signal lines. In the two adjacent groups of signal lines corresponding to the first driving circuit group and the second driving circuit group along the column direction Y, the four signal lines of one group of signal lines are all second sub-signal lines 40, and the four signal lines of the other group of signal lines include three first sub-signal lines 30 and one second sub-signal line 40. Specifically, the three first sub-signal lines 30 in one group are respectively electrically connected to the three second sub-signal lines 40 in the other group through the adapter lines 50.

[0080] In the column direction Y, in the two adjacent groups of signal lines corresponding to the third driving circuit group and the fourth driving circuit group, the four signal lines corresponding to the third driving circuit group include two first sub-signal lines 30 and two second sub-signal lines 40, and the four signal lines corresponding to the fourth driving circuit group include one first sub-signal line 30 and three second sub-signal lines 40. The two first sub-signal lines 30 corresponding to the third driving circuit group are electrically connected to the two second sub-signal lines 40 corresponding to the fourth driving circuit group through the adapter lines 50 respectively. The one first sub-signal line 30 corresponding to the fourth driving circuit group is electrically connected to the one second sub-signal line 40 corresponding to the third driving circuit group through the adapter line 50.

[0081] In some embodiments, Figure 6 A plan view of the peripheral wiring outside the aperture area K of the display panel corresponding to the array substrate of the present application is schematically shown. Figure 7 A connection state of the signal lines and the pixel driving circuit of the present application is schematically shown. Referring to Figure 6 and Figure 7 As shown in the figure, in the two adjacent groups of all signal lines, at least part of the second sub-signal lines 40 include a first part 401, a second part 402 and a cross bridge 403. The connection end of the first sub-signal line 30 is connected to the first part 401. The multiplexing part 40a of the second sub-signal line 40 includes the second part 402. The first part 401 and the second part 402 are located in different metal layers. The cross bridge 403 electrically connects the first part 401 and the second part 402. By flexibly adjusting the metal layers in which the first part 401 and the second part 402 of the second sub-signal line 40 are located, it is easy to realize that in each second sub-signal line 40, the two adjacent multiplexing parts 40a are arranged in two different metal layers, so as to reduce the interference of signals.

[0082] In some examples, the first part 401 and the second part 402 are located in different metal layers from the cross bridge 403, thereby facilitating to reduce the possibility of mutual interference between the first part 401, the second part 402 and the cross bridge 403.

[0083] In some examples, since the cross bridge 403 is used to electrically connect the first part 401 and the second part 402, the first part 401 can be located in the first metal layer (M1), and the second part 402 can be located in the second metal layer (M2). The cross bridge 403 can be located in the same metal layer as the adapter line 50. For example, the cross bridge 403 and the adapter line 50 can be located in the fourth metal layer (M4).

[0084] In some examples, referring to Figure 6 and Figure 7As shown, each group of signal lines may include four signal lines. Along the column direction Y, the four signal lines corresponding to the fourth drive circuit group include one first sub-signal line 30 and three second sub-signal lines 40. At least one of the three second sub-signal lines 40 may include a first part 401, a second part 402, and a bridge 403.

[0085] In some embodiments, each set of signal lines may include a light emission control line and a scan line. The light emission control line is used to provide a light emission control signal to the corresponding pixel driving circuit 20. The scan line is used to provide a scan signal to the corresponding pixel driving circuit 20. The orthogonal projections of the light emission control line and the scan line do not overlap along the thickness direction of the array substrate.

[0086] See in some examples Figure 6 As shown, in two adjacent groups of signal lines, each group includes one light-emitting control line and three scan lines. Of the four signal lines in each group, the uppermost signal line can be designated as the light-emitting control line. Along the column direction Y, the three scan lines are located on one side of the light-emitting control line. Along the thickness direction of the array substrate, the orthographic projections of the light-emitting control line and the three scan lines do not overlap. However, it is understood that the arrangement of the light-emitting control line and scan lines is not limited to the above-described manner; other arrangements that meet the routing requirements can also be used, and this application does not specifically limit this.

[0087] by Figure 6 Taking the first and second driving circuit groups as examples of adjacent signal lines, in one signal line group, the light emission control line and the three scan lines are both second sub-signal lines 40. In the other signal line group, the light emission control line and the two scan lines are first sub-signal lines 30, and the other scan line is a second sub-signal line 40. In the adjacent signal lines, that is, in the adjacent signal lines corresponding to the first and second driving circuit groups, each second sub-signal line 40 is a continuously extending integral structure.

[0088] by Figure 6Taking the adjacent signal lines corresponding to the third and fourth driving circuit groups as examples, in the signal line group corresponding to the third driving circuit group, the light emission control line and one scan line constitute the first sub-signal line 30, and the two scan lines constitute the second sub-signal line 40. Both scan lines are continuous, integrally structured second sub-signal lines 40. In the signal line group corresponding to the fourth driving circuit group, one scan line constitutes the first sub-signal line 30, the light emission control line and two scan lines constitute the second sub-signal line 40, and the light emission control line includes a first part 401, a second part 402, and a bridge 403, while both scan lines are continuous, integrally structured second sub-signal lines 40. It can be understood that in the above embodiments, the first driving circuit group can be the second driving circuit group, the second driving circuit group can be the first driving circuit group, the third driving circuit group can be the second driving circuit group, and the fourth driving circuit group can be the first driving circuit group. That is, the number of first sub-signal lines 30 and second sub-signal lines 40 included in the first and second driving circuit groups is not limited.

[0089] In some embodiments, each of the four adjacent groups of signal lines includes one light emission control line and three scan lines. The arrangement of each signal line can be as follows: Figure 6 The arrangement shown is as follows: In the two adjacent signal lines at the top, one group of signal lines has its light-emitting control line and three scan lines as second sub-signal lines 40, while the other group has its light-emitting control line and two scan lines as first sub-signal lines 30, and another scan line as a second sub-signal line 40. Each second sub-signal line 40 is a continuously extending, integral structure. In the two adjacent signal lines at the bottom, one group of signal lines has its light-emitting control line and one scan line as first sub-signal lines 30, and two scan lines as second sub-signal lines 40. The two scan lines are continuously extending, integrally structured second sub-signal lines 40. In the other group of signal lines, one scan line is the first sub-signal line 30, the light-emitting control line and two scan lines are second sub-signal lines 40, and the light-emitting control line includes a first part 401, a second part 402, and a bridge 403, while the two scan lines are continuously extending, integrally structured second sub-signal lines 40.

[0090] In one specific embodiment, see Figure 6As shown, in the adjacent four groups of driving circuit groups, that is, in the adjacent four groups of signal lines, each group of signal lines includes one light-emitting control line and three scan lines, and each signal line in each group of signal lines is the light-emitting control line, the third scan line, the second scan line and the first scan line in turn along the column direction Y. Specifically, in the group of signal lines corresponding to the first driving circuit group, the light-emitting control line, the third scan line, the second scan line and the first scan line are all the second sub-signal lines 40, and each second sub-signal line 40 is a continuous and integral structure. In the group of signal lines corresponding to the second driving circuit group, the light-emitting control line, the third scan line and the first scan line are the first sub-signal lines 30, and the second scan line is the second sub-signal line 40, and the second scan line is a continuous and integral structure. It can be understood that the light-emitting control line, the third scan line and the first scan line corresponding to the second driving circuit group are electrically connected to the light-emitting control line, the third scan line and the first scan line corresponding to the first driving circuit group through the adapter lines 50. In the group of signal lines corresponding to the third driving circuit group, the light-emitting control line and the first scan line are the first sub-signal lines 30, and the second scan line and the third scan line are the second sub-signal lines 40. The second scan line and the third scan line are the second sub-signal lines 40 which are continuous and integral structures. It can be understood that the light-emitting control line and the first scan line corresponding to the third driving circuit group are electrically connected to the light-emitting control line and the first scan line corresponding to the fourth driving circuit group through the adapter lines 50. In the group of signal lines corresponding to the fourth driving circuit group, the third scan line is the first sub-signal line 30, the light-emitting control line, the first scan line and the second scan line are the second sub-signal lines 40, and the light-emitting control line includes the first part 401, the second part 402 and the cross bridge 403, and the first scan line and the second scan line are the second sub-signal lines 40 which are continuous and integral structures. It can be understood that the third scan line corresponding to the fourth driving circuit group is electrically connected to the third scan line corresponding to the third driving circuit group through the adapter line 50. In this embodiment, in all the second sub-signal lines 40, along the column direction Y, the light-emitting control line, the third scan line, the second scan line and the first scan line corresponding to the first driving circuit group are located in the first metal layer (M1), the second metal layer (M2), the first metal layer (M1), the second metal layer (M2) respectively; the second scan line corresponding to the second driving circuit group is located in the first metal layer (M1); the third scan line and the second scan line corresponding to the third driving circuit group are located in the second metal layer (M2) and the first metal layer (M1) respectively; the second part 402 of the light-emitting control line, the second scan line and the first scan line corresponding to the fourth driving circuit group are located in the second metal layer (M2), the first metal layer (M1) and the second metal layer (M2) respectively. That is, in the adjacent four groups of driving circuit groups, there are 10 second sub-signal lines 40, and adjacent two second sub-signal lines 40 are located in different metal layers, and all the second sub-signal lines 40 are alternately arranged in the first metal layer (M1) and the second metal layer (M2) along the column direction Y.The number of signal line wirings of the display panel can be effectively reduced, and the signal line wiring density can be reduced. It can be understood that the four adjacent driving circuit groups (i.e., the first driving circuit group, the second driving circuit group, the third driving circuit group, and the fourth driving circuit group) provided in the embodiment can be one unit, and the array substrate can include a plurality of the units; or the first driving circuit group and the second driving circuit group provided in the embodiment constitute one unit, and the array substrate can include a plurality of the units; or the third driving circuit group and the fourth driving circuit group provided in the embodiment constitute one unit, and the array substrate can include a plurality of the units, which can be specifically set according to actual conditions, and is not limited herein. Through the setting mode, the number of signal line wirings of the display panel can be effectively reduced, the signal line wiring density can be reduced, and the display effect is improved.

[0091] It should be noted that the above embodiment is described by taking that each group of signal lines can include one signal line, two signal lines, three signal lines, or four signal lines as an example, but it can be understood that the number of signal lines included in each group of signal lines can be other numbers meeting design requirements, and the present application does not make specific limitation thereto.

[0092] In another aspect, the present application provides a display panel, Figure 8 The structure of the display panel of an embodiment of the present application is schematically shown. Figure 9 For Figure 8 The enlarged view of R in the middle. Referring to Figure 8 and Figure 9 As shown in the figure, in the embodiment of the present application, the display panel 10 has a backlight surface and a light emitting surface. The light emitting surface of the display panel 10 is used to emit light rays to display image information. The display panel 10 includes a display area AA, a non-display area NA, and an aperture area K. The display panel 10 can form image information by light rays emitted by pixels arranged in the display area AA. The aperture area K and the non-display area NA can be areas without display function. The aperture area K can be correspondingly provided with a light sensing element (not shown in the figure), for example, the light sensing element can be but is not limited to a camera module or a light sensor.

[0093] It can be understood that the aperture area K of the display panel 10 and the aperture area K of the array substrate are the same area; the non-display area NA of the display panel 10 and the non-display area NA of the array substrate are the same area; that is, in the thickness direction of the display panel 10, the orthographic projection of the aperture area K of the display panel 10 coincides with the orthographic projection of the aperture area K of the array substrate, and the orthographic projection of the non-display area NA of the display panel 10 coincides with the orthographic projection of the non-display area NA of the array substrate.

[0094] The position of the aperture region K can be located in the middle of the top of the display panel 10, or can be located near the edge of the top of the display panel 10, which is not limited in the present application. Since the region where the aperture region K of the display panel 10 is arranged does not arrange pixels and corresponding signal lines, the signal lines used to connect the pixels on both sides of the aperture region K need to bypass the aperture region K. The signal lines are concentratedly arranged near the aperture region K, so it is necessary to arrange a non-display region NA outside the aperture region K. The non-display region NA can form a black border to hide these signal lines.

[0095] Figure 2 The plan view of the array substrate of the display panel of the present application is schematically shown. Referring to Figure 2 As shown, the display region AA of the display panel 10 is provided with a plurality of drive circuit groups. Each drive circuit group includes a plurality of pixel drive circuits 20. Each pixel drive circuit 20 can drive a light emitting unit in the display panel 10, that is, each pixel drive circuit 20 can emit light, such as red light, green light or blue light, through the light emitting unit. The non-display region NA is arranged between the aperture region K and the display region AA. The non-display region NA can not arrange the light emitting unit.

[0096] For ease of description, as Figures 2 to 6 As shown, the display region AA is provided with four drive circuit groups corresponding to the aperture region K. It can be understood that the display region AA can be provided with other number of drive circuit groups corresponding to the aperture region K, which is not limited in the present application. In the first direction, the number of pixel drive circuits 20 included in each drive circuit group is also not limited in the present application.

[0097] It can be understood that the display panel can be an LTPO display panel.

[0098] The display panel in the present application can include the array substrate of any of the above embodiments.

[0099] Specifically, in the embodiment that the display panel 10 includes the aperture region K, the shared multiplexing part 40a on the second sub-signal line 40 can be located in the non-display region NA outside the aperture region K, so as to effectively reduce the number and density of the wires in the non-display region NA, thereby facilitating the reduction of the area of the non-display region NA, and accordingly the area of the display region AA can be increased, which in turn can be beneficial to improve the display effect of the display panel 10.

[0100] It is known that various embodiments of the present application take the non-display area NA between the opening area K and the display area AA as an example, in which the multiplexing unit 40a shared by the second sub-signal lines 40 is located. It can be understood that the multiplexing unit 40a shared by the second sub-signal lines 40 can also be located in the display area AA, that is, the transfer line 50, each driving circuit group and each group of signal lines are located in the display area AA. By this arrangement, the number of signal line traces of the display panel can be effectively reduced, and the signal line trace density can be reduced.

[0101] In some embodiments, referring to Figure 2 It is shown that the first sub-signal lines 30 are disconnected in the opening area K, and the connection end is located in the non-display area NA. The multiplexing unit 40a of the second sub-signal lines 40 is located in the non-display area NA and bypasses the opening area K. The multiplexing unit 40a of the second sub-signal lines 40 can be located on one side of the opening area K, for example, Figure 2 It is shown in the above-mentioned, on the upper side or the lower side in the column direction Y.

[0102] In some embodiments, as Figure 9 It is shown that the boundary of the opening area K can be circular. The shape of the transfer line 50 can match the boundary of the opening area K, for example, the shape of the transfer line 50 can be arc-shaped. The shape of the multiplexing unit 40a of the second sub-signal lines 40 can match the boundary of the opening area K, for example, the shape of the multiplexing unit 40a can be arc-shaped.

[0103] Another aspect of the present application provides a display device including the display panel 10 of the above-mentioned embodiments. The display device of the present application can be a mobile phone, a computer, a tablet computer, a display or a smart wearable device, etc. electronic equipment with display function.

[0104] In the description of the present application, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between each embodiment can be referred to each other.

[0105] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0106] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized by, The array substrate comprises a plurality of driving circuit groups arranged side by side in a second direction; each driving circuit group comprises a plurality of pixel driving circuits arranged in a first direction, and each driving circuit group shares a group of signal lines for providing signals to the pixel driving circuits; The driving circuit groups comprise a first driving circuit group and a second driving circuit group arranged adjacently in the second direction, the first driving circuit group comprises first sub-signal lines which are discontinuous in the same film layer, and the second driving circuit group comprises second sub-signal lines which transmit the same signals as the first sub-signal lines, the second sub-signal lines are continuous in the first direction and share transmission with the first sub-signal lines; The first sub-signal lines and the second sub-signal lines are electrically connected through a switching line; The first sub-signal lines comprise connection ends, and the second sub-signal lines comprise multiplexing parts, in adjacent two groups of the signal lines, the connection end of one of the first sub-signal lines and the multiplexing part of the second sub-signal line for transmitting the same signal in the other group are electrically connected through the switching line.

2. The array substrate of claim 1, wherein, The first direction is a row direction, and the second direction is a column direction.

3. The array substrate of claim 1, wherein The number of the second sub-signal lines is two or more, and the multiplexing parts of adjacent two second sub-signal lines are arranged in different metal layers.

4. The array substrate of claim 1, wherein The array substrate comprises a substrate, a first metal layer, and a second metal layer on the substrate, and an insulating layer is arranged between the first metal layer and the second metal layer, and the multiplexing parts of adjacent two second sub-signal lines are arranged in the first metal layer and the second metal layer in sequence.

5. The array substrate of claim 1, wherein The array substrate comprises a substrate, a first metal layer, a second metal layer, and a third metal layer on the substrate, and the number of the second sub-signal lines is three or more, and the multiplexing parts of adjacent three second sub-signal lines are arranged in the first metal layer, the second metal layer, and the third metal layer in sequence.

6. The array substrate of claim 1, wherein In adjacent two groups of signal lines, the number of all the second sub-signal lines is two or more.

7. The array substrate of claim 1, wherein The pixel driving circuit is a 7T1C circuit.

8. The array substrate of claim 1, wherein In adjacent two groups of the signal lines, each second sub-signal line is a one-piece structure continuously extending.

9. The array substrate of claim 1, wherein In adjacent two groups of the signal lines, each group of the signal lines comprises one light-emitting control line and three scan lines, in one group of the signal lines, the light-emitting control line and the three scan lines are the second sub-signal lines; in the other group of the signal lines, the light-emitting control line and two of the scan lines are the first sub-signal lines, and the other scan line is the second sub-signal line.

10. The array substrate of claim 1, wherein In the two adjacent groups of the signal lines, at least part of the second sub-signal lines comprise a first part, a second part and a bridge, the connection end is connected to the first part, the multiplexing part comprises the second part, the first part and the second part are located in different metal layers, and the bridge electrically connects the first part and the second part.

11. The array substrate of claim 10, wherein, the first part and the second part are located in different metal layers.

12. The array substrate of claim 10, wherein, in the two adjacent groups of the signal lines, each of the second sub-signal lines in one group is a continuous and integral structure, and at least part of the second sub-signal lines in the other group comprise the first part, the second part and the bridge.

13. The array substrate of claim 10, wherein, in the two adjacent groups of the signal lines, each of the signal lines comprises one light-emitting control line and three scan lines, in one of the groups of the signal lines, the light-emitting control line and one of the scan lines are the first sub-signal lines, and the other two scan lines are the second sub-signal lines, in the other group of the signal lines, one of the scan lines is the first sub-signal line, and the light-emitting control line and the other two scan lines are the second sub-signal lines, and the light-emitting control line comprises the first part, the second part and the bridge.

14. The array substrate of claim 10, wherein, the signal lines and the transfer lines are located in different metal layers.

15. The array substrate of claim 10, wherein, the array substrate comprises a fourth metal layer, and the transfer lines are arranged on the fourth metal layer.

16. A display panel, characterized by The array substrate comprises any one of the array substrates of claims 1-15.

17. The display panel of claim 16, wherein, The display panel comprises a display area, an aperture area and a non-display area, the non-display area is located between the aperture area and the display area, the first sub-signal line is disconnected in the aperture area, the connection end is located in the non-display area, the second sub-signal line is arranged around the aperture area, and the multiplexing part is located in the non-display area and arranged around the aperture area.

18. The display panel of claim 16, wherein, the display panel is an LTPO display panel.

19. A display device comprising: The display panel comprises any one of the display panels of claims 16-18.

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