Thin film transistor and preparation method thereof, display panel

Abstract

The application provides a thin film transistor and a preparation method thereof and a display panel, and comprises the following steps: providing a substrate, forming an insulating layer on the surface of the substrate, and forming a semiconductor structure by combining the substrate and the insulating layer; and forming a channel layer on the surface of the semiconductor structure under a preset condition, wherein the material of the channel layer comprises microcrystalline silicon, and the preset condition comprises a preset temperature range. The technical scheme of the application can ensure that the channel layer has better electron mobility, and the preparation process does not cause damage to the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the display field, and particularly to a thin film transistor, a preparation method thereof and a display panel. BACKGROUND

[0002] At present, thin film transistors (TFT) are widely used as switching devices or driving devices in display panels. The thin film transistor includes a channel layer for turning on a circuit. In the prior art, the channel layer is generally prepared by annealing an amorphous semiconductor layer at a high temperature. The amorphous semiconductor layer is formed into a polycrystalline semiconductor layer at a high temperature, so as to increase the atomic order degree and thus improve the electron mobility. The improvement of the electron mobility of the channel layer is particularly important for improving the response speed of the driving device. However, the high-temperature processing process can damage the substrate carrying the channel layer, thereby affecting the working stability of the thin film transistor. How to improve the electron mobility without affecting the structural integrity of the substrate is a subject for continuous exploration in the industry. SUMMARY

[0003] Embodiments of the present application provide a thin film transistor, a preparation method thereof and a display panel. The preparation method of the present application can ensure a better electron mobility of the channel layer while not damaging the substrate during the preparation process.

[0004] In a first aspect, the present application provides a preparation method of a thin film transistor, comprising:

[0005] providing a substrate, forming an insulating layer on the surface of the substrate, and the substrate and the insulating layer constituting a semiconductor structure; and

[0006] forming a channel layer on the surface of the semiconductor structure under a preset condition, the material of the channel layer including microcrystalline silicon, and the preset condition including a preset temperature range.

[0007] It can be understood that, in the process of depositing the channel layer, the microcrystalline silicon is directly formed at a lower temperature. The channel layer of the microcrystalline silicon has better structural order, and the good structural order makes the microcrystalline silicon have higher electron mobility. Moreover, the structure of the substrate is not affected by the temperature when the channel layer is crystallized to form microcrystalline, so that the substrate can maintain an intact structure.

[0008] In a possible implementation, the forming of the channel layer on the surface of the semiconductor structure under the preset condition includes:

[0009] forming a first channel layer on the surface of the substrate under the preset temperature range and a first atmosphere;

[0010] performing a second atmosphere treatment on the first channel layer; and

[0011] forming a second channel layer on a surface of the first channel layer, the first channel layer and the second channel layer together constituting a channel layer.

[0012] In a possible implementation, the first atmosphere includes a first gas and a second gas, the first gas is a reducing gas, and the second gas includes a silicon-containing compound, and a ratio of gas flow rates of the first gas and the second gas is between 30 and 180.

[0013] In a possible implementation, the preset temperature range is 200-400 ℃.

[0014] In a possible implementation, the microcrystalline silicon has an electron mobility of 2 cm 2 Vs-5 cm 2 Vs.

[0015] In a possible implementation, after the substrate is provided, and before the insulating layer is formed on the surface of the substrate, the substrate and the insulating layer constituting a semiconductor structure, the method further includes:

[0016] forming a gate on the surface of the substrate.

[0017] In a possible implementation, the forming a channel layer on a surface of the semiconductor structure under a preset condition further includes:

[0018] forming a source and a drain on the channel layer, and electrically connecting the source and the drain to the channel layer.

[0019] In a possible implementation, after the forming a source and a drain on the channel layer, and electrically connecting the source and the drain to the channel layer, the method further includes:

[0020] forming a protective layer on a side of the source and the drain away from the channel layer.

[0021] In a second aspect, the present application also provides a thin film transistor, which is prepared by using the method described above.

[0022] In a third aspect, the present application also provides a display panel, which includes a light-emitting component and the thin film transistor described above, and the light-emitting component is electrically connected to the thin film transistor. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

[0024] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0025] Figure 2 is Figure 1 is a sectional schematic diagram of a display assembly of a display panel provided by the present application;

[0026] Figure 3 is a thin film transistor of a double-gate structure provided by an embodiment of the present application;

[0027] Figure 4 is a sectional schematic diagram of a thin film transistor with a first channel layer and a second channel layer provided by an embodiment of the present application;

[0028] Figure 5 is a thin film transistor of a bottom-gate structure provided by an embodiment of the present application;

[0029] Figure 6 is a thin film transistor of a top-gate structure provided by an embodiment of the present application;

[0030] Figure 7 is a sectional schematic diagram of a display assembly using a thin film transistor of a bottom-gate structure;

[0031] Figure 8 is a flowchart of a preparation method of a thin film transistor provided by an embodiment of the present application;

[0032] Figure 9 is a sectional schematic diagram of an assembly formed after S100 in the preparation method of the thin film transistor;

[0033] Figure 10 is a sectional schematic diagram of an assembly formed after S200 in the preparation method of the thin film transistor;

[0034] Figure 11 is a flowchart of another preparation method of a thin film transistor provided by an embodiment of the present application;

[0035] Figure 12 is a sectional schematic diagram of an assembly formed after S300 in the preparation method of the thin film transistor;

[0036] Figure 13 is a sectional schematic diagram of an assembly formed after S400 in the preparation method of the thin film transistor;

[0037] Figure 14 This is a schematic cross-sectional view of the component formed after S500 in the fabrication method of thin-film transistors;

[0038] Figure 15 This is a schematic cross-sectional view of the component formed after S600 in the fabrication method of thin-film transistors;

[0039] Figure 16 This is a schematic cross-sectional view of the component formed after S700 in the fabrication method of thin-film transistors;

[0040] Figure 17 This is a schematic flowchart of a method for preparing a quantum dot-doped mesoporous material provided in an embodiment of this application.

[0041] Reference numerals in the figures: Display panel-1000, Housing-100, Display assembly-200, Substrate-210, Driving assembly-220 and Light-emitting assembly-230, Electrical connection-221, Thin film transistor-222, First gate-2220a, Voltage regulator-2221, Insulating layer-2222, Channel layer-2223, Source-2224, Drain-2225, First protective layer-2226, Second protective layer-2227, Second gate-2 220b, Conductive Layer - 2228, Third Protective Layer - 2229, First Channel Layer - 2223a, Second Channel Layer - 2223b, First Via - 2229a, Second Via - 2229b, Light Emitting Diode - 231, Planarization Layer - 232, Matrix Layer - 233, Color Conversion Layer - 234, First Pin - 2311, Second Pin - 2312, Planarization Via - 2320, Green Conversion Layer - 2341, Red Conversion Layer - 2342 Detailed Implementation

[0042] For ease of understanding, the terminology used in the embodiments of this application will be explained first.

[0043] And / or: This is simply a way of describing the relationship between related objects. It indicates that there can be three kinds of relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0044] Multiple: refers to two or more.

[0045] Connection: should be interpreted broadly. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through an intermediary.

[0046] The specific embodiments of this application will now be clearly described in conjunction with the accompanying drawings.

[0047] Please see Figure 1 , Figure 1This is a schematic diagram of the structure of the display panel 1000 provided in an embodiment of this application. The display panel 1000 may include a housing 100 and a display component 200. The display component 200 is fixedly mounted on the housing 100.

[0048] Please see Figure 2 , Figure 2 yes Figure 1 A cross-sectional view of the display component 200 of the provided display panel 1000. The display component 200 may include a substrate 210, a driving component 220, and a light-emitting component 230.

[0049] It should be noted that, Figure 2 The purpose of this illustration is solely to depict the connection relationship between the substrate 210, the driving component 220, and the light-emitting component 230, and is not to specifically limit the connection positions, specific structures, or quantities of each device. Furthermore, the structures illustrated in the embodiments of this application do not constitute a specific limitation on the display component 200. In other embodiments of this application, the display component 200 may include more or fewer components than illustrated, or combine certain components, or split certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0050] For example, substrate 210 can be a glass substrate, a sapphire substrate, or a silicon wafer substrate. Alternatively, substrate 210 can be a flexible substrate, which can be made of any one or more of the following materials: polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), cycloolefin polymer (COP), polycarbonate (PC), polystyrene (PS), polypropylene (PP), and polytetrafluoroethylene (PTFE). In other implementations, substrate 210 can also be a ceramic substrate, etc., and this application does not limit this choice.

[0051] The driving assembly 220 includes a plurality of electrical connection portions 221 and a plurality of thin-film transistors 222. The electrical connection portions 221 and the thin-film transistors 222 are spaced apart on the same side surface of the substrate, and both the electrical connection portions 221 and the thin-film transistors 222 are electrically connected to the light-emitting assembly 230. The structure of a thin-film transistor 222 will be described below.

[0052] The thin film transistor 222 provided in the present application can be a thin film transistor 222 of a double-gate structure, a thin film transistor 222 of a bottom-gate structure, or a thin film transistor 222 of a top-gate structure. The thin film transistors 222 of different structures will be described in detail as follows.

[0053] In a first possible embodiment, referring to Figure 3 , Figure 3 is a thin film transistor 222 of a double-gate structure provided in an embodiment of the present application. The thin film transistor 222 of the double-gate structure comprises a first gate 2220a, a voltage stabilizing device 2221, an insulating layer 2222, a channel layer 2223, a source 2224, a drain 2225, a first protective layer 2226, a second protective layer 2227, a second gate 2220b, a conductive layer 2228, and a third protective layer 2229.

[0054] The first gate 2220a and the voltage stabilizing device 2221 are arranged on the surface of the substrate 210, and the first gate 2220a is spaced apart from the voltage stabilizing device 2221. The insulating layer 2222 is arranged on the substrate 210, and the insulating layer 2222 covers the first gate 2220a and the voltage stabilizing device 2221. The substrate 210, the first gate 2220a, and the insulating layer 2222 constitute a semiconductor structure. The channel layer 2223 is arranged on the surface of the insulating layer 2222, and the channel layer 2223 is arranged opposite to the first gate 2220a. The material of the channel layer 2223 comprises microcrystalline silicon. The channel layer 2223 provided in the present application has a higher electron mobility when the material is microcrystalline silicon, which can improve the corresponding speed of the display assembly 200 during operation, so that the display assembly 200 can quickly adjust the light.

[0055] Referring to Figure 4 , Figure 4 is a cross-sectional schematic view of a thin film transistor 222 provided in an embodiment of the present application, which has a first channel layer 2223a and a second channel layer 2223b. The channel layer 2223 provided in the present application can have a multi-layer structure. The channel layer 2223 can comprise the first channel layer 2223a and the second channel layer 2223b, which are arranged in a stacked manner, and the surface of the first channel layer 2223a away from the second channel layer 2223b is connected to the insulating layer 2222. The material of the first channel layer 2223a and the material of the second channel layer 2223b are both microcrystalline silicon. The channel layer 2223 can also have three or more sub-channel layers.

[0056] It can be understood that the channel layer 2223 arranged in a multi-layer structure can be crystallized in layers in sequence during the crystallization process, so that the crystallinity is more uniform, and the electron mobility of the channel layer 2223 is higher, thereby improving the response speed of the thin film transistor 222.

[0057] Please refer to Figure 3 The source electrode 2224 and the drain electrode 2225 are both connected to the channel layer 2223 away from the surface of the insulating layer 2222, and the source electrode 2224 and the drain electrode 2225 are arranged in a spaced manner. The source electrode 2224 and the drain electrode 2225 cover part of the surface of the insulating layer 2222. The insulating layer 2222 is provided with a metal via hole penetrating through the insulating layer 2222, and the source electrode 2224 is electrically connected to the voltage stabilizing device 2221 through the metal via hole.

[0058] The first protective layer 2226 is arranged on the surface of the insulating layer 2222 away from the substrate 210, and the first protective layer 2226 covers the source electrode 2224, the channel layer 2223 and the drain electrode 2225.

[0059] It can be understood that the first protective layer 2226 can make the surface of the driving assembly 220 more flat, so as to prevent the driving assembly 220 from causing stress concentration and causing the structure to be damaged when subjected to external force. The arrangement of the first protective layer 2226 can also improve the strength of the structure of the driving assembly 220, so that the structure of the driving assembly 220 is more stable.

[0060] The second protective layer 2227 is arranged on the surface of the first protective layer 2226 away from the insulating layer 2222. It can be understood that the second protective layer 2227 can further strengthen the structural strength of the driving assembly 220, and fill the recesses of the first protective layer 2226, so as to flatten the surface of the driving assembly 220.

[0061] The second gate is arranged on the surface of the second protective layer 2227 away from the first protective layer 2226, and the second gate is arranged opposite to the channel layer 2223.

[0062] The conductive layer 2228 is arranged on the surface of the second protective layer 2227, and penetrates through the second protective layer 2227 and the first protective layer 2226, so as to be electrically connected to the drain electrode 2225.

[0063] The third protective layer 2229 is arranged on the surface of the second protective layer 2227 away from the first protective layer 2226, and the third protective layer 2229 covers the second gate. The third protective layer 2229 is also provided with a first through hole 2229a and a second through hole 2229b. The first through hole 2229a is used to expose the conductive layer 2228, so that the conductive layer 2228 can be used to connect with the light emitting assembly 230. The second through hole 2229b is used to expose the electrical connection part 221, so that the electrical connection part 221 can be used to connect with the light emitting assembly 230.

[0064] It can be understood that the third protective layer 2229 can encapsulate the source electrode 2224, the gate and the drain electrode 2225, so that the structure of the driving assembly 220 is more stable.

[0065] In the second possible embodiment, please refer toFigure 5 , Figure 5 This is the bottom-gate structure thin-film transistor 222 provided in the embodiments of this application. The contents that are the same as those of the dual-gate structure thin-film transistor 222 will not be described again. The difference between the dual-gate structure thin-film transistor 222 and the bottom-gate structure thin-film transistor 222 does not include the second gate 2220b.

[0066] Specifically, the bottom-gate thin-film transistor 222 includes a gate 2220, a voltage regulator 2221, an insulating layer 2222, a channel layer 2223, a source 2224, a drain 2225, a first protective layer 2226, a second protective layer 2227, and a third protective layer 2229. The third protective layer 2229 of the bottom-gate thin-film transistor 222 is directly disposed on the surface of the second protective layer 2227 to enhance the structural strength of the driving component 220.

[0067] In the third possible embodiment, please refer to Figure 6 , Figure 6 This is the thin-film transistor 222 with a top-gate structure provided in an embodiment of this application. Wherein, Figure 6 The gate position of the thin-film transistor 222 with a top-middle gate structure is... Figure 3 The gate positions of the dual-gate thin-film transistor 222 are different. The following will describe the structural differences between the top-gate thin-film transistor 222 and the dual-gate thin-film transistor 222 caused by the change in gate position.

[0068] The top-gate thin-film transistor 222 includes a light-shielding layer 222a, a protective layer 222b, a source 2224, a drain 2225, a channel layer 2223, an insulating layer 2222, and a gate 2220. The light-shielding layer 222a is disposed on a portion of the surface of the substrate 210. The protective layer 222b is disposed on the surface of the substrate 210 and covers the light-shielding layer 222a. The source 2224 and drain 2225 are disposed on the surface of the protective layer 222b away from the substrate 210, and are spaced apart. The channel layer 2223 is disposed on the surface of the protective layer 222b away from the substrate 210, covering the surface of the protective layer 222b between the source 2224 and drain 2225, and also covers a portion of the source 2224 and a portion of the drain 2225. The channel layer 2223 is made of microcrystalline silicon. An insulating layer 2222 is disposed on the surface of the channel layer 2223 away from the protective layer 222b, and the insulating layer 2222 covers part of the source 2224 and part of the drain 2225. A gate 2220 is disposed on the surface of the insulating layer 2222 away from the channel layer 2223.

[0069] It should be noted that the structures of the above-described dual-gate thin-film transistor 222, bottom-gate thin-film transistor 222, and top-gate thin-film transistor 222 are only illustrative. This application may also include other existing structures of dual-gate thin-film transistor 222, bottom-gate thin-film transistor 222, and top-gate thin-film transistor 222.

[0070] Please refer to the following: Figure 2 The light-emitting component 230 includes multiple light-emitting diodes 231, a planarization layer 232, a matrix layer 233, and a color conversion layer 234. The light-emitting diodes 231 can be electrically connected to the aforementioned dual-gate thin-film transistors 222, bottom-gate thin-film transistors 222, or top-gate thin-film transistors 222. Specifically, the light-emitting diode 231 includes a first pin 2311 and a second pin 2312. The first pin 2311 is electrically connected to the drain 2225 of the thin-film transistor 222, and the second pin 2312 is connected to the electrical connection portion 221. The light-emitting diodes 231 are connected to the driving component 220 through the first pin 2311 and the second pin 2312, thereby emitting light under the control of the driving component 220.

[0071] In this embodiment, the light-emitting diode 231 is described as a micro light-emitting diode (Micro LED). However, it is understood that in other embodiments, the light-emitting diode 231 can also be other light-emitting devices, such as a mini light-emitting diode (Mini LED) or an organic light-emitting diode (OLED). This application does not limit this.

[0072] A planarization layer 232 is disposed on the surface of the drive assembly 220 away from the substrate 210. For details, please refer to [reference needed]. Figure 2 and Figure 7 , Figure 7FIG. 2 is a cross-sectional view of a display assembly 200 using a bottom-gate thin-film transistor 222. When the thin-film transistor 222 is a dual-gate structure or a bottom-gate structure, a planar layer 232 can be disposed on a surface of the third protective layer 2229 away from the second protective layer 2227. When the thin-film transistor 222 is a top-gate structure, the planar layer 232 can be disposed on a side of the gate insulating layer 2222 away from the channel layer 2223, and covers the gate electrode 2220. The planar layer 232 is provided with a plurality of planar layer through holes 2320, and the light-emitting diodes 231 are connected to the planar layer through holes 2320. The planar layer 232 can fill the gaps between the plurality of light-emitting diodes 231, thereby fixing the positions of the light-emitting diodes 231 and improving the structural strength of the light-emitting assembly 230. The planar layer 232 can also have a heat dissipation function, so that each light-emitting diode 231 can better dissipate heat without affecting each other, so that each light-emitting diode 231 can better independently emit light.

[0073] A matrix layer 233 is disposed on a surface of the planar layer 232 away from the driving assembly 220. The matrix layer 233 is provided with an array of matrix through holes 2330, which can provide mounting positions for the color conversion layer 234. For example, the matrix layer 233 can be black, so as to block the light emitted by the light-emitting diodes 231 from being emitted only from the positions of the matrix through holes 2330 of the matrix layer 233, preventing the light-emitting diodes 231 from affecting the color or brightness displayed by the display assembly 200 due to light leakage.

[0074] A color conversion layer 234 is disposed on a surface of the light-emitting diode 231 away from the thin-film transistor 222. The color conversion layer 234 can include a green conversion layer 2341 and a red conversion layer 2342. The green conversion layer 2341 and the red conversion layer 2342 are respectively disposed on adjacent through holes of the matrix layer 233. The light-emitting diode 231 without the color conversion layer 234 can emit a first color light, and the first color light is emitted from the matrix through hole 2330 of the matrix layer 233. The first color light is blue light. The light-emitting diode 231 provided with the green conversion layer 2341 can emit a second color light, and the second color light is green light. The light-emitting diode 231 provided with the red conversion layer 2342 can emit a third color light, and the third color light is red light. Adjacent one red light-emitting diode 231, one green light-emitting diode 231 and one blue light-emitting diode 231 can form a light-emitting unit capable of emitting white light, and therefore a plurality of light-emitting diodes 231 can form a plurality of light-emitting units, each of which can emit three colors of light (the three colors of light are the first color light, the second color light and the third color light), and the three colors of light can cooperate to form white light. For example, the color conversion layer 234 can include quantum dots.

[0075] The application further provides a preparation method of the thin film transistor 222, which can protect the structure of the substrate 210 and prevent the substrate 210 from being damaged in a high-temperature heat treatment step during the preparation process while preparing the channel layer 2223 with high electron mobility.

[0076] Please refer to Figure 8 , Figure 8 is a flowchart of a preparation method of a thin film transistor 222 provided by the application. The preparation method includes but is not limited to steps S100 and S200, and the detailed description of steps S100 and S200 is as follows.

[0077] S100: providing a substrate 210,

[0078] forming an insulating layer 2222 on the surface of the substrate 210, and forming a semiconductor structure of the substrate 210 and the insulating layer 2222.

[0079] S200: forming a channel layer 2223 on the surface of the semiconductor structure under a preset condition, and the material of the channel layer 2223 includes microcrystalline silicon, and the preset condition includes a preset temperature range.

[0080] The steps will be further described below.

[0081] The above step S100 will be described below in combination with Figure 9 , Figure 9 is a sectional view of an assembly formed after S100 in the preparation method of the thin film transistor 222.

[0082] S100: providing a substrate 210, and forming an insulating layer 2222 on the surface of the substrate 210, and forming a semiconductor structure of the substrate 210 and the insulating layer 2222.

[0083] Specifically, the semiconductor structure includes the following three steps.

[0084] Step one: providing a substrate 210.

[0085] Step two: depositing a first gate 2220a on the surface of the substrate 210, and sequentially performing exposure, development and etching on the first gate 2220a.

[0086] Specifically, first, exposure is performed on the first gate 2220a, and a pattern is formed in the photosensitive material on the surface of the first gate 2220a by the action of a light source. Then, the layer structure of the first gate 2220a is developed to remove the part of the photosensitive material that does not react in the exposure process. Finally, etching is performed on the first gate 2220a to form the required pattern.

[0087] Step three: form an insulating layer 2222 on the surface of the substrate 210, and the insulating layer 2222 covers the first gate 2220a.

[0088] The substrate 210 and the insulating layer 2222 constitute a semiconductor structure.

[0089] The above step S200 will be described below in combination with Figure 10 to describe the above step S200, Figure 10 is a cross-sectional view of the components formed after S200 in the preparation method of the thin film transistor 222.

[0090] S200: depositing a channel layer 2223 on the surface of the semiconductor structure under a preset condition. The material of the channel layer 2223 includes microcrystalline silicon, and the preset condition includes a preset temperature range.

[0091] The electron mobility of the microcrystalline silicon ranges from 2 cm2 / Vs to 5 cm2 / Vs (including the end values 2 cm2 / Vs and 5 cm2 / Vs). The preset temperature range is 200-400°C.

[0092] It should be noted that the channel layer 2223 composed of microcrystalline silicon can include intrinsic microcrystalline silicon film and doped microcrystalline silicon film. The deposition of the channel layer 2223 is specifically: forming an intrinsic microcrystalline silicon film on the surface of the insulating layer 2222 away from the substrate 210, and forming a doped microcrystalline silicon film on the surface of the intrinsic microcrystalline silicon film away from the insulating layer 2222.

[0093] Specifically, forming the channel layer 2223 on the surface of the substrate 210 under the preset condition includes the following four steps:

[0094] Step one: forming a first channel layer on the surface of the substrate 210 under a preset temperature range and a first atmosphere.

[0095] The first atmosphere includes a first gas and a second gas, the first gas is a reducing gas, and the second gas includes a silicon-containing compound. The gas flow ratio of the first gas to the second gas is between 30 and 180.

[0096] For example, the first gas can be hydrogen (H2), and the second gas can be silane (SiH4). The first gas and the second gas can be introduced into the substrate 210 by plasma enhanced chemical vapor deposition (PECVD), so that the first gas and the second gas form the channel layer 2223 on the surface of the insulating layer 2222.

[0097] Step two: treating the first channel layer with a second atmosphere, and the second atmosphere can reduce the first channel layer.

[0098] Specifically, the second atmosphere can include hydrogen, which can treat the unsaturated bond of silicon of the first channel layer, so as to make the structure of silicon atoms more stable.

[0099] Step three: forming a second channel layer 2223b on the surface of the first channel layer 2223a, and the first channel layer 2223a and the second channel layer 2223b together constitute the channel layer 2223.

[0100] Step four: sequentially performing exposure, development and etching on the channel layer 2223.

[0101] Specifically, first, the channel layer 2223 is exposed, and a pattern is formed in the photosensitive material on the surface of the channel layer 2223 by the action of a light source. Then, the layer structure of the channel layer 2223 is developed, and the part of the photosensitive material that does not react in the exposure process is removed. Finally, the channel layer 2223 is etched to form the required pattern.

[0102] It can be understood that the channel layer 2223 made of microcrystalline silicon has good structural order and higher electron mobility, thereby improving the response speed of the display assembly 200. Moreover, the method for preparing the thin film transistor 222 provided in the present application does not affect the structure of the substrate 210 of the display assembly 200 when forming the microcrystalline silicon, and the substrate 210 can maintain the complete structure.

[0103] It should be noted that the present application can only have one channel layer 2223, i.e., the present application can only include the first channel layer. Alternatively, the present application can include three or more channel layers 2223, and the first channel layer and the second channel layer are only examples, and the formation of multiple sub-channel layers by the same method is also within the scope of the present application.

[0104] Please refer to Figure 11 , Figure 11 is a flowchart of another method for preparing a thin film transistor 222 provided in an embodiment of the present application. The same content as the first preparation method is not described again, and the difference from the first preparation method is that, in addition to S100 and S200, the method for preparing the thin film transistor 222 can further include S300, S400, S500, S600 and S700, which are described in detail as follows.

[0105] The step S300 will be described below in combination with Figure 12 . Figure 12 is a cross-sectional view of an assembly formed after S300 in the method for preparing the thin film transistor 222.

[0106] S300: A source 2224 and a drain 2225 are formed on the channel layer 2223, and the source 2224 and the drain 2225 are exposed, developed and etched in sequence to make the source 2224 and the drain 2225 electrically connected to the channel layer 2223.

[0107] Specifically, firstly, the source electrode 2224 and drain electrode 2225 are exposed, and a pattern is formed on the photosensitive material on the surface of the source electrode 2224 and drain electrode 2225 under the influence of a light source. Then, the layer structure of the source electrode 2224 and drain electrode 2225 is developed, removing any unreacted photosensitive material from the exposure process. Finally, the source electrode 2224 and drain electrode 2225 are etched to form the desired pattern.

[0108] The following will be through Figure 13 To describe step S400, Figure 13 This is a schematic cross-sectional view of the component formed after S400 in the fabrication method of thin-film transistor 222.

[0109] S400: A protective layer 222b (also known as the first protective layer 2226 and the second protective layer 2227 mentioned above) is formed on the side of the source 2224 and the drain 2225 away from the channel layer 2223, and the protective layer 222b is exposed, developed and etched in sequence.

[0110] Specifically, the protective layer 222b is first exposed to light, and a pattern is formed on the photosensitive material on the surface of the protective layer 222b under the influence of a light source. Then, the layer structure of the protective layer 222b is developed, removing any unreacted portions of the photosensitive material. Finally, the protective layer 222b is etched to form the desired pattern.

[0111] The following will be through Figure 14 To describe step S500, Figure 14 This is a schematic cross-sectional view of the component formed after S500 in the fabrication method of thin-film transistor 222.

[0112] S500: Form conductive layer 2228, expose, develop and etch conductive layer 2228 to make conductive layer 2228 electrically connected to drain electrode 2225.

[0113] Specifically, the conductive layer 2228 is first exposed to light, and a pattern is formed on the photosensitive material on the surface of the conductive layer 2228 under the influence of a light source. Then, the layer structure of the conductive layer 2228 is developed to remove any unreacted photosensitive material from the exposure process. Finally, the conductive layer 2228 is etched to form the desired pattern.

[0114] The following will be through Figure 15S600 will be described below, Figure 15 is a schematic diagram of a cross section of an assembly formed after S600 in the method of manufacturing the thin film transistor 222.

[0115] S600: Forming a light emitting diode 231, and electrically connecting the light emitting diode 231 with the conductive layer 2228.

[0116] The step S700 will be described below, Figure 16 Figure 16 is a schematic diagram of a cross section of an assembly formed after S700 in the method of manufacturing the thin film transistor 222.

[0117] S700: Forming a color conversion layer 234.

[0118] Exemplarily, please refer to Figure 17 , Figure 17 is a flowchart of a method of manufacturing a quantum dot doped mesoporous material provided by an embodiment of the present application. The color conversion layer 234 can be manufactured by doping quantum dots in a mesoporous material. The method of manufacturing the quantum dots of the color conversion layer 234 at least includes the following steps:

[0119] First, forming a mesoporous material.

[0120] For example, the inorganic perfume Si(OR)4 can be converted into Si(OR)3Si-OH by a sol-gel method, and surfactant micelles can be arranged into a hexagonal matrix by a self-assembly technique, and the micelles of the hexagonal matrix and Si(OR)3Si-OH can be self-assembled by a cooperative assembly technique to form an organic / inorganic hybrid microstructure material, and then the mesoporous material can be formed by drying and calcining. The surfactant can be one of cetyltrimethylammonium bromide (CTAB), polyethylene oxide-polypropylene oxide-polyethylene oxide triblock copolymer (PEO-PPO-PEO, P123), or polyoxyethylene-polyoxypropylene-polyoxyethylene (PEG-PPG-PEG, F127: Poly).

[0121] Second, forming a quantum dot material.

[0122] The quantum dots of the color conversion layer 234 can be blue quantum dots. The material of the blue quantum dots can be gallium nitride (GaN), which can be prepared by reacting trimethyl gallium (Ga(CH3)3) and ammonia (NH3). Silicon germanium (Si x Ge y ) can also be generated by reacting silicon tetrahydride (SiH4), germane (GeH4), and hydrogen (H2), wherein the silicon germanium (Si x Ge y ​) in which X and Y are in different proportions, the size of the quantum dots can be adjusted, thereby adjusting the light-emitting color of the quantum dots (silicon-germanium quantum dots can be blue, red or green). Silicon-germanium (Si x Ge y ) can also be prepared by reacting tetramethylsilane (Si(CH3)4), tetramethylgermanium (Ge(CH3)4) and hydrogen (H2).

[0123] Finally, the quantum dot material is doped into the mesoporous material.

[0124] The mesoporous material of the present application adopts a self-assembly form, the mesoporous material as the main material, and the quantum dots are arranged in the mesoporous material. By arranging the quantum dots in the mesoporous material, the size and uniformity of the arrangement of the quantum dots are adjusted and controlled, and then the light-emitting diodes 231 with different light-emitting colors due to different sizes of the quantum dots are adjusted, so that the uniformity of the light with different light-emitting colors in the active light-emitting display panel 1000 is adjusted, and the display quality and the user's visual experience are improved.

[0125] For example, S200 and S300 can be prepared in the same step. S200 and S300 can be replaced by the following steps:

[0126] A channel layer 2223 is deposited on the surface of the semiconductor structure under a preset condition. A drain 2225 and a source 2224 are formed on the surface of the channel layer 2223, and the drain 2225, the source 2224 and the channel layer 2223 are simultaneously subjected to exposure, development and etching, wherein the exposure, development and etching are sequentially performed.

[0127] Specifically, first, the overall structure of the channel layer 2223, the source 2224 and the drain 2225 is subjected to exposure, and a pattern is formed on the surface of the overall structure of the channel layer 2223, the source 2224 and the drain 2225 by the action of a light source. Then, the overall structure of the channel layer 2223, the source 2224 and the drain 2225 is subjected to development, and the part of the photosensitive material on the surface of the overall structure of the channel layer 2223, the source 2224 and the drain 2225 which does not react in the exposure process is removed. Finally, the overall structure of the channel layer 2223, the source 2224 and the drain 2225 is subjected to etching, so that the channel layer 2223, the source 2224 and the drain 2225 form the required pattern.

[0128] The above describes the embodiments of the present application in detail, and the specific examples are applied to explain the principles and implementation modes of the present application; the above description of the embodiments is only used to help understand the method and core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range can be changed, and the above description of the present application should not be understood as a limitation.

Claims

1. A method for fabricating a thin-film transistor, characterized in that, include: A substrate is provided, and an insulating layer is formed on the surface of the substrate, wherein the substrate and the insulating layer constitute a semiconductor structure; A channel layer is formed on the surface of the semiconductor structure under preset conditions, including forming a first channel layer on the surface of the semiconductor structure under a preset temperature range and a first atmosphere. The material of the first channel layer includes an intrinsic microcrystalline silicon thin film. The first atmosphere includes a first gas and a second gas. The first gas is a reducing gas. The second gas includes a silicon-containing compound. The gas flow rate ratio of the first gas and the second gas is between 30 and 180. The first channel layer is subjected to a second atmosphere treatment, wherein the second atmosphere is a reducing atmosphere; and A second channel layer is formed on the surface of the first channel layer. The material of the second channel layer includes a doped microcrystalline silicon thin film. The first channel layer and the second channel layer together constitute the channel layer.

2. The preparation method according to claim 1, characterized in that, The preset temperature range is 200℃-400℃.

3. The preparation method according to claim 1, characterized in that, The electron mobility of the microcrystalline silicon is 2 cm⁻¹. 2 / Vs-5cm 2 Between / Vs.

4. The preparation method according to claim 1, characterized in that, After providing the substrate, and before forming an insulating layer on the surface of the substrate, wherein the substrate and the insulating layer constitute a semiconductor structure, the method further includes: A gate is formed on the surface of the substrate.

5. The preparation method according to claim 1, characterized in that, After forming the channel layer on the surface of the semiconductor structure under preset conditions, the method further includes: A source and a drain are formed on the channel layer, and the source and the drain are electrically connected to the channel layer.

6. The preparation method according to claim 5, characterized in that, After forming the source and drain on the channel layer and electrically connecting the source and drain to the channel layer, the method further includes: A protective layer is formed on the side of the source and the drain that is away from the channel layer.

7. A thin-film transistor, characterized in that, The thin-film transistor is fabricated using the method described in any one of claims 1-6.

8. A display panel, characterized in that, It includes a light-emitting component and a thin-film transistor as described in claim 7, wherein the light-emitting component is electrically connected to the thin-film transistor.

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