Magnetoresistive random access memory structure

Abstract

A magnetoresistive random access memory structure includes a substrate, a plurality of magnetoresistive random access memory cells on the substrate, wherein the magnetoresistive random access memory cells are located in a memory region, the memory region is adjacent to a logic region, and an ultra low dielectric constant layer covers the magnetoresistive random access memory cells, wherein a surface portion of the ultra low dielectric constant layer is doped with fluorine, and a surface of the ultra low dielectric constant layer at a boundary between the memory region and the logic region has a notch.

Description

Technical Field

[0001] This invention relates to a magnetoresistive random access memory, and more specifically, to a magnetoresistive random access memory structure having a special ultra-low dielectric constant (ULK) layer structure and material ratio distribution. Background Technology

[0002] The magnetoresistance (MR) effect is known to be the change in the resistance of a material as a result of an applied magnetic field. Its physical quantity is defined as the resistance difference under and without a magnetic field, divided by the original resistance, representing the rate of change of resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetoresistive random access memory (MRAM) can be fabricated, which has the advantage of continuously retaining stored data even without power.

[0003] Magnetoresistive random access memory (MRAM) is a new type of memory that has received much attention in recent years. It integrates the advantages of various current memory types, such as access speed comparable to static random access memory (SRAM), non-volatility and low power consumption of flash memory, high density and durability of dynamic random access memory (DRAM), and can be integrated with current semiconductor back-end manufacturing processes. Therefore, it has the potential to become the main memory used in semiconductor chips.

[0004] Magnetoresistive random access memory (MRAM) comprises a memory stack structure disposed between upper and lower interconnect structures, including a magnetic tunneling junction (MTJ). Unlike traditional memory that stores data by storing charge, MRAM operates by applying an external magnetic field to the MTJ to control its magnetization direction, thereby obtaining different tunneling magnetoresistive (TMR) values ​​to store digital data. Summary of the Invention

[0005] This invention proposes a magnetoresistive random access memory structure, characterized in that the surface of its ultra-low dielectric constant layer is doped with fluorine due to the etch-back fabrication process, and the special fabrication process steps result in a concave surface of the ultra-low dielectric constant layer at the boundary between the memory region and the logic region.

[0006] One aspect of the present invention is to provide a magnetoresistive random access memory (RAM) structure, including a substrate, a plurality of magnetoresistive RAM cells located on the substrate, wherein the magnetoresistive RAM cells are located in a memory region adjacent to a logic region, and an ultra-low dielectric constant layer covering the magnetoresistive RAM cells, wherein the surface of the ultra-low dielectric constant layer located at the boundary between the memory region and the logic region has a recess.

[0007] Another aspect of the present invention is to provide a magnetoresistive random access memory (RAM) structure, including a substrate, a plurality of magnetoresistive RAM cells located on the substrate, wherein the magnetoresistive RAM cells are located in a memory region adjacent to a logic region, and an ultra-low dielectric constant layer covering the magnetoresistive RAM cells, wherein the ultra-low dielectric constant layer has a fluorine-doped surface portion, the proportions of silicon, hydrogen, and carbon in the ultra-low dielectric constant layer increase from the surface of the ultra-low dielectric constant layer to their respective levels and then level off, the proportion of oxygen in the ultra-low dielectric constant layer decreases from the surface of the ultra-low dielectric constant layer to a level and then level off, and the proportion of fluorine in the ultra-low dielectric constant layer increases from the surface of the ultra-low dielectric constant layer to a certain depth and then decreases to zero.

[0008] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0009] This specification includes accompanying drawings, which form part of the document, to provide the reader with a further understanding of embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0010] Figures 1 to 5 This is a cross-sectional schematic diagram illustrating the fabrication process of a magnetoresistive random access memory according to Embodiment 1 of the present invention; and

[0011] Figure 6 This is a graph showing the depth of the ultra-low dielectric constant (ULK) layer of a magnetoresistive random access memory according to an embodiment of the present invention, relative to its component ratio.

[0012] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0013] Explanation of main component symbols

[0014] 100 intermetallic dielectric layer

[0015] 100a memory area

[0016] 100b logic area

[0017] 102 Stop Layer

[0018] 104 dielectric layer

[0019] 104a surface

[0020] 106 metal interconnect layer

[0021] 108 guide hole component

[0022] 110 Lower Electrode Layer

[0023] 112 Magnetic Tunneling Stack

[0024] 114 Upper Electrode Layer

[0025] 116 magnetoresistive random access memory cells

[0026] 118 Lining

[0027] 120 atomic layer deposited dielectric layer

[0028] 120a dent

[0029] 120b protrusion

[0030] 122 Ultra-Low Dielectric Coefficient Layer

[0031] 122a Surface Part

[0032] 123 Double Inlay Groove

[0033] 124 Stop Layer

[0034] 126 Intermetallic Dielectric Layer

[0035] 128 Stop Layer

[0036] d1 depth

[0037] M3, M4 metal interconnect layers

[0038] V2, V3 guide hole components Detailed Implementation

[0039] The following detailed description of embodiments of the present invention, illustrated in the accompanying figures, will enable the reader to understand and implement the disclosed invention and to perceive its technical effects. It should be noted that the following description is merely illustrative and is not intended to limit the scope of the invention. Various embodiments and features described in this disclosure can be combined and rearranged in various ways without conflict. Various modifications, counterparts, or improvements to the disclosed content of this invention should be understood by those skilled in the art and are intended to be included within the scope of this invention, without departing from the spirit and scope of this disclosure.

[0040] It should be readily understood that the meanings of "on top of," "above," and "above" in this text should be interpreted in the broadest sense, such that "on top of" not only means "directly on something," but also includes being on something with an intermediate feature or layer between them, and "above" or "above" not only means being on or above something, but also includes the meaning of not having an intermediate feature or layer between them (i.e., being directly on something).

[0041] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used in the specification to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. In addition to the directions depicted in the drawings, these spatial relative terms are intended to cover different orientations or directions of the device in use or operation. The device may be oriented in other ways (e.g., by rotation of 90 degrees or in other directions), and these can also be interpreted accordingly using the spatially related descriptions used in the specification.

[0042] Please refer to Figures 1 to 5 , Figures 1 to 5 This is a cross-sectional schematic diagram of a method for fabricating a magnetoresistive random access memory (MRAM) according to Embodiment 1 of the present invention. Figure 1 As shown, a substrate (not shown) is first provided, such as a substrate made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of materials such as silicon, germanium, silicon-germanium compounds, silicon carbide, and gallium arsenide. A memory region 100a and a logic region 100b are preferably defined on the substrate, which are used to house the memory array and logic circuits (e.g., character lines or peripheral circuits), respectively. It should be noted that the focus of this invention is on the structure and related fabrication process of the magnetoresistive random access memory cells on the magnetoresistive memory region 100a.

[0043] Rereference Figure 1An intermetallic dielectric layer (IMD) 100, a stop layer 102, and a dielectric layer 104 are sequentially formed on a substrate. These layers can be formed using chemical vapor deposition (CVD) or plasma-assisted chemical vapor deposition (PECVD). In this embodiment, the intermetallic dielectric layer 100 may be an intermetallic dielectric layer in a lower interconnect layer (e.g., a second metal layer M2), preferably made of an ultra-low-k (ULK) material, such as porous silicon oxycarbide (SiOC). A metal interconnect layer 106, such as the second metal layer M2, may be formed within the intermetallic dielectric layer 100. The stop layer 102 is preferably made of silicon carbide (SiCN), nitrogen-doped carbide (NDC), or silicon nitride, and can serve as an etch stop layer when fabricating upper contact holes. The dielectric layer 104 is preferably made of tetraethoxysilane (TEOS), but is not limited to this.

[0044] Rereference Figure 1 A plurality of magnetoresistive random access memory (RAM) cells 116 are formed on the dielectric layer 104. Each RAM cell 116 comprises, from bottom to top, a lower electrode layer 110, a magnetic tunneling junction stack 112, and an upper electrode layer 114, and is electrically connected to the metal interconnect layer 106 in the memory region 100a via a via 108 through the lower dielectric layer 104 and the stop layer 102. In this embodiment of the invention, the lower electrode layer 110, the magnetic tunneling junction stack 112, and the upper electrode layer 114 can be formed in-situ in the same cavity using physical vapor deposition (PVD). In this embodiment of the invention, the material of the lower electrode layer 110 preferably comprises a conductive material, such as tantalum nitride (TaN), but is not limited thereto. According to other embodiments of the invention, the lower electrode layer 110 may also comprise tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combinations thereof. The material of the upper electrode layer 114 is preferably titanium nitride (TiN). The materials of the metal interconnect layer 106 and the via 108 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but are not limited to this.

[0045] In this embodiment of the invention, the magnetic tunneling junction stack 112 is a multilayer structure, which may include a seed layer, a pinned layer, a reference layer, a tunneling barrier layer, a free layer, and a metal separator. Generally speaking, the pinned layer can be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The tunneling barrier layer can be made of an insulating material containing oxides, such as aluminum oxide (AlO). X The free layer can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer can be "freely" changed by an external magnetic field. Since the structure of the magnetic tunneling junction stack 112 is not the focus of this invention, the above-mentioned multilayer structures are generally referred to as magnetic tunneling junction stack 112 in the figures.

[0046] In this embodiment of the invention, individual magnetoresistive random access memory (RAM) cells 116 can be defined by patterning the upper electrode layer 114, the magnetic tunneling junction stack 112, and the lower electrode layer 110 using a photolithography and etching process. Specifically, the upper electrode layer 114 can be patterned first using a reactive ion etching (RIE) process in conjunction with a silicon oxide hard mask layer, resulting in fewer sidewall byproducts. Next, the magnetic tunneling junction stack 112 and the lower electrode layer 110 are patterned using an ion beam etching (IBE) process to define the RAM cells 116. This ion beam etching process also removes a portion of the dielectric layer 104. Due to the characteristics of the ion beam etching process, the surface 104a of the remaining dielectric layer 104 after etching is preferably slightly lower than the upper surface of the via 108 and will exhibit an arc or curved shape.

[0047] Rereference Figure 1After the patterning process, a conformal substrate 118 is formed on the surface of the magnetoresistive random access memory cell 116 and the dielectric layer 104. The substrate 118 is preferably made of silicon nitride, but other dielectric materials can be selected depending on the fabrication process requirements, such as silicon oxide, silicon oxynitride, or silicon carbide nitride. The substrate 118 has a uniform thickness and covers the magnetoresistive random access memory cell 116 and the dielectric layer 104 to provide protection and isolation, but exposes the upper electrode layer 114 of the magnetoresistive random access memory cell 116. Subsequently, an atomic-layer deposited dielectric layer 120 is formed on the substrate 118. The material of this dielectric layer may include, but is not limited to, tetraethoxysilane (TEOS), silicon oxide, silicon nitride, or combinations thereof. Compared to existing technologies that directly use ultra-low dielectric constant (ULK) materials to cover the magnetoresistive random access memory (RAM) cells 116, this embodiment uses atomic layer deposition (ALD) to form an additional dielectric layer, which effectively avoids voids between the RAM cells 116 and achieves higher surface coverage. The surface of the atomic layer-deposited dielectric layer 120 surrounding the memory region 100a is curved and recessed to the boundary between the memory region 100a and the logic region 100b, and is flush with the sides of the underlying substrate 118 and dielectric layer 104.

[0048] Rereference Figure 1 In addition to the above structure, an ultra-low dielectric (ULK) layer 122 is also deposited on the entire substrate surface, covering the entire memory region 100a and logic region 100b. The ultra-low dielectric layer 122 can be made of porous silicon carbide (SiCOH), which can be formed by CVD fabrication. It should be noted that the dielectric constants of the atomic layer deposited dielectric layer 120 and the ultra-low dielectric layer 122 are different. In this embodiment of the invention, due to the vias 108 and magnetoresistive random access memory cells 116 provided on the memory region 100a, there will be a considerable height difference between the surfaces of the memory region 100a and the logic region 100b after the formation of the ultra-low dielectric layer 122, which is not conducive to subsequent fabrication processes.

[0049] For this, please refer to Figure 2After the ultra-low dielectric constant layer 122 is formed, a photolithography process is performed to remove a portion of the ultra-low dielectric constant layer 122 located on the memory region 100a (or character line region). This photolithography process may include forming a patterned photoresist (or mask, not shown) on a region outside the memory region 100a, such as the logic region 100b, by photolithography, exposing the ultra-low dielectric constant layer 122 on the memory region 100a. Then, using the photoresist as an etching mask, an anisotropic etching process is performed on the ultra-low dielectric constant layer 122 to remove a certain thickness of the ultra-low dielectric constant layer 122 on the memory region 100a. It should be noted that in this embodiment of the invention, a certain thickness of the ultra-low dielectric constant layer 122 will remain on the atomic layer deposition dielectric layer 120 and the magnetoresistive random access memory cell 116 of the memory region 100a after the etching process. Furthermore, due to this etching process, the ultra-low dielectric constant layer 122 at the junction of memory region 100a and logic region 100b will form a concave feature 120a on the side closer to memory region 100a and a protruding feature 120b on the side closer to memory region 100b. This is because the original ultra-low dielectric constant layer 122 has too large a height difference at the junction.

[0050] In this embodiment of the invention, since there is still a considerable height difference between the protrusion 120b feature and the surface after back etching, further processing is required to eliminate this height difference. Now please refer to... Figure 3 Following the etch-back fabrication process, an organic planarization layer (OPL) 124 is then formed on the ultra-low dielectric layer 122. The purpose of the OPL 124 is to planarize the surface of the ultra-low dielectric layer 122. Its material can be spin-coated carbon, an organic dielectric layer (ODL), an anti-reflective coating (BARC), or a photoresist, etc., and its thickness is approximately [missing information]. It can be formed on the ultra-low dielectric constant layer 122 by spin coating process and fill the recesses 120a thereon.

[0051] Please refer to Figure 4 After forming the organic planarization layer 124, an etch process is then performed to remove the organic planarization layer 124. It should be noted that in this embodiment of the invention, this etch process has the same etch rate for both the organic planarization layer 124 and the underlying ultra-low dielectric constant layer 122. Therefore, while removing the organic planarization layer 124, this etch process also removes a portion of the ultra-low dielectric constant layer 122, resulting in a flat surface after etching. Figure 4As can be seen, the original protrusion 120b feature of the ultra-low dielectric constant layer 122 is removed after the etch-back fabrication process, and a certain thickness of the ultra-low dielectric constant layer 122 remains on the atomic layer deposited dielectric layer 120 and the magnetoresistive random access memory cell 116 of the memory region 100a, and the indentation 120a feature still exists at the boundary between the memory region 100a and the logic region 100b. In other embodiments, the etch-back fabrication process may not completely remove the protrusion 120b feature, but rather reduce its height. After the etch-back fabrication process, an ashing process can be selectively performed to remove the residual organic planarization layer 124 in the indentation 120a.

[0052] After this step, the memory region 100a and the logic region 100b will have substantially the same surface height to provide a flat surface for subsequent fabrication processes. It should be noted that in this embodiment of the invention, the composition of the surface portion of the etched ultra-low dielectric constant layer 122 (the portion above the dotted line in the figure) 122a will be altered by this etch-back fabrication process, such as… Figure 6 As shown. Figure 6 This is a graph showing the relationship between the depth of the ultra-low dielectric constant layer 122 and its compositional proportions. The x-axis represents the vertical depth from the surface of the ultra-low dielectric constant layer 122 inwards, while the y-axis represents the proportions of carbon (C), hydrogen (H), silicon (Si), oxygen (O), and fluorine (F) in the ultra-low dielectric constant layer 122 at that depth. As can be seen from the graph, in this embodiment of the invention, the proportions of carbon, hydrogen, silicon, and oxygen on the surface of the ultra-low dielectric constant layer 122 are approximately the same. Specifically, the proportions of carbon, hydrogen, and silicon increase from the top surface of the ultra-low dielectric constant layer 122 inwards until they reach their respective inherent levels and then plateau, while the proportion of oxygen decreases from the top surface of the ultra-low dielectric constant layer 122 inwards until it reaches its inherent level and then plateaus. Generally, the inherent proportion of carbon in the ultra-low dielectric constant layer 122 is greater than the inherent proportion of hydrogen, which in turn is greater than the inherent proportions of silicon and oxygen. In this embodiment of the invention, a small amount of fluorine is also present in the ultra-low dielectric constant layer 122. The proportion of fluorine increases from the top surface of the ultra-low dielectric constant layer 122 inward until it reaches a peak at depth d1, after which the proportion of fluorine begins to decrease to zero.

[0053] In this embodiment of the invention, the reason why the ultra-low dielectric constant layer 122 exhibits the aforementioned fluorine content ratio curve is due to the aforementioned etch-back fabrication process. This is because the plasma ion bombardment effect during the etch-back fabrication process and the use of hydrocarbon-containing fluorine compounds (CF2) contribute to this process. x H yDue to the etching gas, the proportions of carbon, hydrogen, and silicon, which are already present in the ultra-low dielectric layer 122, gradually increase from the surface to the interior to their inherent levels. Conversely, the proportion of oxygen gradually decreases to its inherent level due to the increase in the proportions of carbon, hydrogen, and silicon. On the other hand, the proportion of fluorine, which was not originally present in the ultra-low dielectric layer 122, increases from the surface to the interior due to plasma ion bombardment, reaching a peak at depth d1. Beyond this depth d1, the influence of the back-etching process gradually decreases, causing the proportion of fluorine to decrease and eventually return to its original 0%.

[0054] Rereference Figure 4 After etch-back planarization, a dual damascene recess 123 is formed in the ultra-low dielectric layer 122, which includes a via and a metal interconnect layer. The dual damascene recess 123 can be formed using a dual damascene fabrication process and connects to the metal interconnect layer 106 in the lower logic region 100b, such as the second metal layer M2. Then, the desired metal material is filled into the dual damascene recess 123, such as a barrier layer including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization process is performed, such as chemical mechanical polishing, to remove the metal material above the surface portion 122a to form a dual damascene structure including a via V2 and the metal interconnect layer M3, with the via V2 electrically connected to the metal interconnect layer 106 in the lower logic region 100b.

[0055] Please refer to Figure 5 After the via V2 and the metal interconnect layer M3 are formed, another stop layer 124 and an intermetallic dielectric layer 126 are sequentially formed on the surface portion 122a and the surface of the metal interconnect layer M3. The material of the stop layer 124 is the same as that of the stop layer 102, and can be silicon carbide (SiCN), nitrogen-doped carbide (NDC), or silicon nitride, etc. The material of the intermetallic dielectric layer 126 is the same as that of the ultra-low dielectric constant layer 122, and can be an ultra-low dielectric constant (ULK) material. After the stop layer 124 and the intermetallic dielectric layer 126 are formed, the above-described dual damascene fabrication process is performed again to form the upper via V3 and the metal interconnect layer M4. The via V3 located above the memory region 100a is electrically connected to the upper electrode layer 114 of the magnetoresistive random access memory cell 116, and the via V3 located above the logic region 100b is electrically connected to the lower metal interconnect layer M3. After the via V3 and the metal interconnect layer M4 are formed, another stop layer 128 can be formed on the surface of the intermetal dielectric layer 126, and the above steps of making the via and the metal interconnect layer can be repeated.

[0056] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A magnetoresistive random access memory structure, characterized in that, include: Base; Multiple magnetoresistive random access memory cells are located on the substrate, wherein the magnetoresistive random access memory cells are located in a memory region adjacent to a logic region. Atomic layer deposition layers are located between and on the outside of these magnetoresistive random access memory cells; as well as An ultra-low dielectric constant layer covers the magnetoresistive random access memory cells and the atomic layer deposition layer, and covers the entire memory region and the entire logic region. The surface of the ultra-low dielectric constant layer located at the boundary between the memory region and the logic region has a recess, and a metal interconnect layer and vias are formed in the ultra-low dielectric constant layer of the logic region.

2. The magnetoresistive random access memory structure according to claim 1, wherein the surface of the ultra-low dielectric layer located at the junction of the memory region and the character line has the indentation.

3. The magnetoresistive random access memory structure according to claim 1, wherein the surface of the ultra-low dielectric layer located outside the indentation further has a protrusion.

4. The magnetoresistive random access memory structure according to claim 1, wherein each magnetoresistive random access memory cell comprises: The lower electrode is located above the substrate; A magnetic tunneling stack is located above the lower electrode layer; and The upper electrode layer is located above the magnetic tunneling stack.

5. The magnetoresistive random access memory structure according to claim 1 further includes a spacer layer located on the sidewall of the magnetoresistive random access memory cells.

6. The magnetoresistive random access memory structure according to claim 1 further comprises a nitrogen-doped carbide layer formed on the surface of the ultra-low dielectric constant layer and filling the indentation.

7. The magnetoresistive random access memory structure according to claim 6 further includes a second via that passes through the nitrogen-doped carbide layer and is electrically connected to the magnetoresistive random access memory cell with respect to the ultra-low dielectric constant layer.

8. A magnetoresistive random access memory structure, comprising: Base; Multiple magnetoresistive random access memory cells are located on the substrate, wherein the magnetoresistive random access memory cells are located in a memory region adjacent to a logic region. Atomic layer deposition layers are located between and on the outside of these magnetoresistive random access memory cells; as well as An ultra-low dielectric constant layer covers the magnetoresistive random access memory cells and the atomic layer deposition layer, and covers the entire memory region and the entire logic region. Metal interconnect layers and vias are formed in the ultra-low dielectric constant layer of the logic region. The ultra-low dielectric constant layer has fluorine-doped surface portions. The proportions of silicon, hydrogen, and carbon in the ultra-low dielectric constant layer increase from the surface to the interior until they reach their respective levels and then plateau. The proportion of oxygen in the ultra-low dielectric constant layer decreases from the surface to the interior until it reaches a certain level and then plateaus. The proportion of fluorine in the ultra-low dielectric constant layer increases from the surface to the interior until it reaches a certain depth and then begins to decrease to zero.

9. The magnetoresistive random access memory structure according to claim 8, wherein the level after the carbon component ratio is balanced is greater than the level after the hydrogen component ratio is balanced, the level after the silicon component ratio is balanced, and the level after the oxygen component ratio is balanced.

10. The magnetoresistive random access memory structure according to claim 8, wherein each magnetoresistive random access memory cell comprises: The lower electrode is located above the substrate; A magnetic tunneling stack is located above the lower electrode layer; and The upper electrode layer is located above the magnetic tunneling stack.

11. The magnetoresistive random access memory structure according to claim 8 further includes a spacer layer located on the sidewall of the magnetoresistive random access memory cells.

12. The magnetoresistive random access memory structure according to claim 8 further comprises a nitrogen-doped carbide layer formed on the surface of the ultra-low dielectric constant layer.

13. The magnetoresistive random access memory structure according to claim 12 further includes a second via that passes through the nitrogen-doped carbide layer and is electrically connected to the magnetoresistive random access memory cell with respect to the ultra-low dielectric constant layer.

Images