Electronic Devices

Abstract

An electronic device includes a semiconductor memory, which includes: a first line, a second line arranged above the first line and spaced apart from the first line; a variable resistance layer arranged between the first line and the second line; a selection element layer arranged between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers arranged above or below the selection element layer or above and below the selection element layer, the one or more electrode layers are adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer includes a second carbon layer containing nitrogen, and the first electrode layer includes a first carbon layer containing a lower concentration of nitrogen or no nitrogen.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0038231 filed on March 24, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This patent document relates to memory circuits or devices and their use in electronic devices or systems. Background Art

[0004] Recently, as electronic devices tend toward miniaturization, low power consumption, high performance, and multifunctionality, etc., semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices are needed in the art, and semiconductor devices have been studied. Such semiconductor devices can store data by switching between different resistance states according to applied voltage or current. Semiconductor devices may include RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), and electric fuses, etc. Summary of the invention

[0005] The technology disclosed in this patent document includes various embodiments of an electronic device capable of improving operating characteristics of a semiconductor memory and preventing process defects.

[0006] In one embodiment, an electronic device includes a semiconductor memory, which includes: a first line; a second line, arranged above the first line and separated from the first line; a variable resistance layer, arranged between the first line and the second line; a selection element layer, arranged between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers, arranged above or below the selection element layer or above and below the selection element layer, and one or more electrode layers are adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer includes a second carbon layer containing nitrogen, the first electrode layer includes a first carbon layer containing nitrogen with a lower concentration than the nitrogen contained in the second carbon layer of the second electrode layer or containing no nitrogen, and the first electrode layer is placed between the second electrode layer and the selection element layer.

[0007] In another embodiment, an electronic device including a semiconductor memory includes: a first line; a second line, arranged above the first line and separated from the first line; a variable resistance layer, arranged between the first line and the second line; a selection element layer, arranged between the first line and the variable resistance layer or between the second line and the variable resistance layer; an electrode layer, arranged below the second line and adjacent to the second line; and a resistance layer, arranged between the second line and the electrode layer, wherein the electrode layer includes a first electrode layer and a second electrode layer, the second electrode layer includes a second carbon layer containing nitrogen, the first electrode layer includes a first carbon layer containing nitrogen with a lower concentration than nitrogen contained in the second carbon layer of the second electrode layer or containing no nitrogen, and the first electrode layer is placed between the second electrode layer and the resistance layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A and Figure 1B A semiconductor memory according to a first embodiment of the present disclosure is shown.

[0009] Figure 2 A semiconductor memory according to a second embodiment of the present disclosure is shown.

[0010] Figure 3 A semiconductor memory according to a third embodiment of the present disclosure is shown.

[0011] Figure 4 A semiconductor memory according to a fourth embodiment of the present disclosure is shown.

[0012] Figure 5 A semiconductor memory according to a fifth embodiment of the present disclosure is shown.

[0013] Figure 6 A semiconductor memory according to a sixth embodiment of the present disclosure is shown.

[0014] Figure 7 A microprocessor including a semiconductor memory based on the disclosed technology is shown.

[0015] Figure 8 A processor including a semiconductor memory based on the disclosed technology is shown.

[0016] Fig. 9 A system including a semiconductor memory based on the disclosed technology is shown.

[0017] Fig.10 A memory system including a semiconductor memory based on the disclosed technology is shown. DETAILED DESCRIPTION

[0018] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0019] The drawings are not necessarily drawn to scale. In some cases, the proportions of at least some structures in the drawings may have been exaggerated to clearly illustrate certain features of the described embodiments. In a specific example of two or more layers in a multilayer structure introduced in the drawings or descriptions, the relative positional relationship of these layers or the order in which the layers are arranged as shown reflects the specific implementation of the described or illustrated example, and different relative positional relationships or the order in which the layers are arranged are possible. In addition, the example of the multilayer structure described or illustrated may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the multilayer structure described or illustrated is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0020] Figure 1A and Figure 1B A semiconductor memory according to a first embodiment of the present disclosure is shown. Figure 1A It is a floor plan. Figure 1B is along Figure 1A A cross-sectional view taken along lines AA' and BB'.

[0021] Reference Figure 1A and Figure 1B The semiconductor memory may include a substrate 100, a first line 110 formed on the substrate 100 and extending in a first direction, a second line 120 formed on the first line 110 and spaced apart from the first line 110 in a third direction and extending in a second direction intersecting the first direction, and a memory cell 130 arranged between the first line 110 and the second line 120 at an intersection of the first line 110 and the second line 120 in a third direction perpendicular to the first direction and the second direction.

[0022] The substrate 100 may include a semiconductor material such as silicon. A desired lower structure (not shown) may be formed in the substrate 100. For example, the substrate 100 may include a driving circuit (not shown) electrically connected to the first line 110 and / or the second line 120 to control the operation of the memory cell 130.

[0023] The first line 110 and the second line 120 may include one or more of various conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof, and may have a single-layer structure or a multi-layer structure. The first line 110 and the second line 120 may be connected to the lower end and the upper end of the memory cell 130, respectively, and may transmit a voltage or a current to the memory cell 130 to drive the memory cell 130. When the first line 110 is used as a word line, the second line 120 may be used as a bit line. Conversely, when the first line 110 is used as a bit line, the second line 120 may be used as a word line.

[0024] The memory cell 130 may include a variable resistance element that stores different data by switching between different resistance states according to a voltage or current applied to the first line 110 and the second line 120. Figure 1A As shown in the plan view of , the storage unit 130 may have a rectangular shape, wherein two side walls in the first direction are aligned with the second line 120 and two side walls in the second direction are aligned with the first line 110. However, the embodiment is not limited thereto. As long as the storage unit 130 overlaps the intersection of the first line 110 and the second line 120, the planar shape of the storage unit 130 may be variously modified.

[0025] The memory cell 130 may include a stacked structure of a lower electrode layer 131, a selection element layer 132, an intermediate electrode layer 133, a variable resistance layer 135, and an upper electrode layer 137. In addition, the memory cell 130 may include a first interface electrode layer 134 disposed between the variable resistance layer 135 and the intermediate electrode layer 133, and a second interface electrode layer 136 disposed between the variable resistance layer 135 and the upper electrode layer 137.

[0026] The lower electrode layer 131 may be placed between the first line 110 and the selection element layer 132, and may electrically connect the first line 110 and the selection element layer 132 to each other while physically separating the first line 110 and the selection element layer 132 from each other. In the present embodiment, the lower electrode layer 131 may include a stacked structure of a first lower electrode layer 131-1 and a second lower electrode layer 131-2. The second lower electrode layer 131-2 may include a carbon layer containing a relatively high concentration of nitrogen, while the first lower electrode layer 131-1 may include a carbon layer containing a relatively low concentration of nitrogen or no nitrogen. Therefore, the nitrogen concentration in the carbon layer of the second lower electrode layer 131-2 is higher than the nitrogen concentration in the carbon layer of the first lower electrode layer 131-1. Here, the nitrogen-containing carbon layer may refer to a layer including carbon atoms and nitrogen atoms, wherein the main atoms are carbon and nitrogen as added elements. The first lower electrode layer 131-1 may be placed between the second lower electrode layer 131-2 and the selection element layer 132. In addition, the thickness T1 of the first lower electrode layer 131 - 1 may be smaller than the thickness T2 of the second lower electrode layer 131 - 1 Advantages of the present embodiment will be described in comparison with the comparative example.

[0027] In the first comparative example using a single carbon layer as the lower electrode layer, there is a problem of poor surface roughness of the lower electrode layer. In this case, a layer (e.g., a selection element layer) formed on the lower electrode layer may have degraded film quality due to the poor surface roughness of the lower electrode layer, so that the operating voltage during the operation of the memory cell may be uneven.

[0028] In order to solve the problem of the first comparative example, a second comparative example in which a carbon layer used as a lower electrode layer is formed at a relatively low temperature by using PVD (physical vapor deposition) can be considered. This is because the carbon layer deposited by the low-temperature PVD method has a reduced surface roughness compared to the carbon layer of the first comparative example. However, in the second comparative example, the resistivity of the lower electrode layer may be greatly increased, and thus it may be difficult to use the lower electrode layer as a component of a memory cell.

[0029] In order to solve the problems of the first and second comparative examples, a third comparative example in which a carbon layer doped with a high concentration of nitrogen is used as the lower electrode layer can be considered. This is because the carbon layer doped with a high concentration of nitrogen has a reduced surface roughness and a similar level of resistivity compared to the carbon layer of the first comparative example. However, in this case, due to nitrogen doping at the interface between the lower electrode layer and the selection element layer, the interface resistance may increase. The increased interface resistance may increase the threshold voltage for turning on the selection element layer, and as a result, the operating voltage of the memory cell may increase.

[0030] On the other hand, in the present embodiment, by using a carbon layer containing a relatively high concentration of nitrogen as the second lower electrode layer 131-2 and placing the first lower electrode layer 131-1 including a carbon layer containing a relatively low concentration of nitrogen or a carbon layer containing no nitrogen between the selection element layer 132 and the second lower electrode layer 131-2, both the surface roughness problem of the lower electrode layer 131 and the increase in the interface resistance between the lower electrode layer 131 and the selection element layer 132 can be alleviated.

[0031] More specifically, when a carbon layer containing a relatively high concentration of nitrogen is used as the second lower electrode layer 131-2, the surface roughness of the second lower electrode layer 131-2 can be reduced. When the first lower electrode layer 131-1 is formed on the second lower electrode layer 131-2, the surface roughness of the second lower electrode layer 131-2 can be reflected to the first lower electrode layer 131-1, and therefore, the surface roughness of the first lower electrode layer 131-1 can also be reduced. In particular, since the thickness T1 of the first lower electrode layer 131-1 is relatively thin, the surface roughness of the first lower electrode layer 131-1 can be further reduced. This is because the surface roughness of the carbon layer is proportional to its thickness, regardless of whether it is doped with nitrogen and the nitrogen concentration. That is, as the thickness of the carbon layer increases, its surface roughness can increase, and as the thickness of the carbon layer decreases, its surface roughness can decrease. As a result, as the thickness of the carbon layer used as the first lower electrode layer 131-1 decreases, the surface roughness of the lower electrode layer 131 can be reduced.

[0032] In addition, by placing the first lower electrode layer 131-1 between the second lower electrode layer 131-2 and the selection element layer 132, an increase in the interface resistance between the lower electrode layer 131 and the selection element layer 132 can be suppressed. In addition, the first lower electrode layer 131-1 can prevent nitrogen of the second lower electrode layer 131-2 from diffusing into the selection element layer 132. The diffusion of nitrogen into the selection element layer 132 can affect the characteristics of the selection element layer 132.

[0033] The nitrogen content of the second lower electrode layer 131-2 may be in the range of 3 at% to 10 at% in order to reduce the surface roughness of the lower electrode layer 131. Since the nitrogen content of the first lower electrode layer 131-1 is lower than that of the second lower electrode layer 131-2, the nitrogen content of the first lower electrode layer 131-1 may be in the range of 0 at% to 3 at%.

[0034] In addition, in order to reduce the surface roughness of the lower electrode layer 131 and prevent nitrogen from diffusing into the selection element layer 132, the thickness T1 of the first lower electrode layer 131-1 may be between 100 and 200 mm. to When the thickness of the first lower electrode layer 131-1 is less than When the thickness of the lower electrode layer 131-1 is greater than When the surface roughness of the first lower electrode layer 131 - 1 is increased, the surface roughness of the lower electrode layer 131 is increased.

[0035] The selection element layer 132 can prevent current leakage between the memory cells 130 sharing the first line 110 or the second line 120. To this end, the selection element layer 132 can have a threshold switching characteristic for blocking or greatly limiting the current flowing through the memory cell 130 when the amplitude of the applied voltage is less than a predetermined threshold, and for allowing the current flowing through the memory cell 130 to suddenly increase when the amplitude of the applied voltage is equal to or greater than the threshold. The selection element layer 132 can be implemented in an on state or an off state based on the threshold. The selection element layer 132 may include a diode, an OTS (bidirectional threshold switch) material such as a chalcogenide material, a MIEC (mixed ion electron conduction) material such as a metal containing a chalcogenide material, a MIT (metal insulator transition) material such as NbO2 or VO2, or a tunneling insulating material with a relatively wide bandgap such as SiO2 or Al2O3.

[0036] The intermediate electrode layer 133 may be disposed between the selection element layer 132 and the variable resistance layer 135, and may electrically connect the selection element layer 132 and the variable resistance layer 135 to each other, while physically separating the selection element layer 132 and the variable resistance layer 135 from each other. In the present embodiment, the intermediate electrode layer 133 may include a stacked structure of a first intermediate electrode layer 133-1 and a second intermediate electrode layer 133-2. The first intermediate electrode layer 133-1 may include a carbon layer containing a relatively low concentration of nitrogen or no nitrogen, and the second intermediate electrode layer 133-2 may include a carbon layer containing a relatively high concentration of nitrogen. Therefore, the nitrogen concentration in the carbon layer of the second intermediate electrode layer 133-2 is higher than the nitrogen concentration in the carbon layer of the first intermediate electrode layer 133-1. The first intermediate electrode layer 133-1 may be disposed between the second intermediate electrode layer 133-2 and the selection element layer 132. In addition, the thickness T3 of the first intermediate electrode layer 133-1 may be less than the thickness T4 of the second intermediate electrode layer 133-2.

[0037] According to this embodiment, the problem of surface roughness of the intermediate electrode layer 133 and the increase in interface resistance between the intermediate electrode layer 133 and the selection element layer 132 can be reduced.

[0038] More specifically, since the thickness T3 of the first intermediate electrode layer 133-1 is relatively thin, the surface roughness of the first intermediate electrode layer 133-1 can be reduced. Since the second intermediate electrode layer 133-2 formed on the first intermediate electrode layer 133-1 includes a carbon layer containing a relatively high concentration of nitrogen, the surface roughness of the second intermediate electrode layer 133-2 can also be reduced. As a result, the surface roughness of the intermediate electrode layer 133 can be reduced.

[0039] In addition, by placing the first intermediate electrode layer 133-1 including a carbon layer containing relatively low concentration of nitrogen or a carbon layer containing no nitrogen between the second intermediate electrode layer 133-2 and the selection element layer 132, an increase in the interface resistance between the intermediate electrode layer 133 and the selection element layer 132 can be suppressed. In addition, the first intermediate electrode layer 133-1 can prevent nitrogen of the second intermediate electrode layer 133-2 from diffusing into the selection element layer 132.

[0040] The nitrogen content of the second intermediate electrode layer 133-2 may be in the range of 3 at% to 10 at%, and the nitrogen content of the first intermediate electrode layer 133-1 may be in the range of 0 at% to 3 at%. In addition, the thickness T3 of the first intermediate electrode layer 133-1 may be in the range of to within the range.

[0041] With respect to the selection element layer 132 disposed between the intermediate electrode layer 133 and the lower electrode layer 131 , the intermediate electrode layer 133 may have a symmetrical structure with the lower electrode layer 131 .

[0042] The variable resistance layer 135 may be an element for storing data in the memory cell 130. To this end, the variable resistance layer 135 may have a variable resistance characteristic of switching between different resistance states according to an applied voltage or current. The variable resistance layer 135 may have a single-layer structure or a multi-layer structure including at least one of materials used for RRAM, PRAM, MRAM, and FRAM, etc. That is, the variable resistance layer 135 may include a metal oxide such as a perovskite-based oxide or a transition metal oxide, a phase change material such as a chalcogenide-based material, a ferromagnetic material, or a ferroelectric material, etc.

[0043] In one embodiment, the variable resistance layer 135 may include a phase change material that switches between an amorphous state and a crystalline state by generating Joule heat according to a current flowing therethrough. When the phase change material is in an amorphous state, the phase change material may be in a relatively high resistance state, and when the phase change material is in a crystalline state, the phase change material may be in a relatively low resistance state. Data may be stored in the variable resistance layer 135 using the resistance difference of the phase change material.

[0044] When the intermediate electrode layer 133 includes a carbon layer, the first interface electrode layer 134 disposed between the intermediate electrode layer 133 and the variable resistance layer 135 can increase adhesion while reducing the contact resistance between the intermediate electrode layer 133 and the variable resistance layer 135. In particular, the first interface electrode layer 134 can reduce the set voltage applied during the set operation in which the variable resistance layer 135 changes from a high resistance state to a low resistance state. The first interface electrode layer 134 may include a conductive material with a lower resistance than the intermediate electrode layer 133 and good adhesion. For example, the first interface electrode layer 134 may include a metal such as tungsten (W), lithium (Li), aluminum (Al), tin (Sn), bismuth (Bi), antimony (Sb), nickel (Ni), copper (Cu), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), zinc (Zn), or molybdenum (Mo).

[0045] The upper electrode layer 137 may be disposed between the variable resistance layer 135 and the second line 120, and may electrically connect the variable resistance layer 135 and the second line 120 while physically separating them from each other. The upper electrode layer 137 may include one or more of various conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. Alternatively, the upper electrode layer 137 may include a carbon layer to which a dopant such as nitrogen is added or a carbon layer to which no dopant is added. The upper electrode layer 137 may have a material or structure different from that of the lower electrode layer 131 and / or the intermediate electrode layer 133.

[0046] When the upper electrode layer 137 includes a carbon layer, the second interface electrode layer 136 disposed between the upper electrode layer 137 and the variable resistance layer 135 can increase adhesion while reducing the contact resistance between the upper electrode layer 137 and the variable resistance layer 135. Specifically, the second interface electrode layer 136 can reduce the set voltage applied during the set operation in which the variable resistance layer 135 changes from a high resistance state to a low resistance state. The second interface electrode layer 136 may include a conductive material with a lower resistance than the upper electrode layer 137 and good adhesion. For example, the second interface electrode layer 136 may include a metal such as tungsten (W), lithium (Li), aluminum (Al), tin (Sn), bismuth (Bi), antimony (Sb), nickel (Ni), copper (Cu), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), zinc (Zn) or molybdenum (Mo).

[0047] Assuming that the variable resistance layer 135 for data storage is included, the layered structure of the above-mentioned memory cell 130 may be variously modified.

[0048] In one embodiment, one of the lower electrode layer 131 and the intermediate electrode layer 133 may include a conductive material, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof, instead of a carbon layer. In another embodiment, one of the lower electrode layer 131 and the intermediate electrode layer 133 may be omitted.

[0049] In yet another embodiment, at least one of the first interface electrode layer 134 , the second interface electrode layer 136 , and the upper electrode layer 137 may be omitted.

[0050] In yet another embodiment, the memory cell 130 may further include one or more layers for improving characteristics of the memory cell 130 in addition to the above-described layers 131 to 137 .

[0051] In yet another embodiment, the positions of the selection element layer 132 and the variable resistance layer 135 may be reversed with respect to each other. In this case, the relative positions / structures of the lower electrode layer 131, the intermediate electrode layer 133, the first and second interface electrode layers 134 and 136, and the upper electrode layer 137 may also be modified. This will refer to Figures 4 to 6 Describe in more detail.

[0052] The spaces between the first lines 110 , the spaces between the second lines 120 , and the spaces between the memory cells 130 may be filled with an insulating material (not shown).

[0053] According to the above-mentioned semiconductor memory, by optimizing the structure of the lower electrode layer 131 and the middle electrode layer 133 respectively located below and above the selection element layer 132, the operating characteristics of the storage unit 130 can be improved, for example, the level of the operating voltage can be reduced or the uniformity of the operating voltage can be increased.

[0054] Furthermore, a method for manufacturing the semiconductor memory according to the present embodiment will be briefly described below.

[0055] First, a conductive layer for forming the first line 110 and a material layer for forming the memory cell 130 are sequentially formed on the substrate 100. Specifically, a layer for forming the lower electrode layer 131 can be formed by depositing a first carbon layer having a relatively high nitrogen content on the conductive layer and depositing a second carbon layer having a relatively low nitrogen content or containing no nitrogen on the first carbon layer. For example, each of the first carbon layer and the second carbon layer can be formed by a physical vapor deposition (PVD) method. More specifically, the first carbon layer can be formed by flowing nitrogen into a deposition chamber provided with a carbon source, and then the second carbon layer can be formed by reducing the flow rate and flow time of nitrogen or blocking nitrogen. However, the embodiment is not limited thereto. In another embodiment, each of the first carbon layer and the second carbon layer can be formed by any deposition method among various deposition methods, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc.

[0056] Similarly, a layer for forming the intermediate electrode layer 133 can be formed by depositing a third carbon layer having a relatively low nitrogen concentration or containing no nitrogen over the layer for forming the selection element layer 132 and depositing a fourth carbon layer having a relatively high nitrogen content over the third carbon layer.

[0057] Subsequently, the conductive layer for forming the first line 110 and the material layer for forming the memory cell 130 may be etched using a linear mask pattern extending in the first direction. As a result, a stacked structure may be formed over the substrate 100. Each stacked structure may include the first line 110 and a material layer pattern for forming the memory cell 130 having a shape overlapping the first line 110 and disposed over the first line 110. Spaces between the stacked structures may be filled with an insulating material.

[0058] Subsequently, a conductive layer for forming the second wire 120 may be formed over the stacked structure and the insulating material filling the space between the stacked structures.

[0059] Subsequently, the conductive layer and the stack structure for forming the second line 120 may be etched using a line-shaped mask pattern extending in the second direction, thereby forming the second line 120 and the memory cell 130 .

[0060] Figure 2 FIG. 2 shows a semiconductor memory according to a second embodiment of the present disclosure. For convenience of explanation, Figure 2 Only one storage unit and part of its upper and lower lines are shown, but as shown in FIG. Figure 1A and Figure 1B As described, a plurality of memory cells may be arranged between a lower line and an upper line crossing the lower line. Figure 2 The second embodiment shown will focus on Figure 1B The differences from the above-mentioned first embodiment are described below.

[0061] Reference Figure 2 , the storage unit 230 may be disposed between the first line 210 and the second line 220 .

[0062] The memory cell 230 may include a stacked structure of a lower electrode layer 231, a selection element layer 232, an intermediate electrode layer 233, a variable resistance layer 235, and an upper electrode layer 237. In addition, the memory cell 230 may include a first interface electrode layer 234 between the variable resistance layer 235 and the intermediate electrode layer 233, and a second interface electrode layer 236 between the variable resistance layer 235 and the upper electrode layer 237. In addition, the memory cell 230 may include a resistance layer 238 between the upper electrode layer 237 and the second line 220.

[0063] The lower electrode layer 231 and / or the middle electrode layer 233 may include any of a variety of conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. Alternatively, the lower electrode layer 231 and / or the middle electrode layer 233 may include a carbon layer to which a dopant such as nitrogen is added or to which no dopant is added.

[0064] The selection element layer 232, the first interface electrode layer 234, the variable resistance layer 235 and the second interface electrode layer 236 may be respectively connected to the Figure 1B The selection element layer 132 , the first interface electrode layer 134 , the variable resistance layer 135 , and the second interface electrode layer 136 are substantially the same.

[0065] The upper electrode layer 237 may include a stacked structure of a first upper electrode layer 237-1 and a second upper electrode layer 237-2. The second upper electrode layer 237-2 may include a carbon layer containing a relatively high concentration of nitrogen, while the first upper electrode layer 237-1 may include a carbon layer containing a relatively low concentration of nitrogen or containing no nitrogen. Therefore, the nitrogen concentration in the carbon layer of the second upper electrode layer 237-2 is higher than the nitrogen concentration in the carbon layer of the first upper electrode layer 237-1. The first upper electrode layer 237-1 may be disposed between the second upper electrode layer 237-2 and the resistor layer 238. In addition, the thickness T5 of the first upper electrode layer 237-1 may be less than the thickness T6 of the second upper electrode layer 237-2.

[0066] According to the present embodiment, the surface roughness of the upper electrode layer 237 and the increase of the interface resistance between the upper electrode layer 237 and the resistance layer 238 can be reduced. Specifically, as will be described later, the resistance layer 238 can prevent excessive current from flowing through the memory cell 230 and can have a relatively high resistance. Therefore, when the interface resistance between the resistance layer 238 and the upper electrode layer 237 is increased by forming the upper electrode layer 237 into a stacked structure having a first upper electrode layer 237-1 and a second upper electrode layer 237-2 in addition to forming the resistance layer 238 having a relatively high resistance, the operating voltage of the memory cell 230 can be significantly increased. In order to prevent this, the first upper electrode layer 237-1, rather than the second upper electrode layer 237-2, can be disposed adjacent to the resistance layer 238. That is, the first upper electrode layer 237-1 is disposed between the second upper electrode layer 237-2 and the resistance layer 238.

[0067] The nitrogen content of the second upper electrode layer 237-2 may be in the range of 3 at% to 10 at%, and the nitrogen content of the first upper electrode layer 237-1 may be in the range of 0 at% to 3 at%. In addition, the thickness T5 of the first upper electrode layer 237-1 may be in the range of to within the range.

[0068] When a large amount of current is provided to drive the memory cell 230, the resistance layer 238 can prevent the operation failure of the memory cell 230 caused by the overshoot current or the spike current flowing through the memory cell 230. The resistance layer 238 may include a conductive material with a higher resistance than the lower electrode layer 231, the middle electrode layer 233, and the upper electrode layer 237. For example, the resistance layer 238 may include tungsten silicon nitride (WSiN). However, the embodiment is not limited thereto. In another embodiment, the resistance layer 238 may include an insulating material layer having a thickness of several angstroms. The thickness is small in the range of to several tens of angstroms to enable current to flow between the upper electrode layer 237 and the second line 220 at an operating voltage of the memory cell 230 .

[0069] according to Figure 2 In the present embodiment shown, by optimizing the structure of the upper electrode layer 237 adjacent to the resistance layer 238, the operating characteristics of the memory cell 230 can be improved. For example, the operating voltage of the memory cell 230 can be reduced and the uniformity of the operating voltage can be improved.

[0070] Figure 3 FIG. 4 shows a semiconductor memory according to a third embodiment of the present disclosure. Figure 1B and Figure 2 The differences between the above-described embodiments are described below.

[0071] Reference Figure 3, the storage unit 330 may be disposed between the first line 310 and the second line 320 .

[0072] The memory cell 330 may include a stacked structure of a lower electrode layer 331, a selection element layer 332, an intermediate electrode layer 333, a variable resistance layer 335, and an upper electrode layer 337. In addition, the memory cell 330 may include a first interface electrode layer 334 between the variable resistance layer 335 and the intermediate electrode layer 333, and a second interface electrode layer 336 between the variable resistance layer 335 and the upper electrode layer 337. In addition, the memory cell 330 may include a resistance layer 338 between the upper electrode layer 337 and the second line 320.

[0073] The lower electrode layer 331 may be Figure 1B The lower electrode layer 131 of the embodiment of the present invention is substantially the same. That is, the lower electrode layer 331 may include a stacked structure of a first lower electrode layer 331-1 and a second lower electrode layer 331-2. The second lower electrode layer 331-2 may include a carbon layer containing a relatively high concentration of nitrogen, while the first lower electrode layer 331-1 may include a carbon layer containing a relatively low concentration of nitrogen or no nitrogen. Instead of the second lower electrode layer 331-2, the first lower electrode layer 331-1 may be disposed closer to the selection element layer 332. That is, the first lower electrode layer 331-1 is disposed between the second lower electrode layer 331-2 and the selection element layer 332.

[0074] The middle electrode layer 333 can be Figure 1B The intermediate electrode layer 133 of the embodiment of the present invention is substantially the same. That is, the intermediate electrode layer 333 may include a stacked structure of a first intermediate electrode layer 333-1 and a second intermediate electrode layer 333-2. The first intermediate electrode layer 333-1 may include a carbon layer containing relatively low concentration of nitrogen or no nitrogen, and the second intermediate electrode layer 333-2 may include a carbon layer containing relatively high concentration of nitrogen. Instead of the second intermediate electrode layer 333-2, the first intermediate electrode layer 333-1 may be disposed closer to the selection element layer 332. That is, the first intermediate electrode layer 333-1 is disposed between the second intermediate electrode layer 333-2 and the selection element layer 332.

[0075] The selection element layer 332, the first interface electrode layer 334, the variable resistance layer 335 and the second interface electrode layer 336 may be respectively Figure 1B The selection element layer 132 , the first interface electrode layer 134 , the variable resistance layer 135 , and the second interface electrode layer 136 are substantially the same.

[0076] The upper electrode layer 337 may be Figure 2The upper electrode layer 237 shown is substantially the same. That is, the upper electrode layer 337 may include a stacked structure of a first upper electrode layer 337-1 and a second upper electrode layer 337-2. The second upper electrode layer 337-2 may include a carbon layer containing a relatively high concentration of nitrogen, while the first upper electrode layer 337-1 may include a carbon layer containing a relatively low concentration of nitrogen or no nitrogen. Instead of the second upper electrode layer 337-2, the first upper electrode layer 337-1 may be disposed closer to the resistor layer 338. That is, the first upper electrode layer 337-1 is disposed between the second upper electrode layer 337-2 and the resistor layer 338.

[0077] The resistor layer 338 may be Figure 2 The resistive layer 238 of the embodiments is substantially the same.

[0078] according to Figure 3 In the present embodiment shown, the operating characteristics of the memory cell 330 can be improved by optimizing the structures of the lower electrode layer 331 and the middle electrode layer 333 respectively located below and above the selection element layer 332, and by optimizing the structure of the upper electrode layer 337 adjacent to the resistance layer 338.

[0079] Figure 4 FIG. 4 shows a semiconductor memory according to a fourth embodiment of the present disclosure. Figure 1B , Figure 2 and Figure 3 The differences between the above-described embodiments are described below.

[0080] Reference Figure 4 , the storage unit 430 may be disposed between the first line 410 and the second line 420 .

[0081] The memory cell 430 may include a stacked structure of a lower electrode layer 431, a variable resistance layer 433, an intermediate electrode layer 435, a selection element layer 436, and an upper electrode layer 437. In addition, the memory cell 430 may include a first interface electrode layer 432 between the variable resistance layer 433 and the lower electrode layer 431, and a second interface electrode layer 434 between the variable resistance layer 433 and the intermediate electrode layer 435.

[0082] The lower electrode layer 431 may include any of a variety of conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. Alternatively, the lower electrode layer 431 may include a carbon layer to which a dopant such as nitrogen is added or to which no dopant is added.

[0083] The first interface electrode layer 432, the variable resistance layer 433 and the second interface electrode layer 434 may be formed as described above. Figure 1B , Figure 2 and Figure 3 The first interface electrode layer, the variable resistance layer, and the second interface electrode layer in any one of the embodiments are substantially the same.

[0084] The intermediate electrode layer 435 may include a stacked structure of a first intermediate electrode layer 435-1 and a second intermediate electrode layer 435-2. The second intermediate electrode layer 435-2 may include a carbon layer containing a relatively high concentration of nitrogen, and the first intermediate electrode layer 435-1 may include a carbon layer containing a relatively low concentration of nitrogen or containing no nitrogen. Instead of the second intermediate electrode layer 435-2, the first intermediate electrode layer 435-1 may be disposed adjacent to the selection element layer 436. That is, the first intermediate electrode layer 435-1 is disposed between the second intermediate electrode layer 435-2 and the selection element layer 436.

[0085] The selection element layer 436 may be connected to the Figure 1B , Figure 2 and Figure 3 The selection element layer in any of the embodiments is substantially the same.

[0086] The upper electrode layer 437 may include a stacked structure of a first upper electrode layer 437-1 and a second upper electrode layer 437-2. The first upper electrode layer 437-1 may include a carbon layer containing relatively low concentration of nitrogen or no nitrogen, and the second upper electrode layer 437-2 may include a carbon layer containing relatively high concentration of nitrogen. Instead of the second upper electrode layer 437-2, the first upper electrode layer 437-1 may be disposed adjacent to the selection element layer 436. That is, the first upper electrode layer 437-1 is disposed between the second upper electrode layer 437-2 and the selection element layer 436.

[0087] The structure of the storage unit 430 may correspond to Figure 1B The memory cell 130 has a structure in which positions of material layers are reversed between the first line 110 and the second line 120 .

[0088] According to the present embodiment, by optimizing the structures of the intermediate electrode layer 435 and the upper electrode layer 437 respectively located below and above the selection element layer 436, the operation characteristics of the memory cell 430 can be improved.

[0089] Figure 5 FIG. 5 shows a semiconductor memory according to a fifth embodiment of the present disclosure. Figure 1B and Figures 2 to 4 The differences between the above-described embodiments are described below.

[0090] Reference Figure 5 , the storage unit 530 may be disposed between the first line 510 and the second line 520 .

[0091] The memory cell 530 may include a stacked structure of a lower electrode layer 531, a variable resistance layer 533, an intermediate electrode layer 535, a selection element layer 536, and an upper electrode layer 537. In addition, the memory cell 530 may include a first interface electrode layer 532 between the variable resistance layer 533 and the lower electrode layer 531, and a second interface electrode layer 534 between the variable resistance layer 533 and the intermediate electrode layer 535. In addition, the memory cell 530 may include a resistance layer 538 between the upper electrode layer 537 and the second line 520.

[0092] The lower electrode layer 531, the first interface electrode layer 532, the variable resistance layer 533 and the second interface electrode layer 534 may be connected to Figure 4 The lower electrode layer 431 , the first interface electrode layer 432 , the variable resistance layer 433 , and the second interface electrode layer 434 of the embodiment are substantially the same.

[0093] The intermediate electrode layer 535 may include any of a variety of conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. Alternatively, the intermediate electrode layer 535 may include a carbon layer to which a dopant such as nitrogen is added or to which no dopant is added.

[0094] The selection element layer 536 may be Figure 4 The selection element layer 436 of the embodiment is substantially the same.

[0095] The upper electrode layer 537 may include a stacked structure of a first upper electrode layer 537-1 and a second upper electrode layer 537-2. The second upper electrode layer 537-2 may include a carbon layer containing a relatively high concentration of nitrogen, while the first upper electrode layer 537-1 may include a carbon layer containing a relatively low concentration of nitrogen or containing no nitrogen. Instead of the second upper electrode layer 537-2, the first upper electrode layer 537-1 may be disposed adjacent to the resistance layer 538. That is, the first upper electrode layer 537-1 is disposed between the second upper electrode layer 537-2 and the resistance layer 538.

[0096] The resistor layer 538 may be Figure 2 and Figure 3 The resistive layer of any of the embodiments is substantially the same.

[0097] The structure of the storage unit 530 may correspond to Figure 2 The structure shown in FIG. 1 is a structure in which the position of the selective element layer 232 and the positions of the first interface electrode layer 234, the variable resistance layer 235 and the second interface electrode layer 236 are switched between the first line 210 and the second line 220. Figure 5In the embodiment shown, the operation characteristics of the memory cell 530 can be improved by optimizing the structure of the upper electrode layer 537 adjacent to the resistance layer 538 .

[0098] Figure 6 FIG. 6 shows a semiconductor memory according to a sixth embodiment of the present disclosure. Figure 1B and Figures 2 to 5 The differences between the above-described embodiments are described below.

[0099] Reference Figure 6 , the storage unit 630 may be disposed between the first line 610 and the second line 620 .

[0100] The memory cell 630 may include a stacked structure of a lower electrode layer 631, a variable resistance layer 633, an intermediate electrode layer 635, a selection element layer 636, and an upper electrode layer 637. In addition, the memory cell 630 may include a first interface electrode layer 632 between the variable resistance layer 633 and the lower electrode layer 631, and a second interface electrode layer 634 between the variable resistance layer 633 and the intermediate electrode layer 635. In addition, the memory cell 630 may include a resistance layer 638 between the upper electrode layer 637 and the second line 620.

[0101] The lower electrode layer 631, the first interface electrode layer 632, the variable resistance layer 633 and the second interface electrode layer 634 may be the same as those described above. Figure 4 implementation method or Figure 5 The lower electrode layer, the first interface electrode layer, the variable resistance layer and the second interface electrode layer of the embodiment are substantially the same.

[0102] The middle electrode layer 635 may be Figure 4 The intermediate electrode layer 435 of the embodiment of the present invention is substantially the same. That is, the intermediate electrode layer 635 may include a first intermediate electrode layer 635-1 and a second intermediate electrode layer 635-2. The second intermediate electrode layer 635-2 may include a carbon layer containing a relatively high concentration of nitrogen, while the first intermediate electrode layer 635-1 may include a carbon layer containing a relatively low concentration of nitrogen or no nitrogen. Instead of the second intermediate electrode layer 635-2, the first intermediate electrode layer 635-1 may be disposed adjacent to the selection element layer 636. That is, the first intermediate electrode layer 635-1 is disposed between the second intermediate electrode layer 635-2 and the selection element layer 636.

[0103] The selection element layer 636 may be the same as described above. Figure 4 implementation method or Figure 5 The selection element layers of the embodiments are substantially the same.

[0104] The upper electrode layer 637 may include a stacked structure of a first upper electrode layer 637-1, a second upper electrode layer 637-2, and a third upper electrode layer 637-3. The second upper electrode layer 637-2 may include a carbon layer containing a relatively high concentration of nitrogen, and the first and third upper electrode layers 637-1 and 637-3 may include carbon layers containing a relatively low concentration of nitrogen or no nitrogen. The first upper electrode layer 637-1 may be disposed adjacent to the selection element layer 636. The third upper electrode layer 637-3 may be disposed adjacent to the resistance layer 638. The second upper electrode layer 637-2 may be disposed between the first upper electrode layer 637-1 and the third upper electrode layer 637-3. The thickness of the second upper electrode layer 637-2 may be greater than the thickness of the first upper electrode layer 637-1 and the thickness of the third upper electrode layer 637-3.

[0105] The resistor layer 638 may be Figure 5 The resistive layer 538 of the embodiment is substantially the same.

[0106] according to Figure 6 In the present embodiment shown, the operation characteristics of the memory cell 630 can be improved by optimizing the structure of the intermediate electrode layer 635 located below the selection element layer 636 and the structure of the upper electrode layer 637 located between the selection element layer 636 and the resistance layer 638 .

[0107] The above and other memory circuits or semiconductor memory devices based on the disclosed technology can be used in a range of devices or systems. Figures 7 to 10 Some examples are provided of devices or systems that may implement the semiconductor memory disclosed herein.

[0108] Figure 7 is an example of a configuration diagram of a microprocessor that implements a memory circuit based on the disclosed technology.

[0109] Reference Figure 7 , the microprocessor 1000 may perform a series of processing tasks for controlling and adjusting receiving data from various external devices, processing data, and outputting processing results to external devices. The microprocessor 1000 may include a storage unit 1010, an operation unit 1020, and a control unit 1030, etc. The microprocessor 1000 may be various data processing units such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0110] The storage unit 1010 is a component for storing data in the microprocessor 1000, such as a processor register, a register, etc. The storage unit 1010 may include various registers, such as a data register, an address register, and a floating point register, etc. The storage unit 1010 may perform a temporary storage function, that is, temporarily store: data to be operated by the operation unit 1020, result data of the operation, and the address where the data for the operation is stored.

[0111] The storage unit 1010 may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the storage unit 1010 may include: a first line; a second line, arranged above the first line and spaced apart from the first line; a variable resistance layer, arranged between the first line and the second line; a selection element layer, arranged between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers, arranged above or below the selection element layer or arranged above and below the selection element layer, and one or more electrode layers are adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer includes a second carbon layer containing nitrogen, the first electrode layer includes a first carbon layer containing nitrogen with a lower concentration than the nitrogen contained in the second carbon layer of the second electrode layer or does not contain nitrogen, and the first electrode layer is placed between the second electrode layer and the selection element layer. Thus, in the storage unit 1010, the storage cell characteristics and the manufacturing process can be improved. As a result, the operating characteristics of the microprocessor 1000 can be improved.

[0112] The operation unit 1020 may perform four arithmetic operations or logic operations according to the result of decoding the command by the control unit 1030. The operation unit 1020 may include at least one arithmetic logic unit (ALU) or the like.

[0113] The control unit 1030 may receive signals from the storage unit 1010 , the operation unit 1020 , and an external device of the microprocessor 1000 , perform extraction and decoding of commands, and control input and output of signals of the microprocessor 1000 , and execute a process represented by a program.

[0114] The microprocessor 1000 according to the present embodiment may further include a cache unit 1040 that can temporarily store data to be input from or output to an external device different from the storage unit 1010. In this case, the cache unit 1040 can exchange data with the storage unit 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

[0115] Figure 8 is an example of a configuration diagram of a processor that implements a memory circuit based on the disclosed technology.

[0116] Reference Figure 8, the processor 1100 may improve performance and realize multifunctionality by including various functions different from the functions of the above-mentioned microprocessor 1000. The processor 1100 may include a core unit 1110 used as a microprocessor, a cache unit 1120 for temporarily storing data, and a bus interface 1130 for transmitting data between internal and external devices. The processor 1100 may include various systems on chip (SoCs) such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0117] The core unit 1110 of this embodiment is a component that performs arithmetic logic operations on data input from an external device, and may include a storage unit 1111, a computing unit 1112, and a control unit 1113. The storage unit 1111, the computing unit 1112, and the control unit 1113 may be substantially the same as the storage unit 1010, the computing unit 1020, and the control unit 1030.

[0118] The cache unit 1120 is a component that temporarily stores data to compensate for the data processing speed difference between the core unit 1110 operating at a high speed and the external device operating at a low speed. The cache unit 1120 may include a primary storage unit 1121 and a secondary storage unit 1122. In addition, in the case where a high storage capacity is required, the cache unit 1120 may include a tertiary storage unit 1123. The cache unit 1120 may include an increased number of storage units as required by the occasion. That is, the number of storage units included in the cache unit 1120 may be changed according to the design. The speeds at which the primary, secondary, and tertiary storage units 1121, 1122, and 1123 store and distinguish data may be the same or different. In the case where the speeds of the respective storage units 1121, 1122, and 1123 are different, the speed of the primary storage unit 1121 may be the largest. At least one of the primary storage unit 1121, the secondary storage unit 1122, and the tertiary storage unit 1123 of the cache unit 1120 may include one or more of the above-mentioned semiconductor devices according to the embodiments. For example, the cache unit 1120 may include: a first line; a second line, arranged above the first line and spaced apart from the first line; a variable resistance layer, arranged between the first line and the second line; a selection element layer, arranged between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers, arranged above or below the selection element layer or arranged above and below the selection element layer, one or more electrode layers are adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer includes a second carbon layer containing nitrogen, the first electrode layer includes a first carbon layer containing nitrogen with a lower concentration than the nitrogen contained in the second carbon layer of the second electrode layer or containing no nitrogen, and the first electrode layer is placed between the second electrode layer and the selection element layer. Thus, the storage cell characteristics and manufacturing process in the cache unit 1120 can be improved. Therefore, the operating characteristics of the processor 1100 can be improved.

[0119] Although in this embodiment, the primary, secondary and tertiary storage units 1121, 1122 and 1123 are all shown to be configured inside the cache unit 1120, at least one of the primary, secondary and tertiary storage units 1121, 1122 and 1123 of the cache unit 1120 may be configured outside the core unit 1110 and may compensate for the difference in data processing speed between the core unit 1110 and the external device.

[0120] The bus interface 1130 is a component that connects the core unit 1110 , the cache section 1120 , and an external device and allows efficient transmission of data.

[0121] The processor 1100 according to the present embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share a cache unit 1120. The plurality of core units 1110 and the cache unit 1120 may be directly connected or connected through a bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the above-described configuration of the core unit 1110. The storage unit in each core unit 1110 may be configured to be shared with a storage unit outside the core unit 1110 through the bus interface 1130.

[0122] The processor 1100 according to the present embodiment may further include an embedded storage unit 1140 storing data, a communication module unit 1150 capable of transmitting and receiving data to and from an external device in a wired or wireless manner, a memory control unit 1160 driving an external storage device, and a media processing unit 1170 processing data processed in the processor 1100 or data input from an external input device and outputting the processed data to an external interface device, etc. In addition, the processor 1100 may include a plurality of various modules and devices. In this case, the added plurality of modules may exchange data with the core unit 1110 and the cache unit 1120 and each other through the bus interface 1130.

[0123] The embedded storage unit 1140 may include not only volatile memory but also non-volatile memory. Volatile memory may include DRAM (dynamic random access memory), mobile DRAM, SRAM (static random access memory) and memory with similar functions to the above memory. Non-volatile memory may include ROM (read-only memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and memory with similar functions.

[0124] The communication module unit 1150 may include a module that can be connected to a wired network, a module that can be connected to a wireless network, and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, a power line communication (PLC), etc., such as various devices that send and receive data through a transmission line. The wireless network module may include an infrared data association (IrDA), a code division multiple access (CDMA), a time division multiple access (TDMA), a frequency division multiple access (FDMA), a wireless local area network, Zigbee, a ubiquitous sensor network (USN), Bluetooth, a radio frequency identification (RFID), a long-term evolution (LTE), a near field communication (NFC), a wireless broadband Internet (Wibro), a high-speed downlink packet access (HSDPA), a broadband CDMA (WCDMA), and an ultra-wideband (UWB), etc.

[0125] The memory control unit 1160 is used to manage and process data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory control unit 1160 may include various memory controllers, for example, devices that can control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Drive), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus), Secure Digital (SD) Card, Mini Secure Digital (mSD) Card, Micro Secure Digital (microSD) Card, Secure Digital High Capacity (SDHC) Card, Memory Stick Card, Smart Media (SM) Card, Multimedia Card (MMC), Embedded MMC (eMMC) and Compact Flash (CF) Card, etc.

[0126] The media processing unit 1170 may process data processed in the processor 1100 or data input from an external input device in the form of an image and voice, etc., and output the data to an external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio device (HD audio), and a high-definition multimedia interface (HDMI) controller, etc.

[0127] Fig. 9 is an example of a configuration diagram of a system that implements a memory circuit based on the disclosed technology.

[0128] Reference Fig. 9, the system 1200 as a device for processing data can perform input, processing, output, communication, storage, etc. to perform a series of operations on data. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, an interface device 1240, etc. The system 1200 of the present embodiment may be various electronic systems that use a processor to operate, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart mobile phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a recorder, telematics, an audio-visual (AV) system, and a smart TV, etc.

[0129] The processor 1210 can decode input commands, perform operations such as calculations and comparisons on data stored in the system 1200, and control these operations. The processor 1210 can be substantially the same as the microprocessor 1000 or the processor 1100 described above.

[0130] The main memory device 1220 is a memory that can temporarily store, call and run program codes or data from the auxiliary memory device 1230 when executing a program, and can save the stored content even when the power is cut off. The auxiliary memory device 1230 is a memory device for storing program codes or data. Although the speed of the auxiliary memory device 1230 is slower than that of the main memory device 1220, the auxiliary memory device 1230 can store a larger amount of data. The main memory device 1220 or the auxiliary memory device 1230 may include one or more of the above-mentioned semiconductor devices according to the embodiments. For example, the main memory device 1220 or the auxiliary memory device 1230 may include: a first line; a second line, arranged above the first line and spaced apart from the first line; a variable resistance layer, arranged between the first line and the second line; a selection element layer, arranged between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers, arranged above or below the selection element layer or arranged above and below the selection element layer, one or more electrode layers are adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer includes a second carbon layer containing nitrogen, the first electrode layer includes a first carbon layer containing nitrogen with a lower concentration than the nitrogen contained in the second carbon layer of the second electrode layer or does not contain nitrogen, and the first electrode layer is placed between the second electrode layer and the selection element layer. Thus, the memory cell characteristics and manufacturing process can be improved in the main memory device 1220 or the auxiliary memory device 1230. Therefore, the operating characteristics of the system 1200 can be improved.

[0131] In addition, the main memory device 1220 or the auxiliary memory device 1230 may include a memory system (see Fig.10 1300), additionally including the above-mentioned semiconductor device or excluding the above-mentioned semiconductor device.

[0132] The interface device 1240 can be used to perform command and data exchange between the system 1200 of the present embodiment and an external device. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human interface devices (HIDs), and a communication device. The communication device can be substantially the same as the above-mentioned communication module unit 1150.

[0133] Fig.10 is an example of a configuration diagram of a memory system that implements a memory circuit based on the disclosed technology.

[0134] Reference Fig.10 , the memory system 1300 may include a memory 1310 having a non-volatile characteristic as a component for storing data, a controller 1320 for controlling the memory 1310, an interface 1330 for connecting to an external device, and a buffer memory 1340 for temporarily storing data so as to efficiently transfer data between the interface 1330 and the memory 1310. The memory system 1300 may simply mean a memory for storing data, or may mean a data storage device for long-term preservation of stored data. The memory system 1300 may be a disk type such as a solid state drive (SSD), and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (microSD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

[0135] The memory 1310 or the buffer memory 1340 may include one or more of the above-mentioned semiconductor devices according to the embodiments. For example, the memory 1310 or the buffer memory 1340 may include: a first line; a second line, arranged above the first line and spaced apart from the first line; a variable resistance layer, arranged between the first line and the second line; a selection element layer, arranged between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers, arranged above or below the selection element layer or arranged above and below the selection element layer, and one or more electrode layers are adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer includes a second carbon layer containing nitrogen, the first electrode layer includes a first carbon layer containing nitrogen with a lower concentration than the nitrogen contained in the second carbon layer of the second electrode layer or does not contain nitrogen, and the first electrode layer is placed between the second electrode layer and the selection element layer. Thus, in the memory 1310 or the buffer memory 1340, the memory cell characteristics and the manufacturing process can be improved. As a result, the operating characteristics of the memory system 1300 can be improved.

[0136] The memory 1310 or the buffer memory 1340 may include various memories, such as a nonvolatile memory or a volatile memory, and additionally include the above-mentioned semiconductor device or exclude the above-mentioned semiconductor device.

[0137] The controller 1320 may control data exchange between the memory 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing operations to process a command input from outside the memory system 1300 through the interface 1330, etc.

[0138] The interface 1330 is used to perform the exchange of commands and data between the memory system 1300 and the external device. In the case where the memory system 1300 is a card type or a disk type, the interface 1330 may be compatible with an interface used in a device having a card type or a disk type, or an interface used in a device similar to the above-mentioned device. The interface 1330 may be compatible with one or more interfaces having different types from each other.

[0139] Based on the memory device disclosed in this article Figures 7 to 10 The features in the above examples of electronic devices or systems in the can be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebooks or laptops, game consoles, smart TVs, TV set-top boxes, multimedia servers, digital cameras with or without wireless communication capabilities, watches or other wearable devices with wireless communication capabilities.

[0140] Although this patent document contains many details, these should not be construed as limitations on the scope of any disclosure or the scope of protection claimed, but rather as descriptions of features of specific embodiments specific to the specific disclosure. Certain features described in this patent document in the context of discrete embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. In addition, although features are described above as working in certain combinations and even claimed as such, one or more features may be deleted from the claimed combination in some cases, and the claimed combination may involve subcombinations or variations of subcombinations.

[0141] Similarly, although operations are shown in a particular order in the drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, in order to achieve the desired results. Furthermore, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0142] Only a few implementations and examples are described. Other implementations, enhancements, and variations can be implemented based on what is described and illustrated in this patent document.

[0143] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined in the following claims.

Claims

1. An electronic device comprising a semiconductor memory, the semiconductor memory comprising: First line; a second line disposed above the first line and spaced apart from the first line; a variable resistance layer, disposed between the first line and the second line; A selection element layer is arranged between the first line and the variable resistance layer or between the second line and the variable resistance layer; as well as one or more electrode layers disposed above or below the selection element layer or above and below the selection element layer, the one or more electrode layers being adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer includes a second carbon layer containing nitrogen, the first electrode layer includes a first carbon layer, the first carbon layer contains nitrogen with a lower concentration than nitrogen contained in the second carbon layer of the second electrode layer or contains no nitrogen, the first electrode layer is disposed between the second electrode layer and the selection element layer, and Wherein, the thickness of the first electrode layer is smaller than the thickness of the second electrode layer.

2. The electronic device according to claim 1, wherein: The thickness of the first electrode layer is to within the range.

3. The electronic device according to claim 1, wherein: The nitrogen content of the second electrode layer is in the range of 3 at % to 10 at %.

4. The electronic device according to claim 1, wherein: The selection element layer is disposed between the first line and the variable resistance layer, The one or more electrode layers include: a lower electrode layer disposed between the first line and the selection element layer, and an intermediate electrode layer disposed between the selection element layer and the variable resistance layer, and The lower electrode layer and the middle electrode layer each include the first electrode layer and the second electrode layer.

5. The electronic device as claimed in claim 4, wherein: The lower electrode layer and the middle electrode layer have a symmetrical structure with respect to the selection element layer interposed therebetween.

6. The electronic device as claimed in claim 4, wherein: The semiconductor memory further comprises: an upper electrode layer disposed between the second line and the variable resistance layer; and A resistance layer, disposed between the upper electrode layer and the second line, for preventing excessive current, Wherein, the upper electrode layer includes a first upper electrode layer and a second upper electrode layer, the second upper electrode layer includes a nitrogen-containing carbon layer, the first upper electrode layer includes a carbon layer containing nitrogen with a lower concentration than the nitrogen contained in the carbon layer of the second upper electrode layer or containing no nitrogen, and the first upper electrode layer is placed between the second upper electrode layer and the resistance layer.

7. The electronic device as claimed in claim 6, wherein: The thickness of the first upper electrode layer is smaller than the thickness of the second upper electrode layer.

8. The electronic device as claimed in claim 1, wherein: The selection element layer is disposed between the second line and the variable resistance layer, The one or more electrode layers include: an upper electrode layer disposed between the second line and the selection element layer, and an intermediate electrode layer disposed between the selection element layer and the variable resistance layer, and The upper electrode layer and the middle electrode layer each include the first electrode layer and the second electrode layer.

9. The electronic device as claimed in claim 8, wherein: The upper electrode layer and the middle electrode layer have symmetrical structures with respect to the selection element layer interposed therebetween.

10. The electronic device according to claim 8, wherein: The semiconductor memory further comprises: A resistance layer, disposed between the upper electrode layer and the second line, for preventing excessive current, The upper electrode layer further includes a third electrode layer disposed between the second electrode layer and the resistance layer, and the third electrode layer includes a carbon layer containing nitrogen with a lower concentration than nitrogen contained in the second carbon layer of the second electrode layer or containing no nitrogen.

11. The electronic device as claimed in claim 1, further comprising a microprocessor, wherein the microprocessor comprises: A control unit receives a signal including a command from outside the microprocessor and performs extraction and decoding of the command, or controls input or output of a signal of the microprocessor; an operation unit, which performs an operation based on a result of the control unit decoding the command; as well as a storage unit storing: data for executing the operation, data corresponding to a result of executing the operation, or an address of data on which the operation is executed, The semiconductor memory is part of a storage unit in the microprocessor.

12. The electronic device of claim 1, further comprising a processor, wherein the processor comprises: A core unit that performs an operation corresponding to a command input from outside the processor by using data based on the command; A cache unit storing: data used to perform the operation, data corresponding to a result of performing the operation, or an address of data on which the operation is performed; as well as a bus interface connected between the core unit and the cache section and transmitting data between the core unit and the cache section, The semiconductor memory is part of a cache unit in the processor.

13. The electronic device of claim 1, further comprising a processing system, the processing system comprising: a processor that decodes commands received by the processor and controls operations on information based on results of decoding the commands; an auxiliary storage device storing a program for decoding the command and the information; a main storage device for calling and storing the program and information from the auxiliary storage device so that the processor can use the program and the information to perform the operation when running the program; as well as an interface device that performs communication between at least one of the processor, the auxiliary storage device, and the main storage device and an external part of the processing system, The semiconductor memory is part of the auxiliary memory device or part of the main memory device in the processing system.

14. The electronic device of claim 1, further comprising a memory system, the memory system comprising: a memory that stores data and retains the stored data independently of a power source; a memory controller that controls input and output of data to and from the memory according to a command input from the outside; a buffer memory for buffering data exchanged between the memory and the outside; as well as an interface for performing communication between at least one of the memory, the memory controller, and the buffer memory and the outside, The semiconductor memory is part of the memory or part of the buffer memory in the memory system.

15. An electronic device comprising a semiconductor memory, the semiconductor memory comprising: First line; a second line disposed above the first line and spaced apart from the first line; a variable resistance layer, disposed between the first line and the second line; A selection element layer is arranged between the first line and the variable resistance layer or between the second line and the variable resistance layer; an electrode layer disposed between the variable resistance layer or the uppermost layer of the selection element layer and the second line; as well as a resistance layer, disposed between the second line and the electrode layer, for preventing excessive current, wherein the electrode layer comprises a first electrode layer and a second electrode layer, the second electrode layer comprises a second carbon layer containing nitrogen, the first electrode layer comprises a first carbon layer, the first carbon layer contains nitrogen with a lower concentration than the nitrogen contained in the second carbon layer of the second electrode layer or contains no nitrogen, the first electrode layer is disposed between the second electrode layer and the resistance layer, and Wherein, the thickness of the first electrode layer is smaller than the thickness of the second electrode layer.

16. The electronic device as claimed in claim 15, wherein: The thickness of the first electrode layer is to within the range.

17. The electronic device as claimed in claim 15, wherein: The nitrogen content of the second electrode layer is in the range of 3 at % to 10 at %.

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