Method for operating an electronic converter, corresponding control circuit and electronic converter

Abstract

Embodiments of the present disclosure provide a method for operating an electronic converter, a corresponding control circuit, and an electronic converter, wherein the switching activity of the switching stage of the electronic converter is active or inactive based on a control signal, and the method includes operating the electronic converter alternately in a first mode or a second mode. In the first mode, a state signal is initially asserted and is de-asserted in response to the amplitude of the input sensing signal failing to reach a first reference threshold. In the second mode, the state signal is initially de-asserted, and the auxiliary power signal changes periodically with a change cycle. After a time interval equal to the change cycle, the comparison signal is asserted in response to the amplitude of the sensing signal reaching a second reference threshold. The state signal is asserted based on the comparison signal and the condition of the periodically changing auxiliary power signal.

Description

Technical Field

[0001] The present description relates to electronic converters, such as single-stage "flyback" or multi-level converter circuit topologies.

[0002] For example, electronic converters may be used in switch mode power supply circuits to convert an AC input voltage supply into a regulated DC supply. Background Art

[0003] An electronic AC-DC converter is an integrated circuit, or IC for short, that is used in (switch-mode) power supply circuits to convert an AC input power waveform into a regulated DC output power.

[0004] Associated with these converters is a mains voltage monitoring function, often referred to as “brown-out / overvoltage monitoring.” This function consists of disabling (brown-out) or enabling (overvoltage) the converter's switching activities based on the value of the mains input voltage.

[0005] As used herein, "brownout" refers to protecting the converter circuit from unexpected low levels of the mains input voltage, i.e., any situation where the input signal fails to reach the minimum normal operating threshold. When the unexpected low level of the input persists for a period of time, the converter may overheat due to the converter circuit drawing higher current.

[0006] Conceptually, the protection involves shutting down the converter during undervoltage and re-enabling it only after the mains input voltage recovers to a certain threshold (overvoltage).

[0007] Meanwhile, existing solutions may have one or more of the following deficiencies, for example, due to the system being not ideal:

[0008] When the system enters an undervoltage condition by interrupting the switching activity of the converter, the (monitored) voltage level may overshoot, especially when the converter is operating under high load;

[0009] For example, when using a matching network (such as an electromagnetic interference (EMI) filter), the leakage inductance may not be negligible and will be energized immediately before the switching activity is interrupted, possibly causing a parasitic voltage spike on the (monitored) voltage;

[0010] After a parasitic voltage spike event, a residual offset may remain on the (monitored) voltage level, e.g. due to the charging capacitance of an EMI filter;

[0011] Any imbalance in the common-mode capacitors in the EMI filter may cause the (monitored) voltage level to slowly increase (drift) over time.

[0012] These shortcomings may trigger spurious overvoltages and lead to (unwanted) system restarts in conditions that are unsafe for the converter. Summary of the invention

[0013] One or more embodiments of the present disclosure help to provide an improved solution to overcome the above-mentioned disadvantages.

[0014] According to an embodiment of the present disclosure, a control method is provided that involves introducing an operation of waiting for a specific time interval (eg, “blanking”) before any overvoltage condition is detected after entering an undervoltage state.

[0015] One or more embodiments may relate to corresponding control circuitry.

[0016] One or more embodiments may relate to corresponding electronic converters (eg flyback or multi-level).

[0017] One or more embodiments may help to cope with any undesired restart of a converter when the converter enters an undervoltage state (ie, once it stops switching).

[0018] One or more embodiments may advantageously reduce the silicon area footprint of a converter circuit, for example, by eliminating any peak detectors and / or complex filtering systems.

[0019] One or more embodiments may reduce or eliminate any residual offset and (slow) increase in voltage levels, for example, at a high voltage (HV) monitoring pin.

[0020] One or more embodiments may utilize recirculating bias signal VCC during an undervoltage phase to mask an overvoltage condition.

[0021] One or more embodiments may use circuit blocks to generate minimum current to free up capacity of the EMI filter, thereby compensating for circuit non-idealities. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0023] Figure 1 and Figure 1A is an example diagram of an electronic converter circuit;

[0024] Figure 2 yes Figure 1 and Figure 1A Example diagrams of components shown;

[0025] Figure 3 is based on Figure 1 and Figure 1AAn example flow chart of steps or activities in a method of controlling an electronic converter;

[0026] Figure 4 Indicated in Figure 3 possible time diagrams of signals that may occur in the method;

[0027] Figure 5 is an example graph of the error function;

[0028] Figure 6 Through Figure 4 The comparison of indicates the non-ideal temporal behavior of the signal;

[0029] Figure 7 is an exemplary flow chart of steps or activities in a method of controlling an electronic converter according to the present disclosure; and

[0030] Figure 8 A timing diagram representing signals in accordance with one or more embodiments. DETAILED DESCRIPTION

[0031] In the following description, one or more specific details are described to provide a deeper understanding of the examples of embodiments of the present specification. The embodiments can be obtained without one or more specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not described or explained in detail so that some aspects of the embodiments will not be obscured.

[0032] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more places in this specification do not necessarily refer to one and the same embodiment.

[0033] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0034] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0035] The drawings are in simplified form and not drawn to exact scale.

[0036] In all drawings attached herein, unless the context indicates otherwise, like parts or elements are denoted by like reference numerals / numbers, and the corresponding description will not be repeated for the sake of brevity.

[0037] Figure 1 and Figure 1AA single-stage flyback electronic converter 10 and a double-stage electronic converter 10a are shown.

[0038] like Figure 1 As shown, a conventional flyback converter includes:

[0039] Input nodes 100a, 100b are configured to be coupled to a main source of alternating current (AC) power (in short, mains) 100 to receive an oscillating power signal VIN therefrom;

[0040] The output nodes 102a, 102b are configured to be coupled to a load to provide an output voltage level VOUT thereto.

[0041] An input matching network 11, for example, an electromagnetic interference (EMI) filter network including a set of inductors and / or capacitors,

[0042] A rectifier bridge 12 coupled to the input nodes 100 a , 100 b via a matching network 11 , the rectifier bridge 12 being configured to receive an input AC voltage VIN and provide a rectified signal as an output;

[0043] Capacitor CIN is coupled to the rectifier bridge 12;

[0044] a transformer LP, LS having a primary side LP coupled to the input nodes 100a, 100b and a secondary side LS coupled to the output nodes 102a, 102b, the transformer LP, LS having a first number of turns and a first inductance LP on the primary side and a second number of turns and a second inductance LS on the secondary side LS, wherein a ratio of the first number of turns to the second number of turns is equal to n; a magnetic core of the transformer LS, LP storing energy from the primary side LP and releasing it to the secondary side LS;

[0045] Optionally, a dissipative snubber circuit 13, coupled to the primary side LP of the transformer LP, LS, the snubber circuit 13 being adapted to mitigate non-idealities in the magnetic coupling of the transformer windings LP, LS in a manner known per se;

[0046] a controlled switch M1, e.g., a transistor made in any known semiconductor technology, coupled to the transformers LS, LP, the switch M1 being configured to switch between a first state and a second state based on a control signal GD, the switch M1 being configured to activate accumulation of energy from the input VIN in the primary side LP of the transformers LP, LS when in the first (e.g., ON) state, and to deactivate such accumulation when in the second (e.g., OFF) state; an energy storage period also referred to as TON, referring to the corresponding "ON" state of the switch M1, and a full switching period indicated as a period T, e.g., T=TON+TOFF;

[0047] A rectifier D0, such as a diode or an active structure (e.g., a synchronous rectifier), is coupled to the second inductor LS and the output node 102b, the rectifier D0 being configured to become active during energy release to the secondary side LS and inhibited during an energy storage phase of the primary side LP;

[0048] an output capacitor COUT coupled to the rectifier D0 and the output node VOUT, the capacitor COUT being configured to filter the switching activity of the switch M1 to provide a continuous voltage or current to the load;

[0049] The control circuit 20 includes a plurality of input / output terminals or nodes HV, VCC, CS, and GD.

[0050] Specifically, Figure 1 and Figure 1A The control circuit 20 shown includes:

[0051] The first input node HV′ is configured to receive a signal HV indicating an input voltage VIN,

[0052] The second input node VCC is configured to receive a bias voltage level VCC, for example by being coupled to a power supply arrangement such as an auxiliary winding of a transformer, a diode and an external capacitor CEXT (the latter is referred to as Figure 1 and Figure 2 ), the power supply arrangement being arranged in a manner known per se to provide energy to operate the control circuit 20 during the switching activity;

[0053] a third input node CS configured to receive a signal CS indicating a switching activity of the converter circuit 10 , 10 a , for example indicating a current flowing through the inductance LP of the primary side of the transformer LP, LS;

[0054] The output node GD is configured to control the switch M1 via one or more control signals GD applied thereto.

[0055] like Figure 1 , Figure 1A As shown, the first input node HV is alternately connected to the downstream of the rectifier bridge 12 ( Figure 1 and 2 solid line in the middle) or upstream ( Figure 1 and Figure 2 ), for example, via diodes D1 and D2 (when arranged upstream). For example, if the HV pin is coupled via diodes D1, D2, the signal HV received by it has a rectified sinusoidal waveform, where the peak value of such a waveform is a function of the power supply input RMS voltage VRMS, that is, Vpk = √2*VRMS.

[0056] like Figure 1 and Figure 1A As shown, a sensing resistor R is coupled in series to the switch M1 and to the control circuit 20 , and the resistor R is configured to read the current CS flowing in the switch M1 and provide a current measurement signal CS to the control circuit 20 .

[0057] For simplicity, one or more embodiments are discussed below primarily with respect to a flyback topology, but it should be understood that such a topology is purely exemplary and not limiting.

[0058] For example, one or more embodiments may be applicable to Figure 1A The multi-stage electronic converter 10a shown in FIG. Figure 1 The transformers LP, LS of the circuit shown are replaced by an inductor L and wherein the output nodes 102a, 102b are coupled to a DC-DC converter stage 14 configured to receive a first stage output voltage VBOOST and provide an output voltage VOUT of the converter 10a at output nodes 102c, 102d.

[0059] like Figure 2 As shown, the control circuit 20 of the converter 10 , 10 a may include a voltage divider 200 , such as resistor dividers R1 , R2 , which is configured to receive a signal indicating a mains input voltage from a first input node HV of the control circuit 20 .

[0060] In one or more embodiments, the voltage divider 200 may alternatively be external to the control circuit 20 or integrated within the control circuit 20, the latter option being Figure 2 Shown in.

[0061] like Figure 2 As shown, the control circuit 20 may further include:

[0062] a startup circuit block 202 coupled to the first HV and second VCC input nodes and the voltage divider 200, the startup circuit block 202 being configured to provide an auxiliary power supply, for example via a current IHV, as described below; optionally, the startup circuit block 202 may include an x-cap discharge circuit block 201, which is configured to perform an x-cap discharge function 201 in a manner known per se, in particular when the first input node HV is coupled to the input nodes 100a, 100b of the converter 10 via diodes D1, D2;

[0063] A threshold selection circuit block 203, comprising one or more switches, the switches being configured to be driven to a first "on" or a second "off" state by a control signal, the threshold selection circuit block 203 being configured to provide a reference threshold VTH as an output, the reference threshold VTH being selected from two or more preset reference thresholds VTHBO, VTHBI;

[0064] The comparator circuit block 204 has:

[0065] i. The non-inverting input node 204a is coupled to the voltage divider 200, such as the intermediate resistors R1, R2, and is configured to receive a signal VD indicating the input voltage Vin therefrom;

[0066] ii. an inverting input node 204b coupled to the threshold selection circuit block 203 and configured to receive the selected threshold VTH therefrom, and

[0067] iii. is coupled to the output node 204c of the logic block 206,

[0068] The comparator circuit block 204 is configured to perform a comparison between the voltage VD and a selected threshold value VTH and provide a comparison signal OUTCOMP at an output node 204c, the comparison signal OUTCOMP indicating that the voltage VD reaches or fails to reach the reference threshold value VTH,

[0069] The logic circuit block 206 is coupled to the output node 204c of the comparator circuit block 204, the third input node CS, and the output node GD of the control circuit 20. The logic circuit block is configured to receive the comparison signal OUTCOMP from the threshold selection block 203, receive the signal CS from the third input node CS of the control circuit 20, and provide a state signal BS to drive the switch of the threshold selection block 203 to select the reference threshold signal VTH.

[0070] like Figure 2 As shown, the logic circuit block 206 of the control circuit 20 is configured to drive the reference threshold selection circuit block 203 to select from the preset reference thresholds VTHBO and VTHBI via the state signal BS:

[0071] a first reference threshold VTHBO when the converter 10, 10a is in an overvoltage state, and

[0072] A second reference threshold VTHBI is provided when the converter 10 , 10 a is in an undervoltage state, wherein the second reference threshold is higher than the first reference threshold, for example, VTHBI>VTHBO.

[0073] The switching activity of the electronic converter is driven by the periodic alternating switching of the output signal GD. In the undervoltage state, the output signal no longer switches, so as to retain its last (digital) value. In the case of overvoltage, the periodic switching of the output signal GD is restarted again.

[0074] when Figure 2 The controller shown is used for Figure 1 and Figure 1AIn the converter 10 , 10 a shown, the mains input voltage level Vin is monitored and the logic circuit block 206 activates (overvoltage) or deactivates (undervoltage) the switching activity of the converter 10 , 10 a by asserting / deasserting the status signal BS.

[0075] As used herein, the term "assert" means "make active." Note that a signal can be active high (positive logic) or active low (negative logic). For example, asserting a signal can mean "make it high" for positive logic and "make it low" for negative logic.

[0076] For simplicity, one or more embodiments are discussed herein with respect to an exemplary case where a signal is asserted in positive logic, but it should be understood that such implementation is not mandatory and limiting.

[0077] For example:

[0078] When the state signal BS is at a first (eg, “high”) value, the switching activity of the converter 10 , 10 a is active (overvoltage state),

[0079] When the state signal BS is at a second (eg, “low”) value, the switching activity of the converter 10 , 10 a is disabled (undervoltage state).

[0080] In one or more embodiments, if the comparison signal OUTCOMP remains at a certain logic level within a certain debounce time interval, the logic circuit block 206 may change the logic value of the state signal BS. Specifically, a first debounce time interval TDBBO may be introduced for transition to an undervoltage state, and a second debounce time interval TDBBI may be introduced for transition to an overvoltage state. For example, these debounce time intervals may be different, for example, TDBBO>TDBBI.

[0081] For example, the logic circuit block 206 may activate / deactivate the periodic alternating switching of the driving signal GD and assert the state signal BS based on the duration of the value of the output signal OUTCOMP reaching the corresponding overvoltage / undervoltage debounce time TDBBI, TDBBO.

[0082] Figure 3 is a flow chart of the operating method of the control circuit 20.

[0083] like Figure 3 As shown, the method includes:

[0084] Block 300: Initializing the converter 10, 10a to an overvoltage state, sensing 200 a signal HV, VD indicative of the input signal VIN and selecting 203 a first reference threshold VTHBO,

[0085] Block 302: performing a comparison 204 of the voltage divider signal VD and a selected 203 reference threshold value VTH, for example VD with VTH=VTHBO, to provide a comparison signal OUTCOMP as a result of this comparison;

[0086] Block 303: If the voltage divider signal VD exceeds the selected threshold VTH (eg, VD>VTHBO), providing a comparison signal OUTCOMP having a first (eg, "high" or "1") value, and

[0087] Block 304: If the voltage divider signal VD reaches or fails to reach the selected threshold VTH (eg, VD ≤ VTHBO), a comparison signal OUTCOMP having a second (eg, "low" or "0") value is provided.

[0088] like Figure 3 As shown, the method also includes:

[0089] Block 306: Detecting the length of time that the comparison signal OUTCOMP remains in the first state (eg, a “low” state), and

[0090] Block 307: If the detected time length fails to reach the first debounce time interval value TDBBO (e.g., while the signal OUTCOMP is "high"), the switching activity of the drive signal GD is kept valid, and the state signal BS is kept in the last state, e.g., "high" or "1",

[0091] Block 308: If the detected time length reaches the first debounce time interval value TDBBO, deactivate the switching activity of the signal GD to put the converter circuit 10, 10a into an undervoltage state, and assert the state signal BS, for example, switch its value to "low" or "0";

[0092] Block 310 : After the converter circuit 10 , 10 a has entered the undervoltage state (eg BS=“0”), another selectable reference threshold value is selected 203 , eg a second reference threshold value VTHBI.

[0093] like Figure 3 As shown, block 310 is coupled to the termination node, but the method activities of blocks 302 - 306 may be iterated using the threshold set in block 310 as the “new” threshold in block 302 .

[0094] Figure 4 Is about Figure 3 Exemplary timing diagrams of signals HV, OUTCOMP, BS, VTH at respective nodes HV, 204c, 206a, 204b of control circuit 20 during operation of circuit 20 are discussed.

[0095] exist Figure 4 In the case of the example, at the initial time t0:

[0096] The input voltage at the first node HV of the control circuit 20 is zero.

[0097] The switch signal BS is "high", causing the converters 10, 10a to be in an overvoltage state.

[0098] The reference threshold VTH of the reference selection circuit block 203 is set to be equal to the first threshold VTHBO.

[0099] As Figure 4 shown:

[0100] From the initial time t0 to the first time t1, the input signal at the first node HV has a low amplitude, such that the divider signal VD fails to reach the threshold VTH. For example, VTHBO and VD < VTH = VTHBO, and the comparator circuit block 204 outputs a comparison signal OUTCOMP with a first (e.g., "0") value.

[0101] At the first time t1, the signal VD from the voltage divider 200 exceeds the undervoltage threshold. For example, VD = VHV * Kp = VHV * (R2 / (R1 + R2)) and VD > VTH = VTHBO; thus, the comparison signal OUTCOMP switches to a second value, e.g., "1".

[0102] At the second time t2, i.e., VHV < VTHBO / Kp, the signal VD from the voltage divider 200 fails to reach the undervoltage threshold. For example, VD = VHV * Kp < VTHBO; thus, the comparison signal OUTCOMP switches to a second value, e.g., "0".

[0103] At the third time t3, the logic circuit block 206 detects that the voltage peak of the signal at the input node HV has been below the undervoltage threshold VTHBO within a time interval equal to the debounce time interval TDBBO. Therefore, the converters 10, 10a enter the undervoltage state (e.g., BS = "low"), thus disabling the switching, and the reference threshold circuit block 203 is driven to select the second threshold VTHBI.

[0104] In the fourth time interval t4, the signal VD from the voltage divider 200 reaches the overvoltage threshold. For example, VD = VHV * Kp > VTH = VTHBI; thus, the comparison signal OUTCOMP returns to the initial value.

[0105] At the fifth time interval t5, the logic circuit block 206 detects that the amplitude VHVBI of the signal at the input node HV is higher than the overvoltage threshold within a time interval equal to the second de-bounce time interval TDBBI (for example, TDBBI=1 millisecond), so the converter 10, 10a enters the overvoltage state (BS="High"), so switching is enabled and the reference threshold circuit block 203 selects the first threshold VTHBO.

[0106] In general, the value of the first debounce time interval TDBBO can be flexibly set based on the application of the converter circuit 10, 10a. For example, TDBBO can be set to a relatively low value (e.g., TDBBO = 0.064 seconds) to limit the tolerance of temporary mains voltage drops whose duration ends with a few (e.g., 2-3) sinusoidal cycles. On the contrary, in the case where an electronic medical device is addressed, TDBBO can be set to a relatively high value (e.g., TDBBO = 0.630 seconds) to avoid the converter shutting down when the input network is replaced by an uninterruptible power supply (UPS) in the event of a power outage.

[0107] On the contrary, the value of the second de-bounce time interval TDBBI may be determined based on the following factors.

[0108] like Figure 4 As shown, at time t5, the amplitude of the signal VD exceeds the second reference threshold VTHBI within a time equal to the second de-bounce time interval TDBBI, that is, VD>VTHBI.

[0109] As a result, the TDBBI debounce time introduces an error ε pk , the error ε pk The HV signal value that causes the converter 10, 10a to enter an overvoltage state is offset relative to the threshold value VHVBI. Such an error ε pk It can be expressed as:

[0110]

[0111] in

[0112] VHVpk is the peak amplitude of the signal at the HV node,

[0113] VHVBI is the amplitude of the input signal HV when the voltage divider signal VD exceeds the second reference threshold VTHBI within the time TDBBI, that is, VHVBI=VTHBI / Kp;

[0114] T is the reciprocal of the frequency of the input AC power VIN signal.

[0115] Figure 5 The error function ε is shown pk(vertical axis, in percentage) versus the second debounce time interval value TDBBI (abscissa, in milliseconds), the input mains voltage frequency is (approximately) 50 Hz. For example, selecting the debounce time interval value TDBBI=0.001s will result in an error of about 1.2% in the overvoltage threshold.

[0116] The choice of TDBBI value may be constrained in order to counter the risk of introducing non-negligible errors at the overvoltage threshold.

[0117] Note that coupling the HV node downstream of the rectifier bridge 12 can help overcome such limitations because in this arrangement the voltage on the HV pin is a DC voltage that follows the peak of the input voltage, also due to the input “tank” capacitance Cin coupled to the diode bridge 12 .

[0118] Figure 6 is with Figure 4 Shown is another timing diagram of the signals HV, OUTCOMP, BS, VTH at respective nodes HV, 204 c , 206 a , 204 b for different situations, such as considering non-ideal situations of operation of the converter circuit 10 .

[0119] like Figure 6 As shown, when the system enters an undervoltage state (e.g., at time t3, BS = "low"), due to non-ideal conditions in the matching network 11, there may be a spike or overshoot VOS in the signal at the HV node voltage. As known to those skilled in the art, this may be the result of the converter 10 being coupled to a high load and the non-negligible leakage inductance of the network 11. For example, the amplitude of this spike Vos is about tens of volts and the duration is about hundreds of microseconds. As known to those skilled in the art, after the spike Vos, the following phenomena may also occur:

[0120] A residual offset (e.g., 30-50 volts) of the peak value Vpk' at the HV node because, for example, the capacitance of the EMI filter 11 has been charged;

[0121] The signal at the HV node slowly increases (drifts) by δ over time.

[0122] like Figure 6 As shown, due to these non-ideal conditions, at time t4, the logic block 206 of the control circuit 20 may trigger an overvoltage (eg, at time t4) even though a sufficient overvoltage condition (eg, VHVpk*Kp) does not exist. <VTHBI)。

[0123] like Figure 7 and Figure 8 One or more of the illustrated embodiments are directed to combating such undesirable "false" overvoltage transitions.

[0124] like Figure 7 and Figure 8 As shown, the improved method of operation of the control circuit 20 can utilize the presence of the startup circuit block 202 to provide an improved configuration of the control logic 206 in driving the overvoltage / undervoltage transition.

[0125] like Figure 2 As shown, the startup circuit block 202 can provide auxiliary power and can generate a power supply current IHV between the HV node and the VCC pin to charge the external VCC capacitor.

[0126] In one or more embodiments, logic circuit block 206 may be configured to periodically activate such startup circuit block 202 when the converter enters an undervoltage state (e.g., BS = "low"), thereby causing VCC to oscillate within thresholds VCCON and VCCOFF to ensure that control circuit 20 receives proper power while switching activity of converter 10, 10a is interrupted.

[0127] For simplicity, one or more embodiments are discussed below mainly for the case where the converter 10 , 10 a has just switched to the undervoltage state at the initial time t3 .

[0128] like Figure 7 As shown, an improved operation method of the control circuit 20 may include:

[0129] Block 700: Switching the converter from an overvoltage state (BS="1") to an undervoltage state (BS="0") and sensing 200 signals HV, VD indicative of the input signal VIN,

[0130] Block 701: Setting 203 the reference threshold signal VTH to be equal to a second reference threshold VTHBI;

[0131] Box 702: Activate the startup circuit block 202 to draw or provide 202 a current IHV from the first node HV of the control circuit 20 (e.g., with a period TCC), for example, a current IHV having a minimum value IHVs (or a maximum value IHVc, as described below); as a result of the current value IHV, the voltage signal VCC at the bias node from VCC changes from an upper limit voltage VCCON to a lower limit VCCOFF (or vice versa); specifically, when providing a current IHV having a minimum value (e.g., IHV=IHVs), the bias signal VCC decreases from VCCON to VCCOFF.

[0132] Block 703: Check whether the bias signal VCC reaches the minimum value VCCOFF, and continue to provide the current IHV at the minimum value I_HVs until the bias signal reaches the minimum voltage level VCC_OFF;

[0133] Block 704: If the bias voltage VCC has reached the minimum value VCCOFF, for example after a TCC / 2 time interval, a current IHV having a maximum current value IHVc is provided until the bias voltage VCC increases from VCCOFF to VCCON.

[0134] Block 705 : Check whether the bias signal VCC reaches the maximum value VCCON, and continue to provide the current IHV with the maximum value IHVc until the bias signal reaches the maximum voltage level VCCON.

[0135] Box 706: If the bias voltage VCC has returned to the maximum value VCCON, for example, after the time interval TCC, a current IHV with a minimum current value I_HVs is provided until the bias voltage VCC drops from VCCON to VCCOFF again; if the bias voltage VCC has reached the minimum value VCCOFF, return to box 704;

[0136] Block 707: Compare the voltage divider signal VD with the reference threshold signal VTH 204, e.g., VTH=VTHBI, and if the voltage divider signal VD fails to reach the selected threshold VTH, provide a comparison signal OUTCOMP having a first (e.g., “low” or “0”) value, and return to block 706, and

[0137] Block 708: if the voltage divider signal VD reaches or exceeds the selected threshold value VTH, provide a comparison signal OUTCOMP having a second (e.g., "high" or "1") value; if the bias voltage VCC has reached the minimum value VCCOFF, return to block 704; Block 709: detect the length of time that the comparison signal OUTCOMP maintains the first (e.g., "low") state, and

[0138] Box 709: if the detected time length fails to reach the second debounce time interval value TDBBI, the state signal BS is maintained at, for example, "low" or "0", and the process returns to box 706;

[0139] Block 710: If the detected time length reaches the second debounce time interval value TDBBI, check whether the bias signal VCC has reached the minimum value VCCOFF, and continue to provide the current IHV with the minimum value IHVs until the bias signal reaches the minimum voltage level VCCOFF

[0140] Block 711 : If the bias voltage VCC has returned to the minimum value VCCOFF, a current IHV having a maximum current value IHVc is provided until the bias voltage VCC increases from VCCOFF to VCCON.

[0141] Block 712: Check whether the voltage level of the bias node VCC is equal to the maximum voltage level VCCON, and

[0142] Block 714: When the bias node has reached the maximum value VCCON, the state signal BS is asserted, for example “high”, so that the converter circuit 10, 10a enters the overvoltage state and the selector 203 switches.

[0143] Figure 8 is an exemplary timing diagram of signals HV, OUTCOMP, BS, VTH, VCC, and IHVSU at respective nodes HV, 204c, 206a, 204b, VCC, and HV in one or more embodiments.

[0144] For the sake of brevity, the behavior of the signal in the time interval t0 to t3 is not discussed here, because the previous reference Figure 4 and Figure 6 The discussion applies mutatis mutandis.

[0145] like Figure 8 As shown, after entering the brownout at time t3, the startup circuit block 202 is turned on, for example, via a signal from the logic circuit 206, thereby providing the bias signal VCC as a power supply signal oscillating between a higher VCCON and a lower VCCOFF level. Figure 8 As shown, the period TCC of the bias signal VCC may be different from the period of the signal at the input node HV.

[0146] like Figure 8 As shown, at time t3:

[0147] The reference threshold VTHBI is selected as the reference threshold VTH by the reference threshold selection circuit block 203;

[0148] Due to the blanking time interval corresponding to the first VCC discharge phase within time interval Tcc after the status signal BS is asserted low, the voltage spike Vos occurring when the converter is stopped due to the non-ideality of the EMI filter 11 does not trigger any overvoltage condition.

[0149] like Figure 8 As shown, at time t4, the comparison signal OUTCOMP becomes "high" (and remains high) for a duration of up to the second debounce time interval value TDBBI. This situation is mainly monitored during the VCC discharge phase, that is, after Tcc has passed. During these phases, the startup circuit block 202 sinks the IHV current from the HV pin into the ground, which keeps the voltage at the pin locked to the input voltage. For example, this current can discharge the capacitance of the EMI filter 11. As a result, any residual offset or error on the peak value Vpk" due to the overshoot Vos can be eliminated.

[0150] like Figure 8 As shown, if the voltage at the HV pin exceeds the overvoltage threshold for a time interval exceeding the TDBBI debounce time during the VCC discharge phase, the event is memorized and the switching activity resumes the next time the condition VCC=VCCON occurs, for example, at time t4'.

[0151] As about Figure 7 and Figure 8 The discussed solution has the further advantage of facilitating the selection of a small value for the second debounce time interval TDBBI resulting in an effective overvoltage threshold close to VHVBI.

[0152] As shown herein, a method of operating an electronic converter (e.g., 10, 10a), the electronic converter including a switching stage (e.g., LS, LP, L, M1) having an inductance (e.g., Lp, LS, L), the electronic converter having an input terminal (e.g., 100a, 100b) configured to receive an AC input signal (e.g., VIN) from an energy source (e.g., 100) and having an output terminal (e.g., 102a, 102b, 102c, 102d) configured to provide a DC output signal (VOUT) to a user circuit (ZL), the switching stage being capable of switching between an active state and an inactive state based on a state signal (e.g., BS) (e.g., via a control signal GD applied thereto), the method comprising:

[0153] generating (e.g., 300, 700) an input sense signal (e.g., HV, VD) in response to receiving the AC input signal at the input terminal,

[0154] The electronic converter is operated in one of a first mode and a second mode, wherein:

[0155] a. In the first mode, the state signal is initially asserted to set the switch stage to the active state, and the method comprises:

[0156] providing a first reference threshold (e.g., VTHBO) and a first time value (e.g., TDBBO),

[0157] In response to the amplitude of the input sensing signal failing to reach the first reference threshold within a time length (e.g., t2, t3) equal to the first time value, de-asserting the control signal,

[0158] b. In the second mode, the state signal is initially de-asserted to set the switch stage to the inactive state, and the method comprises:

[0159] providing (e.g., CEXT) an auxiliary power signal (e.g., VCC), and periodically varying (e.g., 701) the auxiliary power signal with a varying period (e.g., TCC) with a negative slope from a higher value (e.g., VCCON) to a lower value (e.g., VCCOFF) and with a positive slope from a lower value (e.g., VCCOFF) to a higher value (e.g., VCCON),

[0160] providing (e.g., 702) a second reference threshold (e.g., VTHBI) and a second time value (e.g., TDBBI),

[0161] After a time interval equal to the variation period (TCC) has elapsed (e.g., 703), in response to the amplitude of the input sense signal reaching the second reference threshold, asserting (e.g., 706) a comparison signal (e.g., OUTCOMP),

[0162] performing a first check (e.g., 708) regarding the comparison signal being asserted for a length of time (e.g., t4, t4') equal to the second time value,

[0163] performing a second check (e.g., 710) regarding whether the periodically varying auxiliary power signal changes with a negative slope when the comparison signal is asserted,

[0164] Based on an affirmative result of the first check and the second check, periodically varying the auxiliary power signal and asserting the status signal are stopped.

[0165] In the method described herein, in the second mode described above, the method comprises:

[0166] Setting (e.g., 702) a reference threshold signal (e.g., VTH) equal to the second reference threshold, and

[0167] A first comparison (302) of the amplitude of the input sensing signal and the reference threshold signal is performed (e.g., 704), providing the comparison signal having a first comparison value in response to the amplitude of the input sensing signal reaching the reference threshold and providing the comparison signal having a second comparison value in response to the amplitude of the input sensing signal failing to reach the reference threshold signal.

[0168] In the method as described herein, in the second mode, performing the first check includes performing a second comparison (eg, 306 ) between the length of time the comparison signal is asserted (eg, t4 , t4 ′) and the second time value.

[0169] In the method as described herein, in the second mode, periodically changing the auxiliary power signal includes, alternately:

[0170] For a first part of the variation period (TCC), a current (IHV) having a first current value (IHVS) is provided, and

[0171] For a second part of said variation period (TCC), said current (IHV) is provided with a second current value (IHVC), said positive slope being a function of said second current value (IHVS).

[0172] As shown herein, a control circuit (e.g., 20) for controlling switching activity of a switching stage, the switching stage comprising an inductor of an electronic converter having an input terminal configured to be coupled to an energy source to receive an AC input signal (e.g., VIN) therefrom and an output terminal (e.g., 102a, 102b, 102c, 102d) configured to be coupled to a user circuit (e.g., ZL) to provide a DC output signal (e.g., VOUT) thereto, the switching stage (e.g., LS, LP, L, M1) being capable of switching between an active state and an inactive state based on a state signal (e.g., BS) (e.g., via a control signal GD applied thereto), the control circuit (20) comprising:

[0173] a first input node (eg, HV) configured to be coupled to an input terminal of the electronic converter to sense therefrom a sense signal indicative of the above-mentioned input signal (eg, VIN),

[0174] a second input node (eg, VCC) configured to be coupled to an auxiliary power supply (eg, CEXT) to receive an auxiliary power supply signal therefrom, and

[0175] a first output node (e.g., GD) configured to be coupled to the switching stage of the electronic converter to control the switching activity thereof;

[0176] The processing circuit system (eg, 200, 202, 203, 204, 206) is configured to operate the electronic converter described above according to a method consistent with one or more embodiments.

[0177] As shown herein, according to one or more embodiments, an electronic converter includes a switching stage having an inductor, the electronic converter having an input terminal coupled to an energy source to receive an AC input signal therefrom and having an output terminal coupled to a user circuit to provide a DC output signal thereto, wherein a switching activity of the switching stage is active or inactive based on a status signal, wherein the electronic converter is equipped with a control circuit (e.g., 20).

[0178] As shown in this article, the electronic converter includes:

[0179] A matching network (eg, 11) is coupled to the input terminal,

[0180] a rectifier bridge (e.g., 12), coupled to the matching network and to the output terminal via the switching stage,

[0181] Wherein the first input node of the control circuit is alternately:

[0182] - coupled to the matching network via a pair of diodes (e.g., D1, D2), wherein a first diode (e.g., D1) of the pair of diodes is located between the first input node and the matching network, and a second diode (e.g., D2) of the pair of diodes is located between the first input node and the second input terminal,

[0183] - is coupled to the output node (eg 12) of the above-mentioned rectifier bridge.

[0184] As shown herein, the electronic converter includes a flyback converter (eg, 10).

[0185] As shown herein, the electronic converter includes a two-stage converter (e.g., 10a), which includes a DC-DC electronic converter (e.g., 14) coupled to the above-mentioned switching stage, and the DC-DC electronic converter has additional output terminals (e.g., for example, 102c, 102d) coupled to the above-mentioned user circuit.

[0186] It will be further understood that the various individual implementation options shown in the drawings accompanying this specification are not necessarily intended to be employed in the same combination shown in the drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations shown in the drawings.

[0187] Without prejudice to the essential principles, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of protection.

[0188] A method of operating an electronic converter (10, 10a), the electronic converter (10, 10a) comprising a switching stage (LS, LP, L, M1) having an inductance (Lp, LS, L), the electronic converter (10, 10a) having an input terminal (100a, 100b) configured to receive an AC input signal (VIN) from an energy source (100) and having an output terminal (102a, 102b, 102c, 102d) configured to provide a DC output signal (VOUT) to a user circuit (ZL), the switching stage (LS, LP, L, M1) being switchable between an active state and an inactive state based on a state signal (BS), the method can be summarized as comprising: in response to a state signal at the input terminal (100a, 100b), b) receiving the AC input signal (VIN) to generate (300, 700) an input sense signal (HV, VD), and operating the electronic converter in one of a first mode and a second mode, wherein: a. in the first mode, the state signal (BS) is initially asserted to set the switching stage (LS, LP, L, M1) to the active state, and the method includes: providing a first reference threshold (VTHBO) and a first time value (TDBBO), and in response to the amplitude of the input sense signal (HV, VD) failing to reach the first reference threshold (VTHBO) within a time length (t2, t3) equal to the first time value (TDBBO), de-asserting the state signal (BS), b.In the second mode, the state signal (BS) is initially de-asserted to set the switching stages (LS, LP, L, M1) to the inactive state, and the method comprises: providing (CEXT) an auxiliary power supply signal (VCC), and periodically varying (701) the auxiliary power supply signal (VCC) with a variation period (TCC) with a negative slope from a higher value (VCCON) to a lower value (VCCOFF) and with a positive slope from a lower value (VCCOFF) to a higher value (VCCON), providing (702) a second reference threshold value (VTHBI) and a second time value (TDBBI), after a time interval equal to the variation period (TCC) has elapsed (703), in response to the input When the amplitude of the input sense signal (HV, VD) reaches the second reference threshold value (VTH), the comparison signal (OUTCOMP) is asserted (706), a first check (708) is performed regarding the comparison signal (OUTCOMP) being asserted within a time length (t4, t4') equal to the second time value (TDBBI), a second check (710) is performed regarding the periodically changing auxiliary power signal (VCC) changing with a negative slope when the comparison signal (OUTCOMP) is asserted, and based on the positive results of the first check (708) and the second check (710), the periodically changing auxiliary power signal (VCC) is stopped and the state signal (BS) is asserted.

[0189] In the second mode, the method may include setting (702) a reference threshold signal (VTH) equal to the second reference threshold signal (VTHBI), performing (704) a first comparison (302) of the amplitude of the input sense signal (HV, VD) with the reference threshold signal (VTH), providing (706) the comparison signal (OUTCOMP) having a first comparison value (VTH) in response to the amplitude of the input sense signal (HV, VD) reaching the reference threshold signal (VTH) and providing (706) the comparison signal (OUTCOMP) having a second comparison value in response to the amplitude of the input sense signal (HV, VD) failing to reach the reference threshold signal (VTH).

[0190] In the second mode, performing the first check (708) may include performing a second comparison (306) between the length of time (t4, t4') that the comparison signal (OUTCOMP) is asserted and the second time value (TDBBI).

[0191] In the above-mentioned second mode, periodically changing the above-mentioned auxiliary power supply signal (VCC) may include, alternately: for a first part of the above-mentioned change period (TCC), providing a current (IHV) having a first current value (IHVS), and for a second part of the above-mentioned change period (TCC), providing the above-mentioned current (IHV) having a second current value (IHVC), and the above-mentioned positive slope is a function of the above-mentioned second current value (IHVS).

[0192] A control circuit (20) for controlling the switching activity of a switching stage (LS, LP, L, M1), the switching stage comprising an inductor (Lp, LS, L) of an electronic converter (10, 10a), the electronic converter having an input terminal (100a, 100b) configured to be coupled to an energy source (100) to receive an AC input signal (VIN) therefrom and an output terminal (102a, 102b, 102c, 102d) configured to be coupled to a user circuit (ZL) to provide a DC output signal (VOUT) thereto, the switching stage (LS, LP, L, M1) being capable of switching between an active state and an inactive state based on a state signal (BS), the control circuit being generally comprised of: A first input node (HV) configured to be coupled to an input terminal (100a, 100b) of an electronic converter (10, 10a) to sense a sense signal (HV) indicating the input signal (VIN) therefrom; a second input node (VCC) configured to be coupled to an auxiliary power supply (CEXT) to receive an auxiliary power supply signal (VCC) therefrom; a first output node (GD) configured to be coupled to the switching stage (LS, LP, L, M1) of the electronic converter (10, 10a) to control the switching activity thereof; and a processing circuit system (200, 202, 203, 204, 206) configured to operate the electronic converter (10, 10a) according to the method described herein.

[0193] An electronic converter (10, 10a) can be summarized as comprising a switching stage (LS, LP, L, M1) having an inductor (LS, LP, L), the electronic converter (10, 10a) having an input terminal (100a, 100b) coupled to an energy source (100) to receive an AC input signal (VIN) therefrom and having an output terminal (102a, 102b, 102c, 102d) coupled to a user circuit (ZL) to provide a DC output signal (VOUT) thereto, the switching activity of the switching stage (LS, LP, L, M1) being active or inactive based on a state signal (BS), wherein the electronic converter (10, 10a) is provided with a control circuit (20) as described herein.

[0194] The electronic converter (10, 10a) may include a matching network (11) coupled to the input terminal, a rectifier bridge (12) coupled to the matching network (11) and coupled to the output terminal (102a, 102b) via the switching stage (LS, LP, L, M1), wherein the first input node (HV) of the control circuit (20) is alternately: coupled to the matching network (11) via a pair of diodes (D1, D2), wherein the first diode (D1) of the pair of diodes is located between the first input node (HV) and the matching network, and the second diode (D2) of the pair of diodes (D1, D2) is located between the first input node (HV) and the second input terminal (100b); coupled to the output node of the rectifier bridge (12).

[0195] The electronic converter (10, 10a) may include a flyback converter (10).

[0196] The electronic converter (10, 10a) may comprise a two-stage converter (10a) comprising a DC-DC electronic converter (14) coupled to the above-mentioned switching stages (LS, LP, L, M1), the DC-DC electronic converter (14) having further output terminals (102c, 102d) coupled to the above-mentioned user circuit (ZL).

[0197] The various embodiments described above can be combined to provide other embodiments. These and other changes can be made to the embodiments according to the above detailed description. In general, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full scope to which such claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A method of operating an electronic converter, the electronic converter comprising a switching stage having an inductor, the electronic converter having an input terminal and an output terminal, the input terminal being configured to receive an AC input signal from an energy source, the output terminal being configured to provide a DC output signal to a user circuit, the switching stage being switchable between an active state and an inactive state based on a state signal, the method comprising: generating an input sense signal in response to receiving the AC input signal at the input terminal; as well as operating the electronic converter in one of a first mode or a second mode, wherein: a. In the first mode, the state signal is initially asserted to set the switch stage to the active state, and the method comprises: providing a first reference threshold and a first time value; and in response to the magnitude of the input sense signal failing to reach the first reference threshold for a length of time equal to the first time value, deasserting the status signal, and b. In the second mode, the state signal is initially de-asserted to set the switch stage to the inactive state, and the method comprises: Providing an auxiliary power signal, and periodically changing the auxiliary power signal with a change period and a negative slope from an upper limit value to a lower limit value and a positive slope from the lower limit value to an upper limit value; providing a second reference threshold and a second time value; asserting a comparison signal in response to the amplitude of the input sense signal reaching the second reference threshold after a time interval equal to the variation period has elapsed; performing a first check that the comparison signal is asserted for a length of time equal to the second time value; performing a second check that the periodically varying auxiliary power supply signal varies with a negative slope when the comparison signal is asserted; and Based on an affirmative result of the first check and the second check, periodically varying the auxiliary power signal and asserting the status signal are stopped.

2. The method according to claim 1, wherein in the second mode, the method comprises: setting a reference threshold signal equal to the second reference threshold; as well as A first comparison of the amplitude of the input sense signal and the reference threshold signal is performed, the comparison signal having a first comparison value is provided in response to the amplitude of the input sense signal reaching the reference threshold signal, and the comparison signal having a second comparison value is provided in response to the amplitude of the input sense signal failing to reach the reference threshold signal.

3. The method of claim 1 , wherein in the second mode, performing the first check comprises: A second comparison is performed between the length of time the comparison signal is asserted and the second time value.

4. The method according to claim 1, wherein in the second mode, periodically changing the auxiliary power signal comprises: Alternately: For a first portion of the variation period, providing a current having a first current value; as well as For a second part of the variation period, the current is provided with a second current value, the positive slope being dependent on the second current value. The method of claim 4 , wherein the first current value is a non-zero current value.

6. The method according to claim 5, further comprising: In the second mode, a current having the first current value is sunk in response to the comparison signal being asserted after the variation period has elapsed.

7. A control circuit for controlling a switching activity of a switching stage, the switching stage comprising an inductor of an electronic converter, the electronic converter having an input terminal and an output terminal, the input terminal being configured to be coupled to an energy source to receive an AC input signal from the energy source, the output terminal being configured to be coupled to a user circuit to provide a DC output signal to the user circuit, the switching stage being capable of switching between an active state and an inactive state based on a state signal, the control circuit comprising: a first input node configured to be coupled to an input terminal of the electronic converter to sense an input sense signal indicative of the input signal from the input terminal; a second input node configured to be coupled to an auxiliary power supply to receive an auxiliary power supply signal from the auxiliary power supply; a first output node configured to be coupled to the switching stage of the electronic converter to control the switching activity of the switching stage; as well as processing circuitry configured to: operate the electronic converter in one of a first mode or a second mode, wherein: a. In the first mode, the state signal is initially asserted to set the switch stage to the active state, and the processing circuit system is configured to: providing a first reference threshold and a first time value; and in response to the magnitude of the input sense signal failing to reach the first reference threshold for a length of time equal to the first time value, deasserting the status signal, and b. In the second mode, the state signal is initially de-asserted to set the switch stage to the inactive state, and the processing circuit system is configured to: Periodically changing the auxiliary power signal with a changing period and a negative slope from an upper limit value to a lower limit value and a positive slope from a lower limit value to an upper limit value; providing a second reference threshold and a second time value; asserting a comparison signal in response to the amplitude of the input sense signal reaching the second reference threshold after a time interval equal to the variation period has elapsed; performing a first check that the comparison signal is asserted for a length of time equal to the second time value; performing a second check that the periodically varying auxiliary power supply signal varies with a negative slope when the comparison signal is asserted; and Based on an affirmative result of the first check and the second check, periodically varying the auxiliary power signal and asserting the status signal are stopped.

8. The control circuit of claim 7 , wherein in the second mode, the processing circuit system is configured to: setting a reference threshold signal equal to the second reference threshold; and performing a first comparison of the amplitude of the input sense signal with the reference threshold signal, and The comparison signal having a first comparison value is provided in response to the amplitude of the input sense signal reaching the reference threshold signal, and the comparison signal having a second comparison value is provided in response to the amplitude of the input sense signal failing to reach the reference threshold signal.

9. A control circuit as claimed in claim 7, wherein in the second mode the processing circuitry is configured to perform the first check by performing a second comparison between the length of time the comparison signal is asserted and the second time value.

10. The control circuit of claim 7, wherein in the second mode, the processing circuit system is configured to periodically vary the auxiliary power signal by alternately performing: For a first portion of the variation period, providing a current having a first current value; and For a second part of the variation period, the current is provided with a second current value, the positive slope being dependent on the second current value. The control circuit of claim 10 , wherein the first current value is a non-zero current value.

12. The control circuit of claim 11 , wherein the processing circuit system is configured to: In the second mode, a current having the first current value is sunk in response to the comparison signal being asserted after the variation period has elapsed.

13. An electronic converter comprising: Switching stage, with inductance; an input terminal coupled to an energy source and configured to receive an AC input signal from the energy source; an output terminal configured to be coupled to a user circuit to provide a DC output signal to the user circuit, the switching activity of the switch stage being active or inactive based on the status signal; as well as a control circuit configured to control the switching activity of the switch stage, the control circuit comprising: a first input node configured to be coupled to an input terminal of the electronic converter to sense an input sense signal indicative of the input signal from the input terminal; a second input node configured to be coupled to an auxiliary power supply to receive an auxiliary power supply signal from the auxiliary power supply; a first output node configured to be coupled to the switching stage of the electronic converter to control the switching activity of the switching stage; and processing circuitry configured to operate the electronic converter in one of a first mode or a second mode, wherein: a. In the first mode, the state signal is initially asserted to set the switch stage to the active state, and the processing circuit system is configured to: providing a first reference threshold and a first time value; and in response to the magnitude of the input sense signal failing to reach the first reference threshold for a length of time equal to the first time value, deasserting the status signal, and b. In the second mode, the state signal is initially de-asserted to set the switch stage to the inactive state, and the processing circuit system is configured to: Periodically changing the auxiliary power signal with a changing period and a negative slope from an upper limit value to a lower limit value and a positive slope from a lower limit value to an upper limit value; providing a second reference threshold and a second time value; asserting a comparison signal in response to the amplitude of the input sense signal reaching the second reference threshold after a time interval equal to the variation period has elapsed; performing a first check that the comparison signal is asserted for a length of time equal to the second time value; performing a second check that the periodically varying auxiliary power supply signal varies with a negative slope when the comparison signal is asserted; and Based on an affirmative result of the first check and the second check, periodically varying the auxiliary power signal and asserting the status signal are stopped.

14. An electronic converter according to claim 13, comprising: a matching network coupled to the input terminal; as well as a rectifier bridge coupled to the matching network and coupled to the output terminal via the switching stage, wherein the first input node of the control circuit is alternately: is coupled to the matching network via a pair of diodes, wherein a first diode of the pair of diodes is located between the first input node and the matching network and a second diode of the pair of diodes is located between the first input node and a second input terminal, is coupled to the output node of the rectifier bridge.

15. An electronic converter according to claim 13, comprising a flyback converter.

16. An electronic converter according to claim 13, comprising a double-stage converter comprising a DC-DC electronic converter coupled to the switching stage, the DC-DC electronic converter having a further output terminal coupled to the user circuit.

17. The electronic converter of claim 13, wherein in the second mode, the processing circuitry is configured to: setting a reference threshold signal equal to the second reference threshold; and performing a first comparison of the amplitude of the input sense signal with the reference threshold signal, and The comparison signal having a first comparison value is provided in response to the amplitude of the input sense signal reaching the reference threshold signal, and the comparison signal having a second comparison value is provided in response to the amplitude of the input sense signal failing to reach the reference threshold signal.

18. An electronic converter as claimed in claim 13, wherein in the second mode the processing circuitry is configured to perform the first check by performing a second comparison between the length of time the comparison signal is asserted and the second time value.

19. The electronic converter of claim 13, wherein in the second mode, the processing circuitry is configured to periodically vary the auxiliary power signal by alternately performing: For a first portion of the variation period, providing a current having a first current value; and For a second part of the variation period, the current is provided with a second current value, the positive slope being dependent on the second current value.

20. An electronic converter according to claim 19, wherein the first current value is a non-zero current value, and wherein the processing circuitry is configured to: In the second mode, a current having the first current value is sunk in response to the comparison signal being asserted after the variation period has elapsed.

Images