analog-to-digital converters

Abstract

The present invention discloses an analog-to-digital converter, comprising a logic control module, an input voltage selection module, a reference voltage generation module, a reference voltage selection module, and a comparison module. Under the control of the logic control module, a Q signal and a corresponding reference voltage are selected as inputs of the comparison module to confirm the polarity of the Q signal. Thus, at the beginning of the next time sequence, an I signal and a suitable reference voltage are selected as inputs of the comparison module using a successive approximation method to facilitate determining the reference voltage closest to the I signal, thereby quantizing the analog signal into a corresponding digital signal. The analog-to-digital converter provided by the present invention generates a reference voltage through the reference voltage generation module, and utilizes the reference voltage to implement the process of quantizing the analog signal into a digital signal, thereby avoiding static power consumption and facilitating reduced static power consumption. Furthermore, the reference voltage generation module has a simple structure and is also conducive to reduced dynamic power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an analog-to-digital converter. Background Art

[0002] Traditional analog-to-digital converters belong to voltage domain analog-to-digital converters, but now there is a phase domain analog-to-digital converter that can more conveniently and efficiently achieve demodulation by directly quantizing the phase information of the analog signal into a digital signal. In addition, the phase domain analog-to-digital converter is more power-efficient and cost-effective than the voltage domain analog-to-digital converter. Among them, the phase information involves the baseband in-phase signal (referred to as the I signal) and the orthogonal signal (referred to as the Q signal). Among the existing phase domain analog-to-digital converters, there is a fully parallel analog-to-digital converter and a phase domain analog-to-digital converter based on a binary search algorithm assisted by the I signal and the Q signal. However, both of these phase domain analog-to-digital converters consume static power, resulting in higher static power consumption of the phase domain analog-to-digital converter. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides an analog-to-digital converter that can reduce static power consumption.

[0004] An analog-to-digital converter provided according to an embodiment of the present invention includes a logic control module, an input voltage selection module, a reference voltage generation module, a reference voltage selection module, and a comparison module;

[0005] The first input terminal of the logic control module is used to input a first clock signal;

[0006] The controlled end of the input voltage selection module is connected to the first control end of the logic control module, and the input end of the input voltage selection module is used to input an analog signal;

[0007] The first input terminal of the reference voltage generating module is used to input the first clock signal, and the second input terminal of the reference voltage generating module is used to input a second clock signal, wherein the polarity of the second clock signal is opposite to that of the first clock signal;

[0008] The input terminal of the reference voltage selection module is connected to the output terminal of the reference voltage generation module, and the controlled terminal of the reference voltage selection module is connected to the first control terminal of the logic control module;

[0009] The first input end of the comparison module is connected to the output end of the input voltage selection module, the second input end of the comparison module is connected to the output end of the reference voltage selection module, the output end of the comparison module is connected to the second input end of the logic control module, and the output end of the comparison module is used to output a digital signal.

[0010] The analog-to-digital converter according to an embodiment of the present invention has at least the following beneficial effects: a reference voltage generation module is used to generate multiple reference voltages; a reference voltage selection module is used to select one from the multiple reference voltages as the input of the comparison module; an input voltage selection module is used to select one from the input analog signal as the input of the comparison module; and a logic control module is used to control the actions of each module in an orderly manner; wherein, under the action of the first clock signal and the second clock signal, the reference voltage generation module generates multiple reference voltages with smaller dynamic power consumption to avoid consuming static power, which is conducive to reducing static power consumption.

[0011] According to some embodiments of the present invention, the reference voltage generation module includes a timing control unit, multiple first voltage generation units and multiple second voltage generation units, the input end of the timing control unit and the input end of the first voltage generation unit are both used to input the first clock signal, the input end of the second voltage generation unit is used to input the second clock signal, the output end of the timing control unit is respectively connected to the controlled end of the first voltage generation unit and the controlled end of the second voltage generation unit, the input end of the reference voltage selection module includes a first voltage input end and a second voltage input end, the output end of the first voltage generation unit is connected to the first voltage input end, and the output end of the second voltage generation unit is connected to the second voltage input end, so that under the control of the timing control unit, multiple reference voltages can be generated with smaller dynamic power consumption, which is conducive to reducing static power consumption.

[0012] According to some embodiments of the present invention, the timing control unit includes a phase-locked loop circuit and a demultiplexing circuit, the input end of the phase-locked loop circuit is used to input the first clock signal, the output end of the phase-locked loop circuit is connected to the input end of the demultiplexing circuit, and the output end of the demultiplexing circuit is respectively connected to the controlled end of the first voltage generating unit and the controlled end of the second voltage generating unit to facilitate timing control.

[0013] According to some embodiments of the present invention, the first voltage generating unit includes a first switching circuit and a first energy storage circuit, the input end of the first switching circuit is used to input the first clock signal, the controlled end of the first switching circuit is connected to the output end of the timing control unit, the output end of the first switching circuit is connected to the input end of the first energy storage circuit, and the output end of the first energy storage circuit is connected to the first voltage input end of the reference voltage selection module, so as to generate a reference voltage by consuming dynamic power.

[0014] According to some embodiments of the present invention, the second voltage generating unit includes a second switching circuit and a second energy storage circuit, the input end of the second switching circuit is used to input the second clock signal, the controlled end of the second switching circuit is connected to the output end of the timing control unit, the output end of the second switching circuit is connected to the input end of the second energy storage circuit, and the output end of the second energy storage circuit is connected to the second voltage input end of the reference voltage selection module, so as to generate a reference voltage by consuming dynamic power.

[0015] According to some embodiments of the present invention, a signal buffer module is further included, the analog signal includes a baseband in-phase signal and an orthogonal signal, the first input end of the signal buffer module is used to input the baseband in-phase signal, the second input end of the signal buffer module is used to input the common-mode voltage signal, the controlled end of the signal buffer module is connected to the third control end of the logic control module, the input end of the input voltage selection module includes a first signal input end and a second signal input end, the first signal input end is connected to the output end of the signal buffer module, and the second signal input end is used to input the orthogonal signal to facilitate impedance matching and reduce signal distortion.

[0016] According to some embodiments of the present invention, the baseband in-phase signal includes a first in-phase signal and a second in-phase signal having opposite polarities, the first signal input terminal of the input voltage selection module includes a first in-phase input terminal and a second in-phase input terminal, the third control terminal of the logic control module includes a first signal control terminal and a second signal control terminal, and the signal buffer module includes a first signal selection unit, a second signal selection unit, a first buffer unit, a second buffer unit, a first offset elimination unit, and a second offset elimination unit;

[0017] The first input terminal of the first signal selection unit is used to input the first in-phase signal, the first input terminal of the second signal selection unit is used to input the second in-phase signal, and the second input terminal of the first signal selection unit, the second input terminal of the second signal selection unit, the third input terminal of the first offset elimination unit, and the third input terminal of the second offset elimination unit are all used to input the common-mode voltage signal;

[0018] an output terminal of the first signal selection unit connected to a first input terminal of the first offset cancellation unit and a first input terminal of the second offset cancellation unit respectively through the first buffer unit, an output terminal of the second signal selection unit connected to a second input terminal of the first offset cancellation unit and a second input terminal of the second offset cancellation unit respectively through the second buffer unit, an output terminal of the first offset cancellation unit connected to the first non-inverting input terminal, and an output terminal of the second offset cancellation unit connected to the second non-inverting input terminal;

[0019] The controlled end of the first signal selection unit, the controlled end of the second signal selection unit, the first controlled end of the first offset elimination unit, and the first controlled end of the second offset elimination unit are all connected to the first signal control end, and the second controlled end of the first elimination unit and the second controlled end of the second elimination unit are both connected to the second signal control end;

[0020] The first signal selection unit, the second signal selection unit, the first buffer unit, the second buffer unit, the first offset elimination unit and the second offset elimination unit cooperate with each other to eliminate the offset generated during the signal buffering process, thereby facilitating the avoidance of signal distortion.

[0021] According to some embodiments of the present invention, the first offset elimination unit includes a first selection circuit, a second selection circuit, a first sampling circuit, a second sampling circuit, a third switching circuit, and a fourth switching circuit;

[0022] The input end of the first selection circuit is connected to the output end of the first buffer unit, the input end of the second selection circuit is connected to the output end of the second buffer unit, the controlled end of the first selection circuit and the controlled end of the second selection circuit are both connected to the first signal control end, and the controlled end of the third switch circuit and the controlled end of the fourth switch circuit are both connected to the second signal control end;

[0023] The first end of the first sampling circuit is connected to the first output end of the first selection circuit and the first end of the third switch circuit respectively, and the second end of the first sampling circuit is connected to the first output end of the second selection circuit and the first non-inverting input end respectively;

[0024] The first end of the second sampling circuit is connected to the second output end of the first selection circuit and the second end of the third switch circuit respectively, the second end of the second sampling circuit is connected to the second output end of the second selection circuit and the first end of the fourth switch circuit respectively, and the second end of the fourth switch circuit is used to input the common mode voltage signal;

[0025] The first selection circuit, the second selection circuit, the first sampling circuit, the second sampling circuit, the third switch circuit and the fourth switch circuit cooperate with each other to eliminate the offset in the first in-phase signal.

[0026] According to some embodiments of the present invention, the structure of the second offset elimination unit is the same as that of the first offset elimination unit, so as to eliminate the offset in the second in-phase signal and simplify the circuit.

[0027] According to some embodiments of the present invention, a holding module is further included, and the input end of the input voltage selection module is used to input the analog signal through the holding module to facilitate sampling and holding of the analog signal.

[0028] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0030] Figure 1 A circuit block diagram of an analog-to-digital converter provided in an embodiment of the present invention;

[0031] Figure 2 for Figure 1 The circuit block diagram of the reference voltage generating module of the analog-to-digital converter shown;

[0032] Figure 3 for Figure 2 A circuit schematic diagram of a first voltage generating unit of the analog-to-digital converter shown;

[0033] Figure 4 for Figure 2 A circuit schematic diagram of a second voltage generating unit of the analog-to-digital converter shown;

[0034] Figure 5 for Figure 2 A circuit block diagram of a timing control unit of an analog-to-digital converter is shown;

[0035] Figure 6 for Figure 2 The timing diagram of the reference voltage generation module of the analog-to-digital converter shown;

[0036] Figure 7 for Figure 1 The specific circuit block diagram of the analog-to-digital converter shown;

[0037] Figure 8 for Figure 7 The circuit block diagram of the signal buffer module of the analog-to-digital converter shown;

[0038] Figure 9 for Figure 8 Partial circuit schematic diagram of the signal buffer module of the analog-to-digital converter shown;

[0039] Figure 10 for Figure 8 Another circuit schematic diagram of a signal buffer module of the analog-to-digital converter shown;

[0040] Figure 11 Partial circuit schematic diagram of a signal buffer module of an analog-to-digital converter provided by some embodiments of the present invention.

[0041] The reference numerals are as follows:

[0042] Logic control module 100, input voltage selection module 200, reference voltage generation module 300, timing control unit 310, phase-locked loop circuit 311, demultiplexing circuit 312, first voltage generation unit 320, second voltage generation unit 330, reference voltage selection module 400, comparison module 500, signal buffer module 600, first signal selection unit 610, second signal selection unit 620, first buffer unit 630, second buffer unit 640, first offset elimination unit 650, second offset elimination unit 660, and holding module 700. DETAILED DESCRIPTION

[0043] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0044] In the description of the present invention, "several" means one or more, "more" means two or more, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The terms "first," "second," "third," and "fourth" are used solely to distinguish technical features and are not to be construed as indicating or implying relative importance, or as implicitly specifying the number or order of the technical features.

[0045] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0046] Before further explaining the embodiments of the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are subject to the following interpretations:

[0047] Static power consumption refers to leakage current power consumption, which is the power consumption when the circuit is in a stable state and its order of magnitude is very small; static power consumption is also called leakage power consumption, which refers to the power consumption generated by leakage current when the circuit is in a waiting or inactive state.

[0048] Dynamic power consumption refers to the power consumption of capacitor charging and discharging and short-circuit power consumption, which is caused by the reversal of the circuit.

[0049] In the prior art, a fully parallel analog-to-digital converter determines the initial phase condition by detecting the zero-crossing point after the initial phase rotation. This requires the use of a linear resistor or a current combiner, and consumes static current to generate a phase-shifted sine wave for zero-crossing detection. A phase-domain analog-to-digital converter based on a binary search algorithm assisted by I and Q signals requires an active tracking and holding circuit and a charge redistribution digital-to-analog converter to track the voltages of the I and Q signals. That is, both phase-domain analog-to-digital converters in the prior art consume static power, resulting in high static power consumption.

[0050] Therefore, the present invention provides an analog-to-digital converter that generates a reference voltage by consuming less dynamic power under time domain operation, thereby using the reference voltage to compare with the I signal and the Q signal, and then quantizing the analog signal into a digital signal, which is beneficial to reducing static power consumption.

[0051] Reference Figure 1 The present invention provides an analog-to-digital converter, comprising a logic control module 100, an input voltage selection module 200, a reference voltage generation module 300, a reference voltage selection module 400, and a comparison module 500; the first input terminal of the logic control module 100 is used to input a first clock signal; the controlled terminal of the input voltage selection module 200 is connected to the first control terminal of the logic control module 100, and the input terminal of the input voltage selection module 200 is used to input an analog signal; the first input terminal of the reference voltage generation module 300 is used to input the first clock signal, and the second input terminal of the reference voltage generation module 300 is used to input the second clock signal. signal, the polarity of the second clock signal is opposite to that of the first clock signal; the input end of the reference voltage selection module 400 is connected to the output end of the reference voltage generation module 300, and the controlled end of the reference voltage selection module 400 is connected to the first control end of the logic control module 100; the first input end of the comparison module 500 is connected to the output end of the input voltage selection module 200, the second input end of the comparison module 500 is connected to the output end of the reference voltage selection module 400, the output end of the comparison module 500 is connected to the second input end of the logic control module 100, and the output end of the comparison module 500 is used to output a digital signal.

[0052] Among them, the logic control module 100 is used to control the orderly operation of each module; the reference voltage generation module 300 is used to generate multiple reference voltages under the action of a first clock signal and a second clock signal; the reference voltage selection module 400 is used to select a corresponding reference voltage as an output under the control of the logic control module 100; the input voltage selection module 200 is used to select a corresponding I signal or Q signal as an output under the control of the logic control module 100; and the comparison module 500 is used to compare the output of the reference voltage selection module 400 with the output of the input voltage selection module 200 and output the comparison result.

[0053] Specifically, under the control of the logic control module 100, the Q signal and the corresponding reference voltage are selected as the input of the comparison module 500 to confirm the polarity of the Q signal. Therefore, at the beginning of the next timing, the I signal and the appropriate reference voltage are selected as the input of the comparison module 500 using a successive approximation method to facilitate the confirmation of the reference voltage closest to the I signal, and then the analog signal is quantized into a corresponding digital signal. In the above process, the reference voltage is generated by the reference voltage generation module 300. In the process of generating the reference voltage, the reference voltage generation module 300 consumes less dynamic power to avoid consuming static power, which is conducive to reducing static power consumption.

[0054] Specifically, the reference voltage is generated by the reference voltage generation module 300. In the process of generating the reference voltage, the reference voltage generation module 300 consumes less dynamic power to avoid consuming static power, which is beneficial to reducing static power consumption. Under the control of the logic control module 100, the input voltage selection module 200 and the reference voltage selection module 400 respectively select the Q signal and the corresponding reference voltage as inputs of the comparison module 500 to confirm the polarity of the Q signal. At the beginning of the next timing, the I signal and the appropriate reference voltage are selected as inputs of the comparison module 500 using a successive approximation method to facilitate determining the reference voltage closest to the I signal, thereby quantizing the analog signal into a corresponding digital signal. That is, under the control of the logic control module 100, the analog signal is quantized into a digital signal by comparing it with the corresponding reference voltage, which is beneficial to reducing the static power consumption of the process. In addition, the reference voltage is generated by consuming less dynamic power, thereby also reducing the dynamic power consumption of the process.

[0055] In addition, the polarity of the first clock signal is opposite to that of the second clock signal, which means that at a certain moment, if the polarity of the first clock signal is positive, the polarity of the second clock signal is negative, or if the polarity of the first clock signal is negative, the polarity of the second clock signal is positive; for example, if the first clock signal is a sine signal, the second clock signal is a cosine signal; through the input of the first clock signal and the second clock signal, the reference voltage generation module 300 can generate a reference voltage with a positive polarity and a reference voltage with a negative polarity in a shorter time.

[0056] It should be noted that the logic control module 100 can be implemented using an existing controller. In this embodiment, the logic control module 100 uses an existing logic circuit to control each module. The existing logic circuit is constructed by multiple logic gates, logic devices (e.g., adders, encoders, counters, registers, etc.). That is, the control of each module is achieved through hardware, which is conducive to improving reliability. The reference voltage selection module 400 and the input voltage selection module 200 can both use a voltage selector, such as a 2-to-1 voltage selector, a 4-to-1 voltage selector, or an 8-to-1 voltage selector. The comparison module 500 can use a voltage comparator, such as a hysteresis comparator, a window comparator, or an operational amplifier.

[0057] Reference Figure 2 The reference voltage generating module 300 includes a timing control unit 310, multiple first voltage generating units 320 and multiple second voltage generating units 330. The input end of the timing control unit 310 and the input end of the first voltage generating unit 320 are both used to input the first clock signal, and the input end of the second voltage generating unit 330 is used to input the second clock signal. The output end of the timing control unit 310 is respectively connected to the controlled end of the first voltage generating unit 320 and the controlled end of the second voltage generating unit 330. The input end of the reference voltage selecting module 400 includes a first voltage input end and a second voltage input end. The output end of the first voltage generating unit 320 is connected to the first voltage input end, and the output end of the second voltage generating unit 330 is connected to the second voltage input end.

[0058] The timing control unit 310 is used to output a timing control signal to the first voltage generating unit 320 and the second voltage generating unit 330 to control the operation of the first voltage generating unit 320 and the second voltage generating unit 330. Figure 2 Taking four first voltage generating units 320 and four second voltage generating units 330 as an example, the timing control unit 310 outputs four timing control signals, namely Fr1, Fr2, Fr3 and Fr4, under the action of the first clock signal. One timing control signal controls one first voltage generating unit 320 and one second voltage generating unit 330 respectively, so that the first voltage generating unit 320 and the second voltage generating unit 330 controlled by the same timing control signal can generate a reference voltage at the same time, which is conducive to simplifying the timing control unit 310, thereby reducing the structural complexity of the timing control unit 310 and improving reliability.

[0059] In addition, the first voltage generating unit 320 and the second voltage generating unit 330 can both be implemented using a relatively simple circuit structure to reduce structural complexity and improve reliability; for example, Figure 3 The first voltage generating unit 320 and Figure 4The second voltage generating unit 330 is shown.

[0060] It should be noted that in this embodiment, if the first clock signal is a sine signal, the first voltage generating unit 320 is configured to generate a reference voltage with a positive polarity. If the second clock signal is a cosine signal, the second voltage generating unit 330 is configured to generate a reference voltage with a negative polarity. Furthermore, the simultaneous generation of the reference voltages by the first and second voltage generating units 320 and 330, controlled by the same timing control signal, can reduce the time required to generate the reference voltages and improve the efficiency of analog-to-digital conversion.

[0061] Reference Figure 3 The first voltage generating unit 320 includes a first switching circuit and a first energy storage circuit. The input end of the first switching circuit is used to input the first clock signal. The controlled end of the first switching circuit is connected to the output end of the timing control unit 310. The output end of the first switching circuit is connected to the input end of the first energy storage circuit. The output end of the first energy storage circuit is connected to the first voltage input end of the reference voltage selection module 400.

[0062] Among them, Figure 3 In the embodiment, the switch S1, the switch S2, the switch S3, and the switch S4 are all first switch circuits, the capacitors C1, C2, C3, and C4 are all first energy storage circuits, and the switch S1 and the capacitor C1 form a first voltage generating unit 320, the switch S2 and the capacitor C2 form a first voltage generating unit 320, the switch S3 and the capacitor C3 form a first voltage generating unit 320, and the switch S4 and the capacitor C4 form a first voltage generating unit 320; Figure 3 In the figure, T1 represents the first clock signal. Under the control of the corresponding timing control signal, the first clock signal supplies power to the corresponding first energy storage circuit to store energy, thereby generating a reference voltage. For example, under the action of Fr1, the switch S1 is closed, and the first clock signal charges the capacitor C1, so that the capacitor C1 stores the corresponding reference voltage.

[0063] In addition, Figure 2 and Figure 3 Ref1 to Ref4 respectively represent reference voltages generated by corresponding first energy storage circuits. Under the selection of the reference voltage selection module 400 , the corresponding first energy storage circuit can be selected to discharge, thereby inputting the reference voltage into the comparison module 500 .

[0064] Furthermore, the first voltage generating unit 320 is formed by the first switching circuit and the first energy storage circuit, generating a reference voltage with less dynamic power consumption, thereby avoiding static power consumption and reducing static power consumption. In this embodiment, the first switching circuit is formed by a switch, and the first energy storage circuit is formed by a capacitor, resulting in a simple structure and further facilitating the reduction of dynamic power consumption.

[0065] It should be noted that the first energy storage circuit can also be obtained by connecting multiple capacitors in series or in parallel, and the first switch circuit can also be obtained by connecting multiple switches in series or in parallel. The switches can be devices with switching functions such as transistors or MOS tubes.

[0066] Reference Figure 4 The second voltage generating unit 330 includes a second switching circuit and a second energy storage circuit. The input end of the second switching circuit is used to input the second clock signal. The controlled end of the second switching circuit is connected to the output end of the timing control unit 310. The output end of the second switching circuit is connected to the input end of the second energy storage circuit. The output end of the second energy storage circuit is connected to the second voltage input end of the reference voltage selection module 400.

[0067] Among them, Figure 4 , the switch S5, the switch S6, the switch S7, and the switch S8 are all second switch circuits, the capacitors C5, C6, C7, and C8 are all second energy storage circuits, and the switch S5 and the capacitor C5 form a second voltage generating unit 330, the switch S6 and the capacitor C6 form a second voltage generating unit 330, the switch S7 and the capacitor C7 form a second voltage generating unit 330, and the switch S8 and the capacitor C8 form a second voltage generating unit 330; Figure 3 In the figure, T2 represents the second clock signal. Under the control of the corresponding timing control signal, the second clock signal supplies power to the corresponding second energy storage circuit to store energy, thereby generating a reference voltage. For example, under the action of Fr1, the switch S5 is closed, and the second clock signal charges the capacitor C5, so that the capacitor C5 stores the corresponding reference voltage.

[0068] In addition, Figure 2 and Figure 4 In the figure, -Ref1 to -Ref4 respectively represent reference voltages generated by corresponding second energy storage circuits. Under the selection of the reference voltage selection module 400, the corresponding second energy storage circuit can be selected to discharge, thereby inputting the reference voltage into the comparison module 500.

[0069] Furthermore, the second switching circuit and the second energy storage circuit constitute the second voltage generating unit 330, generating a reference voltage with less dynamic power consumption, thereby avoiding static power consumption and reducing static power consumption. In this embodiment, the second switching circuit is composed of switches, and the second energy storage circuit is composed of capacitors, resulting in a simple structure and further facilitating reduced dynamic power consumption.

[0070] It should be noted that the second energy storage circuit can also be obtained by connecting multiple capacitors in series or in parallel, and the second switch circuit can also be obtained by connecting multiple switches in series or in parallel. The switches can be devices with switching functions such as transistors or MOS tubes.

[0071] Reference Figure 5 The timing control unit 310 includes a phase-locked loop circuit 311 and a demultiplexing circuit 312. The input end of the phase-locked loop circuit 311 is used to input the first clock signal. The output end of the phase-locked loop circuit 311 is connected to the input end of the demultiplexing circuit 312. The output end of the demultiplexing circuit 312 is respectively connected to the controlled end of the first voltage generating unit 320 and the controlled end of the second voltage generating unit 330.

[0072] Among them, the phase-locked loop circuit 311 is used to generate a target signal and keep the phase of the target signal consistent with the input first clock signal. For example, in this embodiment, the frequency of the first clock signal is 1 MHz. After the first clock signal is input into the phase-locked loop circuit 311, the phase-locked loop circuit 311 outputs a 16 MHz target signal to the demultiplexing circuit 312; the demultiplexing circuit 312 can use a demultiplexer to generate a timing control signal. For example, in this embodiment, the demultiplexing circuit 312 decomposes the 16 MHz target signal to obtain 4 timing control signals, namely Fr1, Fr2, Fr3 and Fr4.

[0073] In addition, in this embodiment, the relationship between the four timing control signals and the first clock signal and the second clock signal is as follows: Figure 6 As shown, taking one cycle of the first clock signal as the measurement standard, there is a delay of 0.25 cycles between Fr1 and the first clock signal, a delay of 0.3125 cycles between Fr2 and the first clock signal, a delay of 0.375 cycles between Fr3 and the first clock signal, and a delay of 0.4375 cycles between Fr4 and the first clock signal. Moreover, the pulse widths of Fr1, Fr2, Fr3, and Fr4 are all 0.0625 cycles. In addition, according to actual needs, the number of first voltage generating units 320 and second voltage generating units 330 can also be 2 each, and the timing control unit 310 can be adjusted accordingly to output two timing control signals. Then, there is a delay of 0.25 cycles between one timing control signal and the first clock signal, and a delay of 0.375 cycles between the other timing control signal and the first clock signal. Moreover, the pulse widths of the two timing control signals are both 0.125 cycles.

[0074] The timing control unit 310 outputs multiple different timing control signals, thereby controlling multiple first voltage generating units 320 and multiple second voltage generating units 330 to obtain multiple different reference voltages. This process generates reference voltages by consuming dynamic power, which is beneficial to reducing static power consumption. The structure is simple and also beneficial to reducing dynamic power consumption.

[0075] Reference Figure 7The analog-to-digital converter provided by the present invention also includes a signal buffer module 600. The analog signal includes a baseband in-phase signal and an orthogonal signal. The first input end of the signal buffer module 600 is used to input the baseband in-phase signal, and the second input end of the signal buffer module 600 is used to input the common-mode voltage signal. The controlled end of the signal buffer module 600 is connected to the third control end of the logic control module 100. The input end of the input voltage selection module 200 includes a first signal input end and a second signal input end. The first signal input end is connected to the output end of the signal buffer module 600, and the second signal input end is used to input the orthogonal signal.

[0076] The signal buffer module 600 is used to perform impedance matching on the input signal and eliminate offsets in the input signal to reduce signal distortion. In this embodiment, by inputting a common-mode voltage signal to the signal buffer module 600 and, under the orderly control of the logic control module 100, offsetting the offsets of the common-mode voltage signal generated during the impedance matching process with the offsets of the baseband in-phase signal generated during the impedance matching process, the offsets of the baseband in-phase signal generated during the impedance matching process are eliminated, thereby reducing signal distortion and improving the accuracy and reliability of analog-to-digital conversion.

[0077] In addition, refer to Figure 7 The analog-to-digital converter provided by the present invention may further include a holding module 700, and the input end of the input voltage selection module 200 is used to input an analog signal through the holding module 700. The holding module 700 is used to sample and hold the analog signal so as to input the analog signal into the input voltage selection module 200.

[0078] Reference Figure 8 The baseband in-phase signal includes a first in-phase signal and a second in-phase signal with opposite polarities. The first signal input terminal of the input voltage selection module 200 includes a first in-phase input terminal and a second in-phase input terminal. The third control terminal of the logic control module 100 includes a first signal control terminal and a second signal control terminal. The signal buffer module 600 includes a first signal selection unit 610, a second signal selection unit 620, a first buffer unit 630, a second buffer unit 640, a first offset elimination unit 650 and a second offset elimination unit 660.

[0079] The first input terminal of the first signal selection unit 610 is used to input the first in-phase signal, the first input terminal of the second signal selection unit 620 is used to input the second in-phase signal, and the second input terminal of the first signal selection unit 610, the second input terminal of the second signal selection unit 620, the third input terminal of the first offset elimination unit 650 and the third input terminal of the second offset elimination unit 660 are all used to input the common-mode voltage signal.

[0080] The output end of the first signal selection unit 610 is connected to the first input end of the first offset cancellation unit 650 and the first input end of the second offset cancellation unit 660 respectively through the first buffer unit 630. The output end of the second signal selection unit 620 is connected to the second input end of the first offset cancellation unit 650 and the second input end of the second offset cancellation unit 660 respectively through the second buffer unit 640. The output end of the first offset cancellation unit 650 is connected to the first non-inverting input end, and the output end of the second offset cancellation unit 660 is connected to the second non-inverting input end.

[0081] The controlled end of the first signal selection unit 610, the controlled end of the second signal selection unit 620, the first controlled end of the first offset elimination unit 650, and the first controlled end of the second offset elimination unit 660 are all connected to the first signal control end, and the second controlled end of the first offset elimination unit 650 and the second controlled end of the second offset elimination unit 660 are all connected to the second signal control end.

[0082] exist Figure 8 In the figure, Fs and Fcm are control signals outputted from the first signal control terminal of the logic control module 100, and FSH is a control signal outputted from the second signal control terminal of the logic control module 100; the three control signals Fs, Fcm and FSH are all used to control the orderly operation of the signal buffer module 600.

[0083] Specifically, the logic control module 100 sequentially outputs the two control signals Fs and Fcm through the first signal control terminal, causing the first signal selection unit 610 to sequentially select the first in-phase signal and the common-mode voltage signal as outputs, and causing the second signal selection unit 620 to sequentially select the second in-phase signal and the common-mode voltage signal as outputs. Furthermore, the first offset cancellation unit 650 and the second offset cancellation unit 660 store the offsets of the first in-phase signal, the second in-phase signal, and the common-mode voltage signal. The logic control module 100 then outputs the control signal FSH through the second signal control terminal, causing the first offset cancellation unit 650 to offset the offset of the first in-phase signal with the offset of the common-mode voltage signal, thereby obtaining a first in-phase signal with impedance matching and offset cancellation, and causing the second offset cancellation unit 660 to offset the offset of the second in-phase signal with the offset of the common-mode voltage signal, thereby obtaining a second in-phase signal with impedance matching and offset cancellation.

[0084] Reference Figure 9The first offset elimination unit 650 includes a first selection circuit, a second selection circuit, a first sampling circuit, a second sampling circuit, a third switch circuit, and a fourth switch circuit; the input end of the first selection circuit is connected to the output end of the first buffer unit 630, the input end of the second selection circuit is connected to the output end of the second buffer unit 640, the controlled end of the first selection circuit and the controlled end of the second selection circuit are both connected to the first signal control end, and the controlled end of the third switch circuit and the controlled end of the fourth switch circuit are both connected to the second signal control end; the first end of the first sampling circuit is respectively connected to the first output end of the first selection circuit and the first end of the third switch circuit, the second end of the first sampling circuit is respectively connected to the first output end and the first non-inverting input end of the second selection circuit; the first end of the second sampling circuit is respectively connected to the second output end of the first selection circuit and the second end of the third switch circuit, the second end of the second sampling circuit is respectively connected to the second output end of the second selection circuit and the first end of the fourth switch circuit, and the second end of the fourth switch circuit is used to input a common-mode voltage signal.

[0085] exist Figure 9 In the embodiment, the first selection circuit adopts voltage selector U1, the second selector adopts voltage selector U2, the first sampling circuit adopts capacitor C9, the second sampling circuit adopts capacitor C10, the third switching circuit adopts switch S10, and the fourth switching circuit adopts switch S11. Figure 8 and Figure 9 In , VIn represents the first in-phase signal with impedance matching and offset cancellation, and VIp represents the second in-phase signal with impedance matching and offset cancellation. Figure 10 In the embodiment, the first buffer unit 630 uses the buffer U7, the second buffer unit 640 uses the buffer U8, In represents the first in-phase signal, Ip represents the second in-phase signal, and Vcm represents the common-mode voltage signal.

[0086] It should be noted that, referring to Figure 11 The first selection circuit may also use a switch, such as a triode or a MOS tube, and the second selection circuit may also use a switch, such as a triode or a MOS tube.

[0087] In addition, the structure of the second offset cancellation unit 660 may be the same as that of the first offset cancellation unit 650 to simplify the circuit structure.

[0088] The following combination Figure 9 and Figure 10The principle of the signal buffer module 600 is described below. The logic control module 100 outputs the control signal Fs. The voltage selector U5 causes In to be input into the first offset cancellation unit 650 and the second offset cancellation unit 660 through the buffer U7. Furthermore, the voltage selector U6 causes Ip to be input into the first offset cancellation unit 650 and the second offset cancellation unit 660 through the buffer U8. Due to the mismatch between the buffers U7 and U8, there is an offset in the outputs of the buffers U7 and U8. The capacitor C10 can sample and store the offset of In, and the capacitor C12 can sample and store the offset of Ip. Similarly, the logic control module 100 outputs the control signal Fcm. The voltage selector U5 causes Vcm to be input into the first offset cancellation unit 650 and the second offset cancellation unit 660. The first offset cancellation unit 650 and the second offset cancellation unit 660 are input through the buffer U7. The voltage selector U6 allows Vcm to be input through the buffer U8. The capacitors C9 and C11 respectively sample and store the offset of Vcm. The logic control module 100 outputs the control signal FSH, turning on switches S9 to S12, so that the common-mode voltage signal is input into the first offset cancellation unit 650 and the second offset cancellation unit 660, respectively. This cancels out the offset stored in the capacitors C9 to C12 and the common-mode voltage signal, causing the first offset cancellation unit 650 to output VIn and the second offset cancellation unit 660 to output VIp.

[0089] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the scope of the present invention.

Claims

1. An analog-to-digital converter, characterized in that include: a logic control module, wherein a first input terminal of the logic control module is used to input a first clock signal; an input voltage selection module, wherein a controlled terminal of the input voltage selection module is connected to the first control terminal of the logic control module, and an input terminal of the input voltage selection module is used to input an analog signal; a reference voltage generating module, wherein a first input terminal of the reference voltage generating module is used to input the first clock signal, and a second input terminal of the reference voltage generating module is used to input a second clock signal, wherein the polarity of the second clock signal is opposite to that of the first clock signal; a reference voltage selection module, wherein an input terminal of the reference voltage selection module is connected to an output terminal of the reference voltage generation module, and a controlled terminal of the reference voltage selection module is connected to a first control terminal of the logic control module; A comparison module, wherein a first input end of the comparison module is connected to the output end of the input voltage selection module, a second input end of the comparison module is connected to the output end of the reference voltage selection module, an output end of the comparison module is connected to the second input end of the logic control module, and the output end of the comparison module is used to output a digital signal.

2. The analog-to-digital converter according to claim 1, wherein The reference voltage generation module includes a timing control unit, multiple first voltage generation units and multiple second voltage generation units. The input end of the timing control unit and the input end of the first voltage generation unit are both used to input the first clock signal, and the input end of the second voltage generation unit is used to input the second clock signal. The output end of the timing control unit is respectively connected to the controlled end of the first voltage generation unit and the controlled end of the second voltage generation unit. The input end of the reference voltage selection module includes a first voltage input end and a second voltage input end. The output end of the first voltage generation unit is connected to the first voltage input end, and the output end of the second voltage generation unit is connected to the second voltage input end.

3. The analog-to-digital converter according to claim 2, wherein: The timing control unit includes a phase-locked loop circuit and a demultiplexing circuit, the input end of the phase-locked loop circuit is used to input the first clock signal, the output end of the phase-locked loop circuit is connected to the input end of the demultiplexing circuit, and the output end of the demultiplexing circuit is respectively connected to the controlled end of the first voltage generating unit and the controlled end of the second voltage generating unit.

4. The analog-to-digital converter according to claim 2, wherein: The first voltage generating unit includes a first switching circuit and a first energy storage circuit, the input end of the first switching circuit is used to input the first clock signal, the controlled end of the first switching circuit is connected to the output end of the timing control unit, the output end of the first switching circuit is connected to the input end of the first energy storage circuit, and the output end of the first energy storage circuit is connected to the first voltage input end of the reference voltage selection module.

5. The analog-to-digital converter according to claim 4, wherein: The second voltage generating unit includes a second switching circuit and a second energy storage circuit, the input end of the second switching circuit is used to input the second clock signal, the controlled end of the second switching circuit is connected to the output end of the timing control unit, the output end of the second switching circuit is connected to the input end of the second energy storage circuit, and the output end of the second energy storage circuit is connected to the second voltage input end of the reference voltage selection module.

6. The analog-to-digital converter according to claim 1, wherein: It also includes a signal buffer module, the analog signal includes a baseband in-phase signal and an orthogonal signal, the first input end of the signal buffer module is used to input the baseband in-phase signal, the second input end of the signal buffer module is used to input the common-mode voltage signal, the controlled end of the signal buffer module is connected to the third control end of the logic control module, the input end of the input voltage selection module includes a first signal input end and a second signal input end, the first signal input end is connected to the output end of the signal buffer module, and the second signal input end is used to input the orthogonal signal.

7. The analog-to-digital converter according to claim 6, wherein: The baseband in-phase signal includes a first in-phase signal and a second in-phase signal with opposite polarities, the first signal input terminal of the input voltage selection module includes a first in-phase input terminal and a second in-phase input terminal, the third control terminal of the logic control module includes a first signal control terminal and a second signal control terminal, and the signal buffer module includes a first signal selection unit, a second signal selection unit, a first buffer unit, a second buffer unit, a first offset elimination unit and a second offset elimination unit; The first input terminal of the first signal selection unit is used to input the first in-phase signal, the first input terminal of the second signal selection unit is used to input the second in-phase signal, and the second input terminal of the first signal selection unit, the second input terminal of the second signal selection unit, the third input terminal of the first offset elimination unit, and the third input terminal of the second offset elimination unit are all used to input the common-mode voltage signal; an output terminal of the first signal selection unit connected to a first input terminal of the first offset cancellation unit and a first input terminal of the second offset cancellation unit respectively through the first buffer unit, an output terminal of the second signal selection unit connected to a second input terminal of the first offset cancellation unit and a second input terminal of the second offset cancellation unit respectively through the second buffer unit, an output terminal of the first offset cancellation unit connected to the first non-inverting input terminal, and an output terminal of the second offset cancellation unit connected to the second non-inverting input terminal; The controlled end of the first signal selection unit, the controlled end of the second signal selection unit, the first controlled end of the first offset elimination unit, and the first controlled end of the second offset elimination unit are all connected to the first signal control end, and the second controlled end of the first offset elimination unit and the second controlled end of the second offset elimination unit are both connected to the second signal control end.

8. The analog-to-digital converter according to claim 7, wherein: The first offset elimination unit includes a first selection circuit, a second selection circuit, a first sampling circuit, a second sampling circuit, a third switching circuit and a fourth switching circuit; The input end of the first selection circuit is connected to the output end of the first buffer unit, the input end of the second selection circuit is connected to the output end of the second buffer unit, the controlled end of the first selection circuit and the controlled end of the second selection circuit are both connected to the first signal control end, and the controlled end of the third switch circuit and the controlled end of the fourth switch circuit are both connected to the second signal control end; The first end of the first sampling circuit is connected to the first output end of the first selection circuit and the first end of the third switch circuit respectively, and the second end of the first sampling circuit is connected to the first output end of the second selection circuit and the first non-inverting input end respectively; The first end of the second sampling circuit is respectively connected to the second output end of the first selection circuit and the second end of the third switch circuit, the second end of the second sampling circuit is respectively connected to the second output end of the second selection circuit and the first end of the fourth switch circuit, and the second end of the fourth switch circuit is used to input the common-mode voltage signal.

9. The analog-to-digital converter according to claim 8, wherein: The structure of the second offset cancellation unit is the same as that of the first offset cancellation unit.

10. The analog-to-digital converter according to claim 1, wherein: It also includes a holding module, and the input end of the input voltage selection module is used to input the analog signal through the holding module.

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