VCSEL arrays with different transmitter structures

Abstract

A VCSEL array includes VCSEL structures on a substrate. Each VCSEL structure includes a first reflector region on the substrate, an active region on the first reflector region, a second reflector region on the active region, and an oxide aperture adjacent to the active region. The oxide aperture of the VCSEL structure located in the central region of the VCSEL array is larger than the oxide aperture of the VCSEL structure located in the edge region of the VCSEL array.

Description

Technical Field

[0001] This invention relates to the field of vertical cavity surface-emitting laser (VCSEL) array technology, and in particular, to a VCSEL array with different emitter structures. Background Technology

[0002] Compared to edge-emitting semiconductor lasers with horizontal Fabry-Perot resonators and cleaved surfaces used as mirrors, VCSELs have vertical cavities and can emit circular beams perpendicular to the surface. VCSELs offer numerous advantages over edge-emitting semiconductor lasers, such as compact size, low power input, low temperature sensitivity, low cost, high reliability, and ease of fabrication of two-dimensional (2-D) VCSEL arrays.

[0003] In recent years, VCSEL arrays have played a crucial role in high-resolution 3D sensing applications. For example, many smartphones are equipped with VCSEL-based 3D sensors, using time-of-flight (ToF) or structured light methods for facial recognition. Furthermore, VCSEL-based systems, such as LiDAR (Light Detection and Ranging) systems, have entered the emerging field of autonomous driving. LiDAR is based on the time-of-flight measurement principle. It illuminates a scene with a laser beam. The beam is scattered by objects in the scene. The bounce of the beam is then detected. The distance is calculated based on the time required for the beam to reach and return from the object. LiDAR can create real-time 3D maps of the surrounding environment and helps to effectively and quickly identify vehicles and pedestrians on the road, thus preventing fatal accidents and alleviating one of the most challenging problems facing autonomous vehicles.

[0004] In traditional VCSEL arrays, each VCSEL emitter has the same structure; for example, the VCSEL emitters are all the same size. For instance, the contact metal, p-type reflector region, and oxide aperture are all the same size within the VCSEL emitter. In the early stages of operation, the VCSEL emitters initially have the same temperature and produce the same output power. Subsequently, the heat generated by each individual VCSEL emitter accumulates within the chip, increasing the VCSEL temperature. The VCSEL emitters in the central region have higher temperatures because they are surrounded by other VCSEL emitters that also generate heat. Therefore, the temperature distribution in the VCSEL array gradually increases from the edge regions to the array center. As the temperature of a VCSEL emitter increases, its output power decreases. Consequently, the output light intensity in the center region of the array is lower than that in the edge regions, affecting the uniformity of light intensity. The uniformity of light intensity in a VCSEL array is a crucial factor in 3D sensing. When the light intensity is non-uniform, the quality of 3D sensing is affected.

[0005] Therefore, it is necessary to improve the structure of the VCSEL array and enhance the uniformity of light intensity in the VCSEL array. Summary of the Invention

[0006] This invention discloses a method and apparatus for using VCSEL arrays with different emitter structures. In one aspect, the VCSEL array includes a substrate and VCSEL structures on the substrate. Each VCSEL structure includes a first reflector region formed above the substrate; an active region formed above the first reflector region; a second reflector region formed above the active region; and an oxide aperture formed adjacent to the active region. The oxide aperture of the VCSEL structure located in the central region of the VCSEL array is larger than the oxide aperture of the VCSEL structure located in the edge region of the VCSEL array.

[0007] On the other hand, a method for manufacturing a VCSEL array includes fabricating a plurality of VCSEL structures over a substrate. Fabricating each VCSEL structure includes forming a first reflector region over the substrate; forming an active region over the first reflector region; forming a second reflector region over the active region; and forming an oxide aperture adjacent to the active region, wherein the oxide aperture of the VCSEL structure located in the central region of the VCSEL array is larger than the oxide aperture of the VCSEL structure located in the edge region of the VCSEL array.

[0008] On the other hand, a VCSEL array includes a substrate, a plurality of first VCSEL structures on the substrate, and a plurality of second VCSEL structures on the substrate. Each of the plurality of first VCSEL structures is closer to the central region of the VCSEL array than the plurality of second VCSEL structures, and the size of the oxide pores of the plurality of first VCSEL structures is larger than the size of the oxide pores of the plurality of second VCSEL structures. Attached Figure Description

[0009] The subject matter considered to be the invention is specifically pointed out and explicitly claimed in the claims. The subject matter and other features and advantages of the invention will be described in detail below with reference to the accompanying drawings. Furthermore, the graphic representation first appears with the leftmost numeral.

[0010] Figures 1A and 1B are top and cross-sectional views of a prior art VCSEL array structure.

[0011] Figure 2A and 2B A top view and a cross-sectional view of a VCSEL array according to an embodiment of the present invention are schematically shown.

[0012] Figure 3A and 3BA top view and a cross-sectional view of a VCSEL array according to another embodiment of the present invention are schematically shown.

[0013] Figure 4 A top view of a VCSEL array according to another embodiment of the present invention is shown schematically.

[0014] Figure 5A and 5B A top view and a cross-sectional view of a VCSEL array according to another embodiment of the present invention are schematically shown.

[0015] Figure 6A and 6B A top view and a cross-sectional view of a VCSEL array according to another embodiment of the present invention are schematically shown.

[0016] Figure 7A and 7B A top view and a cross-sectional view of a VCSEL array according to another embodiment of the present invention are schematically shown.

[0017] Figure 8A , 8B Figures 8C schematically illustrate a top view and a cross-sectional view of a VCSEL array according to another embodiment of the present invention.

[0018] Figure 9A , 9B Figure 9C schematically shows a top view of a VCSEL array according to another embodiment of the present invention. Specific Implementation

[0019] The following detailed description of the present invention, in conjunction with the accompanying drawings and embodiments, further clarifies the objectives, technical solutions, and advantages of the invention. It should be noted that the illustrative embodiments discussed in this invention are for illustrative purposes only. The invention is not limited to the disclosed embodiments.

[0020] Figures 1A and 1B show a top view and a cross-sectional view of a prior art VCSEL array 100. Figure 1B shows a cross-sectional view along line AA' of Figure 1A. The VCSEL array 100 includes VCSEL emitters 1-9. The VCSEL emitters are separated by isolation structures (e.g., isolation regions or ion implantation regions). The VCSEL array 100 represents a top-emitting VCSEL array structure. Each VCSEL emitter emits a laser beam through its top surface when powered on. As used herein, VCSEL, VCSEL structure, and VCSEL emitter have the same meaning and are used interchangeably.

[0021] As shown in Figure 1B, the VCSEL emitter (e.g., VCSEL 4, 5, or 6) includes an active region 101, a top reflector region 102, and a bottom reflector region 103, each comprising multiple layers epitaxially grown over a substrate 104. The active region 101 comprises a single quantum well region or a multiple quantum well (MQW) region. The VCSEL emitter also includes an oxide layer 105 forming an oxide aperture 106.

[0022] The top reflector region 102 contains a p-type distributed Bragg reflector (DBR). The bottom reflector region 103 contains an n-type DBR. Reflector regions 102 and 103 are conductive. A metal layer 107, serving as the contact metal, is deposited on the top surface of the reflector region 102, followed by the deposition of a dielectric layer (not shown). A metal layer 108 is deposited on the bottom surface of the substrate 104. Metal layers 107 and 108 serve as the anode and cathode contacts, respectively.

[0023] VCSEL emitters 1-9 have identical dimensions. For example, the area of ​​metal layer 107 is the same for all emitters, as shown in Figure 1A. Furthermore, the area of ​​reflector region 102 is the same for all emitters, and the area of ​​oxide aperture 106 is also the same. During operation, each VCSEL emitter initially generates the same amount of heat. Because emitter 5 is located at the center of array 100 and surrounded by other emitters, emitter 5 has the highest temperature in the array. Therefore, the output power of emitter 5 is adversely affected and becomes lower than the output power of the other emitters. The brightness at the center of the VCSEL array 100 may be lower than the brightness of the edge regions, which can distort the images obtained in 3D sensing applications.

[0024] Figure 2A and 2B A VCSEL array 200 according to an embodiment of the present invention is illustrated schematically. Figure 2A The image shown is a top view. Figure 2B The following is along Figure 2A A cross-sectional view of line BB'. VCSEL arrays, such as array 200, can include thousands or tens of thousands of VCSEL transmitters or VCSELs. Figure 2A and 2B And in the other figures shown below, only a few VCSELs are used to explain the principles and methods of VCSEL arrays.

[0025] like Figure 2A and 2BAs shown, array 200 may include VCSELs 1-9. VCSEL 5 is located at the center of the array and is surrounded by VCSELs 1-4 and 6-9. In the XY plane, some dimensions of VCSEL 5 are larger than the dimensions of VCSELs 1-4 and 6-9. VCSEL 5 may include an active region 201, a top reflector region 202, a bottom reflector region 203, and an oxide layer 204 forming an oxide aperture 205. VCSELs 1-4 and 6-9 may each include an active region 211, a top reflector region 212, a bottom reflector region 213, and an oxide layer 214 forming an oxide aperture 215. Regions 201-203 and 211-213 each include multiple layers epitaxially grown on substrate 206. Top reflector regions 202 and 212 may include conductive p-type DBR structures. Bottom reflector regions 203 and 213 may include conductive n-type DBR structures. In some embodiments, substrate 206 may include an n-type substrate, such as an n-type gallium arsenide (GaAs) substrate or an indium phosphide (InP) substrate. In some embodiments, active regions 201 and 211 may include MQW regions.

[0026] Regions 203 and 213, 201 and 211, and 202 and 212 are sequentially formed during epitaxial growth. For example, regions 203 and 213 can be epitaxially grown on substrate 206, regions 201 and 211 can be epitaxially grown on regions 203 and 213, and regions 202 and 212 can be epitaxially grown on regions 201 and 211, respectively. After forming regions 201-203 and 211-213 during epitaxial growth, a metal deposition process can be performed to form metal layers 207 and 216 on portions of regions 202 and 212, respectively. The metal layers 207 and 216, serving as contact metals, are electrically contacted with the p+ layer of the DBR structure, and thus electrically connected to the top reflector regions 202 and 212, respectively. A dielectric layer (not shown) having a material such as silicon nitride or silicon oxide can then be deposited. For example, dielectric layers can be formed on metal layers 207 and 216 and on portions of regions 202 and 212 that are not covered by metal layers 207 and 216.

[0027] Subsequently, a selective etching process, such as selective dry etching or wet-dry etching, can be performed to form openings (not shown) in the VCSELs 1-9 of the discrete array 200. In some embodiments, the openings may extend vertically through the top reflector regions 202 and 212, the active regions 201 and 211, and at least partially through the bottom reflector regions 203 and 213. The selective etching process exposes the sides of the aluminum-rich or relatively high-aluminum-content layer near the active regions 201 or 211.

[0028] Then, a wet oxidation process is performed to oxidize the aluminum-rich layer and form oxide layers 204 and 214. Oxide layers 204 and 214 are arranged to form oxide apertures 205 and 215, respectively. The laser output beam of each VCSEL emitter is aligned with oxide aperture 205 or 215. Figure 2B As shown, the top reflector region 202, oxide aperture 205, active region 201, and bottom reflector 203 form an optical cavity or laser cavity. Similarly, the top reflector region 212, oxide aperture 215, active region 211, and bottom reflector 213 also form an optical cavity or laser cavity. The oxide aperture, such as oxide aperture 205 or 215, is used not only to form the laser cavity but also to guide current through the central region of the cavity.

[0029] After forming oxide layers 204 and 214 and oxide apertures 205 and 215, the openings can be filled with a dielectric material (e.g., silicon oxide and / or silicon nitride) to form isolation region 209. Isolation region 209 extends vertically through top reflector regions 202 and 212, active regions 201 and 211, and at least partially through bottom reflector regions 203 and 213.

[0030] Subsequently, other manufacturing processes (e.g., forming pad metal layers connected to metal layers 207 and 216) are performed to complete the fabrication of the VCSEL array 200. For example, a metal layer 208 may be deposited on the bottom surface of the substrate 206. Metal layers 207 and 216 serve as the anode of the VCSEL array 200, and metal layer 208 serves as the cathode of the array 200.

[0031] As mentioned above, some dimensions of VCSEL 5 may be larger than those of VCSEL 1-4 and 6-9. In some embodiments, such as Figure 2A As shown, metal layers 207 and 216 can be annular. The area of ​​metal layer 207 can be larger than the area of ​​metal layer 216. Furthermore, region 202 can be larger than region 212, and the oxide aperture 205 can be larger than the oxide aperture 215. Therefore, the series resistance of the VCSEL5 can be the smallest in array 200.

[0032] Because VCSELs 1-9 are electrically coupled in parallel, and VCSEL 5 has the smallest series resistance, it has the largest input current, resulting in the largest output power. Since VCSEL 5 is located at the center of array 200 and experiences the highest temperature among the VCSELs in array 200, its output drops the most during operation. VCSEL 5 can be configured to maintain a similar output power level to the other VCSELs in array 200 after its output power decreases due to increased operating temperature. Therefore, the light intensity uniformity of array 200 can be improved by configuring VCSELs of different sizes.

[0033] Figure 3A and 3B A VCSEL array 300 according to another embodiment of the present invention is illustrated schematically. Figure 3A The image shown is a top view. Figure 3B The following is along Figure 3A A cross-sectional view of line CC'. (See figure) Figure 3A and 3B As shown, array 300 may include VCSELs 1-9. VCSEL 5 is located at the center of the array and is surrounded by VCSELs 1-4 and 6-9. VCSELs 1-9 may include an active region 301, a top reflector region 302, a bottom reflector region 303, and an oxide layer 304 forming an oxide aperture 305. Regions 301-303 may each include multiple layers epitaxially grown on substrate 306. Top reflector region 302 may include a conductive p-type DBR structure. Bottom reflector region 303 may include a conductive n-type DBR structure. In some embodiments, substrate 306 may include an n-type substrate, such as an n-type GaAs substrate or an InP substrate. In some embodiments, active region 301 may include an MQW region.

[0034] Regions 303, 301, and 302 are sequentially formed during epitaxial growth. For example, region 303 can be epitaxially grown on substrate 306, region 301 can be epitaxially grown on region 303, and region 302 can be epitaxially grown on region 301. After regions 301-303 are formed during epitaxial growth, a metal deposition process can be performed to form metal layers 307 and 310 on portions of region 302. The area of ​​layer 307 is configured to be larger than the area of ​​layer 310. Metal layer 307 is deposited on region 302 of VCSEL 5, and metal layer 310 is deposited on regions 302 of VCSELs 1-4 and 6-9, respectively. Therefore, metal layers 307 and 310, as contact metals, are electrically contacted with the p+ layer of the DBR structure and electrically connected to the top reflector region 302, respectively. Then, a dielectric layer (not shown) having a dielectric material (e.g., silicon nitride or silicon oxide) can be deposited. For example, a dielectric layer can be formed on metal layers 307 and 310 and on the portion of region 302 not covered by metal layers 307 and 310.

[0035] Subsequently, a selective etching process, such as selective dry etching or wet-dry etching, can be performed to form openings (not shown) in the VCSELs 1-9 of the discrete array 300. In some embodiments, the openings may extend vertically through the top reflector region 302, the active region 301, and at least partially through the bottom reflector region 303. The selective etching process exposes the sides of the aluminum-rich layer disposed near the active region 301.

[0036] Next, a wet oxidation process is performed to oxidize the aluminum-rich layer and form an oxide layer 304. The oxide layer 304 is arranged to form oxide apertures 305 for the VCSEL. The laser output beam of each VCSEL is aligned with one of the oxide apertures 305.

[0037] After forming the oxide layer 304 and oxide aperture 305, the openings can be filled with a dielectric material (e.g., silicon oxide and / or silicon nitride) to form an isolation region 309. The isolation region 309 may extend vertically through the top reflector region 302, the active region 301, and at least partially through the bottom reflector region 303.

[0038] Subsequently, other manufacturing processes (e.g., forming pad metal layers connected to metal layers 307 and 310) are performed to complete the fabrication of the VCSEL array 300. For example, a metal layer 308 may be deposited on the bottom surface of the substrate 306. Metal layers 307 and 310 may be used as the anode of the VCSEL array 300, and metal layer 308 may be used as the cathode of the array 300.

[0039] As described above, metal layer 307 is larger than metal layer 310, and other dimensions of VCSEL 1-9, such as the dimensions of the top reflector region 302 and the oxide aperture 305, are the same. Figure 2A As shown, metal layers 307 and 310 are annular rings with the same inner diameter. Because layer 307 has a larger outer diameter, its area is larger than that of layer 310. Therefore, the series resistance of VCSEL 5 may be smaller compared to VCSELs 1-4 and 6-9.

[0040] Because VCSELs 1-9 of array 300 are electrically coupled in parallel, and VCSEL 5 has the smallest series resistance, it has the largest input current, and thus the largest output power. Since VCSEL 5 is located at the center of array 300 and has the highest temperature among the VCSELs in array 300, its output power may decrease the most during operation. VCSEL 5 can be configured to have an output power level similar to other VCSELs in array 300 after its output power decreases due to increased operating temperature. Therefore, the light intensity uniformity of array 300 can be improved by making metal layer 307 larger than metal layer 310.

[0041] Figure 4 A top view of a VCSEL array 400 according to another embodiment of the present invention is schematically shown. Figure 3A and 3B Compared to the VCSEL array 300 shown, array 400 has more VCSEL transmitters. For example... Figure 4As shown, array 400 may include VCSEL A located at the center of array 400, multiple VCSEL B surrounding VCSEL A, and multiple VCSELCs surrounding VCSEL B. Therefore, VCSEL B is located between the center and edge regions of the array, and VCSEL C is located in the edge region. Since VCSEL A is located in the center region of array 400, its temperature is likely to be the highest among the multiple VCSELs during operation of array 400. Since VCSEL B is located between the center and edge regions of the array, its temperature may be lower than VCSEL A but higher than VCSEL C during operation.

[0042] Similar to the VCSEL of array 300, the VCSEL of array 400 includes an active region, a top reflector region, a bottom reflector region, and an oxide layer forming oxide apertures. The top and bottom reflector regions may include a conductive p-type DBR structure and a conductive n-type DBR structure, respectively. The active region includes an MQW region.

[0043] Similar to the manufacturing process of VCSEL array 300, a metal deposition process can be performed to form metal layers 410, 420, and 430 as contact metals on portions of the top reflector region. Metal layer 410 is deposited on region A of VCSEL, metal layer 420 is deposited on region B of VCSEL, and metal layer 430 is deposited on region C of VCSEL. Metal layers 410, 420, and 430 are electrically contacted with the p+ layer of the DBR structure and electrically connected to the top reflector region of array 400, respectively.

[0044] like Figure 4 As shown, the area of ​​layer 410 is configured to be larger than the area of ​​layer 420, and the area of ​​layer 420 is configured to be larger than the area of ​​layer 430. VCSELs A, B, and C can have the same dimensions, but the areas of metal layers 410, 420, and 430 are different. Therefore, VCSEL A has the smallest series resistance, VCSEL B has a series resistance greater than VCSEL A but less than VCSEL C, and VCSEL C has the largest series resistance.

[0045] VCSELs A, B, and C in array 400 are electrically coupled in parallel. VCSEL A has the lowest series resistance and the highest input current, resulting in the highest output power. VCSEL C has the highest series resistance and therefore the lowest output power. VCSEL B's output power is less than VCSEL A's but greater than VCSEL C's. During array 400 operation, VCSEL A's output power may decrease the most due to its central location and highest temperature. VCSEL A can be configured to have an output power similar to that of VCSEL C in array 400 after its output power decreases due to increased operating temperature. Similarly, VCSEL B can be configured to have an output power similar to that of VCSEL C in array 400 after its output power decreases due to increased operating temperature. Therefore, the light intensity uniformity of array 400 can be improved by configuring VCSELs with metal layers of different sizes. For example, when one VCSEL is closer to the center of array 400 than another VCSEL, the metal layer of that VCSEL can be configured to be larger than the metal layer of the other VCSEL.

[0046] Figure 5A and 5B A VCSEL array 500 according to another embodiment of the present invention is illustrated schematically. Figure 5A The image shown is a top view. Figure 5B The following is along Figure 5A A cross-sectional view of line DD'. (See figure) Figure 5A and 5B As shown, array 500 includes VCSELs 1-9. VCSEL 5 is located at the center of array 500 and is surrounded by VCSELs 1-4 and 6-9. Each VCSEL includes an active region 501, a top reflector region 502, a bottom reflector region 503, and an oxide layer 504 forming an oxide aperture 505. VCSELs 1-4 and 6-9 include an active region 511, a top reflector region 512, a bottom reflector region 513, and an oxide layer 514 forming an oxide aperture 515. Regions 501-503 and 511-513 each include multiple layers epitaxially grown on substrate 506. Top reflector regions 502 and 512 include conductive p-type DBR structures. Bottom reflector regions 503 and 513 include conductive n-type DBR structures. In some embodiments, substrate 506 includes an n-type substrate, such as an n-type GaAs substrate or an InP substrate. In some embodiments, active regions 501 and 511 include MQW regions.

[0047] Regions 503 and 513, 501 and 511, and 502 and 512 are sequentially formed during epitaxial growth. After forming regions 501-503 and 511-513 during epitaxial growth, a metal deposition process is performed to form metal layers 507 and 516 on portions of regions 502 and 512. Layers 507 and 516 can be configured to have the same shape and size. Metal layer 507 is deposited on region 502 of VCSEL 5, and metal layer 516 is deposited on regions 512 of VCSELs 1-4 and 6-9, respectively. Thus, metal layers 507 and 516 are electrically contacted with the p+ layer of the DBR structure and electrically connected to the top reflector regions 502 and 512, respectively. Then, a dielectric layer (not shown) with a dielectric material (e.g., silicon nitride or silicon oxide) is deposited. For example, dielectric layers can be deposited on metal layers 507 and 516, as well as on regions 502 and 512 that are not covered by metal layers 507 and 516.

[0048] Subsequently, a selective etching process, such as selective dry etching or wet-dry etching, may be performed to form openings 509 in the VCSELs 1-9 of the discrete array 500. In some embodiments, the openings 509 extend vertically through the top reflector regions 502 and 512, the active regions 501 and 511, and at least partially through the bottom reflector regions 503 and 513.

[0049] like Figure 5A and 5B As shown, a selective etching process forms top reflector regions 502 and 512, which are gear-shaped in the XY plane (e.g., a plane parallel to the substrate 506). The gear in region 502 is larger than the gear in region 512. Therefore, the area of ​​region 502 is larger than the area of ​​region 512. To some extent, the area of ​​region 503 is also larger than the area of ​​region 513.

[0050] A selective etching process exposes the sides of the aluminum-rich layer disposed near the active regions 501 and 511. Next, a wet oxidation process is performed to oxidize the aluminum-rich layer and form oxide layers 504 and 514. Oxide layers 504 and 514 are used to form oxide apertures 505 and 515 of the VCSEL. Oxide apertures 505 and 515 are of identical size. The laser output beam of each VCSEL is aligned with one of oxide apertures 505 and 515.

[0051] Since the oxide apertures and metal layers 507 and 516 of VCSELs 1-9 have the same dimensions, VCSEL 5 has the smallest series resistance because the top reflector region 502 is larger than the top reflector region 512. Similar to arrays 200, 300, and 400, the difference in series resistance can be used to improve the light intensity uniformity of VCSEL array 500.

[0052] In some embodiments, after forming oxide layers 504 and 514 and oxide apertures 505 and 515, a dielectric material (e.g., silicon oxide and / or silicon nitride) can be filled into the opening 509. Other fabrication processes are then performed to complete the fabrication of the VCSEL array 500. For example, a metal layer 508 can be deposited on the bottom surface of the substrate 506. Metal layers 507 and 516 can be used as the anode of the VCSEL array 500, and metal layer 508 can be used as the cathode of the array 500.

[0053] As described above, among the VCSELs in array 500, VCSEL 5 has the smallest series resistance. Since VCSELs 1-9 in array 500 are electrically coupled in parallel, and VCSEL 5 has the smallest series resistance, it has the largest input current, and thus the largest output power. Because VCSEL 5 is located at the center of array 500 and has the highest temperature among the VCSELs, its output power may decrease the most during operation. Therefore, VCSEL 5 can be configured to have an output power level similar to that of the other VCSELs in array 500 after its output power decreases due to increased operating temperature. Therefore, the light intensity uniformity of array 500 can be improved by configuring VCSELs with different top reflector regions.

[0054] In some embodiments, array 500 may include more than nine VCSELs. For example, array 500 may include some VCSELs located in the central region of the array, some VCSELs located in the edge region, and some VCSELs located between the central and edge regions. The VCSELs of the array can then be configured according to the distance between the VCSELs and the array center. If one VCSEL is closer to the array center than another VCSEL, that VCSEL has a larger top reflector area, resulting in a smaller series resistance than the other VCSEL, which in turn improves the light intensity uniformity of the array.

[0055] Figure 6A and 6B A VCSEL array 600 according to another embodiment of the present invention is illustrated schematically. Figure 6A The image shown is a top view. Figure 6B The following is along Figure 6A A cross-sectional view of line EE'. (See diagram below.) Figure 6A and 6BAs shown, array 600 includes VCSELs 1-9. VCSEL 5 is located at the center of array 600 and is surrounded by VCSELs 1-4 and 6-9. VCSEL 5 includes an active region 601, a top reflector region 602, a bottom reflector region 603, and an oxide layer 604 forming an oxide aperture 605. VCSELs 1-4 and 6-9 include an active region 611, a top reflector region 612, a bottom reflector region 613, and an oxide layer 614 forming an oxide aperture 615. Regions 601-603 and 611-613 each include multiple layers epitaxially grown on substrate 606. Top reflector regions 602 and 612 include conductive p-type DBR structures. Bottom reflector regions 603 and 613 include conductive n-type DBR structures. In some embodiments, substrate 606 includes an n-type substrate, such as an n-type GaAs substrate or an InP substrate. In some embodiments, active regions 601 and 611 include MQW regions.

[0056] Regions 603 and 613, 601 and 611, and 602 and 612 are sequentially deposited during epitaxial growth. After regions 601-603 and 611-613 are formed during epitaxial growth, a metal deposition process is performed to form metal layers 607 and 616 on portions of regions 602 and 612. Layers 607 and 616 have the same shape and size. Metal layer 607 is deposited on region 602 of VCSEL 5, and metal layer 616 is deposited on regions 612 of VCSELs 1-4 and 6-9, respectively. Thus, metal layers 607 and 616 are electrically contacted with the p+ layer of the DBR structure and electrically connected to the top reflector regions 602 and 612, respectively. A dielectric layer (not shown) with a dielectric material (e.g., silicon nitride or silicon oxide) can then be deposited. For example, dielectric layers can be deposited on metal layers 607 and 616, as well as on regions 602 and 612 that are not covered by metal layers 607 and 616.

[0057] Subsequently, a selective etching process, such as selective dry etching or wet-dry etching, can be performed to form openings 609 and 617 surrounding VCSEL 5 and VCSELs 1-4 and 6-9, respectively. In some embodiments, openings 609 and 617 extend vertically through top reflector regions 602 and 612, active regions 601 and 611, and bottom reflector regions 603 and 613, and reach the substrate 606. In some embodiments, openings 609 and 617 may extend through top reflector regions 602 and 612, active regions 601 and 611, and partially through bottom reflector regions 603 and 613.

[0058] A selective etching process exposes the sides of the aluminum-rich layer disposed near the active regions 601 and 611. Next, a wet oxidation process is performed to oxidize the aluminum-rich layer and form oxide layers 604 and 614. Oxide layers 604 and 614 form oxide apertures 605 and 615 for the VCSEL. Oxide apertures 605 and 615 have the same or similar dimensions. The laser output beam of each VCSEL is aligned with one of oxide apertures 605 and 615.

[0059] Following the wet oxidation process, an ion implantation process is performed to form an ion implantation region 610, which serves as an isolation region to separate the VCSELs 1-9 of the array 600. For example... Figure 6A and 6B As shown, selective etching and ion implantation processes form top reflector regions 602 and 612, which have a gear shape in the XY plane (a plane parallel to the substrate 606). The gear in region 602 is larger than the gear in region 612. Therefore, the area of ​​region 602 is larger than the area of ​​region 612. To some extent, the area of ​​region 603 is also larger than the area of ​​region 613. In some embodiments, the ion implantation process may be performed before the selective etching process.

[0060] Since the metal layers 607 and 616 of VCSELs 1-9 have the same dimensions, and the oxide apertures have the same or similar dimensions, VCSEL 5 has the smallest series resistance because the top reflector region 602 is larger than the top reflector region 612. Similar to arrays 200-500, the difference in series resistance can be used to improve the light intensity uniformity of VCSEL array 600.

[0061] In some embodiments, after forming oxide layers 604 and 614 and oxide apertures 605 and 615, dielectric material can be filled into openings 609 and 617. Then, other fabrication processes are performed to complete the fabrication of the VCSEL array 600. For example, a metal layer 608 can be deposited on the bottom surface of substrate 606. Metal layers 607 and 616 can be used as the anode of the VCSEL array 600, and metal layer 608 can be used as the cathode of the array 600.

[0062] As described above, among the VCSELs in array 600, VCSEL 5 has the smallest series resistance. Because VCSELs 1-9 in array 600 are electrically coupled in parallel, and VCSEL 5 has the smallest series resistance, it has the largest input current, and thus the largest output power. Since VCSEL 5 is located at the center of array 600 and experiences the largest temperature rise among the VCSELs, its output power is likely to decrease the most during operation. Therefore, VCSEL 5 can be configured to have an output power level similar to the other VCSELs in array 600 after its output power decreases due to temperature rise during operation. Therefore, the light intensity uniformity of array 600 can be improved by configuring VCSELs with different top reflector regions.

[0063] In some embodiments, array 600 may include more than nine VCSELs. For example, multiple VCSELs may exist between the VCSEL located at the center of array 600 and the VCSELs located at the edges of the array. The VCSELs of the array can then be configured according to the distance between the VCSELs and the array center. If one VCSEL is closer to the array center than another VCSEL, that VCSEL can be configured to have a larger top reflector region, resulting in a smaller series resistance than the other VCSEL, thereby improving the light intensity uniformity of the array.

[0064] Figure 7A and 7B A VCSEL array 700 according to another embodiment of the present invention is illustrated schematically. Figure 7A The image shown is a top view. Figure 7B The following is along Figure 7A A cross-sectional view of line FF'. (See figure) Figure 7A and 7B As shown, array 700 includes VCSELs 1-9. VCSEL 5 is located at the center of array 700 and is surrounded by VCSELs 1-4 and 6-9. VCSEL 5 includes an active region 701, a top reflector region 702, a bottom reflector region 703, and an oxide layer 704 forming an oxide aperture 705. VCSELs 1-4 and 6-9 include an active region 711, a top reflector region 712, a bottom reflector region 713, and an oxide layer 714 forming an oxide aperture 715. Regions 701-703 and 711-713 each include multiple layers epitaxially grown on substrate 706. Top reflector regions 702 and 712 include conductive p-type DBR structures. Bottom reflector regions 703 and 713 include conductive n-type DBR structures. In some embodiments, substrate 706 may include an n-type substrate, such as an n-type GaAs substrate or an InP substrate. In some embodiments, active regions 701 and 711 include MQW regions.

[0065] Regions 703 and 713, 701 and 711, and 702 and 712 are sequentially deposited during epitaxial growth. After regions 701-703 and 711-713 are formed during epitaxial growth, a metal deposition process is performed to form metal layers 707 and 716 on portions of regions 702 and 712. Layers 707 and 716 have the same size and shape. Metal layer 707 is deposited on region 702 of VCSEL 5, and metal layer 716 is deposited on regions 712 of VCSELs 1-4 and 6-9, respectively. Thus, metal layers 707 and 716 are electrically contacted with the p+ layer of the DBR structure and electrically connected to the top reflector regions 702 and 712, respectively. A dielectric layer (not shown) with a dielectric material (e.g., silicon nitride or silicon oxide) can then be deposited. For example, a dielectric layer can be deposited to cover metal layers 707 and 716 as well as portions of regions 702 and 712 that are not blocked by metal layers 707 and 716.

[0066] Subsequently, a selective etching process, such as selective dry etching or wet-dry etching, is performed to form openings 709 and 717 surrounding VCSEL 5 and VCSELs 1-4 and 6-9, respectively. In some embodiments, openings 709 and 717 have the same dimensions and extend vertically through the top reflector regions 702 and 712, the active regions 701 and 711, and the bottom reflector regions 703 and 713, reaching the substrate 706. In some embodiments, openings 709 and 717 may extend through the top reflector regions 702 and 712, the active regions 701 and 711, and partially through the bottom reflector regions 703 and 713.

[0067] A selective etching process exposes the sides of the aluminum-rich layer disposed near the active regions 701 and 711. A wet oxidation process is then performed to oxidize the aluminum-rich layer and form oxide layers 704 and 714. Oxide layers 704 and 714 are used to form oxide apertures 705 and 715 of the VCSEL. Oxide apertures 705 and 715 have the same dimensions. The laser output beam of each VCSEL is aligned with one of oxide apertures 705 and 715.

[0068] Following the wet oxidation process, an ion implantation process is performed to form ion implantation regions 710 and 718, electrically isolating the VCSELs 1-9 of the array 700. (See also...) Figure 7A and 7BAs shown, selective etching and ion implantation processes form gear-shaped top reflector regions 702 and 712 on the XY plane. The gear in region 702 is larger than the gear in region 712, and the area of ​​region 702 is larger than the area of ​​region 712. Region 718 is adjacent to the gear in region 712 and serves to reduce the speed of region 712. To some extent, the area of ​​region 703 is also larger than the area of ​​region 713. In some embodiments, the ion implantation process may be performed before the selective etching process.

[0069] Since the oxide apertures 705 and 715 and the metal layers 707 and 716 of VCSELs 1-9 have the same dimensions, VCSEL 5 has the smallest series resistance because the top reflector region 702 is larger than the top reflector region 712. Similar to arrays 200-600, the difference in series resistance can be used to improve the light intensity uniformity of VCSEL array 700.

[0070] In some embodiments, after forming oxide layers 704 and 714 and oxide apertures 705 and 715, dielectric material can be filled into openings 709 and 717. Then, other fabrication processes are performed to complete the fabrication of the VCSEL array 700. For example, a metal layer 708 can be deposited on the bottom surface of substrate 706. Metal layers 707 and 716 can be used as the anode of the VCSEL array 700, and metal layer 708 can be used as the cathode of the array 700.

[0071] As described above, VCSEL 5 has the lowest series resistance among the VCSELs in array 700. Since VCSELs 1-9 of array 700 are electrically coupled in parallel, and VCSEL 5 has the lowest series resistance, it has the highest input current, resulting in the highest output power. Because VCSEL 5 is located at the center of array 700 and experiences the greatest temperature rise among the VCSELs in array 700, its output power may decrease the most during operation. Therefore, VCSEL 5 can be configured such that its output power, after decreasing due to temperature rise during operation, is similar to that of the other VCSELs in array 700. Thus, the light intensity uniformity of array 700 can be improved by configuring different top reflector regions.

[0072] In some embodiments, array 700 may include more than nine VCSELs. For example, multiple VCSELs may exist between the VCSEL located at the center of array 700 and the VCSELs located at the edges of the array. The VCSELs of the array can then be configured according to the distance between the VCSELs and the array center. If one VCSEL is closer to the array center than another VCSEL, that VCSEL may have a larger top reflector area than the other VCSEL, thereby improving the light intensity uniformity of the array.

[0073] Figure 8A , 8B The diagram above (8C) schematically illustrates a VCSEL array 800 according to another embodiment of the present invention. Figure 8A The image shown is a top view in the XY plane. Figure 8B and 8C The figure shows the XZ plane along Figure 8A A cross-sectional view of line GG'. (See figure) Figures 8A-8C As shown, array 800 includes VCSELs 1-9. VCSEL 5 is located in the central region of array 800 and is surrounded by VCSELs 1-4 and 6-9. VCSEL 5 includes an active region 801, a top reflector region 802, a bottom reflector region 803, and an aluminum-rich layer 804. VCSELs 1-4 and 6-9 include an active region 811, a top reflector region 812, a bottom reflector region 813, and an aluminum-rich layer 814. Aluminum-rich layers 804 and 814 include a single aluminum-rich layer or multiple aluminum-rich layers and are respectively arranged near the active regions 801 and 811. In some embodiments, after forming the active regions 801 and 811, aluminum-rich layers 804 and 814 are grown and arranged on top of the active layers, as shown. Figure 8B As shown. Alternatively, aluminum-rich layers 804 and 814 are grown and disposed below the active regions 801 and 811 before forming the active regions. Regions 801-803 and 811-813 each comprise multiple layers epitaxially grown on substrate 806. Top reflector regions 802 and 812 comprise conductive p-type DBR structures. Bottom reflector regions 803 and 813 comprise conductive n-type DBR structures. In some embodiments, substrate 806 may comprise an n-type substrate, such as an n-type GaAs substrate or an InP substrate. In some embodiments, active regions 801 and 811 comprise MQW regions.

[0074] Regions 803 and 813, 801 and 811, and 802 and 812 are sequentially formed during epitaxial growth. After regions 801-803 and 811-813 are formed during epitaxial growth, a metal deposition process is performed to form metal layers 807 and 816 on portions of regions 802 and 812. Metal layers 807 and 816 have the same size and shape. Metal layer 807 is deposited on region 802 of VCSEL 5, and metal layer 816 is deposited on regions 812 of VCSELs 1-4 and 6-9, respectively. Metal layers 807 and 816 are electrically contacted with the p+ layer of the DBR structure and electrically connected to the top reflector regions 802 and 812, respectively. Then, a dielectric layer (not shown) having a dielectric material (e.g., silicon nitride or silicon oxide) is deposited. For example, the dielectric layer may be deposited on metal layers 807 and 816 and on portions of regions 802 and 812 not covered by metal layers 807 and 816.

[0075] Subsequently, a selective etching process, such as selective dry etching or wet-dry etching, is performed to form openings 809 surrounding VCSEL 5 of array 800 and openings 817 surrounding VCSELs 1-4 and 6-9, respectively. In some embodiments, openings 809 and 817 extend vertically through top reflector regions 802 and 812, active regions 801 and 811, and at least partially through bottom reflector regions 803 and 813. Optionally, openings 809 and 817 comprise a pair of openings, and the pair of openings may be symmetrical about the center of the VCSEL structure in the XY plane, such as... Figure 8A As shown.

[0076] like Figures 8A-8B As shown, openings 809 and 817 have curved inner edges that face the center of the VCSEL structure and are concentric with respect to the center of the VCSEL structure. The distance between opening 809 and the center of VCSEL 5 is S1, and the distance between opening 817 and the center of any one of VCSELs 1-5 and 6-9 is S2. Optionally, S1 or S2 can be the distance between the inner edge of opening 809 or 817 and the center of the respective VCSEL. In some embodiments, such as as described below, S1 can be greater than S2.

[0077] A selective etching process exposes the sides of the aluminum-rich layers 804 and 814 in openings 809 and 817. Next, a wet oxidation process is performed to partially oxidize the aluminum-rich layers 804 and 814 and form oxide layers 810 and 818. Oxide layers 810 and 818 are initially formed around openings 809 and 817 and then extend inward to form oxide apertures 805 and 815 for the VCSEL, as shown. Figure 8CAs shown. The lateral oxidation rates of the aluminum-rich layers 804 and 814 are uniformly arranged. Therefore, the oxide pores 805 and 815 have circular or near-circular shapes. The diameter of the oxide pores is determined by the value of S1 or S2, the lateral oxidation rate, and the oxidation time. After the oxidation process is complete, the remaining aluminum-rich layer remains in the oxide pores. For simplicity, Figure 8C The remaining aluminum-rich layer is omitted. Let D1 and D2 be the diameters of the oxide apertures 805 and 815, respectively. Because S1 is greater than S2, D1 is greater than D2. Furthermore, the areas of the active region, top reflector region, and bottom reflector region of VCSEL 5 can be larger than the areas of VCSELs 1-4 and 6-9, respectively. Alternatively, the areas of the active region, top reflector region, and bottom reflector region of VCSELs 1-9 can be arranged to be the same or similar. In the following description, as an example, the areas of the active region, top reflector region, and bottom reflector region of VCSEL 5 are larger than the areas of VCSELs 1-4 and 6-9, respectively. The laser output beam of the VCSEL is aligned with the oxide apertures 805 and 815, respectively.

[0078] Since the metal layers 807 and 816 of VCSELs 1-9 have the same dimensions, VCSEL 5 has the smallest series resistance in the VCSEL array 800 because it has the largest oxide aperture, active region, top reflector region, and bottom reflector region. Similar to the VCSEL arrays mentioned above, the difference in series resistance can be used to improve the light intensity uniformity of the VCSEL array 800.

[0079] In some embodiments, after forming oxide layers 810 and 818 and oxide apertures 805 and 815, dielectric material (e.g., silicon oxide and / or silicon nitride) can be filled into openings 809 and 817. Other fabrication processes are then performed to complete the fabrication of the VCSEL array 800. For example, isolation trenches or isolation regions can be formed to surround and isolate each VCSEL. A metal layer 808 is deposited on the bottom surface of substrate 806. Metal layers 807 and 816 can serve as the anode of the VCSEL array 800, and metal layer 808 can serve as the cathode of the array.

[0080] As mentioned above, among the VCSELs in array 800, VCSEL 5 has the lowest series resistance. Since VCSELs 1-9 in array 800 are electrically coupled in parallel, and VCSEL 5 has the lowest series resistance, it has the highest input current, and thus the highest output power. Because VCSEL 5 is located in the central region of array 800 and experiences the highest temperature among all VCSELs, its output power may decrease the most during operation. Therefore, VCSEL 5 can be configured to have an output power similar to that of the other VCSELs in array 800 after its output power decreases due to increased operating temperature. Thus, the intensity uniformity of array 800 can be improved by configuring VCSELs with different oxide apertures.

[0081] In some embodiments, the size of the oxide aperture of the VCSEL array can be adjusted individually using the output power of each VCSEL. Take VCSEL array 800 as an example. Let P1 be the output power of VCSEL 5, and P2 be the output power of VCSELs 1-4 and 6-9. Assume that D1 and D2 initially have the same value D0. Since VCSEL 5 is located in the central region of the array, after a predetermined period of operation, the temperature of VCSEL 5 is higher than that of the other VCSELs. Therefore, P1 may become smaller than P2, which can lead to light intensity uniformity problems. The light intensity uniformity of VCSEL array 800 can be improved by adjusting D1 and / or D2. For example, D2 can be decreased to decrease P2. Alternatively, D1 can be increased to increase P1, which can also achieve better light intensity uniformity.

[0082] Optionally, an adjustment factor V can be calculated. For a VCSEL array 800, V can be equal to the square root of P2 divided by P1. That is, V = SQRT(P2 / P1). Then, in some cases, we can let D1 = D0, D2 = D0 / V. Since P1 is less than P2, V is greater than 1. Therefore, the value of D1 remains unchanged, while D2 decreases after being divided by V. Alternatively, in some other cases, we might get D1 = D0*V, and D2 = D0. That is, the value of D1 increases after being multiplied by V, while the value of D2 remains unchanged. In both cases, increasing the ratio of D1 to D2 improves the light intensity uniformity of the VCSEL array 800. After determining the values ​​of D1 and D2, the values ​​of S1 and S2 can be calculated. Then, S1, S2, the lateral oxidation rate, and the calculated oxidation time can be used to form oxide apertures with diameters of D1 and D2.

[0083] Figure 9A , 9BFigure 9C schematically illustrates a top view of a VCSEL array 900 according to another embodiment of the present invention. The top view shows VCSELs 1-20, typically representing a portion of the VCSEL array 900. In the VCSELs, VCSELs 1 and 2 may be located in or near the central region of the array, VCSELs 5, 10, 15, and 16-19 may be located in or near the edge region of the array, and VCSEL 20 may be located in or near the corner region of the array. The VCSELs of array 900 have a similar structure and manufacturing process to those of array 800, but the number of VCSELs and the configuration of openings for the oxidation process differ. For example, each VCSEL 1-20 includes an active region, a top reflector region, a bottom reflector region, and an aluminum-rich layer. The aluminum-rich layer may be arranged near the corresponding active region. The top reflector region includes a conductive p-type DBR structure. The bottom reflector region includes a conductive n-type DBR structure. The bottom reflector region, the active region, and the top reflector region are epitaxially grown on an n-type substrate during an epitaxial process. The active region includes the MQW region.

[0084] Following the epitaxial growth process, a metal layer 902 is formed on the top reflector region. For example... Figure 9A As shown, metal layer 902 has rings of the same or substantially similar size. Metal layer 902 serves as the anode of VCSEL array 900, is electrically contacted with the p+ layer of the p-type DBR structure, and is electrically connected to the top reflector region of the VCSEL. Subsequently, a dielectric layer (not shown) with dielectric material is deposited on metal layer 902 and a portion of the top reflector region.

[0085] Subsequently, a selective etching process, such as selective dry etching or wet-dry etching, can be performed to form an opening 904 around each VCSEL of the array 900, such as... Figure 9B As shown. Opening 904 is used for the oxidation process. (And...) Figures 8A-8C Similar to openings 809 and 817, opening 904 can extend vertically through the top reflector region, the active region, and at least partially through the bottom reflector region. Optionally, opening 904 can include a pair of symmetrical openings relative to the center of the VCSEL structure, such as... Figure 9B As shown.

[0086] Opening 904 has curved edges that are positioned opposite each other and face the centers of two adjacent VCSEL structures sharing the opening. The edge of opening 904 facing the center of the VCSEL structure is concentric with the center of the VCSEL structure. The distance between opening 904 and the center of the VCSEL structure is S. Optionally, S can be the distance between the curved edge of opening 904 and the center of the VCSEL structure, such as... Figure 9B As shown.

[0087] The sides of the aluminum-rich layer are exposed in opening 904 using a selective etching process. Next, an oxidation process (e.g., a wet oxidation process) is performed to partially oxidize the aluminum-rich layer and form an oxide layer. The oxide layer extends laterally to form circular or near-circular oxide apertures for the VCSELs of array 900. The diameter of the oxide aperture can be determined by the S value, the lateral oxidation rate, and the oxidation time. Therefore, when a VCSEL has a larger S value than another VCSEL, the diameter of the oxide aperture of the VCSEL may be larger. Furthermore, when a VCSEL has a large S value, the VCSEL can be configured to have a larger active region, a larger top reflector region, and a larger bottom reflector region. In some cases, when the VCSELs of the array have different S values, the VCSELs can have active regions, top reflector regions, and bottom reflector regions with the same or similar areas, respectively. In the description below, as an example, when the VCSELs of array 900 have a large S value, the VCSELs have a larger active region, a larger top reflector region, and a larger bottom reflector region.

[0088] Since the metal layers of VCSELs 1-20 have the same or similar dimensions, some VCSELs may have smaller series resistances when they have larger oxide apertures, larger active regions, larger top reflector regions, and larger bottom reflector regions. Similar to the VCSEL arrays mentioned above, the difference in series resistance can be used to improve the light intensity uniformity of the VCSEL array 900.

[0089] In some embodiments, after forming the oxide apertures, dielectric material can be filled into the openings 904. Subsequently, other manufacturing processes are performed to complete the fabrication of the VCSEL array 900. For example, isolation trenches or isolation regions can be formed to surround and isolate each VCSEL. A metal layer can be deposited on the bottom surface of the substrate as the cathode of the VCSEL array 900.

[0090] The series resistance can be configured to have different values ​​among VCSELs 1-20 of array 900. For example, if some VCSELs are located near the central region of array 900 and have higher temperatures among VCSELs 1-20, these VCSELs may have smaller series resistances to cope with larger power reductions during operation. Therefore, different oxide apertures can be configured to improve the light intensity uniformity of array 900.

[0091] In some embodiments, the VCSELs of an array can be grouped based on the output power or temperature of an individual VCSEL. For example, VCSELs with similar output power or similar temperatures can form a group. A group may have one or more VCSELs, and all VCSELs in a group have oxide apertures of the same or similar size. The oxide apertures of each group of VCSELs are adjusted individually to adjust the output power of the VCSELs, thereby obtaining better light intensity uniformity. Assume that the VCSELs of array 900 are divided into five groups, namely groups A to E. Before the adjustment process of adjusting the oxide aperture size, the oxide apertures of array 900 have the same size. Figure 9C As shown, letters A through E are used as group labels, with metal layer 902 omitted for simplicity. For example, VCSELs 3 and 6-8 each have a label "B," indicating they are in group B. In array 900, VCSELs in groups A and B are located at or closer to the center of the array, with relatively lower output power and higher temperatures for individual VCSELs in groups A and B. On the other hand, VCSELs in groups D and E are located away from the center, near the edge, with relatively higher output power and lower temperatures for individual VCSELs in groups D and E.

[0092] As shown above, groups A to E can be formed based on the individual output power of VCSELs. VCSELs within a group have similar or substantially similar output power, for example, within a predetermined power range. Alternatively, groups A to E can be formed based on the temperature of the VCSELs. VCSELs within a group can have similar or substantially similar temperatures, for example, within a predetermined temperature range. When a sample VCSEL array is available, the output power or temperature of the VCSELs can be measured using a power meter or temperature sensor. Measurements can be performed after the array 900 has been running for a certain period of time. Alternatively, the output power or temperature of the VCSELs can be obtained through a simulation method that simulates the operation of the VCSEL array. For array 900, the output power of individual VCSELs may gradually increase from group A to group E, while the temperature may gradually decrease from group A to group E.

[0093] Let P1, P2, P3, P4, and P5 be the output power of individual VCSELs in groups A through E. For example, P2 is the output power of each of VCSELs 3 and 6-8 in group B. Assume D1, D2, D3, D4, and D5 are the sizes (e.g., diameters) of the oxide pores of VCSELs in groups A through E. For example, D2 is the size of the oxide pores of VCSELs 3 and 6-8 in group B. Before the adjustment process, let the individual values ​​of D1 through D5 be D0. In some cases, D0 may be close to the desired number. Optionally, an adjustment factor V can be calculated. For VCSEL array 900, the adjustment factor Vn = SQRT(Pn / P1), where n = 1-5, corresponding to groups A through E. In some cases, we might have Dn = D0 / Vn, where n = 1-5. Since P1 is the smallest in groups A through E, Vn is greater than 1, and Dn decreases after dividing by Vn (n = 2-5). That is, the oxide pore size of group A remains unchanged, while the oxide pore size of other groups decreases. From group A to group E (i.e., from the center region to the edge region of array 900), the size of the oxide pore size gradually decreases, corresponding to an increase in output power or a decrease in temperature from group A to group E obtained by measurement or simulation.

[0094] After determining the values ​​of D1 to D5, the S-value for each group can be calculated. Then, the S-value, lateral oxidation rate, and calculated oxidation time can be used to form oxide apertures with diameters D1 and D5. Adjusting the oxide apertures can improve the light intensity uniformity of array 900.

[0095] Alternatively, the oxide aperture of array 900 can be adjusted using another method. Let the adjustment coefficient Vm = SQRT(P5 / Pm), where m = 1-5, corresponding to groups A to E. We can have Dm = D0 * Vm, where m = 1-5. Since Vm is greater than 1 (except for V5), Dm increases from D0 after multiplying by Vm, where m = 1-4. That is, the oxide aperture of group E remains unchanged, while the oxide aperture of other groups increases. From group A to group D, the increase in oxide aperture decreases. Then, the S-values ​​for groups A to E can be calculated. Using the S-values, the lateral oxidation rate, and the calculated oxidation time, the diameters of the oxide apertures, D1 and D5, can be calculated. After adjusting the oxide aperture of VCSEL array 900, the output power difference between VCSELs can be reduced to some extent. The light intensity uniformity of array 900 can be improved.

[0096] In some embodiments, epitaxial growth can be performed using metal-organic chemical vapor deposition (MOCVD), for example, epitaxial growth of the active region 201 or 801, the top reflector region 202 or 802, and the bottom reflector region 203 or 803. In some cases, the openings can be filled using chemical vapor deposition (CVD) and / or physical vapor deposition (PVD). Optionally, the metal layer can be deposited using CVD, PVD, or atomic layer deposition (ALD), or a combination of at least two of CVD, PVD, and ALD.

[0097] While specific embodiments of the invention have been disclosed, those skilled in the art will understand that modifications can be made to the specific embodiments without departing from the spirit and scope of the invention. Therefore, the scope of the invention is not limited to the specific embodiments. Furthermore, it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the invention.

Claims

1. A vertical-cavity surface-emitting laser (VCSEL) array, comprising: Substrate; as well as A plurality of VCSEL structures on the substrate, each of the VCSEL structures comprising: A first reflector region is formed above the substrate; An active region formed above the first reflector region; A second reflector region is formed above the active region; and The oxide pore size formed near the active region, The feature is that the oxide pore size of the VCSEL structure located in the central region of the VCSEL array is larger than that of the VCSEL structure located in the edge region of the VCSEL array; the output power of each VCSEL is used to calculate the size of the oxide pore size of the VCSEL structure located in the central region of the VCSEL array and the size of the oxide pore size of the VCSEL structure located in the edge region of the VCSEL array.

2. The VCSEL array according to claim 1, characterized in that, Both the first reflector region and the second reflector region include a distributed Bragg reflector (DBR) structure.

3. The VCSEL array according to claim 1, characterized in that, Adjustment factors are obtained using measurement or simulation results.

4. The VCSEL array according to claim 1, characterized in that, The first reflector region, second reflector region, or active region of the VCSEL structure located in the central region of the VCSEL array are larger than the first reflector region, second reflector region, or active region of the VCSEL structure located in the edge region of the VCSEL array.

5. The VCSEL array according to claim 1, characterized in that, It also includes multiple metal layers formed above each second reflector region.

6. The VCSEL array according to claim 5, characterized in that, The multiple metal layers have the same shape and the same or similar size.

7. The VCSEL array according to claim 1, characterized in that, Multiple VCSEL structures are divided into multiple groups, and the oxide pore sizes of one group in each group are the same or similar.

8. A method for manufacturing a vertical-cavity surface-emitting laser (VCSEL) array, comprising: Multiple VCSEL structures are fabricated on the substrate. The characteristic feature is that manufacturing each VCSEL structure includes: A first reflector region is formed above the substrate; An active region is formed above the first reflector region; A second reflector region is formed above the active region; and Forming oxide pores adjacent to the active region, Specifically, the oxide pore size of the VCSEL structure located in the central region of the VCSEL array is larger than that of the VCSEL structure located in the edge region of the VCSEL array; the output power of each VCSEL is used to calculate the size of the oxide pore size of the VCSEL structure located in the central region of the VCSEL array and the size of the oxide pore size of the VCSEL structure located in the edge region of the VCSEL array.

9. The method according to claim 8, characterized in that, Forming the first reflector region or forming the second reflector region includes forming a distributed Bragg reflector (DBR) structure.

10. The method according to claim 8, characterized in that, Adjustment factors are obtained using measurement or simulation results.

11. The method according to claim 8, characterized in that, The first reflector region, second reflector region, or active region of the VCSEL structure located in the central region of the VCSEL array are larger than the first reflector region, second reflector region, or active region of the VCSEL structure located in the edge region of the VCSEL array.

12. The method according to claim 8, characterized in that, It also includes forming multiple metal layers above each second reflector region.

13. The method according to claim 12, characterized in that, The multiple metal layers have the same shape and the same or similar size.

14. The method according to claim 8, characterized in that, It also includes dividing multiple VCSEL structures into multiple groups, wherein the oxide pore size of one of the multiple groups has the same or similar size.

15. A vertical-cavity surface-emitting laser (VCSEL) array, comprising: Substrate; Multiple first VCSEL structures on the substrate; as well as Multiple second VCSEL structures on the substrate, The feature is that each of the plurality of first VCSEL structures is closer to the central region of the VCSEL array than the plurality of second VCSEL structures, and the size of the oxide pore size of the plurality of first VCSEL structures is larger than the size of the oxide pore size of the plurality of second VCSEL structures. The output power of each VCSEL is used to calculate the size of the oxide pores of the VCSEL structures located in the central region of the VCSEL array and the size of the oxide pores of the VCSEL structures located in the edge region of the VCSEL array.

16. The VCSEL array according to claim 15, characterized in that, Adjustment factors are obtained using measurement or simulation results.

17. The VCSEL array according to claim 15, characterized in that, The dimensions of the first reflector region, second reflector region, or active region of the multiple first VCSEL structures are larger than the dimensions of the first reflector region, second reflector region, or active region of the multiple second VCSEL structures.

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