Serdes interface circuit and control device

Abstract

Provided is a SerDes interface circuit and a control device capable of data transmission at different communication rates using the same SerDes. A FIFO (31) receives a first clock at a first frequency, first transmission data based on the first clock, and a second clock at a second frequency different from the first frequency, and outputs the first transmission data in the order of input according to the second clock. A flip-flop (32) takes in the output of the FIFO and holds the output according to the second clock. An output state machine (33) receives the output of the FIFO and the output of the flip-flop, and generates parallel data in which the same data corresponding to the first transmission data is continuous according to the second clock.

Description

TECHNICAL FIELD

[0001] Embodiments described in this application relate to a SerDes interface circuit and a control device. BACKGROUND

[0002] In recent years, a computer numerical control (CNC) device that controls a machine tool has become faster with installation of various functions, and, for example, in data communication between a machine tool that is a control target and the CNC device, a SerDes (SERializer / DESerializer) that enables high-capacity high-speed data transmission is used.

[0003] The SerDes is used, for example, to convert parallel data used in one device into serial data to be transmitted to another device, and in the other device, the received serial data is converted again into parallel data to be used, and thus, regardless of a time lag caused by a wiring length or stray capacitance between bits in parallel communication, high-speed data communication can be performed with a reduced number of wirings or terminals.

[0004] Therefore, various schemes related to data communication using a SerDes have been proposed in the past.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2019-140489

[0008] Patent Document 2: Japanese Patent Application Publication No. 2009-109488

[0009] Patent Document 3: Japanese Patent Application Publication No. 2011-193068

[0010] Patent Document 4: Japanese Patent Application Publication No. 2016-072772 SUMMARY

[0011] Problems to be Solved by the Invention

[0012] As described above, the SerDes enables high-capacity high-speed data communication, and thus is used in various fields. For example, the range of communication rates with which the SerDes can communicate is determined by the manufacturer or the technology of an ASIC (Application Specific Integrated Circuit), and thus it is not possible to use a communication rate lower than the lower limit of the SerDes. Therefore, it is difficult to use the same SerDes to perform communication of machine types (including devices, circuit blocks, and the like) that differ in communication rate.

[0013] In recent years, however, there are cases in which different types of data (for example, data having different communication rates (action clocks)) are used in one device. Therefore, for example, it is required that, in a device (a device itself) on one side, data having different communication rates be converted into serial data having a predetermined communication rate using the same (one) SerDes, and transmitted to a device (a device on the other side) on the other side. In the device on the other side, the transmitted serial data is processed using a SerDes or by another communication interface.

[0014] Specifically, for example, in a case in which the device itself is a CNC device, it is required that 16-bit parallel data based on a clock of 180 MHz and a 1-bit signal based on a clock of 160 MHz be converted into serial data having a communication rate of 2.88 Gbps using the same SerDes, and transmitted to a device (for example, a motor amplifier that controls a servo motor of a machine tool) on the other side. These devices are not limited to CNC devices and machine tools, and, for example, a robot control device can be applied as the device itself, and an industrial robot, a collaborative robot, or the like controlled by the robot control device can be applied as the device on the other side.

[0015] Furthermore, the 16-bit parallel data of 180 MHz and the 1-bit signal of 160 MHz are merely simple examples, and the frequencies of the clocks of 180 MHz and 160 MHz can be appropriately changed, and the parallel data of 16 bits is not limited to 16 bits. In addition, the 1-bit signal of 160 MHz is set to 1 bit for simplicity of explanation, and, of course, for example, it can be parallel data of a plurality of bits such as 32 bits or 64 bits.

[0016] In view of the above-described problems, an object of the present application is to provide a SerDes interface circuit and a control device that enable transmission of data having different communication rates using the same SerDes.

[0017] Means for solving the problem

[0018] According to the embodiment of the present application, a SerDes interface circuit is provided that has a FIFO that receives a first clock of a first frequency, first transmission data based on the first clock, and a second clock of a second frequency different from the first frequency, and outputs the first transmission data in the order of input based on the second clock, a flip-flop that takes in and holds the output of the FIFO based on the second clock, and an output state machine that receives the output of the FIFO and the output of the flip-flop, and generates parallel data in which the same data corresponding to the first transmission data is continuous based on the second clock.

[0019] Effects of the Invention

[0020] The SerDes interface circuit and the control device of the present disclosure have an effect that different communication rates of data transmission can be performed using the same SerDes.

[0021] The object and effects of the present application can be recognized and obtained particularly by using the constituent elements and combinations indicated in the scope of protection. Both the above general description and the following detailed description are illustrative and explanatory, and do not limit the present application recited in the scope of protection. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a block diagram showing an embodiment of the control device of the present application.

[0023] Figure 2 For explanation Figure 1 An example of the SerDes in the control device shown.

[0024] Figure 3 For explanation Figure 1 A first embodiment of the SerDes interface circuit in the control device shown.

[0025] Figure 4 For explanation Figure 3 The operation of the SerDes interface circuit shown.

[0026] Figure 5 is a block diagram showing an example of the data recovery circuit in the control device shown. Figure 1

[0027] For explanation Figure 6 The operation of the data recovery circuit shown. Figure 5

[0028] For explanation Figure 7 Another application example of the SerDes interface circuit shown. Figure 3

[0029] For explanation Figure 8 The operation of the SerDes interface circuit shown. Figure 7

[0030] For explanation Figure 9 A modified example of the SerDes interface circuit in the control device shown. Figure 1

[0031] For explanation Figure 10 A FIFO having an output number control function in the SerDes interface circuit shown. Figure 9 DETAILED DESCRIPTION

[0032] ​An embodiment of the SerDes interface circuit and the control device of the present application will be described in detail below with reference to the accompanying drawings. Figure 1 is a block diagram showing an embodiment of the control device of the present application.

[0033] As shown in Figure 1 , the control device 10 of the present embodiment has a new communication control circuit 1, a compatible communication control circuit 2, a SerDes interface circuit 3, a Data Recovery (DR) circuit 4, a bit conversion circuit 5, a selector 6, and a SerDes (Serializer / Deserializer) 7.

[0034] The control device 10 converts, for example, 16-bit parallel data of 180 MHz (16-bit parallel data based on a clock of 180 MHz: second transmission data) via the new communication control circuit 1 and a 1-bit signal of 160 MHz (1-bit signal based on a clock of 160 MHz: first transmission data) via the compatible communication control circuit 2 into serial data of a communication rate of 2.88 Gbps (bit / s) by the SerDes 7, and transmits and receives between the counterpart device (device on the communication target side) 200.

[0035] For example, a SerDes is also provided in the counterpart device 200, and it is possible to convert the 2.88 Gbps serial data transmitted from the control device 10 (the device 100) into parallel data and use it. That is, it is possible to convert the 2.88 Gbps serial data into 16-bit parallel data of 180 MHz and a 160 MHz signal by the SerDes of the counterpart device 200, and input it to, for example, a circuit controlled by 16-bit parallel data of 180 MHz and a circuit controlled by a 160 MHz signal.

[0036] Alternatively, it is also possible not to provide a SerDes in the counterpart device 200, but to process the transmitted serial data by another communication interface circuit. In addition, in order to simplify the description, the 160 MHz signal via the compatible communication control circuit 2 is set to 1 bit, but as described above, it can also be parallel data of a plurality of bits.

[0037] Here, as the device 100, various control devices such as a CNC device and a robot control device can be cited, and as the counterpart device 200, devices such as various machine tools and industrial robots, collaborative robots controlled by a CNC device (or a motor amplifier for controlling a motor in the machine tool and the robot), but not limited thereto.

[0038] The SerDes interface circuit 3 receives a 160 MHz 1-bit signal (first transmission data) from the compatible communication control circuit 2, converts it into a parallel signal based on a 180 MHz clock having the same logical value as the first transmission data, and outputs it. The selector 6 receives 180 MHz 16-bit parallel data (second transmission data) from the new communication control circuit 1 and 180 MHz 16-bit parallel data from the SerDes interface circuit 3, selects one of them, and outputs it to the transmit parallel data input (TX_pData) of the SerDes 7.

[0039] Figure 2 For explanation Figure 1 An example of the SerDes in the control device shown. Here, Figure 2 (a) of FIG. 7 is a block diagram showing the input and output data of the SerDes 7, Figure 2 (b) of FIG. 7 is a diagram for explaining the processing (parallel / serial conversion processing) at the time of data transmission of the SerDes 7, Figure 2 (c) of FIG. 7 is a diagram for explaining the processing (serial / parallel conversion processing) at the time of data reception of the SerDes 7. The SerDes is particularly used in the case of connecting in series between parallel interfaces and the like in high-speed interfaces, but as the SerDes 7 of the control device 10 of the present embodiment, a general SerDes can be applied.

[0040] In Figure 2 In (a) of FIG. 7, the reference symbol TX_pData indicates transmit parallel data (for example, 16-bit parallel transmit parallel data based on a 180 MHz clock: and input of the transmit parallel data) transmitted from the device (the device on the side where the control device 10 is provided) 100 to the partner device 200, and TX_sData indicates transmit serial data (for example, transmit serial data at a communication rate of 2.88 Gbps: and output of the transmit serial data) transmitted to the partner device 200 after converting the transmit parallel data TX_pData into serial data.

[0041] Further, in Figure 2In (a) of FIG. 10, reference symbol RX_sData indicates received serial data (for example, received serial data and input of received serial data at a communication rate of 2.88 Gbps) transmitted from the partner device 200, and RX_pData indicates received parallel data (for example, 16-bit parallel received parallel data based on a 180 MHz clock: and output of received parallel data) obtained by converting the received serial data RX_sData into parallel data. pCLK indicates a clock (for example, a 180 MHz clock: and input of a clock of transmission parallel data) of the transmission parallel data TX_pData, and RCLK indicates a recovery clock (and output of a recovery clock) obtained by receiving the received serial data and regenerating the recovery clock from the received serial data by CDR (Clock Data Recovery).

[0042] First, as shown in Figure 2 In (b) of FIG. 10, at the time of data transmission, the SerDes 7 performs parallel / serial conversion on the transmission parallel data TX_pData of 16 bits based on the pCLK of 180 MHz, for example, so that the output starts from the lower bits, that is, the transmission serial data TX_sData at a communication rate of 2.88 Gbps is converted based on 180 MHz x 16 bits, and output to the partner device 200. Figure 2 In (c) of FIG. 10, at the time of data reception, the SerDes 7 receives the received serial data RX_sData at a communication rate of 2.88 Gbps from the partner device 200, converts it into the received parallel data RX_pData of 16 bits, and outputs it.

[0043] Thus, when the frequency of the operation clock is set to X (for example, 180 MHz) and the number of bits of the parallel data is set to Y (for example, 16 bits), the SerDes 7 can make the communication rate Z of the serial data Z = X x Y [bps] (for example, 180 MHz x 16 bits = 2.88 Gbps).

[0044] Figure 3 A first embodiment of the SerDes interface circuit in the control device shown in FIG. 9 will be described. Here, Figure 1 (a) of FIG. 10 is a block diagram showing the first embodiment of the SerDes interface circuit, Figure 3 (b) and Figure 3 (c) of FIG. 10 are used to describe the operation of the output state machine in the SerDes interface circuit shown in (a) of FIG. 10. As shown in Figure 3 Figure 3 Figure 3 ​​The SerDes interface circuit 3 has a FIFO (First In First Out) 31 with an output enable (EN), a flip-flop (FF) 32, and an output state machine 33, as shown in (a).

[0045] The FIFO 31 receives an input clock (first clock) having a frequency of 160 MHz, a 1-bit signal based on a 160 MHz clock (160 MHz transmission data: first transmission data), and an output clock (second clock) having a frequency of 180 MHz, and takes in the first transmission data based on the first clock, and outputs the taken-in data in order based on the second clock in a case where the output EN is "1". In addition, in a case where the output EN is "0", the immediately preceding output is maintained. The output of the FIFO 31 is input to the output state machine 33 as a signal A, and is input to a data terminal of the flip-flop 32. Here, the frequency of the second clock corresponds to the operation clock (180 MHz) of the 16-bit parallel data output from the new communication control circuit 1 described below. Figure 1

[0046] The second clock of 180 MHz is input to a clock terminal of the flip-flop 32, the first transmission data from the FIFO 31 is taken in based on the second clock and the data is held, and the held data is output to the output state machine 33 as a signal B. That is, the output state machine 33 receives the first transmission data from the FIFO 31 at a certain timing (A: FIFO output) and the first transmission data from the FIFO 31 at a timing that is 1 clock of the second clock earlier than the timing (B: FF output). The second clock is input to a clock input terminal of the output state machine 33, and in addition, an enable signal (EN) from the output state machine 33 is input to an output enable terminal of the FIFO 31.

[0047] The output state machine 33 generates parallel data in which 18 bits are the same (have the same logic value) in series, for example, based on the signal (A) input to terminal A and the signal (B) input to terminal B. Here, in Figure 3 In (b), for example, the data "B" of the state "1" is data taken in by the flip-flop 32 by 1 clock (180 MHz) earlier, and thus has the same logic value as the data "A" of the state "0". Therefore, by adding the 16-bit parallel data of the data "A" of the state "0" and the 2-bit parallel data of the data "B" of the state "1", 16-bit parallel data having the same logic value of 18 bits is generated.

[0048] ​Similarly, for example, by adding 14 bits of parallel data of data "A" in state "1" and 4 bits of parallel data of data "B" in state "2", 16 bits of parallel data with the same 18-bit logical value are generated. Similarly, by adding 8 bits of parallel data of data "A" in state "4" and 10 bits of parallel data of data "B" in state "5", 16 bits of parallel data with the same 18-bit logical value are generated. Furthermore, since EN in state "7" is "0", the FIFO output is not updated in state "8". The next FIFO output data, which has already been input to "A" in state "7" and "B" in state "8", is input to "A" in state "0" and "B" in state "1".

[0049] Thus, for example, a 1-bit signal from the compatible communication control circuit 2 at 160MHz is processed into 8 bits between state "0" and state "8", and this processing is repeated. Figure 3 (c) indicates to Figure 3 The input and output signals and internal states of FIFO31, FF32 and output state machine 33 every 1 clock cycle (180MHz) when FIFO31 is input with data D0, D1, D2, ... (where D0, D1, D2, ... are “0” or “1” respectively).

[0050] like Figure 3 As shown in (c), for example, in state "8", "A" will not appear in the parallel data of output state machine 33, therefore it is necessary to stop updating the output data of FIFO 31, and set EN to "0" in state "7". Additionally, the output "A" of FIFO 31 in state "8" and the output "B" of FF32 in state "0" are both D8, but this does not affect the parallel data (i.e., it is D8 because the data update of FIFO 31 has been stopped, but it could also be "0" or "1"). Thus, according to Figure 3 As can be seen from (c), in group 1 from state "0" to state "8", 8 bits of data are output for every 18 bits as parallel data.

[0051] Here, in the parallel data (16-bit parallel data) generated by the output state machine 33, when the number of consecutive bits of the same data corresponding to the first transmitted data (1-bit signal of 160MHz) is set to V (18), the frequency of the first clock is set to W (160MHz), the frequency of the second clock is set to X (180MHz), and the number of bits of parallel data in the second transmitted data based on the second clock is set to Y (16), the number of consecutive bits of the same data V can be represented by V = (X × Y) / W.

[0052] In the above, in a case where the first transmission data input to the FIFO 31 is a plurality of bits, for example, in a case where the signal from the compatible communication control circuit 2 is a plurality of signals of 160 MHz, substantially the same processing can be performed.

[0053] Figure 4 For explaining Figure 3 the operation of the SerDes interface circuit. As described above, as the transmission parallel data TX_pData, the continuous same data such as "1111111111111111" generated by the SerDes interface circuit 3 (output state machine 33) is input to the SerDes 7, so that the substantial communication rate can be reduced.

[0054] As Figure 4 described above, for example, in a case where a signal of 160 Mbps is transmitted at a communication rate of 2.88 Gbps, in order to transmit the signal of 1 bit of 160 Mbps (MHz) at the same SerDes 7 (the same communication rate), 2.88 G / 160 M = 18 is obtained, so that the signal of 1 bit of 160 Mbps is converted into 18-bit same data continuous parallel data and input to the SerDes 7.

[0055] Thus, the SerDes interface circuit 3 (output state machine 33) outputs 16-bit parallel data of 180 MHz, but since the data corresponding to 1 bit of 160 Mbps is 18-bit parallel data of the same logic value in succession, the communication rate of the transmission serial data TX_sData is actually reduced to perform data transmission. Thus, data transmission of different communication rates (different specifications) can be performed using the same SerDes 7.

[0056] Figure 5 is a block diagram of an example of a data recovery circuit in the control device shown in Figure 1 Figure 6 For explaining Figure 5 the operation of the data recovery circuit. In Figure 5 , the reference symbol RX_sData represents received serial data, REFCLK represents a reference clock, RX_pData represents n-bit received parallel data, RCLK represents a recovery clock of a frequency of 1 / n of the communication rate, and Edg_data represents edge position data. In addition, the reference symbol Calc_edg represents edge prediction position data, Sample_point represents a sampling position data, cntup represents a phase control signal for advancing the phase, cntdn represents a phase control signal for delaying the phase, rdata represents recovery data, and Rdata_en represents a data enable signal.

[0057] ​Figure 5 The illustrated data recovery (DR) circuit 4 corresponds to the data reproducing circuit disclosed in the above-mentioned Patent Literature 4. Previously, as described with reference to Figure 1 and Figure 2 As described above, for example, the received serial data RX_sData at a communication rate of 2.88 Gbps is converted into 16-bit parallel received parallel data RX_pData based on a clock of 180 MHz by the SerDes 7. Then, as Figure 1 illustrated, the received parallel data RX_pData converted by the SerDes 7 is input to the DR circuit 4. In addition, the DR circuit 4 outputs a 2-bit signal together with a data enable Rdata_en to the bit conversion circuit 5, which generates a 1-bit signal in accordance with the data enable Rdata_en, and outputs a 1-bit signal at 160 MHz to the compatible communication control circuit 2. That is, the DR circuit 4 and the bit conversion circuit 5 constitute a conversion processing circuit that receives the received parallel data RX_pData converted by the SerDes 7, converts it into a signal of the same specification as the 1-bit signal at 160 MHz (first transmission data), and outputs it to the compatible communication control circuit 2.

[0058] As illustrated in Figure 5 , the DR circuit 4 receives signals (received parallel data RX_pData and a recovery clock RCLK) from the oversampling section (SerDes) 7. The oversampling section 7 samples serial data (received serial data) RX_sData received through serial communication at a clock of a higher frequency than the communication rate of the serial data, and outputs n (n is an integer of 2 or more) bits of received parallel data RX_pData and a recovery clock RCLK at 1 / n of the frequency of the sampling clock.

[0059] The DR circuit 4 has an edge detection section 41, an edge position calculation section 42, a data sampling section 43, and a phase comparison section 44. As illustrated in Figure 6 , the edge detection section 41 detects the edge position of the parallel data and outputs it as edge data. The edge position calculation section 42 predicts the edge position of the next parallel data output from the oversampling section 7 in accordance with a phase control signal output from the phase comparison section 44, and outputs it as edge predicted position data, and outputs data shifted by half a phase with respect to the edge predicted position data as sampling position data.

[0060] The phase comparison section 44 compares the edge data output from the edge detection section 41 with the edge predicted position data output from the edge position calculation section 42, and outputs a phase control signal (cntup, cntdn). The data sampling section 43 extracts data from the parallel data output from the oversampling section 7 in accordance with the sampling position data output from the edge position calculation section 42, that is,Figure 6 As shown, the data center is sampled and output as recovered data (regenerated data) along with the data enable Rdata_en, which indicates the validity of the data.

[0061] Furthermore, for example, the bit conversion circuit 5 converts the 2-bit signal output from the DR circuit 4 into a 1-bit signal based on the data enable Rdata_en, and outputs a 160MHz 1-bit signal to the compatible communication control circuit 2. In this way, the control device 10 can use the same SerDes for data transmission at different communication rates (different specifications) in both the data sending and receiving sides. The DR circuit 4 and the bit conversion circuit 5 are just one example; various modifications and variations are possible, and various known circuits can also be used.

[0062] Figure 7 For explanation Figure 3 This is another application example of the SerDes interface circuit shown. Figure 7 (a) is a block diagram illustrating another application example of the SerDes interface circuit. Figure 7 (b) is used to explain Figure 7 The operation of the output state machine in the SerDes interface circuit shown in (a) is illustrated. Furthermore, Figure 7 The structure of (a) is essentially the same as the one described above. Figure 3 (a) is the same, so its explanation is omitted.

[0063] The above Figure 3 and Figure 4 This illustrates an application example of a SerDes interface circuit that converts 16 bits of parallel data based on a 180MHz clock and a 1-bit signal based on a 160MHz clock into 2.88Gbps serial data via a SerDes7 converter for transmission to a remote device 200. Figure 7 and Figure 8 This illustrates an application example of the SerDes interface circuit 3, which converts 18 bits of parallel data based on a 120MHz clock and a 1-bit signal based on a 90MHz clock into 2.16Gbps serial data via SerDes7 for transmission to the other device 200.

[0064] The output state machine 33 generates parallel data in which 24 bits of the same data (having the same logic value) in series data, for example, using the signal input to terminal A (A: FIFO output) and the signal input to terminal B (B: FF output), which is the output of a flip-flop that takes in the signal (A) one clock in advance and holds the signal (A). The signal output from the output state machine 33 (Ser Des interface circuit 3) corresponds to 18 bits of parallel data of 120 MHz output from the new communication control circuit 1.

[0065] That is, as shown in (b) of FIG. 6, the output state machine 33 generates parallel data having 24 bits of the same logic value from the signal A and the signal B. For example, the data "B" of state "1" is data taken in by the flip-flop 32 one clock in advance, and thus has the same logic value as the data "A" of state "0". Therefore, by adding 6 bits of parallel data of the data "B" of state "1" to 18 bits of parallel data of the data "A" of state "0", 18 bits of parallel data having 24 bits of the same logic value are generated. Figure 7

[0066] Similarly, for example, 18 bits of parallel data having 24 bits of the same logic value are generated by adding 12 bits of parallel data of the signal A of state "1" to 12 bits of parallel data of the signal B of state "2". Further, since the EN of state "2" is "0", the output of the FIFO 31 is not updated in state "3", and the output data of the FIFO 31 of the next of the data input to "A" of state "2" and "B" of state "3" is input to "A" of state "0" and "B" of state "1". In this way, for example, a 1-bit signal of 90 MHz from the compatible communication control circuit 2 is processed by 3 bits from state "0" to state "3", and this processing is repeated.

[0067] Figure 8 to explain the operation of the Ser Des interface circuit shown in FIG. 6. As described above, by adding the continuous same data "111111111111111111" generated by the Ser Des interface circuit 3 (output state machine 33) to the transmitted parallel data TX_pData, the actual communication rate can be reduced. Figure 7

[0068] That is, as shown in (b) of FIG. 6, the output state machine 33 generates parallel data having 24 bits of the same logic value from the signal A and the signal B. For example, the data "B" of state "1" is data taken in by the flip-flop 32 one clock in advance, and thus has the same logic value as the data "A" of state "0". Therefore, by adding 6 bits of parallel data of the data "B" of state "1" to 18 bits of parallel data of the data "A" of state "0", 18 bits of parallel data having 24 bits of the same logic value are generated. Figure 8 ​​As shown, for example, when a 120 Mbps signal is transmitted at a communication rate of 2.16 Gbps, in order to transmit a 90 Mbps 1-bit signal at the same SerDes 7 (the same communication rate), because 2.16G / 120M = 24, the 90 Mbps 1-bit signal is converted into 24-bit parallel data in which the same data is continuous and input to the SerDes 7.

[0069] Thus, the SerDes interface circuit 3 (the output state machine 33) outputs 120 MHz 18-bit parallel data, and because the data corresponding to the 90 Mbps 1-bit becomes parallel data in which the same logic value is continuous for 24 bits, the communication rate of the transmitted serial data TX_sData is actually reduced to perform data transmission. Thus, data transmission at different communication rates can be performed using the same SerDes 7.

[0070] Here, in the parallel data (18-bit parallel data) generated by the output state machine 33, when the number of bits in which the same data is continuous with respect to the first transmission data (a 90 MHz 1-bit signal) is set to V (24), the frequency of the first clock is set to W (90 MHz), the frequency of the second clock is set to X (120 MHz), and the number of bits of the parallel data in the second transmission data based on the second clock is set to Y (18), the number of bits V in which the same data is continuous can be expressed by V = (X x Y) / W.

[0071] Figure 9 For explanation Figure 1 A modification example of the SerDes interface circuit in the control device shown. Here, Figure 9 (a) of FIG. 10 is a block diagram showing a modification example of the SerDes interface circuit, Figure 9 (b) of FIG. 10 is for explaining Figure 9 the operation of the output state machine in the SerDes interface circuit shown in (a) of FIG. 10. Also, according to Figure 9 (a) of FIG. 10 and Figure 3 (a) of FIG. 10 and Figure 7 (a) of FIG. 10, in the SerDes interface circuit 3 of the present modification example, the FIFO 31 having the output enable is made the FIFO 31' having the output quantity control function, and the output state machine 33 is made the output state machine 33' in correspondence therewith. Also, in the present modification example, an application example of the SerDes interface circuit 3 when 16-bit parallel data based on a 80 MHz clock and a 1-bit signal based on a 128 MHz clock are converted into 1.28 Gbps serial data via the SerDes 7 and transmitted to the partner device is shown.

[0072] As Figure 9As shown in (a), FIFO 31' receives an input clock (first clock) with a frequency of 128MHz, a 1-bit signal based on the 128MHz clock (transmit data with an operating frequency of 128MHz: first transmit data), and an output clock (second clock) with a frequency of 80MHz. It receives the first transmit data based on the first clock and outputs the received data sequentially based on the second clock. The output (first FIFO output) O1 of FIFO 31' is input as signal A to the output state machine 33', and the output (second FIFO output) O2 is input as signal B to the output state machine 33', and also input to the data terminal of flip-flop 32.

[0073] Furthermore, FIFO31' receives the output quantity control signal Next_Num from the output state machine 33' via the output quantity control terminal Out_Num. In this variant example, for instance, to transmit 16 bits of parallel data at 80 MHz and a 1 bit signal at 128 MHz via a SerDes7 with a communication rate of 1.28 Gbps, since 1.28 G / 128 M = 10, the 1 bit signal at 128 MHz can be converted into 10 bits of identical data in consecutive parallel data and input to SerDes7.

[0074] Figure 10 For explanation Figure 9 The SerDes interface circuit shown includes a FIFO with output quantity control function. Figure 10 (a) represents the case where Out_Num = 1. Figure 10 (b) represents the case where Out_Num = 2.

[0075] First, such as Figure 10 As shown in (a), when Out_Num = 1, the initially input and stored data (the initially output data: the data stored in the "1" of the FIFO) is output to output (first FIFO output) O2, and no output is made to output (second FIFO output) O1. Then, as... Figure 10 As shown in (b), when Out_Num = 2, the data stored in FIFO "1" is output to output O1, and the data stored in FIFO "2" (the data output after "1") is output to output O2. Thus, compared with the above reference... Figure 3 as well as Figure 4 Examples and references Figure 7 as well as Figure 8 Similarly, the example illustrates how the same SerDes7 can be used for data transmission at different communication rates (different specifications).

[0076] That is, such as Figure 9As shown in (b), the output state machine 33' generates 10-bit identical data-continuous parallel data from the signal of terminal A (A: O1), the signal of terminal B (B: O2), and the signal of terminal C (C: the output signal of the flip-flop 32). Here, in Figure 9 In (b), for example, the data "C" of the state "1" is data taken into the output O2 by the flip-flop 32 by the previous 1 clock, and thus has the same logic value as the data "B: O2" of the state "0". Therefore, not only 10-bit identical data-continuous parallel data of the data "A" of the state "0" is generated, but also parallel data having 10 bits of the same logic value obtained by adding 6-bit parallel data of the data "B" of the state "0" to 4-bit parallel data of the data "C" of the state "1" is generated.

[0077] As for the generation of the parallel data having 10 bits of the same logic value, for example, it is also possible to generate by adding 8-bit parallel data of the data "B" of the state "2" to 2-bit parallel data of the data "C" of the state "3". In this way, the output O1 and O2 of the FIFO 31' are controlled by the output number control signal Next_Num output from the output state machine 33', and thus the same processing can be performed.

[0078] That is, the FIFO 31' is controlled not to output the first FIFO output (O1) and to output only the second FIFO output (O2), or to output the first FIFO output (O1: data of the state "1") and to output the data ("2") to be output next in order as the second FIFO output (O2), according to the control signal from the output state machine 33'. Further, the SerDes interface circuit 3 described above is merely an example, and various modifications and variations can be made.

[0079] Here, in the parallel data (16-bit parallel data) generated by the output state machine 33', when the number of bits of identical data-continuous data corresponding to the first transmission data (1-bit signal of 128 MHz) is set to V (10), the frequency of the first clock is set to W (128 MHz), the frequency of the second clock is set to X (80 MHz), and the number of bits of parallel data in the second transmission data based on the second clock is set to Y (16), the number of bits V of identical data-continuous data can be represented by V = (X x Y) / W.

[0080] Thus far, the embodiments have been described, all the examples and conditions described herein are for the purpose of helping to understand the inventive concept applied in the invention and the technology, and in particular, the described examples and conditions are not intended to limit the scope of the invention. In addition, such description of the specification is not indicative of the advantages and disadvantages of the invention. Although the embodiments of the invention have been described in detail, it should be understood that various changes, substitutions, modifications, etc. can be made without departing from the spirit and scope of the invention.

[0081] Symbol explanation

[0082] 1 New communication control circuit

[0083] 2 Compatible communication control circuit

[0084] 3 SerDes interface circuit

[0085] 4 Data recovery (DR) circuit

[0086] 6 Selector

[0087] 7 SerDes (serializer / deserializer), oversampling section

[0088] 10 Control device

[0089] 31 FIFO (FIFO with output enable)

[0090] 31' FIFO (FIFO with output quantity control function)

[0091] 32 Flip-flop (FF)

[0092] 33, 33' Output state machine

[0093] 41 Edge detection section

[0094] 42 Edge position calculation section

[0095] 43 Data sampling section

[0096] 44 Phase comparison section

[0097] 100 This device (control device)

[0098] 200 Opponent device

Claims

1. A control device which processes transmission data based on a first clock of a first frequency, characterized by, Possessing: a SerDes that converts transmission parallel data into serial data of a predetermined communication rate by a second clock of a second frequency different from the first frequency; and a SerDes interface circuit that receives the transmission data and converts and outputs Y-bit parallel signals of identical data in succession corresponding to the transmission data, the SerDes interface circuit has: a FIFO that receives a first clock, transmission data based on the first clock, and the second clock, and outputs the transmission data in input order by the second clock based on a control signal output from an output state machine; a flip-flop that latches and holds the output of the FIFO based on the second clock; and the output state machine that receives the output of the FIFO and the output of the flip-flop, and generates parallel data including identical logical value data of consecutive bits corresponding to the transmission data based on the second clock.

2. The control device according to claim 1, wherein, in the parallel data generated by the output state machine, the number of bits of identical data in succession corresponding to the transmission data is V, the frequency of the first clock is W, the frequency of the second clock is X, and the number of bits of the transmission parallel data based on the second clock is Y, the output state machine outputs parallel data of V bits of identical logical value data in succession based on the second clock specified by the following equation, V = (X x Y) / W.

3. The control device according to claim 2, wherein, the number of bits of the parallel data output by the output state machine is the same as the number of bits Y of the transmission parallel data.

4. The control device according to claim 2 or 3, wherein, the output state machine receives a FIFO output from the FIFO and a flip-flop output from the flip-flop that latched the FIFO output from the FIFO one clock before the second clock, and generates the parallel data of V bits of identical data in succession based on the FIFO output and the flip-flop output.

5. The control device according to claim 4, wherein, the FIFO is enabled and controlled by a control signal from the output state machine.

6. The control device according to claim 2 or 3, wherein, the output state machine receives a first FIFO output and a second FIFO output from the FIFO and a flip-flop output from the flip-flop that latched the second FIFO output one clock before the second clock, and generates the parallel data of V bits of identical data in succession from the first FIFO output, the second FIFO output, and the flip-flop output.

7. The control device according to claim 6, wherein, According to a control signal from the output state machine, the FIFO is controlled not to output the first FIFO output only to output the second FIFO output, or to output the first FIFO output and output the next sequentially output data of the first FIFO output as the second FIFO output.

8. The control device according to any one of claims 1 to 3, 5, and 7, wherein The control device further has a selector that selects one of the transmission data and an output of the SerDes interface circuit to output to the SerDes.

9. The control device according to claim 8, wherein When a frequency of the second clock is set to X and a predetermined communication rate of serial data to be converted by the SerDes is set to Z, the predetermined communication rate Z is represented by Z = X x Y.

10. The control device according to any one of claims 1 to 3, 5, 7, and 9, wherein The SerDes has a function of converting received serial data of a predetermined communication rate into received parallel data, The control device further has a data recovery circuit that inputs the received parallel data converted by the SerDes and a bit conversion circuit that converts the received parallel data into a signal of the same specification as the transmission data.

11. The control device according to any one of claims 1 to 3, 5, 7, and 9, wherein The control device performs data transmission based on serial data with a counterpart device, An operation of the counterpart device is controlled based on serial data from the control device.

12. The control device according to claim 11, wherein The control device is a CNC device, The counterpart device is a machine tool controlled by the CNC device.

13. The control device according to claim 11, wherein The control device is a robot control device, The counterpart device is an industrial robot or a collaborative robot controlled by the robot control device.

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