Channel signal readout method, channel signal readout circuit and chip

Abstract

The present application relates to a channel signal readout method, a channel signal readout circuit, and a chip. The method includes: obtaining the voltage threshold value of each readout channel in a time-sharing manner, performing digital-to-analog conversion processing on the voltage threshold value of each readout channel to obtain the voltage threshold of each readout channel respectively, and determining the output value of the channel signal readout circuit based on the voltage threshold of each readout channel and the signal of each readout channel. The present method can obtain the voltage threshold of all readout channels through only one digital-to-analog converter provided inside the channel signal readout circuit, thereby reducing the number of digital-to-analog converters in the channel signal readout circuit and the scale of the channel signal readout circuit. Since the channel signal readout circuit is integrated into the chip, on the basis of reducing the scale of the channel signal readout circuit, the above-mentioned channel signal readout circuit can also reduce the area of ​​the chip and reduce the power consumption of the chip during operation.

Description

Technical Field

[0001] The present application relates to the field of medical imaging technology, and in particular to a channel signal readout method, a channel signal readout circuit, and a chip. Background Art

[0002] Medical imaging systems typically consist of detectors and chips. For example, an X-ray photon counting detector in a medical imaging system is connected to a chip, which integrates multiple channel signal readout circuits. Medical images are generated from the pixel values ​​output by each channel signal readout circuit.

[0003] In related art, the channel signal readout circuit includes a front-end amplifier, N digital-to-analog converters (DACs) that acquire threshold voltages, and N threshold comparators. Each threshold comparator is connected to a DAC and compares the threshold voltage output by the corresponding DAC with the output voltage of the front-end amplifier to output the corresponding pixel value based on the comparison result. However, the design of the channel signal readout circuit in related art results in high chip power consumption and area. Summary of the Invention

[0004] Based on this, it is necessary to provide a channel signal readout method, a channel signal readout circuit and a chip to address the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a channel signal readout method, the method comprising:

[0006] Obtain the voltage threshold value of each readout channel in a time-sharing manner;

[0007] Performing digital-to-analog conversion on the voltage threshold values ​​of each readout channel to obtain the voltage threshold values ​​of each readout channel;

[0008] The output value of the channel signal readout circuit is determined according to the voltage threshold of each readout channel and the signal of each readout channel.

[0009] In one embodiment, the method further includes:

[0010] After the voltage threshold of the last readout channel is obtained and before the output value of the channel signal readout circuit is determined, the voltage threshold values ​​of each readout channel are obtained in a time-sharing manner until the output value of the channel signal readout circuit is determined, and the cycle ends.

[0011] In one embodiment, obtaining the voltage threshold value of each readout channel in a time-sharing manner includes:

[0012] The voltage threshold value of each readout channel is obtained in at least two sub-time periods according to a preset time-sharing selection logic.

[0013] In one embodiment, the readout channel comprises a pixel readout channel; and / or the signal comprises a photon pulse.

[0014] In a second aspect, an embodiment of the present application provides a channel signal readout circuit, the channel signal readout circuit comprising: a control circuit, a first gate, a digital-to-analog converter, and a threshold comparison circuit;

[0015] The output end of the control circuit is connected to the first input end of the first gate; the output end of the first gate is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to multiple threshold comparison circuits, each threshold comparison circuit corresponds to at least one readout channel.

[0016] In one embodiment, the first gate includes a plurality of first gate switches, a first end of each first gate switch is connected to a corresponding storage unit, and second ends of the plurality of first gate switches are connected to a digital-to-analog converter.

[0017] In one embodiment, each threshold comparison circuit includes a second gate and a threshold comparison module, the first end of the second gate is connected to the digital-to-analog converter, the second end of the second gate is connected to the threshold comparison module, and the third end of the second gate is connected to the control circuit.

[0018] In one embodiment, the second gate is a second gate switch, the threshold comparison module includes a threshold comparator, and the second gate switch in the second gate is connected to the threshold comparator in the corresponding threshold comparison module.

[0019] In one embodiment, the threshold comparison circuit further includes a voltage holding circuit connected between the second gate switch and the threshold comparator in the threshold comparison circuit.

[0020] In a third aspect, an embodiment of the present application provides a chip comprising the channel signal readout circuit in any embodiment of the second aspect.

[0021] The above-mentioned channel signal readout method, channel signal readout circuit and chip include obtaining the voltage threshold value of each readout channel in time sharing, performing digital-to-analog conversion processing on the voltage threshold value of each readout channel to obtain the voltage threshold of each readout channel respectively, and determining the output value of the channel signal readout circuit according to the voltage threshold of each readout channel and the signal of each readout channel; the method can obtain the voltage threshold of each readout channel in time sharing by using the voltage threshold value of each readout channel obtained in time sharing, and process the voltage threshold of each readout channel obtained in time sharing to obtain the output value of the channel signal readout circuit. This process can avoid data congestion caused by parallel processing of data. The problem of data congestion is solved by processing data in a serial data processing manner, which can improve the speed of the channel signal readout process; at the same time, the method can obtain the voltage thresholds of all readout channels through only one digital-to-analog converter set inside the channel signal readout circuit, thereby reducing the number of digital-to-analog converters in the channel signal readout circuit and reducing the scale of the channel signal readout circuit. In addition, since the channel signal readout circuit is integrated into the chip, on the basis of reducing the scale of the channel signal readout circuit, the above-mentioned channel signal readout circuit can also reduce the area of ​​the chip and reduce the power consumption of the chip during operation, thereby improving the chip's data processing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 1 is a flow chart of a channel signal reading method according to an embodiment;

[0023] Figure 2 Schematic diagram of a flow chart of a channel signal reading method in another embodiment;

[0024] Figure 3 is a structural block diagram of a channel signal readout circuit in one embodiment;

[0025] Figure 4 for Figure 3 A schematic structural diagram of a channel signal readout circuit in an embodiment;

[0026] Figure 5 for Figure 4 A schematic structural diagram of a channel signal readout circuit in an embodiment;

[0027] Figure 6 for Figure 5 A schematic structural diagram of a channel signal readout circuit in an embodiment;

[0028] Figure 7 for Figure 6 Schematic diagram of the structure of the channel signal readout circuit in the embodiment.

[0029] Description of reference numerals:

[0030] 11: control circuit; 12: first gate;

[0031] 13: Digital-to-analog converter; 14: Threshold comparator circuit;

[0032] 15: threshold value memory; 121: first selection switch;

[0033] 141: a second gate; 142: a threshold comparison module;

[0034] 143: voltage holding circuit; 151: storage unit;

[0035] 1411: a second selection switch; 1421: a threshold comparator. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0037] Typically, the pixels of an X-ray photon counting detector are approximately one-tenth of a square millimeter. A single chip may integrate thousands of channel signal readout circuits. Each readout channel in the channel signal readout circuit relies on N threshold comparator circuits to quantify the voltage threshold generated by the photon pulses output by the X-ray photon counting detector. Based on the quantization results, the corresponding pixel value is classified and counted. However, during chip manufacturing, the threshold comparator circuits corresponding to different pixels are subject to various non-idealities, such as offset voltage, necessitating appropriate adjustment of the voltage threshold value for each pixel. The voltage threshold can be generated using either a current-steering digital-to-analog converter (DAC) or a resistor-based DAC. To meet the requirements of an X-ray photon counting detector, each pixel requires N threshold comparator circuits, resulting in N comparison threshold voltages and correspondingly N DACs to generate the voltage threshold values. Given the energy threshold resolution requirements of medical imaging systems, the DACs generating the comparison threshold voltages must have a precision of 7 to 10 bits. Therefore, when designing the circuit for each readout channel in the channel signal readout circuit, it includes a front-end amplifier, an event-triggered comparator, N threshold comparison circuits, and N digital-to-analog converters that generate threshold voltages. However, this design method of generating voltage threshold digital-to-analog converters consumes a lot of power and chip area, and may not be implemented in some cases in actual circuit design. Based on this, the present application proposes a channel signal readout method.

[0038] The channel signal readout method provided in the present application can be applied to medical imaging systems. Among them, the medical imaging system generally includes a detector and a chip. The detector can be an infrared imaging detector, a digital imaging flat-panel detector, an X-ray detector, etc. Optionally, multiple channel signal readout circuits are integrated on the chip; the detector can emit detection pulses to the entire chip area or a partial area of ​​the chip to ensure that each channel signal readout circuit can receive the detection pulse. Among them, the intensity of the detection pulses received by different channel signal readout circuits can be the same or different. Each channel signal readout circuit integrated on the chip processes the received detection pulse to generate a corresponding pixel value, and finally combines the output values ​​of all channel signal readout circuits to generate a medical image. In the embodiment of the present application, the channel signal readout method and the channel signal readout circuit are explained by taking the detector as an X-ray photon counting detector as an example.

[0039] like Figure 1 FIG. 1 is a flow chart of a channel signal readout method provided in an embodiment of the present application. The method is described by taking a channel signal readout circuit as an example. The method includes the following steps:

[0040] S100 , obtaining the voltage threshold value of each readout channel in a time-sharing manner.

[0041] Specifically, the above-mentioned time sharing can be understood as different time points within a certain time period and / or multiple different sub-time periods within a certain time period. For example, if it is necessary to obtain the voltage threshold values ​​of three readout channels in a time period T1-T2 in a time-sharing manner, and a voltage threshold value can be obtained at one time point, the corresponding three time points are t1, t2, and t3, then t1 and t2 can be called adjacent time points, and t2 and t3 can be called adjacent time points; wherein, the time intervals between adjacent time points in different time points can be equal or unequal; and the time intervals between adjacent time points can be equal to 0 or greater than 0.

[0042] Continuing with the previous example, if a voltage threshold value can be obtained within a sub-time period, the corresponding three sub-time periods for obtaining the three voltage threshold values ​​are (t1-t2), (t3-t4), and (t5-t6). Then (t1-t2) and (t3-t4) can be called adjacent sub-time periods, and (t3-t4) and (t5-t6) can be called adjacent sub-time periods. The time intervals between adjacent sub-time periods can be equal or unequal, and the time intervals between adjacent time points can be equal to or greater than 0.

[0043] It is understood that the voltage threshold values ​​of the aforementioned readout channels may be values ​​pre-stored by the channel signal readout circuit, or values ​​generated in real time by a portion of the channel signal readout circuit. Alternatively, the voltage threshold values ​​of different readout channels may be the same or different. Alternatively, the channel signal readout circuit may include multiple readout channels.

[0044] S200 , performing digital-to-analog conversion on the voltage threshold value of each readout channel to obtain the voltage threshold of each readout channel.

[0045] Specifically, the digital-to-analog conversion process can be understood as the process of converting a digital signal into a voltage signal. The channel signal readout circuit can perform digital-to-analog conversion on the voltage threshold values ​​of each readout channel to obtain the voltage threshold values ​​corresponding to each readout channel.

[0046] It should be noted that the same voltage threshold value corresponds to the same voltage threshold, and different voltage threshold values ​​correspond to different voltage thresholds.

[0047] S300 , determining the output value of the channel signal readout circuit according to the voltage threshold of each readout channel and the signal of each readout channel.

[0048] Specifically, the signals of the above-mentioned readout channels may be pulse signals, such as imaging pulses, X-ray pulses, radio frequency pulses, etc. In the embodiment of the present application, if the types of detectors are different, the types of signals of the corresponding readout channels are different.

[0049] In one embodiment, the readout channels include pixel readout channels; the signals from each readout channel include photon pulses. For example, when the detector is an X-ray photon counting detector, the signals are photon pulses. The photon pulses can all be photon detection signals emitted by the X-ray photon counting detector and received by the channel signal readout circuit. That is, the photon pulses received by each readout channel in the channel signal readout circuit are identical.

[0050] It should be noted that the channel signal readout circuit can perform a first operation on the voltage threshold of each readout channel and the signal of each readout channel to obtain the operation result of each readout channel, and then perform a second operation on the operation result to obtain the channel signal readout circuit output value, that is, the pixel value output by the channel signal readout circuit. In the embodiment of the present application, the channel signal readout circuit can output a corresponding pixel value.

[0051] It is understood that the first and second operation processes are different; however, both the first and second operation processes can be judgment processes, comparison processes, and / or arithmetic operations, etc. Optionally, the judgment process can be understood as a process of determining whether the voltage threshold of each readout channel is greater than, less than, or equal to the value of the signal, or as a process of determining whether the voltage threshold of some readout channels is greater than the value of the signal and determining whether the voltage threshold of the remaining readout channels in the channel signal readout circuit is less than or equal to the value of the signal. Of course, other judgment processes are also possible. Optionally, the arithmetic operation process can be a process of performing addition, subtraction, multiplication, logarithm operation, and / or exponential operation on the voltage threshold of each readout channel and the value of the signal.

[0052] The channel signal readout method provided in the embodiment of the present application can obtain the voltage threshold value of each readout channel in a time-sharing manner, perform digital-to-analog conversion on the voltage threshold value of each readout channel, obtain the voltage threshold of each readout channel respectively, and determine the output value of the channel signal readout circuit based on the voltage threshold of each readout channel and the signal of each readout channel; the method can obtain the voltage threshold of each readout channel in a time-sharing manner by using the voltage threshold value of each readout channel obtained in a time-sharing manner, and process the voltage threshold of each readout channel obtained in a time-sharing manner to determine the output value of the channel signal readout circuit. This process can avoid the problem of data congestion caused by parallel data processing. Processing data in a serial manner can increase the speed of the channel signal readout process. At the same time, this method can obtain the voltage thresholds of all readout channels through only one digital-to-analog converter provided within the channel signal readout circuit, thereby reducing the number of digital-to-analog converters in the channel signal readout circuit and reducing the scale of the channel signal readout circuit. In addition, since the channel signal readout circuit is integrated into the chip, on the basis of reducing the scale of the channel signal readout circuit, the above-mentioned channel signal readout circuit can also reduce the chip area and reduce the power consumption of the chip during operation, thereby increasing the chip's data processing speed.

[0053] In some scenarios, there may be a problem that the temporary storage time of the voltage threshold value of the readout channel is relatively short. Before the voltage threshold value of the readout channel at the back of the channel signal readout circuit is obtained, the voltage threshold value of the readout channel at the front of the channel signal readout circuit has automatically disappeared, and the calculation processing of the voltage threshold value of the readout channel at the front and the signal value has not been completed at this time. Therefore, it is necessary to re-acquire the voltage threshold value of each readout channel in the channel signal readout circuit in sequence to ensure that the channel signal readout circuit outputs the corresponding pixel value. Based on this, in one embodiment, before determining the output value of the channel signal readout circuit, the above-mentioned channel signal readout method may include:

[0054] After the voltage threshold of the last readout channel is obtained and before the output value of the channel signal readout circuit is determined, the voltage threshold values ​​of each readout channel are obtained in a time-sharing manner until the output value of the channel signal readout circuit is determined, and the cycle ends.

[0055] Specifically, the channel signal readout circuit can first obtain the voltage threshold value of each readout channel in the channel signal readout circuit in a time-sharing manner, and after determining the voltage threshold value of the last readout channel and when the output value of the channel signal readout circuit is not determined, the voltage threshold value of each readout channel in the channel signal readout circuit can continue to be obtained in a time-sharing manner until the output value of the channel signal readout circuit is determined, and then the step of obtaining the voltage threshold value of each readout channel in the channel signal readout circuit in a time-sharing manner is stopped.

[0056] It should be noted that the order of obtaining the voltage threshold values ​​of each readout channel in a complete time-sharing manner can be any arrangement order of the readout channels in the channel signal readout circuit. For example, if there are 5 readout channels in the channel signal readout circuit, namely, readout channel 1, readout channel 2, readout channel 3, readout channel 4 and readout channel 5, readout channel 1 is close to the input end of the channel signal readout circuit, readout channel 5 is close to the output end of the channel signal readout circuit, and the arrangement order of the 5 readout channels from the input end to the output end of the channel signal readout circuit is readout channel 1, readout channel 2, readout channel 3, readout channel 4 and readout channel 5, then in a complete time-sharing manner, the voltage threshold values ​​of each readout channel can be obtained in any arrangement order of the readout channels in the channel signal readout circuit. In the process of obtaining the voltage threshold value of the channel, the voltage threshold values ​​of the read-out channel 3, the read-out channel 2, the read-out channel 4, the read-out channel 5 and the read-out channel 1 can be obtained in sequence in a time-sharing manner. The voltage threshold values ​​of the read-out channel 4, the read-out channel 3, the read-out channel 5, the read-out channel 2 and the read-out channel 1 can also be obtained in sequence in a time-sharing manner. Of course, the voltage threshold values ​​of the read-out channel 2, the read-out channel 4, the read-out channel 5, the read-out channel 1 and the read-out channel 3 can also be obtained in sequence in a time-sharing manner. The embodiment of the present application does not limit the time-sharing acquisition order.

[0057] In an embodiment of the present application, in order to increase the speed of acquiring the voltage threshold value of each readout channel, the voltage threshold values ​​of adjacent readout channels can be acquired in a time-sharing manner according to the arrangement order of the readout channels. For example, the voltage threshold values ​​of readout channel 1, readout channel 2, readout channel 3, readout channel 4, and readout channel 5 can be acquired in a time-sharing manner, or the voltage threshold values ​​of readout channel 5, readout channel 4, readout channel 3, readout channel 2, and readout channel 1 can be acquired in a time-sharing manner.

[0058] In order to adapt to different application scenarios, Figure 1 On the basis of Figure 2 As shown, the step of obtaining the voltage threshold value of each readout channel in time sharing in the above S100 may include:

[0059] S110 , obtaining a voltage threshold value of each readout channel in at least two sub-time periods according to a preset time-sharing selection logic.

[0060] It is understood that the preset time-sharing selection logic can be a user-defined fixed selection frequency or a user-defined variable selection frequency, or can be a selection frequency determined by the timing of the voltage threshold values ​​of each readout channel generated in real time by the channel signal readout circuit. Of course, the embodiments of the present application do not limit this time-sharing selection logic. In order to increase the speed at which the channel signal readout circuit outputs pixel values, the above-mentioned selection frequency can be set slightly larger.

[0061] In the embodiment of the present application, the channel signal readout circuit obtains the voltage threshold values ​​in a time-sharing manner. Therefore, the sub-time periods required to obtain different voltage threshold values ​​are the same. However, in the embodiment of the present application, due to errors, the sub-time periods required to obtain different voltage threshold values ​​are different. In actual applications, the durations corresponding to different sub-time periods will not differ greatly.

[0062] The channel signal readout method provided in the embodiment of the present application can continue to execute time-sharing acquisition of the voltage threshold values ​​of each readout channel after obtaining the voltage threshold of the last readout channel and before determining the output value of the channel signal readout circuit, until the output value of the channel signal readout circuit is determined, and the loop ends; this method can avoid the situation where the voltage threshold of the frontmost readout channel automatically disappears before the calculation processing is completed when the voltage threshold of the last readout channel is obtained, thereby ensuring that the channel signal readout circuit can obtain the corresponding pixel value by cyclically obtaining the voltage threshold of each readout channel, and the cyclic acquisition method can also improve the efficiency of the channel signal readout circuit in obtaining the corresponding pixel value.

[0063] like Figure 3 The figure shows a block diagram of the channel signal readout circuit provided in an embodiment of the present application. The channel signal readout circuit includes: a control circuit 11, a first gate 12, a digital-to-analog converter 13, and a threshold comparison circuit 14. The output of the control circuit 11 is connected to the first input of the first gate 12; the output of the first gate 12 is connected to the input of the digital-to-analog converter 13; the output of the digital-to-analog converter 13 is connected to multiple threshold comparison circuits 14, each of which corresponds to at least one readout channel.

[0064] Specifically, the control circuit 11 in the channel signal readout circuit can have multiple output terminals; the control circuit 11 can also have one or more input terminals, or no input terminals. In actual operation of the channel signal readout circuit, some of the output terminals and input terminals in the control circuit 11 can be suspended, but at least one output terminal of the control circuit 11 must be in an operational state. Optionally, the control circuit 11 can be implemented using a sensor, a signal input circuit, a trigger circuit, an error correction circuit, a signal processing circuit, and / or a drive circuit, among others. Optionally, the control circuit 11 can be a programmable logic controller, a relay, and the like. Furthermore, the control circuit 11 can also be other devices capable of implementing control functions.

[0065] Optionally, the first selector 12 in the channel signal readout circuit may be a multiplexer, a multi-way switch, or a switch circuit. Optionally, the switch circuit may be a single-pole multi-throw switch or a combinational logic circuit, which may be implemented by an AND gate, an OR gate, an XOR gate, an AND-OR gate, or the like.

[0066] It should be noted that the digital-to-analog converter 13 in the channel signal readout circuit can be implemented by a resistor network, a capacitor network, an operational amplifier, a reference power supply, and / or an analog switch, etc. Optionally, the digital-to-analog converter 13 can be a weighted resistor digital-to-analog converter, a T-type resistor digital-to-analog converter, an inverted T-type resistor digital-to-analog converter, a weighted current digital-to-analog converter, or a weighted capacitance digital-to-analog converter, etc.

[0067] It can be understood that the threshold comparison circuit 14 in the channel signal readout circuit can realize the function of data comparison. Optionally, the threshold comparison circuit 14 can be implemented by a combinational logic circuit and / or a switching circuit. Optionally, the channel signal readout circuit may include multiple threshold comparison circuits 14; wherein, the total number of threshold comparison circuits 14 may be less than or equal to the total number of readout channels arranged in the channel signal readout circuit. Optionally, if the total number of threshold comparison circuits 14 included in the channel signal readout circuit is equal to the total number of readout channels, then each threshold comparison circuit 14 corresponds to one readout channel; if the total number of threshold comparison circuits 14 included in the channel signal readout circuit is less than the total number of readout channels, then each threshold comparison circuit 14 may correspond to one readout channel or to multiple readout channels. Optionally, Figure 3 Only two threshold comparison circuits 14 are shown in the channel signal readout circuit, and the other one or more threshold comparison circuits 14 are represented by ellipsis.

[0068] Among them, the control circuit 11, the first gate 12, the digital-to-analog converter 13 and the threshold comparison circuit 14 in the channel signal readout circuit can be implemented by the same devices, such as resistors, capacitors, inductors, logic circuits, etc. However, the connection relationship between the same devices in the control circuit 11, the first gate 12, the digital-to-analog converter 13 and the threshold comparison circuit 14 can be the same, that is, the internal structures of the control circuit 11, the first gate 12, the digital-to-analog converter 13 and the threshold comparison circuit 14 are different, so that the control circuit 11, the first gate 12, the digital-to-analog converter 13 and the threshold comparison circuit 14 can achieve different functions.

[0069] Optionally, the control circuit 11 in the channel signal readout circuit can send a control signal to the first selector 12, so that the first selector 12 selects the voltage threshold value of each readout channel in a time-sharing manner, and inputs the voltage threshold value of each readout channel after time-sharing selection into the digital-to-analog converter 13. The digital-to-analog converter 13 performs digital-to-analog conversion on the received voltage threshold value of each readout channel in a time-sharing manner to obtain the voltage threshold value of each readout channel, and then inputs the voltage threshold value of each readout channel obtained in a time-sharing manner into the corresponding threshold comparison circuit 14, so that the threshold comparison circuit 14 processes the received signal and the voltage threshold value corresponding to each readout channel to obtain the corresponding pixel value output by the channel signal readout circuit. Optionally, the above-mentioned control signal can be a high-level signal or a low-level signal.

[0070] In the embodiments of the present application, when the intervals between photon pulses emitted by an X-ray photon counting detector are relatively short, the threshold comparison circuit will frequently operate, causing the threshold comparison circuit to quickly interfere with the energy decision error limit. In this case, when designing the channel signal readout circuit, consideration can be given to reducing the number of readout channels. Furthermore, a circuit array composed of multiple channel signal readout circuits can achieve monolithic chip integration, thereby facilitating two-dimensional splicing of X-ray photon counting detectors and achieving CT scanning-level X-ray photon counting detector detection planes.

[0071] It is understood that in the embodiment of the present application, the voltage threshold values ​​of each readout channel selected by the first selector 12 are pre-stored. The channel signal readout circuit may further include a threshold value memory, which may be a read-only memory. Optionally, the threshold value memory stores preset voltage threshold values ​​for each readout channel. Optionally, the first selector 12 may time-share the preset voltage threshold values ​​stored in the threshold value memory for each readout channel.

[0072] The channel signal readout circuit provided in the embodiment of the present application includes a control circuit, a first selector, a digital-to-analog converter and a threshold comparison circuit. The output end of the digital-to-analog converter is connected to multiple threshold comparison circuits, and each threshold comparison circuit corresponds to at least one readout channel. The channel signal readout circuit can avoid the situation where a large number of digital-to-analog converters are required to generate a set of voltage thresholds. Only one digital-to-analog converter can provide the voltage thresholds of each readout channel for multiple threshold comparison circuits. This reduces the number of digital-to-analog converters in the channel signal readout circuit without affecting the normal operation of the channel signal readout circuit, thereby reducing the scale of the channel signal readout circuit, simplifying the structure of the channel signal readout circuit, and reducing the design cost. It can also reduce the temperature rise of the channel signal readout circuit during use and will not affect the performance of the detection crystal in the front-end detector corresponding to the channel signal readout circuit. At the same time, since the channel signal readout circuit is integrated into the chip, on the basis of reducing the scale of the channel signal readout circuit, the above-mentioned channel signal readout circuit can also reduce the area of ​​the chip and reduce the power consumption of the chip during operation, thereby improving the chip's data processing speed. The structure is simpler, the energy consumption is lower, and the cost is lower.

[0073] In order to time-share the voltage threshold values ​​of each readout channel, the internal structure of the first selector 12 provided in the above-mentioned channel signal readout circuit and the connection relationship between the internal structure and other structures in the channel signal readout circuit are described below. Figure 4 As shown, the first selector 12 in the channel signal readout circuit includes multiple first selection switches 121, the first end of each first selection switch 121 is correspondingly connected to a storage unit, the second ends of the multiple first selection switches 121 are connected to the digital-to-analog converter 13, and the third ends of the multiple first selection switches 121 are connected to the first end of the control circuit 11.

[0074] in, Figure 4 Only four first selection switches 121 are shown, and the other one or more first selection switches 121 are represented by ellipsis, and Figure 4 A storage unit is shown in FIG. 1 , and the storage unit is arranged outside the channel signal readout circuit.

[0075] Specifically, the first selector 12 in the channel signal readout circuit can be implemented by a plurality of first selector switches 121, and the total number of the first selector switches 121 can be equal to the total number of all readout channels in the channel signal readout circuit. Optionally, the first selector switch 121 can be a voice-activated switch, a light-activated switch, a touch switch, a button switch, a membrane switch, a sliding switch, or the like. Optionally, the plurality of first selector switches 121 in the first selector 12 can be selector switches of the same type or of different types, and if the plurality of first selector switches 121 are selector switches of the same type, the models of the first selector switches 121 can be different, which is not limited in the embodiment of the present application.

[0076] It should be noted that each first selection switch 121 may include two ports, namely a first end and a second end. The first end of each first selection switch 121 may be connected to the same storage unit, and the second ends of multiple first selection switches 121 are simultaneously connected to the input end of the digital-to-analog converter 13. In the embodiment of the present application, the control circuit 11 may include two ports, namely a first end and a second end, both of which are output ends; the first end of the control circuit 11 is connected to the third end of each first selection switch 121.

[0077] Alternatively, the storage unit may be a structure having a storage function external to or internal to the channel signal readout circuit. There may be one or more storage units. A storage unit may store a voltage threshold value of a readout channel. Alternatively, the storage unit may be a register, a memory, or the like.

[0078] Among them, since the digital-to-analog converter 13 determines the voltage threshold of each readout channel in a time-sharing manner, it is necessary to input the voltage threshold of each readout channel into each threshold comparison circuit 14 for processing in a time-sharing manner. Based on this, a gate needs to be set in each threshold comparison circuit 14 to achieve time-sharing gating to obtain the voltage threshold of each readout channel output by the digital-to-analog converter 13. The internal structure of the threshold comparison circuit 14, the connection relationship of the internal structure, and the connection relationship between the internal structure and other structures in the channel signal readout circuit will be introduced below. In one embodiment, in Figure 4 On the basis of Figure 5 As shown, each threshold comparison circuit 14 in the above-mentioned channel signal readout circuit includes a second gate 141 and a threshold comparison module 142, a first end of the second gate 141 is connected to the digital-to-analog converter 13, a second end of the second gate 141 is connected to the threshold comparison module 142, and a third end of the second gate 141 is connected to the control circuit 11.

[0079] In the embodiment of the present application, the second gate 141 in the threshold comparison circuit 14 may include three ports, namely a first terminal, a second terminal, and a third terminal. Optionally, the first terminal and the third terminal of the second gate 141 may be two input terminals of the second gate 141, and the second terminal of the second gate 141 may be an output terminal of the second gate 141. One input terminal of the second gate 141 is connected to the output terminal of the digital-to-analog converter 13, the output terminal of the second gate 141 is connected to the input terminal of the threshold comparison module 142, and the other input terminal of the second gate 141 is connected to the second terminal of the control circuit 11.

[0080] It is understood that each threshold comparison circuit 14 may include a second gate 141. The second gate 141 may be a single-pole multi-throw switch, a relay, or the like. The single-pole multi-throw switches in each threshold comparison circuit 14 may be of the same or different types. Alternatively, the threshold comparison module 142 in the threshold comparison circuit 14 may be implemented using a combinational logic circuit and components such as resistors and capacitors.

[0081] In an actual channel signal readout circuit, the total number of second gates 141 can be equal to the total number of readout channels, and the total number of threshold comparison modules 142 can be equal to the total number of readout channels. In other words, the total number of second gates 141 and the total number of threshold comparison modules 142 in the channel signal readout circuit are the same.

[0082] Among them, Figure 5 On the basis of Figure 6 As shown, the second gate 141 in the threshold comparison circuit 14 includes a second gate switch 1411 , the threshold comparison module 142 includes a threshold comparator 1421 , and the second gate switch 1411 in the second gate 141 is connected to the threshold comparator 1421 in the corresponding threshold comparison module 142 .

[0083] In the embodiment of the present application, each second selector 141 includes a second selector switch 1411. The second selector switch 1411 is a single-pole single-throw switch, such as a voice-activated switch, a light-activated switch, a touch switch, a button switch, a membrane switch, or a slide switch. In addition, the single-pole single-throw switch in each threshold comparison circuit 14 can be the same or different in type.

[0084] Optionally, the threshold comparison module 142 in the threshold comparison circuit 14 may include a threshold comparator. In the actual channel signal readout circuit, the second selection switch 1411 in each second selection device 141 is respectively connected to the threshold comparison module 142 in the corresponding threshold comparison circuit 14. Optionally, the threshold comparator 1421 may be a digital comparator of any model. The digital comparators included in the threshold comparison module 142 may be of the same model or different models.

[0085] The channel signal readout circuit provided in an embodiment of the present application includes a first selector, which includes multiple first selection switches. The input ends of the multiple first selection switches are all connected to the output end of the control circuit. The control circuit provided in the channel signal readout circuit can control the conduction of the multiple first selectors in a time-sharing manner, so as to input the voltage threshold values ​​of the readout channels time-sharingly selected by each first selection switch into the same data converter in a time-sharing manner, so that the channel signal readout circuit can determine the voltage threshold values ​​of each readout channel in a time-sharing manner through the same data converter, thereby reducing the number of digital-to-analog converters in the channel signal readout circuit and reducing the scale of the channel signal readout circuit.

[0086] In some scenarios, in order to prevent the voltage threshold of the corresponding readout channel received by each threshold comparator 1421 from disappearing instantly, a circuit structure with a data retention function can be set in the threshold comparison circuit 14, so that the voltage threshold of the readout channel received by each threshold comparator 1421 can be maintained for a period of time. Figure 6 On the basis of Figure 7 As shown, the threshold comparison circuit 14 in the channel signal readout circuit further includes a voltage holding circuit 143 , which is connected between the second selection switch 1411 and the threshold comparator 1421 in the threshold comparison circuit 14 .

[0087] The control circuit 11 is used to control the second selection switch 1411 to conduct the path between the digital-to-analog converter 13 and the corresponding threshold comparator 1421, and then maintain the voltage threshold of each readout channel through the voltage holding circuit 143 on the corresponding path.

[0088] Specifically, each threshold comparison circuit 14 may include a voltage holding circuit. That is, each threshold comparison circuit 14 includes a second selection switch, a threshold comparator, and a voltage holding circuit; in each threshold comparison circuit 14, one end of the voltage holding circuit 143 is connected between the second selection switch 1411 and the threshold comparator 1421 in the threshold comparison circuit 14, and the other end of the voltage holding circuit 143 is grounded. Optionally, the voltage holding circuit 143 can be implemented by devices such as a switch, an operational amplifier, a transistor, a diode, a triode, a resistor, and / or a capacitor. However, in the embodiment of the present application, the above-mentioned voltage holding circuit 143 can be implemented by a capacitor.

[0089] The voltage holding circuit 143 in the threshold comparison circuit 14 can hold the voltage threshold of the readout channel selected by each second selection switch 1411 so that the voltage threshold of the corresponding readout channel can be maintained at the input end of the threshold comparator 1421 for a period of time.

[0090] In another embodiment, see Figure 7 As shown, the above-mentioned channel signal readout circuit also includes: a threshold value memory 15; the threshold value memory 15 includes a plurality of storage units 151, and the output end of each storage unit is connected to the second input end of the first selector 12; each storage unit 151 stores the preset voltage threshold value of each readout channel.

[0091] It should be noted that the channel signal readout circuit further includes a threshold value memory 15, which may include a plurality of storage units 151. The total number of storage units 151 may be less than the total number of readout channels, or may be equal to the total number of first selection switches 121. In the embodiment of the present application, the total number of storage units 151 is equal to the total number of readout channels, and each storage unit 151 stores a preset voltage threshold value for a readout channel. Figure 7 Only four storage units 151 are shown, and the other one or more storage units 151 are represented by ellipsis.

[0092] The threshold comparison circuit in the channel signal readout circuit provided in the embodiment of the present application is further provided with a voltage holding circuit, so as to maintain the voltage threshold of the readout channel selected by each second selection switch through the voltage holding circuit, thereby preventing the voltage threshold of the corresponding readout channel received by each threshold comparator from disappearing instantaneously, so that the voltage threshold of the corresponding readout channel can be maintained at the input end of the threshold comparator for a period of time, thereby extending the data processing time of the threshold comparator in the threshold comparison circuit, and further improving the processing performance of the channel signal readout circuit.

[0093] Based on the channel signal readout circuit provided above, the present application further provides a chip, which includes the channel signal readout circuit provided by any of the above embodiments.

[0094] Optionally, the channel signal readout circuit is integrated on a chip, and a processor is also integrated on the chip, and the operating state of the channel signal readout circuit can be controlled by the processor.

[0095] The chip provided in the embodiment of the present application may include the channel signal readout circuit provided in any of the above embodiments, and its implementation principles and technical effects are similar, which will not be repeated here.

[0096] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A channel signal readout method, characterized in that: The method comprises: Obtain the voltage threshold value of each readout channel in a time-sharing manner; Performing digital-to-analog conversion on the voltage threshold values ​​of the readout channels in sequence to obtain the voltage threshold values ​​of the readout channels respectively; Comparison is performed in sequence based on the voltage threshold of each readout channel and the signal of the corresponding readout channel to determine the output value of the channel signal readout circuit.

2. The channel signal reading method according to claim 1, wherein: The method further comprises: After obtaining the voltage threshold of the last readout channel and before determining the output value of the channel signal readout circuit, continue to execute the time-sharing acquisition of the voltage threshold values ​​of each readout channel until the output value of the channel signal readout circuit is determined, and the loop ends.

3. The channel signal reading method according to claim 2, wherein: The time-sharing acquisition of the voltage threshold value of each readout channel includes: The voltage threshold value of each readout channel is obtained in at least two sub-time periods according to a preset time-sharing selection logic.

4. The channel signal readout method according to any one of claims 1 to 3, characterized in that: The readout channel comprises a pixel readout channel; and / or the signal comprises a photon pulse.

5. A channel signal readout circuit, characterized in that: Used to perform the method according to any one of claims 1 to 4 above; the channel signal readout circuit comprises: a control circuit, a first gate, a digital-to-analog converter and a threshold comparison circuit; The output end of the control circuit is connected to the first input end of the first gate; the output end of the first gate is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to multiple threshold comparison circuits, each threshold comparison circuit corresponds to at least one readout channel.

6. The channel signal readout circuit according to claim 5, characterized in that: The first gate includes a plurality of first gate switches, a first end of each first gate switch is connected to a corresponding storage unit, and second ends of the plurality of first gate switches are connected to the digital-to-analog converter.

7. The channel signal readout circuit according to claim 5 or 6, characterized in that: Each threshold comparison circuit includes a second gate and a threshold comparison module, the first end of the second gate is connected to the digital-to-analog converter, the second end of the second gate is connected to the threshold comparison module, and the third end of the second gate is connected to the control circuit.

8. The channel signal readout circuit according to claim 7, characterized in that: The second gate includes a second gate switch, the threshold comparison module includes a threshold comparator, and the second gate switch in the second gate is connected to the threshold comparator in the corresponding threshold comparison module.

9. The channel signal readout circuit according to claim 8, characterized in that: The threshold comparison circuit further includes a voltage holding circuit connected between the second gate switch and the threshold comparator in the threshold comparison circuit.

10. A chip, characterized in that: The chip includes the channel signal readout circuit according to any one of claims 5 to 9.

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