Partial erase management method, storage device and memory control circuit

Abstract

The present invention provides a partial erasing management method, a memory storage device, and a memory control circuit unit. The method includes: performing a first partial erasing operation on a first physical region among a plurality of physical regions of a first physical erasing unit to erase first data in the first physical region; after performing the first partial erasing operation on the first physical region, performing a first programming operation on the first physical region to store second data in the first physical region; and updating first status information associated with the first physical region in response to at least one of the first partial erasing operation and the first programming operation. Thus, the management efficiency of a physical unit supporting partial erasing can be improved.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and in particular to a partial erase management method, a memory storage device and a memory control circuit unit. Background Art

[0002] Portable electronic devices such as mobile phones and notebook computers have experienced rapid growth in recent years, leading to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideal for integration into various portable electronic devices, due to their non-volatility, power efficiency, compact size, and lack of mechanical structure.

[0003] Traditionally, erase operations in rewritable non-volatile memory modules are performed using one or more physical blocks as the basic unit. However, this erase method lacks flexibility. Furthermore, while some memory device types support partial erase of physical blocks, the associated management mechanisms are not well-developed, resulting in reduced system stability when performing partial erases. Summary of the Invention

[0004] The present invention provides a partial erasure management method, a memory storage device and a memory control circuit unit, which can improve the management efficiency of a physical unit supporting partial erasure.

[0005] An exemplary embodiment of the present invention provides a partial erase management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical erase units. The plurality of physical erase units include a first physical erase unit. The partial erase management method includes: performing a first partial erase operation on a first physical area among a plurality of physical areas in the first physical erase unit to erase first data in the first physical area, wherein the plurality of physical areas are used sequentially based on a preset order; after performing the first partial erase operation on the first physical area, performing a first programming operation on the first physical area to store second data in the first physical area; and updating first status information related to the first physical area in response to at least one of the first partial erase operation and the first programming operation.

[0006] In an exemplary embodiment of the present invention, when the first physical region is in the erased state, the remaining physical regions of the plurality of physical regions are not in the erased state.

[0007] In an exemplary embodiment of the present invention, after the first programming operation is performed on the first physical region, the second physical region among the plurality of physical regions still stores third data to be erased.

[0008] In an exemplary embodiment of the present invention, the partial erase management method further includes: after performing the first programming operation on the first physical area, performing a second partial erase operation on a second physical area among the plurality of physical areas to erase third data in the second physical area, wherein the second physical area is different from the first physical area.

[0009] In an exemplary embodiment of the present invention, the partial erase management method further includes: after performing the second partial erase operation on the second physical area, performing a second programming operation on the second physical area to store fourth data in the second physical area; and in response to at least one of the second partial erase operation and the second programming operation, updating second status information related to the second physical area, wherein the updated second status information is the same as the updated first status information.

[0010] In an exemplary embodiment of the present invention, sequentially using the plurality of physical regions based on the preset order includes sequentially erasing and programming the plurality of physical regions based on the preset order.

[0011] In an exemplary embodiment of the present invention, the partial erase management method further includes: obtaining a usage status of the first physical area according to the first status information.

[0012] In an exemplary embodiment of the present invention, the partial erase management method further includes: reconstructing a mapping table according to the first status information, wherein the mapping table records logic-to-physical mapping information related to the second data.

[0013] In an exemplary embodiment of the present invention, the partial erase management method further includes: obtaining a distribution state of new data and old data in the first physical erase unit according to the first state information; and performing a second partial erase operation on the old data.

[0014] In an exemplary embodiment of the present invention, the first status information reflects at least one of an erase progress and a programming progress of the first physical erase unit.

[0015] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The connection interface unit is used to connect to a host system. The rewritable non-volatile memory module includes multiple physical erase units. The multiple physical erase units include a first physical erase unit. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: instruct a first physical area among multiple physical areas in the first physical erase unit to perform a first partial erase operation to erase first data in the first physical area, wherein the multiple physical areas are used sequentially based on a preset order; after performing the first partial erase operation on the first physical area, instruct a first programming operation to perform on the first physical area to store second data in the first physical area; and update first status information related to the first physical area in response to at least one of the first partial erase operation and the first programming operation.

[0016] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: after performing the first programming operation on the first physical region, instruct to perform a second partial erase operation on a second physical region of the plurality of physical regions to erase third data in the second physical region, wherein the second physical region is different from the first physical region.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: after performing the second partial erase operation on the second physical region, instruct to perform a second programming operation on the second physical region to store fourth data in the second physical region; and in response to at least one of the second partial erase operation and the second programming operation, update second status information related to the second physical region, wherein the updated second status information is the same as the updated first status information.

[0018] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to obtain a usage status of the first physical area according to the first status information.

[0019] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: reconstruct a mapping table according to the first state information, wherein the mapping table records logic-to-physical mapping information related to the second data.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: obtain a distribution state of new data and old data in the first physical erase unit according to the first state information; and perform a second partial erase operation on the old data.

[0021] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical erase units. The plurality of physical erase units include a first physical erase unit. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to: instruct a first physical region among a plurality of physical regions in the first physical erase unit to perform a first partial erase operation to erase first data in the first physical region, wherein the plurality of physical regions are used sequentially based on a preset order; after performing the first partial erase operation on the first physical region, instruct a first programming operation to perform on the first physical region to store second data in the first physical region; and update first status information associated with the first physical region in response to at least one of the first partial erase operation and the first programming operation.

[0022] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: after performing the first programming operation on the first physical area, instruct to perform a second partial erase operation on a second physical area among the plurality of physical areas to erase third data in the second physical area, wherein the second physical area is different from the first physical area.

[0023] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: after performing the second partial erase operation on the second physical region, instruct a second programming operation to be performed on the second physical region to store fourth data in the second physical region; and in response to at least one of the second partial erase operation and the second programming operation, update second status information associated with the second physical region, wherein the updated second status information is the same as the updated first status information.

[0024] In an exemplary embodiment of the present invention, the memory management circuit is further configured to obtain a usage status of the first physical area according to the first status information.

[0025] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: reconstruct a mapping table according to the first status information, wherein the mapping table records logic-to-physical mapping information related to the second data.

[0026] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: obtain a distribution state of new data and old data in the first physical erasing unit according to the first state information; and perform a second partial erasing operation on the old data.

[0027] Based on the above, for a first physical erase unit supporting partial erase, after performing a first partial erase operation on a first physical region in the first physical erase unit to erase first data, a first programming operation can be subsequently performed on the first physical region to write second data. In particular, in response to the first partial erase operation and / or the first programming operation, first state information associated with the first physical region can be updated. This first state information can then be used to improve the efficiency of managing the partial erase mechanism of the first physical erase unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0034] Figure 7 is a schematic diagram of multiple physical areas in a physical erase unit and their use order according to an exemplary embodiment of the present invention;

[0035] Figures 8A to 8C is a schematic diagram illustrating an operation mechanism of partial erasure according to an exemplary embodiment of the present invention;

[0036] Figure 9 is a schematic diagram showing how to store state information in various physical areas according to an exemplary embodiment of the present invention;

[0037] 10A to 10D is a schematic diagram illustrating updating state information in response to a partial erase and / or programming operation according to an exemplary embodiment of the present invention;

[0038] Figure 11 FIG. 4 is a flow chart of a partial erase management method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0039] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0040] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to the memory storage device or read data from the memory storage device.

[0041] Figure 1 FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0042] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 , and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 , and the data transmission interface 114 may be connected to a system bus 110 .

[0043] In one exemplary embodiment, the host system 11 may be connected to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 may be connected to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I / O device 12 or receive input signals from the I / O device 12 via the system bus 110.

[0044] In one exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 via a wired or wireless method.

[0045] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a Wi-Fi (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a display 209, and a speaker 210, via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0046] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can each include Figure 3 The memory storage device 30 and the host system 31 are connected.

[0047] Figure 3 FIG. 1 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0048] Please refer to Figure 3, the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0049] Figure 4 FIG. 1 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0050] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 and a rewritable non-volatile memory module 43 .

[0051] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In one exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0052] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to instructions from the host system 11.

[0053] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which each cell can store one bit), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which each cell can store two bits), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which each cell can store three bits), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which each cell can store four bits), other flash memory modules, or other memory modules with similar characteristics.

[0054] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell." As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining the one or more bits stored in this memory cell.

[0055] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical erasing cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If a memory cell can store more than two bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0056] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit may be a physical page or a physical sector. If a physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area includes 32 physical sectors, and the size of each physical sector is 512 bytes (bytes). However, in other exemplary embodiments, the data bit area may include 8, 16, or a larger or smaller number of physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erase. That is, each physical erase unit contains the minimum number of storage cells to be erased together. For example, a physical erase unit is a physical block.

[0057] Figure 5 FIG. 1 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0058] Please refer to Figure 5The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0059] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 includes a microprocessor unit (not shown) and a read-only memory (ROM) (not shown), and these control instructions are burned into the ROM. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0060] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in the form of program code in a specific area of the rewritable non-volatile memory module 43 (e.g., a system area of the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (RAM) (not shown). Specifically, the ROM includes a boot code. When the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the RAM of the memory management circuit 51. The microprocessor unit then executes these control instructions to perform operations such as writing, reading, and erasing data.

[0061] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 43 to write data to the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0062] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0063] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and corresponding command sequences for instructing various memory operations (e.g., changing a read voltage level or performing a garbage collection operation). These command sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0064] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0065] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure data accuracy. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates an error correcting code (ECC) and / or an error detecting code (EDC) corresponding to the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it also reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0066] The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10 .

[0067] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0068] Figure 6 FIG. 1 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0069] Please refer to Figure 6 The memory management circuit 51 may logically group the physical erase units 610(0)-610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602. Each physical erase unit may include a plurality of physical programming units.

[0070] The physical erase units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1 User data of the host system 11). For example, the physical erase units 610(0) to 610(A) in the storage area 601 can store valid data and / or invalid data. The physical erase units 610(A+1) to 610(B) in the idle area 602 do not store data (for example, valid data). For example, if a physical erase unit does not store valid data, the physical erase unit can be associated (or added) to the idle area 602. In addition, the physical erase units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical erase units can be extracted from the idle area 602 to store the new data. In one exemplary embodiment, the idle area 602 is also referred to as a free pool.

[0071] The memory management circuit 51 can configure the logical units 612(0)-612(C) to map the physical erase units 610(0)-610(A) in the storage area 601. In one exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple consecutive or non-consecutive logical addresses.

[0072] It should be noted that a logical unit can be mapped to one or more physical erase units. If a physical erase unit is currently mapped by a logical unit, it means that the data currently stored in this physical erase unit includes valid data. Conversely, if a physical erase unit is not currently mapped by any logical unit, it means that the data currently stored in this physical erase unit is invalid data.

[0073] The memory management circuit 51 may record management data describing the mapping relationship between logical units and physical erase units (also known as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wishes to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 based on the information in the logical-to-physical mapping table.

[0074] In one exemplary embodiment, at least some of the physical erase units in the rewritable non-volatile memory module 43 support partial erase. Specifically, for a physical erase unit supporting partial erase, multiple physical areas in the physical erase unit are used sequentially based on a predetermined order.

[0075] Figure 7 FIG. 1 is a schematic diagram illustrating multiple physical areas in a physical erase unit and their usage order according to an exemplary embodiment of the present invention.

[0076] Please refer to Figure 7 , assuming Figure 6 The physical erase unit 610(0)~610(B) includes a physical erase unit 710, and the physical erase unit 710 supports partial erase. The physical erase unit 710 includes physical areas 71~73. The physical areas 71~73 respectively include multiple physical programming units in the physical erase unit 710. That is, the multiple physical programming units in the physical erase unit 710 can be logically grouped into physical areas 71~73. In particular, the physical areas 71~73 are used sequentially based on a preset order. For example, the physical areas 71~73 are used in accordance with or can only be used in Figure 7 The arrow directions in FIG. 1 are used sequentially to erase and program the physical areas 71 to 73 based on a preset order.

[0077] It should be noted that in the following exemplary embodiments, a physical erase unit includes three physical regions as an example, but the present invention is not limited thereto. In other exemplary embodiments, a physical erase unit may also include two, four, or other numbers of physical regions, and the present invention is not limited thereto.

[0078] Figures 8A to 8C FIG. 1 is a schematic diagram illustrating an operation mechanism of partial erase according to an exemplary embodiment of the present invention.

[0079] Please refer to Figure 8A Before the partial erasure of the physical erasure unit 710 is started, the physical areas 71 to 73 in the physical erasure unit 710 respectively store data 801 to 803. The data 801 to 803 are all invalid data.

[0080] After initiating a partial erase operation on the physical erase unit 710, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to perform a partial erase operation on the physical area 71. This partial erase operation may be used to erase (e.g., clear) the data 801 in the physical area 71. After performing the partial erase operation on the physical area 71 to erase the data 801, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to subsequently perform a program operation on the physical area 71. This program operation may be used to store data 811 in the physical area 71. The data 811 is valid data. It should be noted that after performing the partial erase and program operations on the physical area 71 to write the data 811, the physical areas 72 and 73 still store the data 802 and 803 to be erased.

[0081] Please refer to Figure 8B , continued by Figure 8A After performing a partial erase and programming operation on the physical area 71 to store data 811, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to perform a partial erase operation on the physical area 72. This partial erase operation may be used to erase (e.g., clear) the data 802 in the physical area 72. After performing the partial erase operation on the physical area 72 to erase the data 802, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to subsequently perform a programming operation on the physical area 72. This programming operation may be used to store data 812 in the physical area 72. The data 812 is valid data. It should be noted that after performing the partial erase and programming operation on the physical area 72 to write the data 812, the physical area 73 still stores the data 803 to be erased.

[0082] Please refer to Figure 8C , continued by Figure 8BAfter performing a partial erase and programming operation on the physical area 72 to store data 812, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to perform a partial erase operation on the physical area 73. This partial erase operation may be used to erase (e.g., clear) the data 803 in the physical area 73. After performing a partial erase operation on the physical area 73 to erase the data 803, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to continue to perform a programming operation on the physical area 73. This programming operation may be used to store data 813 in the physical area 73. Data 813 is valid data. At this point, the old data 801-803 (i.e., invalid data) originally stored in the physical erase unit 710 has been sequentially erased based on a predetermined order and replaced by the new data 811-813, respectively.

[0083] It should be noted that according to Figures 8A to 8C In an exemplary embodiment, during the period of performing partial erasure on the physical erasure unit 710, when a certain physical area in the physical erasure unit 710 is in the erase state, the remaining physical areas in the physical erasure unit 710 cannot be in the erase state at the same time. Figure 8A For example, when physical region 71 is in the erase state (i.e., a partial erase operation is being performed on physical region 71), the remaining physical regions 72 and 73 in physical erase unit 710 cannot be in the erase state at the same time, and so on. Similarly, physical regions 71-73 can be erased sequentially.

[0084] In one exemplary embodiment, during a partial erase operation on the physical erase unit 710, only a single physical region in the physical erase unit 710 can be erased (i.e., in an erased state) at a single point in time. Alternatively, from another perspective, during a partial erase operation on the physical erase unit 710, no more than two physical regions in the physical erase unit 710 can be in an erased state simultaneously.

[0085] In one exemplary embodiment, while performing a partial erase on the physical erase unit 710, the memory management circuit 51 suspends or delays the partial erase operations on the physical regions 72 and 73 before completing the partial erase and programming operations on the physical region 71. After completing the partial erase and programming operations on the physical region 71, the memory management circuit 51 allows the partial erase and programming operations to continue on the physical region 72. Similarly, the physical regions 71-73 can be used sequentially.

[0086] exist Figure 8AIn an exemplary embodiment, in response to a partial erase operation and / or a program operation on the physical area 71, the memory management circuit 51 may update status information related to the physical area 71. This status information may reflect the current or most recent usage status of the physical area 71. For example, this status information may be stored in the physical area 71 or in a specific management table for query by the memory management circuit 51.

[0087] exist Figure 8B In an exemplary embodiment, in response to a partial erase operation and / or a program operation on the physical area 72, the memory management circuit 51 may update status information related to the physical area 72. This status information may reflect the current or most recent usage status of the physical area 72. For example, this status information may be stored in the physical area 72 or in a specific management table for query by the memory management circuit 51.

[0088] exist Figure 8C In an exemplary embodiment, in response to a partial erase operation and / or a program operation on the physical area 73, the memory management circuit 51 may update status information related to the physical area 73. This status information may reflect the current or most recent usage status of the physical area 73. For example, this status information may be stored in the physical area 73 or in a specific management table for query by the memory management circuit 51.

[0089] Figure 9 FIG. 2 is a schematic diagram showing how to store state information in various physical areas according to an exemplary embodiment of the present invention.

[0090] Please refer to Figure 9 , assuming Figure 6 The physical erase units 610(0)-610(B) include a physical erase unit 910, and the physical erase unit 910 supports partial erase. Figure 7 The physical erasing unit 710 includes physical areas 91-93.

[0091] The status tag 901 may be stored or configured in a physical programming unit in the physical area 91. For example, the status tag 901 may be stored or configured in the last physical programming unit or in a spare area of the remaining physical programming units in the physical area 91. In particular, the status tag 901 may be used to store status information related to the physical area 91. For example, in response to a partial erase operation and / or a programming operation on the physical area 91, the memory management circuit 51 may update the status tag 901 to reflect the latest usage status of the physical area 91.

[0092] The status tag 902 may be stored or configured in a physical programming unit in the physical area 92. For example, the status tag 902 may be stored or configured in the last physical programming unit or in an unused area of the remaining physical programming units in the physical area 92. In particular, the status tag 902 may be used to store status information related to the physical area 92. For example, in response to a partial erase operation and / or a program operation on the physical area 92, the memory management circuit 51 may update the status tag 902 to reflect the latest usage status of the physical area 92.

[0093] The status tag 903 may be stored or configured in a physical programming unit in the physical area 93. For example, the status tag 903 may be stored or configured in the last physical programming unit or in an unused area of the remaining physical programming units in the physical area 93. In particular, the status tag 903 may be used to store status information related to the physical area 93. For example, in response to a partial erase operation and / or a programming operation on the physical area 93, the memory management circuit 51 may update the status tag 903 to reflect the latest usage status of the physical area 93.

[0094] 10A to 10D FIG. 1 is a schematic diagram illustrating updating state information in response to a partial erase and / or program operation according to an exemplary embodiment of the present invention.

[0095] Please refer to Figure 10A Before the partial erasure of the physical erasure unit 910 is started, the physical areas 91 to 93 in the physical erasure unit 910 respectively store data 1001 to 1003. The data 1001 to 1003 are all invalid data.

[0096] After partial erasure of the physical erase unit 910 is initiated, partial erasure operations and program operations can be continuously performed on the physical area 91 to erase old data 1001 in the physical area 91 and store new data 1011 in the physical area 91. The data 1011 is valid data.

[0097] In response to a partial erase operation and / or a program operation on the physical area 91, the memory management circuit 51 may update the status tag 901 associated with the physical area 91. For example, the memory management circuit 51 may update the status bit in the status tag 901 from bit “0” to bit “1” to reflect that the new data 1011 has been written to the physical area 91. However, in Figure 10A In the exemplary embodiment, the status tags 902 and 903 are still bits “0” and are not updated.

[0098] Please refer to Figure 10B , continued by Figure 10AAfter performing a programming operation on the physical area 91 to store data 1011, a partial erase operation and a programming operation can be continuously performed on the physical area 92 to erase the old data 1002 in the physical area 92 and store new data 1012 in the physical area 92. The data 1012 is valid data.

[0099] In response to a partial erase operation and / or a program operation on the physical area 92, the memory management circuit 51 may update the status tag 902 associated with the physical area 92. For example, the memory management circuit 51 may update the status bit in the status tag 902 from bit "0" to bit "1" to reflect that the new data 1012 has been written to the physical area 92. Figure 10B In the exemplary embodiment of , the status tag 903 is still bit “0” and has not been updated.

[0100] Please refer to Figure 10C , continued by Figure 10B After performing a programming operation on the physical area 92 to store data 1012, a partial erase operation and a programming operation can be continuously performed on the physical area 93 to erase the old data 1003 in the physical area 93 and store new data 1013 in the physical area 93. The data 1013 is valid data.

[0101] In response to a partial erase operation and / or a program operation on the physical region 93, the memory management circuitry 51 may update the status tag 903 associated with the physical region 93. For example, the memory management circuitry 51 may update the status bit in the status tag 903 from bit "0" to bit "1" to reflect that the new data 1013 has been written to the physical region 93. At this point, the status bits in the status tags 901-903 have all been updated to bit "1" to reflect that erasure of the entire physical erase unit 910 has been completed and / or that the physical regions 91-93 all store the same type of data (e.g., valid data).

[0102] Please refer to Figure 10D , continued by Figure 10C Assume that after a period of time, the data 1011 - 1013 previously stored in the physical erasing unit 910 becomes invalid data. Therefore, the memory management circuit 51 may restart the partial erasing of the physical erasing unit 910 .

[0103] After partial erasure of the physical erase unit 910 is initiated, partial erasure operations and program operations can be continuously performed on the physical area 91 to erase old data 1011 in the physical area 91 and store new data 1021 in the physical area 91. The data 1021 is valid data.

[0104] In response to a partial erase operation and / or a program operation on the physical area 91, the memory management circuit 51 may update the status tag 901 associated with the physical area 91. For example, the memory management circuit 51 may update the status bit in the status tag 901 from bit "1" to bit "0" to reflect that the new data 1021 has been written to the physical area 91. However, in Figure 10D In the exemplary embodiment, status tags 902 and 903 remain at bits "1" and have not been updated. Similarly, in response to a partial erase operation and / or program operation acting on a particular physical region, the status information associated with that physical region may be updated to reflect the latest usage status of that physical region. The relevant operational details have been described above and will not be repeated here.

[0105] In an exemplary embodiment, the memory management circuit 51 can obtain the current usage status of one or more physical areas according to the status information. Figure 10A For example, the memory management circuit 51 can obtain the current usage status of the physical areas 91-93 based on the status tags 901-903. For example, before updating the status tag 901, the status tags 901-903 are bits "0," "0," and "0," respectively. Therefore, based on the status tags 901-903 (i.e., bits "0," "0," and "0"), the memory management circuit 51 can determine that the data currently stored in the physical areas 91-93 are of the same data type. For example, the memory management circuit 51 can determine that the physical areas 91-93 all currently store valid data (or invalid data).

[0106] However, after the status tag 901 is updated, the status tags 901-903 are bits "1," "0," and "0," respectively. Therefore, based on the updated status tags 901-903 (i.e., bits "1," "0," and "0"), the memory management circuit 51 can determine that the data type of the data currently stored in the physical area 91 is different from the data type of the data currently stored in the physical areas 92 and 93. For example, the memory management circuit 51 can determine that the data currently stored in the physical area 91 is newly written valid data, while the data stored in the physical areas 92 and 93 is invalid data.

[0107] And so on, in Figure 10BIn the exemplary embodiment, after status tag 902 is updated, status tags 901-903 are bits "1," "1," and "0," respectively. Therefore, based on updated status tags 901-903, memory management circuit 51 can determine that the data type of the data currently stored in physical regions 91 and 92 is different from the data type of the data currently stored in physical region 93. For example, memory management circuit 51 can determine that the data currently stored in physical regions 91 and 92 is newly written valid data, while the data currently stored in physical region 93 is invalid data.

[0108] In one exemplary embodiment, assume that the memory storage device 10 experiences an unexpected power outage during a partial erase operation on a specific physical erase unit (also referred to as a first physical erase unit). After power is restored, the memory management circuit 51 can obtain the usage status of each physical area in the first physical erase unit based on the recorded status information related to each physical area.

[0109] In one exemplary embodiment, the usage status may reflect the distribution of valid data and / or invalid data waiting to be erased in the first physical erase unit. In one exemplary embodiment, the usage status may reflect the distribution of new data and / or old data in the first physical erase unit. The new data may include valid data, and the old data may include invalid data. In one exemplary embodiment, the first status information may also reflect at least one of an erase progress and a programming progress of the first physical erase unit.

[0110] by Figure 10A For example, assume that a power outage occurs after the status tag 901 is updated. After power is restored, the memory management circuit 51 can obtain the current usage status of the physical areas 91 to 93 based on the status tags 901 to 903, which is that the physical area 91 stores valid data (i.e., new data), while the remaining physical areas 92 and 93 still store invalid data (i.e., old data). Alternatively, from another perspective, the memory management circuit 51 can obtain the erase progress (and / or programming progress) of the first physical erase unit before the power outage based on the status tags 901 to 903, which is that the partial erase operation and programming operation on the physical area 91 have been completed (and the physical areas 92 and 93 have not yet been erased). Therefore, after power is restored, the memory management circuit 51 can perform partial erase operations and programming operations starting from the physical area 92 according to the usage status of each physical area in the first physical erase unit, so as to gradually complete the erasure of the entire physical erase unit 910 and the writing of new data. The relevant operation details have been described in detail above and will not be repeated here. Compared to the need to re-erase and reprogram the entire physical erase unit after an unexpected power outage, the exemplary embodiments of the present invention can effectively improve the management efficiency of the partial erase mechanism.

[0111] In one exemplary embodiment, an unexpected power outage of the memory storage device 10 may cause part of the management table to be lost or damaged. Therefore, after the memory storage device 10 is powered on again, the memory management circuit 51 may reconstruct the mapping table based on the recorded status information related to each physical area. The mapping table may record the logic-to-physical mapping information related to the second data. For example, the memory management circuit 51 may obtain the usage status of each physical area in the first physical erase unit based on the recorded status information related to each physical area. Then, the memory management circuit 51 may reconstruct the mapping table based on the usage status. For example, the memory management circuit 51 may reconstruct the mapping table based on the distribution status of valid data and invalid data (or new data and old data) in the first physical erase unit.

[0112] In an exemplary embodiment, the mapping table may include a logical-to-physical mapping table. The logical-to-physical mapping table may record logical-to-physical mapping information related to at least a portion of valid data (including the second data) in the first physical erase unit. For example, the logical-to-physical mapping information may reflect a mapping relationship between a logical unit to which at least a portion of valid data (including the second data) in the first physical erase unit belongs and a physical unit (e.g., a physical programming unit or a physical erase unit).

[0113] by Figure 10A For example, assume that the memory management circuit 51 loses power after updating the status tag 901. After power is restored, the memory management circuit 51 can rebuild the mapping table based on the mapping information associated with the valid data 1011 (i.e., the second data) stored in the physical area 91. This mapping information can be stored in the physical area 91, in another management table, or in another storage location. For example, based on the mapping information, the memory management circuit 51 can re-add the logical-to-physical mapping information that reflects the mapping relationship between the logical unit to which the valid data 1011 (i.e., the second data) belongs and the physical unit to the mapping table.

[0114] It should be noted that in the aforementioned exemplary embodiments, the status information (eg Figure 9 and 10A to 10D The status tags in are only examples and are not intended to limit the present invention. Figure 10DIn another exemplary embodiment, in response to a partial erase operation and / or a programming operation acting on the physical area 91, the memory management circuit 51 may update the status bit in the status tag 901 from bit "1" to bit "2" or another bit value to indicate the latest usage status of the physical area 91. Alternatively, in an exemplary embodiment, the status tag may also include status bits presented in other forms, which are not limited by the present invention. Alternatively, in an exemplary embodiment, the status information related to each physical area may also be recorded in system information (e.g., a customized management table). Thereafter, the memory management circuit 51 may obtain the latest usage status of each physical area in a physical erase unit based on this system information. The relevant operation details have been described above and will not be repeated here.

[0115] Figure 11 FIG. 4 is a flow chart of a partial erase management method according to an exemplary embodiment of the present invention.

[0116] Please refer to Figure 11 In step S1101, a first partial erase operation is performed on a first physical region of the plurality of physical regions to erase first data in the first physical region. In step S1102, a first partial write operation is performed on the first physical region to store second data in the first physical region. In step S1103, first state information associated with the first physical region is updated in response to at least one of the first partial erase operation and the first partial write operation.

[0117] However, Figure 11 The steps have been described in detail above and will not be repeated here. Figure 11 Each step can be implemented as multiple program codes or circuits, which is not limited in this case. Figure 11 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and this case is not limited thereto.

[0118] In summary, exemplary embodiments of the present invention can update the corresponding status information based on the latest usage status of each physical area within the same physical erase unit. This status information can then be used to determine which physical area within the physical erase unit to use next (e.g., which physical area within the physical erase unit to perform a partial erase on). In particular, if an unexpected power outage occurs during a partial erase of a specific physical erase unit, this status information can be used to quickly restore the physical erase unit to its pre-power-off state after power is restored, effectively improving the management efficiency of the partial erase mechanism.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A partial erase management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erase units, wherein the plurality of physical erase units includes a first physical erase unit, and the partial erase management method comprises: performing a first partial erase operation on a first physical area among a plurality of physical areas in the first physical erase unit to erase first data in the first physical area, wherein the plurality of physical areas are used sequentially based on a predetermined order; After performing the first partial erase operation on the first physical region, performing a first programming operation on the first physical region to store second data in the first physical region; as well as In response to at least one of the first partial erase operation and the first programming operation, status information related to the first physical erase unit is updated, wherein the status information reflects an execution status of at least a partial erase operation associated with all the physical regions in the first physical erase unit, and the at least a partial erase operation includes the first partial erase operation. 2 . The partial erase management method according to claim 1 , wherein when the first physical region is in an erase state, the remaining physical regions of the plurality of physical regions are not in the erase state. 3 . The partial erase management method according to claim 1 , wherein after the first programming operation is performed on the first physical area, the second physical area among the plurality of physical areas still stores third data to be erased.

4. The partial erase management method according to claim 1 , further comprising: After performing the first programming operation on the first physical region, performing a second partial erase operation on a second physical region of the plurality of physical regions to erase third data in the second physical region, The second physical region is different from the first physical region.

5. The partial erase management method according to claim 4, further comprising: After performing the second partial erase operation on the second physical region, performing a second programming operation on the second physical region to store fourth data in the second physical region; as well as In response to at least one of the second partial erase operation and the second programming operation, updating second state information related to the second physical region, The updated second status information is the same as the updated first status information. 6 . The partial erase management method according to claim 1 , wherein sequentially using the plurality of physical regions based on the preset order comprises sequentially erasing and programming the plurality of physical regions based on the preset order.

7. The partial erase management method according to claim 1 , further comprising: The usage status of the first physical area is obtained according to the status information.

8. The partial erase management method according to claim 1 , further comprising: A mapping table is rebuilt according to the state information, wherein the mapping table records logic-to-physical mapping information related to the second data.

9. The partial erase management method according to claim 1 , further comprising: Obtaining, according to the state information, a distribution state of new data and old data in the first physical erasure unit; as well as A second partial erase operation is performed on the old data. 10 . The partial erase management method according to claim 1 , wherein the status information reflects at least one of an erase progress and a programming progress of the first physical erase unit.

11. A memory storage device comprising: A connection interface unit for connecting to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, the plurality of physical erasing units comprising a first physical erasing unit; and a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module; The memory control circuit unit is used to: instructing to perform a first partial erase operation on a first physical area among a plurality of physical areas in the first physical erase unit to erase first data in the first physical area, wherein the plurality of physical areas are used sequentially based on a preset order; After performing the first partial erase operation on the first physical area, instructing to perform a first programming operation on the first physical area to store second data in the first physical area; as well as In response to at least one of the first partial erase operation and the first programming operation, status information related to the first physical erase unit is updated, wherein the status information reflects an execution status of at least a partial erase operation associated with all the physical regions in the first physical erase unit, and the at least a partial erase operation includes the first partial erase operation. 12 . The memory storage device of claim 11 , wherein when the first physical region is in an erased state, the remaining physical regions of the plurality of physical regions are not in the erased state. 13 . The memory storage device of claim 11 , wherein after the first programming operation is performed on the first physical region, a second physical region among the plurality of physical regions still stores third data to be erased.

14. The memory storage device according to claim 11, wherein the memory control circuit unit is further configured to: After performing the first programming operation on the first physical region, instructing to perform a second partial erase operation on a second physical region of the plurality of physical regions to erase third data in the second physical region, The second physical region is different from the first physical region.

15. The memory storage device according to claim 14, wherein the memory control circuit unit is further configured to: After performing the second partial erase operation on the second physical region, instructing to perform a second programming operation on the second physical region to store fourth data in the second physical region; and In response to at least one of the second partial erase operation and the second programming operation, updating second state information related to the second physical region, The updated second status information is the same as the updated first status information. 16 . The memory storage device of claim 11 , wherein sequentially using the plurality of physical regions based on the preset order comprises sequentially erasing and programming the plurality of physical regions based on the preset order.

17. The memory storage device according to claim 11, wherein the memory control circuit unit is further configured to: The usage status of the first physical area is obtained according to the status information.

18. The memory storage device according to claim 11, wherein the memory control circuit unit is further configured to: A mapping table is rebuilt according to the state information, wherein the mapping table records logic-to-physical mapping information related to the second data.

19. The memory storage device according to claim 11, wherein the memory control circuit unit is further configured to: Obtaining a distribution state of new data and old data in the first physical erasure unit according to the state information; and A second partial erase operation is performed on the old data. 20 . The memory storage device of claim 11 , wherein the status information reflects at least one of an erase progress and a programming progress of the first physical erase unit.

21. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, the plurality of physical erasing units including a first physical erasing unit, the memory control circuit unit comprising: A host interface for connecting to a host system; A memory interface, configured to connect to the rewritable non-volatile memory module; as well as A memory management circuit connected to the host interface and the memory interface, The memory management circuit is used to: instructing to perform a first partial erase operation on a first physical area among a plurality of physical areas in the first physical erase unit to erase first data in the first physical area, wherein the plurality of physical areas are used sequentially based on a preset order; After performing the first partial erase operation on the first physical area, instructing to perform a first programming operation on the first physical area to store second data in the first physical area; as well as In response to at least one of the first partial erase operation and the first programming operation, status information related to the first physical erase unit is updated, wherein the status information reflects an execution status of at least a partial erase operation associated with all the physical regions in the first physical erase unit, and the at least a partial erase operation includes the first partial erase operation. 22 . The memory control circuit unit according to claim 21 , wherein when the first physical region is in an erased state, the remaining physical regions of the plurality of physical regions are not in the erased state. 23 . The memory control circuit unit according to claim 21 , wherein after the first programming operation is performed on the first physical region, a second physical region among the plurality of physical regions still stores third data to be erased.

24. The memory control circuit unit according to claim 21, wherein the memory management circuit is further configured to: After performing the first programming operation on the first physical region, instructing to perform a second partial erase operation on a second physical region of the plurality of physical regions to erase third data in the second physical region, The second physical region is different from the first physical region.

25. The memory control circuit unit according to claim 24, wherein the memory management circuit is further configured to: After performing the second partial erase operation on the second physical region, instructing to perform a second programming operation on the second physical region to store fourth data in the second physical region; and In response to at least one of the second partial erase operation and the second programming operation, updating second state information related to the second physical region, The updated second status information is the same as the updated first status information. 26 . The memory control circuit unit according to claim 21 , wherein sequentially using the plurality of physical regions based on the preset order comprises sequentially erasing and programming the plurality of physical regions based on the preset order.

27. The memory control circuit unit according to claim 21, wherein the memory management circuit is further configured to: The usage status of the first physical area is obtained according to the status information.

28. The memory control circuit unit according to claim 21, wherein the memory management circuit is further configured to: A mapping table is rebuilt according to the state information, wherein the mapping table records logic-to-physical mapping information related to the second data.

29. The memory control circuit unit according to claim 21, wherein the memory management circuit is further configured to: Obtaining a distribution state of new data and old data in the first physical erasure unit according to the state information; and A second partial erase operation is performed on the old data. 30 . The memory control circuit unit according to claim 21 , wherein the status information reflects at least one of an erase progress and a programming progress of the first physical erase unit.

Images