A BMC chip management method and device, computer equipment and storage medium

Abstract

The application belongs to the field of BMC and relates to a BMC chip management method and device, computer equipment and a storage medium. The method comprises the following steps: a GPIO register for detecting an interrupt is arranged in a BMC chip; the GPIO register for detecting the interrupt is configured, so that the falling edge of the signal of an input GPIO generates an interrupt; a program running in a CPU enters a system, a driver of a Super I / O device related to GPIO interrupt processing is automatically loaded in the system, and an lpc_gic_int interrupt processing program is registered; an application program is started, the pin of the GPIO input pin generates a falling edge change, and the BMC chip generates a GPIO interrupt; the Super I / O device transmits the GPIO interrupt information to the CPU through an LPC, and the lpc_gic_int interrupt is generated in the CPU; an interrupt response program registered in the system is entered, the GPIO generating the interrupt signal is identified, and counting processing is performed; the interrupt counting value in the driver is acquired and the interrupt counting value is displayed through the running GPIO interrupt processing application program. The system function based on the BMC chip is expanded, and the BMC chip resources are fully utilized.

Description

Technical Field

[0001] This application relates to the field of BMC technology, and in particular to BMC chip management methods, apparatus, computer equipment and storage media. Background Technology

[0002] The BMC (Baseboard Management Controller) can perform firmware upgrades, view machine devices, perform local and remote diagnostics, provide console support, manage configurations, manage hardware, and troubleshoot problems even when the machine is not powered on.

[0003] In the existing technology, the system expansion based on BMC chip is limited and the system function is simple, which is not conducive to the full utilization of BMC chip resources. Summary of the Invention

[0004] The purpose of this application is to provide a BMC chip management method, apparatus, computer device, and storage medium to solve the problems in the prior art where BMC chip-based systems have limited expansion capabilities, simple system functions, and are not conducive to the full utilization of BMC chip resources.

[0005] To address the aforementioned technical problems, this application provides a BMC chip management method, which employs the following technical solution and includes the following steps:

[0006] The BMC chip has a GPIO register for interrupt detection. Configuring the GPIO register for interrupt detection will cause an interrupt to be generated on the falling edge of the input GPIO signal.

[0007] This allows the program running on the CPU to enter the system, automatically loads the SuperI / O device driver related to GPIO interrupt handling in the system, and registers the lpc_gic_int interrupt handler.

[0008] When the application starts, a falling edge changes on the GPIO input pin, and the BMC chip generates a GPIO interrupt.

[0009] Super I / O devices transmit GPIO interrupt information to the CPU via LPC, generating an lpc_gic_int interrupt in the CPU;

[0010] The interrupt response routine registered by the driver in the system is entered, the GPIO that generated the interrupt signal is identified, and counting is performed.

[0011] The interrupt count value in the driver is obtained and displayed by running the GPIO interrupt handling application.

[0012] Preferably, the step of configuring the registers of the BMC management chip so that an interrupt is generated on the falling edge of the input GPIO signal further includes:

[0013] Configure the UART1 and UART2 registers of the BMC chip to enable bidirectional connection between UART1 and UART PORT1, and bidirectional connection between UART2 and UART PORT2.

[0014] Preferably, the steps of enabling the program running on the CPU to enter the system, automatically loading the driver for the Super I / O device related to GPIO interrupt handling in the system, and registering the lpc_gic_int interrupt handler specifically include:

[0015] In the BMC chip firmware, register functions to generate interrupts on the falling edge of multiple GPIOs.

[0016] Preferably, the step of the interrupt response program registered in the system driver to identify the GPIO that generated the interrupt signal and perform counting processing specifically includes:

[0017] The function that generates an interrupt on the falling edge of multiple GPIOs identifies the pin that is currently generating the interrupt by obtaining the register value transmitted from the LPC channel and incrementing the variable that records the interrupt count for that pin.

[0018] Preferably, the step of obtaining and displaying the interrupt count value from the driver through the running GPIO interrupt handling application specifically includes:

[0019] Get the value of the variable that records the interrupt count for each pin in the driver. If the current value has changed compared to the original value, it is determined that an interrupt has occurred on a pin, and the current value, i.e., the interrupt count value in the driver, is displayed.

[0020] Preferably, in the BMC chip management method, the BMC chip reads the first GPIO level state used for detecting the slot and performs slot identification;

[0021] The BMC chip reads the second GPIO level state used to detect the chassis number and performs chassis number identification.

[0022] Preferably, the BMC chip implements two IPMB interfaces through two I2C channels for communication with other electronic devices. One IPMB interface serves as the primary IPMB communication path, and the other serves as a backup IPMB communication path. The two IPMB interfaces in the same slot are set to different addresses. IPMB commands are sent to the BMC chip through a control terminal or other electronic devices to control the power on / off of other electronic devices or to check whether other electronic devices are online.

[0023] To address the aforementioned technical problems, this application also provides a BMC chip management device, which employs the following technical solution, including:

[0024] The configuration module is used to configure the GPIO register for interrupt detection in the BMC chip, so that an interrupt is generated on the falling edge of the input GPIO signal;

[0025] The registration module is used to enable programs running on the CPU to enter the system, automatically load the drivers of Super I / O devices related to GPIO interrupt handling in the system, and register the lpc_gic_int interrupt handler.

[0026] The startup module is used to start the application. When the pin of the GPIO input changes with a falling edge, the BMC chip generates a GPIO interrupt.

[0027] The interrupt module is used by Super I / O devices to transmit GPIO interrupt information to the CPU via LPC, and generate an lpc_gic_int interrupt in the CPU.

[0028] The identification module is used to enter the interrupt response program registered by the driver in the system, identify the GPIO that generated the interrupt signal, and perform counting processing.

[0029] The display module is used to obtain and display the interrupt count value from the driver through the running GPIO interrupt handling application.

[0030] To address the aforementioned technical problems, this application also provides a computer device that employs the technical solution described below, including a memory and a processor. The memory stores computer-readable instructions, and the processor executes the computer-readable instructions to implement the steps of the aforementioned BMC chip management method.

[0031] To address the aforementioned technical problems, this application also provides a computer-readable storage medium, which employs the technical solution described below:

[0032] The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, implement the steps of the BMC chip management method described above.

[0033] Compared with the prior art, this application has the following main advantages: by using Super The I / O expansion includes GPIO to monitor server operating status and handle alarms in case of abnormalities; it monitors platform fan operation and controls fan operation based on detected temperature; it controls LED indicators to show server operating status; it utilizes IPMI network and serial communication functions to receive IPMI interactive control statements from users through various communication channels to query server status or control functions such as power on / off; users can develop other applications to interact with the BMC via IPMI or other communication protocols to control the server or understand its operating status; it features fault reporting, power-on self-test, and operating status self-test functions; it has a software interface to output information such as current and voltage, main chip temperature, operating system and version, and firmware version to user software; the BMC chip has two access network ports, one RGMII and one NCSI interface; it has slot number, chassis number, and rack number identification functions; it has two IPMB interfaces to receive management and query data from the exchange via IPMB; it can obtain system status information through the BMC chip maintenance serial port and perform corresponding maintenance; the system functions based on the BMC chip are extensive, making full use of BMC chip resources. Attached Figure Description

[0034] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is an exemplary system architecture diagram to which this application can be applied;

[0036] Figure 2 This is a flowchart of one embodiment of the BMC chip management method of this application;

[0037] Figure 3 This is a block diagram illustrating the principle of the BMC chip extended serial port in the BMC chip management method of this application.

[0038] Figure 4 This is a flowchart of the rack and chassis identification method in the BMC chip management method of this application;

[0039] Figure 5 This is a flowchart of the slot identification method in the BMC chip management method of this application;

[0040] Figure 6 This is a flowchart of the extended serial port method in the BMC chip management method of this application;

[0041] Figure 7 This is a flowchart of another embodiment of the BMC chip management method of this application;

[0042] Figure 8 This is a schematic diagram of the structure of one embodiment of the BMC chip management device of this application;

[0043] Figure 9 This is a schematic diagram of the structure of one embodiment of the computer device of this application. Detailed Implementation

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0045] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0046] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0047] like Figure 1 As shown, the system architecture 100 may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 serves as a medium for providing communication links between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0048] Users can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, etc. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as web browser applications, shopping applications, search applications, instant messaging tools, email clients, social media platform software, etc.

[0049] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with displays and support web browsing, including but not limited to smartphones, tablets, e-book readers, MP3 players (Moving Picture Experts Group Audio Layer III), MP4 players (Moving Picture Experts Group Audio Layer IV), laptops, and desktop computers, etc.

[0050] Server 105 can be a server that provides various services, such as a backend server that supports the pages displayed on the first terminal device 101, the second terminal device 102, and the third terminal device 103.

[0051] It should be noted that the BMC chip management method provided in this application embodiment is generally executed by a server / terminal device, and correspondingly, the BMC chip management device is generally located in the server / terminal device.

[0052] It should be understood that Figure 1 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0053] Example 1

[0054] Continue to refer to Figure 2 The diagram illustrates a flowchart of an embodiment of the BMC chip management method of this application. The BMC chip management method includes the following steps:

[0055] Step S201: The BMC chip has a GPIO register for detecting interrupts. Configure the GPIO register for detecting interrupts so that an interrupt is generated on the falling edge of the input GPIO signal.

[0056] In this embodiment, the BMC chip management method runs on an electronic device (e.g., Figure 1The server / terminal device shown can receive BMC chip management requests via wired or wireless connection. It should be noted that the aforementioned wireless connection methods may include, but are not limited to, 3G / 4G / 5G connections, WiFi connections, Bluetooth connections, WiMAXX connections, Zigbee connections, UWB (ultra wideband) connections, and other currently known or future known wireless connection methods.

[0057] In this embodiment, the BMC chip can be the AST2400. The AST2400's interrupt control supports four GPIO interrupts, implemented using the GPIO interrupt detection function of the dedicated BMC chip AST2400 and the Super I / O device under the LPC path connecting the chip to the CPU. The BMC software program runs within the AST2400 BMC chip, primarily requiring configuration of the relevant registers for interrupt detection GPIOs and the ability to quickly transmit corresponding information to the microprocessor, such as the FT-1500A / 16, via the Super I / O device when a GPIO interrupt occurs.

[0058] In specific implementation, before step S201, the following may also be included:

[0059] Configure the UART1 and UART2 registers of the BMC chip to enable bidirectional connection between UART1 and UART PORT1, and bidirectional connection between UART2 and UART PORT2.

[0060] Configuring the UART1 and UART2 registers of the BMC chip is to expand the serial port of the BMC chip, making it easier for the BMC chip to interact with external electronic devices.

[0061] like Figure 3 The diagram shown is a schematic diagram of the BMC chip extended serial port in the BMC chip management method of this application. Figure 3 As shown, during the AST2400 startup initialization process, the main function is to configure the UART1 and UART2 registers, enabling bidirectional connection between UART1 and UART PORT1, and bidirectional connection between UART2 and UART PORT2. Furthermore, the pins associated with UART PORT1 are configured to be used as corresponding pins for UART PORT1, rather than as GPIO or other auxiliary functions, and the pins associated with UART PORT2 are configured to be used as corresponding pins for UART PORT2, rather than as GPIO or other auxiliary functions.

[0062] Step S202 allows the program running on the CPU to enter the system, automatically loads the driver for the Super I / O device related to GPIO interrupt handling in the system, and registers the lpc_gic_int interrupt handler.

[0063] In this embodiment, the driver program runs within the FT-1500A / 16 and is primarily used to drive relevant Super I / O devices to receive GPIO interrupt information transmitted from the BMC. After receiving GPIO interrupt information through the Super I / O devices, the T-1500A / 16 generates an lpc_gic_int interrupt. The driver program registers an lpc_gic_int interrupt response function, which quickly identifies which GPIO device generated the interrupt and performs interrupt counting or other user-required processing. This part of the program can be automatically loaded into the system during system startup.

[0064] In step S203, the application is started, the pin of the GPIO input changes with a falling edge, and the BMC chip generates a GPIO interrupt.

[0065] In this embodiment, the function is described as: void PDK_CountGpioInt_Thrd(int BMCInst). This function is used in the BMC firmware to register a function that generates an interrupt on the falling edge of four GPIOs.

[0066] In step S204, the Super I / O device transmits GPIO interrupt information to the CPU via LPC, generating an lpc_gic_int interrupt in the CPU.

[0067] Step S205: Enter the interrupt response program registered by the driver in the system, identify the GPIO that generated the interrupt signal, and perform counting processing.

[0068] Function description: static irqreturn_t lpc_handle_irq(int irq, void *dev_id), this function is part of the GPIO interrupt handling driver and runs in FT-1500A / 16. It is an interrupt handling function registered in the driver. This function identifies the pin that is currently generating an interrupt by obtaining the register value passed from the LPC channel.

[0069] Step S206: Obtain the interrupt count value from the driver and display the interrupt count value through the running GPIO interrupt handling application.

[0070] The application's main function is to obtain the interrupt count value from the driver and display it on the terminal. It can also clear the interrupt count value in the driver. During runtime, after the system automatically loads the driver, the user starts the application and connects the signals to the corresponding BMC's GPIO.

[0071] Function Description: `int main(int argc, char**argv)` is the main function of the application program in the system, running in the FT-1500A / 16. It uses the program statement `read(fd, iIntCount, sizeof(iIntCount))` to retrieve the value of the variable `iIntCount[n]` that records the interrupt count for each pin in the driver. If the current value differs from the previous value, it indicates that an interrupt has occurred on a pin, and the new value is printed to the display screen.

[0072] In some optional implementations of this embodiment, the electronic device may further perform the following steps:

[0073] The BMC chip reads the level status of the first GPIO used to detect the slot. For example, if six GPIO ports are designed to display the level status, the slot can be identified.

[0074] The BMC chip reads the level status of the second GPIO used to detect the chassis number. If another 6 GPIOs are designed to display the level status, the chassis number can be identified.

[0075] Figure 4 This is a flowchart of the rack / chassis identification method in the BMC chip management method of this application. Figure 4 As shown, a rack / chassis identification method in a BMC chip management method includes the following steps:

[0076] S401, Run the cabinet and chassis identification program;

[0077] S402: Read the level values ​​of the six GPIOs used to detect the rack and chassis number;

[0078] S403. Place the pin value for detecting the parity check bit in the 5th position, place the two pin values ​​for detecting the rack number in the 4th and 3rd positions, place the pin value for detecting the reserved bit in the 2nd position, and place the two pin values ​​for detecting the chassis number in the 1st and 0th positions, thus forming a value with 6 valid data bits.

[0079] S404. Determine whether the verification passes. If it passes, proceed to step S405; otherwise, proceed to step S402.

[0080] S405. Assuming the reserved bit is 1, each chassis position has 6 detection pins that should detect a numerical constant, forming a truth table; assuming the reserved bit is 0, each chassis position has another corresponding numerical constant, forming another truth table.

[0081] S406. Does the detected 6-bit data match a certain data in the aforementioned two truth tables? If yes, proceed to step S407; otherwise, proceed to step S402.

[0082] S407. By matching the truth data, we can know which rack or chassis the blade is located in.

[0083] S408, End.

[0084] This method can clearly identify server racks and chassis, improving the accuracy and speed of rack and chassis identification and laying the foundation for determining the status of server racks and chassis.

[0085] Figure 5 This is a flowchart of the slot identification method in the BMC chip management method of this application. Figure 5 As shown, a slot identification method in a BMC chip management method includes the following steps:

[0086] S501, Run the program to detect slot number;

[0087] S502: Read the level values ​​of the six GPIOs used to detect the slot number;

[0088] S503. Combine the detected level values ​​of the 6 pins into a value with 6 bits of valid data;

[0089] S504. Using the above detection method, each slot obtains a numerical constant with 6 valid data bits, which is listed to form a truth table.

[0090] S505. Does the detected 6-bit data match a certain data in the aforementioned truth table? If yes, proceed to step S506; otherwise, proceed to step S502.

[0091] S506. Determine the slot number corresponding to the true value based on the matched true value data;

[0092] S507, End.

[0093] This application uses a method that can clearly identify slots, improving the accuracy and speed of slot identification and laying the foundation for accurate determination of the chassis status.

[0094] Figure 6 This is a flowchart of the extended serial port method in the BMC chip management method of this application. Figure 6 As shown, a method for expanding a serial port, taking UART1 as an example, includes the following steps:

[0095] Load the driver;

[0096] Configure the SuperIO control registers related to the SUART1 device, enable SUART1, and set the serial interrupt level;

[0097] Call the system-provided function devm_kcalloc to allocate

[0098] struct ast2400_lpc_superio_suart_data{

[0099] struct uart_8250_port uart;

[0100] intline;

[0101] };

[0102] The type variable requires dynamic space, and the returned pointer is assigned to the pointer variable data for storage;

[0103] The serial port's operating parameters, such as port type, port access address, port input function interface, and output function interface, are set through the memory space pointed to by the data pointer.

[0104] The serial port is registered by calling the system's built-in function serial8250_register_8250_port;

[0105] Determine if registration was successful. If successful, proceed to the next step. If unsuccessful, report an error, release space, and end the process.

[0106] Determine if the driver was successfully uninstalled. If not, free up space and end the process. If yes, proceed to the next step.

[0107] Waiting for lpc_gic_int interrupt;

[0108] Enter the registered lpc_gic_int interrupt response function lpc_uart1_irq;

[0109] The interrupt flag is used to identify whether the interrupt was generated by SUART1. If not, the above steps are taken to determine whether the driver was successfully uninstalled. If so, the system's built-in uart_8250_port member function port.handle_irq is called for processing.

[0110] The process is complete.

[0111] The BMC chip and VPX can also be configured for connection. The VPX I / O interfaces include one RS232 port, one RS422 port, one management network port, four GPIO ports, two IPMB ports, a slot number identification PIN, and chassis and rack number identification PINs. Two standard IPMB (I2C) output interfaces can be isolated, supporting configurable communication rates of 100Kbps / 400Kbps. It supports the IPMI 2.0 standard protocol and iKVM functionality, allowing control of electronic devices' power on / off and status information via IPMI commands. UART3 registers can be configured to enable bidirectional connection between UART3 and UART4. This allows communication with the BMC's IPMI serial communication port UART4 using the IPMI serial communication protocol.

[0112] The two standard IPMB (I2C) interfaces are isolated and have a configurable communication rate of 100Kbps / 400Kbps. It supports the IPMI 2.0 standard protocol and iKVM function, and can control the XX power switch and report the module's position information via IPMI commands.

[0113] As can be seen, by using Super I / O to expand GPIO, the operating status of the server equipped with the BMC chip can be monitored. If the server malfunctions, alarms can be triggered, and the platform fan's operating status can be monitored and controlled based on the detected temperature. Additionally, LEDs can be configured and controlled to indicate the server's operating status. Using IPMI's network and serial communication functions, IPMI interactive control statements sent by users through various communication channels can be received to query the server's status or control functions such as power on / off. Users can develop other applications to communicate with the BMC via the IPMI protocol or... It interacts with other communication protocols to control the server or understand its working status; it has fault reporting, power-on self-test, and running status self-test functions; it has a software interface to output information such as current and voltage, main chip temperature, operating system and version, and firmware version to user software; it is designed with two access network ports for the BMC chip, one RGMII and one NCSI interface; it has slot number, chassis number, and rack number identification functions; it has two IPMB interfaces, which can receive and exchange management and query through IPMB; it can obtain system status information through the BMC chip maintenance serial port and perform corresponding maintenance; the system functions based on the BMC chip are extensive, making full use of the BMC chip resources.

[0114] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0115] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing related hardware with computer-readable instructions. These computer-readable instructions can be stored in a computer-readable storage medium. When executed, the program can include the processes of the embodiments of the above methods. The aforementioned storage medium can be a non-volatile storage medium such as a magnetic disk, optical disk, or read-only memory (ROM), or random access memory (RAM).

[0116] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0117] Example 2

[0118] Further reference Figure 7 This is a flowchart of another embodiment of the BMC chip management method of this application. Figure 7 As shown, a BMC chip management method includes the following steps:

[0119] The S701 and BMC programs run, configuring the relevant registers of the AST2400 so that an interrupt is generated on the falling edge of the input GPIO signal;

[0120] S702, the program running in CPUFT1500A / 16 enters the system, and the system automatically loads the driver registration lpc_gic_int interrupt handler for the Super I / O device related to GPIO interrupt handling.

[0121] S703, User starts application;

[0122] S704: A falling edge occurs on one of the four GPIO input pins.

[0123] S705 and AST2400 generate GPIO interrupts;

[0124] S706 and Super I / O devices transmit GPIO interrupt information to the CPU FT1500A / 16 via LPC;

[0125] S707, generates an lpc_gic_int interrupt in CPU FT1500A / 16;

[0126] S708: Enter the interrupt response routine registered by the driver in the system, identify which GPIO generated the interrupt signal, and perform counting and other processing.

[0127] S709: Obtain the interrupt count value in the driver through the running GPIO interrupt handling APP program and display it.

[0128] Implementing this embodiment, by using the BMC chip to handle system interrupts, can improve CPU efficiency, eliminating the need for the CPU to spend excessive time waiting for and querying peripheral devices. It features real-time processing capabilities, enabling rapid response and timely handling of various parameters and states in the real-time control system. It also has fault handling capabilities, promptly transferring necessary data and information to a backup power supply in the power-off interrupt service routine for protection, and restoring it when power is restored. Furthermore, it enables time-division multiplexing, allowing simultaneous operation of multiple peripherals. The interrupt system can also be used for program debugging, multi-machine connections, and more. Therefore, systems based on the BMC chip offer numerous functional extensions and fully utilize BMC chip resources.

[0129] Example 3

[0130] Further reference Figure 8 As a response to the above Figure 2 or Figure 7 The implementation of the method shown in this application provides an embodiment of a BMC chip management device, which is similar to... Figure 2 , Figure 7 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.

[0131] like Figure 8 As shown, the BMC chip management device 800 described in this embodiment includes: a configuration module 801, a registration module 802, a startup module 803, an interrupt module 804, an identification module 805, and a display module 806.

[0132] in:

[0133] The configuration module 801 is used to configure the GPIO register for interrupt detection in the BMC chip, so that an interrupt is generated on the falling edge of the input GPIO signal.

[0134] The registration module 802 is used to enable the program running on the CPU to enter the system, automatically load the Super I / O device driver related to GPIO interrupt handling in the system, and register the lpc_gic_int interrupt handler.

[0135] The startup module 803 is used to start the application. When the pin of the GPIO input changes with a falling edge, the BMC chip generates a GPIO interrupt.

[0136] The interrupt module 804 is used by the SuperI / O device to transmit GPIO interrupt information to the CPU via LPC, and generate an lpc_gic_int interrupt in the CPU.

[0137] The identification module 805 is used to enter the interrupt response program registered by the driver in the system, identify the GPIO that generated the interrupt signal, and perform counting processing.

[0138] Display module 806 is used to obtain and display the interrupt count value in the driver through the running GPIO interrupt handling application.

[0139] Implementing this embodiment, by using Super The I / O expansion includes GPIO to monitor server operating status and handle alarms in case of abnormalities; it monitors platform fan operation and controls fan operation based on detected temperature; it controls LED indicators to show server operating status; it utilizes IPMI network and serial communication functions to receive IPMI interactive control statements from users through various communication channels to query server status or control functions such as power on / off; users can develop other applications to interact with the BMC via IPMI or other communication protocols to control the server or understand its operating status; it features fault reporting, power-on self-test, and operating status self-test functions; it has a software interface to output information such as current and voltage, main chip temperature, operating system and version, and firmware version to user software; the BMC chip has two access network ports, one RGMII and one NCSI interface; it has slot number, chassis number, and rack number identification functions; it has two IPMB interfaces to receive management and query data from the exchange via IPMB; it can obtain system status information through the BMC chip maintenance serial port and perform corresponding maintenance; the system functions based on the BMC chip are extensive, making full use of BMC chip resources.

[0140] Example 4

[0141] To address the aforementioned technical problems, embodiments of this application also provide a computer device. Please refer to [link / reference needed] for details. Figure 9 , Figure 9 This is a basic structural block diagram of the computer device in this embodiment.

[0142] The computer device 9 includes a memory 91, a processor 92, and a network interface 93 that are interconnected via a system bus. It should be noted that only the computer device 9 with components 91, 92, and 93 is shown in the figure; however, it should be understood that it is not required to implement all the shown components, and more or fewer components can be implemented alternatively. Those skilled in the art will understand that the computer device described here is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0143] The computer device can be a desktop computer, laptop, handheld computer, or cloud server, etc. The computer device can interact with the user via a keyboard, mouse, remote control, touchpad, or voice control.

[0144] The memory 91 includes at least one type of readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 91 may be an internal storage unit of the computer device 9, such as the hard disk or memory of the computer device 9. In other embodiments, the memory 91 may also be an external storage device of the computer device 9, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the computer device 9. Of course, the memory 91 may include both the internal storage unit and its external storage device of the computer device 9. In this embodiment, the memory 91 is typically used to store the operating system and various application software installed on the computer device 9, such as computer-readable instructions for BMC chip management methods. In addition, the memory 91 can also be used to temporarily store various types of data that have been output or will be output.

[0145] In some embodiments, the processor 92 may be a central processing unit (CPU), controller, microcontroller, microprocessor, or other data processing chip. The processor 92 is typically used to control the overall operation of the computer device 9. In this embodiment, the processor 92 is used to execute computer-readable instructions stored in the memory 91 or to process data, for example, to execute computer-readable instructions of the BMC chip management method.

[0146] The network interface 93 may include a wireless network interface or a wired network interface, which is typically used to establish communication connections between the computer device 9 and other electronic devices.

[0147] Implementing this embodiment, by using Super The I / O expansion includes GPIO to monitor server operating status and handle alarms in case of abnormalities; it monitors platform fan operation and controls fan operation based on detected temperature; it controls LED indicators to show server operating status; it utilizes IPMI network and serial communication functions to receive IPMI interactive control statements from users through various communication channels to query server status or control functions such as power on / off; users can develop other applications to interact with the BMC via IPMI or other communication protocols to control the server or understand its operating status; it features fault reporting, power-on self-test, and operating status self-test functions; it has a software interface to output information such as current and voltage, main chip temperature, operating system and version, and firmware version to user software; the BMC chip has two access network ports, one RGMII and one NCSI interface; it has slot number, chassis number, and rack number identification functions; it has two IPMB interfaces to receive management and query data from the exchange via IPMB; it can obtain system status information through the BMC chip maintenance serial port and perform corresponding maintenance; the system functions based on the BMC chip are extensive, making full use of BMC chip resources.

[0148] Example 5

[0149] This application also provides another embodiment, namely, providing a computer-readable storage medium storing computer-readable instructions that can be executed by at least one processor to cause the at least one processor to perform the steps of the BMC chip management method described above.

[0150] Implementing this embodiment, by using Super The I / O expansion includes GPIO to monitor server operating status and handle alarms in case of abnormalities; it monitors platform fan operation and controls fan operation based on detected temperature; it controls LED indicators to show server operating status; it utilizes IPMI network and serial communication functions to receive IPMI interactive control statements from users through various communication channels to query server status or control functions such as power on / off; users can develop other applications to interact with the BMC via IPMI or other communication protocols to control the server or understand its operating status; it features fault reporting, power-on self-test, and operating status self-test functions; it has a software interface to output information such as current and voltage, main chip temperature, operating system and version, and firmware version to user software; the BMC chip has two access network ports, one RGMII and one NCSI interface; it has slot number, chassis number, and rack number identification functions; it has two IPMB interfaces to receive management and query data from the exchange via IPMB; it can obtain system status information through the BMC chip maintenance serial port and perform corresponding maintenance; the system functions based on the BMC chip are extensive, making full use of BMC chip resources.

[0151] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0152] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.

Claims

1. A BMC chip management method, characterized in that, The method comprises the following steps: The BMC chip is provided with a GPIO register for detecting an interrupt, and the GPIO register for detecting the interrupt is configured so that the falling edge of the signal of the input GPIO generates an interrupt; The program running in the CPU enters a system, the system automatically loads the driver of the Super I / O device related to the GPIO interrupt processing, and registers the interrupt processing program of lpc_gic_int; An application program is started, the pin of the GPIO input pin generates a falling edge change, and the BMC chip generates a GPIO interrupt; The Super I / O device transmits the GPIO interrupt information to the CPU through the LPC, and generates the lpc_gic_int interrupt in the CPU; The interrupt response program registered in the system is entered, the GPIO generating the interrupt signal is identified, and counting processing is performed; The interrupt counting value in the driver is obtained through the running GPIO interrupt processing application program, and the interrupt counting value is displayed.

2. The BMC chip management method of claim 1, wherein, Before the GPIO register for detecting the interrupt is configured so that the falling edge of the signal of the input GPIO generates an interrupt, the following step is further included: The UART1 and UART2 registers of the BMC chip are configured, so that the UART1 and UART PORT1 are bidirectionally connected, and the UART2 and UART PORT2 are bidirectionally connected.

3. The BMC chip management method of claim 1, wherein, The step of making the program running in the CPU enter the system, and making the system automatically load the driver of the Super I / O device related to the GPIO interrupt processing, and registering the interrupt processing program of lpc_gic_int specifically comprises the following steps: In the firmware program of the BMC chip, the falling edge of a plurality of GPIOs generates an interrupt function.

4. The BMC chip management method according to claim 3, wherein, The step of entering the interrupt response program registered in the system, identifying the GPIO generating the interrupt signal, and performing counting processing specifically comprises the following steps: The falling edge of the plurality of GPIOs generates an interrupt function, which identifies the pin currently generating the interrupt by obtaining the register value transmitted by the LPC channel, and adds one to the variable recording the interrupt number of the pin.

5. The BMC chip management method according to claim 4, wherein, The step of obtaining the interrupt counting value in the driver through the running GPIO interrupt processing application program, and displaying the interrupt counting value specifically comprises the following steps: The value of the variable recording the interrupt number of each pin in the driver is obtained, if the current value is changed compared with the original value, it is judged that the pin generates the interrupt, and the current value, that is, the interrupt counting value in the driver is displayed.

6. The BMC chip management method according to any one of claims 1 to 5, characterized in that: The BMC chip reads the first GPIO level state for detecting the slot position, and performs slot position identification; The BMC chip reads the second GPIO level state for detecting the chassis number, and performs chassis number identification.

7. The BMC chip management method according to claim 6, characterized in that: The BMC chip realizes two-way IPMB interface through two-way I2C, which is used for communication with other electronic devices. One-way IPMB interface is used as the main IPMB communication path, and the other is used as the backup IPMB communication path. The addresses of the two-way IPMB in the same slot are different. By controlling the terminal or other electronic devices, the BMC chip sends IPMB commands to control the power on / off of other electronic devices or query whether other electronic devices are online.

8. A BMC chip management device, characterized by, The method comprises the following steps: A configuration module is configured in the BMC chip to detect the GPIO register, and the GPIO register for detecting the interrupt is configured to generate an interrupt at the falling edge of the input GPIO signal. A registration module is configured to enable the program running in the CPU to enter the system, automatically load the Super I / O device driver related to the GPIO interrupt processing in the system, and register the lpc_gic_int interrupt processing program. A start module is configured to start the application program, and the pin of the GPIO input pin generates a falling edge change, and the BMC chip generates a GPIO interrupt. An interrupt module is configured to transmit the GPIO interrupt information to the CPU through the Super I / O device, and generate the lpc_gic_int interrupt in the CPU. An identification module is configured to enter the interrupt response program registered in the system, identify the GPIO that generates the interrupt signal, and perform counting processing. A display module is configured to obtain the interrupt count value in the driver program and display the interrupt count value through the running GPIO interrupt processing application program.

9. A computer device comprising a memory and a processor, wherein the memory stores computer readable instructions, and the processor executes the computer readable instructions to implement the steps of the BMC chip management method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer readable instructions, and the processor executes the computer readable instructions to implement the steps of the BMC chip management method according to any one of claims 1 to 7.

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