Data transmission method, device, electronic device and storage medium

Abstract

The present invention discloses a data transmission method, device, electronic device, and storage medium. The method includes: constructing a first message unit according to a first target instruction to be transmitted; wherein the first message unit includes a message header and a message body, the message header includes a command field of the first target instruction and a structure identifier of the message body, and the message body includes a data field of the first target instruction; sending the first message unit to a first memory to transmit the first message unit to other processors through the first memory; wherein the number of data bits in the message header of the first message unit is the same as the bit width of the first memory. The technical solution of the embodiment of the present invention improves the data transmission efficiency between processors, simplifies the data transmission logic between processors, and at the same time, avoids the occurrence of data reading and writing errors and improves the accuracy of transmitted data.

Description

Technical Field

[0001] The present invention relates to the fields of communication technology and chip technology, and in particular to a data transmission method, device, electronic device and storage medium. Background Art

[0002] In a system on a chip (SoC), multiple processors (eg, central processing units) often need to communicate information to collaborate and complete specific tasks. Therefore, the communication efficiency between processors directly affects the operating efficiency of the SoC.

[0003] Since the software of the system-on-chip usually runs on a bare core and does not have the communication mechanisms such as shared memory, pipes, and sockets provided by the operating system, communication between processors generally needs to be implemented based on specific hardware (for example, memory). The transmission efficiency between the processor and the memory directly determines the communication efficiency between the processors in the system-on-chip.

[0004] In the prior art, the transmission of commands and data between processors is usually executed through different memories to achieve separate transmission of commands and data. However, this transmission method has low information transmission efficiency between processors and overly complex transmission logic, which leads to poor system performance of the system on chip. Summary of the Invention

[0005] The present invention provides a data transmission method, device, electronic device and storage medium to solve the problem of low data transmission efficiency between processors in a system on chip.

[0006] According to one aspect of the present invention, a data transmission method includes:

[0007] Constructing a first message unit according to the first target instruction to be transmitted; wherein the first message unit includes a message header and a message body, the message header includes a command field of the first target instruction and a structure identifier of the message body, and the message body includes a data field of the first target instruction;

[0008] The first message unit is sent to a first memory, so as to transmit the first message unit to other processors through the first memory; wherein the number of data bits of the message header in the first message unit is the same as the bit width of the first memory.

[0009] The method of constructing a first message unit based on the first target instruction to be transmitted further includes: determining whether the number of data bits in the message body is an integer multiple of the bit width of the first memory; if the number of data bits in the message body is not an integer multiple of the bit width of the first memory, adding placeholder data to the message body to ensure that the number of data bits in the message body is an integer multiple of the bit width of the first memory. This ensures that the data read by the first memory each time comes from the same message unit, avoids the first memory confusing data in different message units, resulting in read and write errors, and improves the accuracy of transmitted data.

[0010] The method of constructing a first message unit based on a first target instruction to be transmitted further includes: obtaining a first recipient identifier that matches the first target instruction to be transmitted; and constructing a first message unit based on the first target instruction and the first recipient identifier; wherein a header of the first message unit includes the first recipient identifier. This method implements the transmission of directed instructions based on shared memory, saving memory hardware resources while ensuring the orderly issuance of directed instructions.

[0011] The method further includes: in response to obtaining a second message unit through a second memory, parsing the second message unit to obtain a message header and a message body of the second message unit; wherein the second message unit is constructed based on a second target instruction; and executing the second target instruction according to the message header and the message body of the second message unit. Through different memories, the first processor implements data transmission and reception respectively, greatly expanding the functionality of the first processor.

[0012] The method of parsing the second message unit in response to obtaining the second message unit through the second memory to obtain the message header and message body of the second message unit includes: in response to the bus-based hardware arbitration mechanism, obtaining the second message unit through the second memory, parsing the second message unit to obtain the message header and message body of the second message unit; determining whether the second receiver identifier in the second message unit is the same as the identifier of the first processor; if the second receiver identifier in the second message unit is the same as the identifier of the first processor, continuing to obtain the message body in the second message unit. The hardware arbitration mechanism based on the on-chip bus realizes natural mutual exclusion, avoiding communication conflicts between processors without affecting system performance.

[0013] After determining whether the second recipient identifier in the second message unit is the same as the identifier of the first processor, the method further includes: if the second recipient identifier in the second message unit is different from the identifier of the first processor, then judging whether there is a dedicated memory between the first processor and the second recipient based on the second recipient that matches the second recipient identifier; if it is determined that there is a dedicated memory between the first processor and the second recipient, then sending the second message unit to the dedicated memory to transmit the second message unit to the second recipient through the dedicated memory; if it is determined that there is no dedicated memory between the first processor and the second recipient, then sending the second message unit to the second memory to continue transmitting the second message unit to the second recipient through the second memory. Switching from shared channel transmission to dedicated channel transmission improves the transmission efficiency of the message unit.

[0014] The sending of the second message unit to the dedicated memory to transmit the second message unit to the second recipient via the dedicated memory includes: adjusting the data structure of the second message unit according to the bit width of the dedicated memory so that the number of data bits in the message header of the second message unit is the same as the bit width of the dedicated memory, and the number of data bits in the message body of the second message unit is an integer multiple of the bit width of the dedicated memory. When the first processor transmits the second message unit via the dedicated memory, the data structure of the second message unit is adjusted to adapt to the bit width of the dedicated memory, thereby further improving the data transmission efficiency between the first processor and the dedicated memory.

[0015] According to another aspect of the present invention, there is provided a data transmission device, comprising:

[0016] a message unit construction module, configured to construct a first message unit according to a first target instruction to be transmitted; wherein the first message unit includes a message header and a message body, the message header includes a command field of the first target instruction and a structure identifier of the message body, and the message body includes a data field of the first target instruction;

[0017] A message unit sending module is used to send the first message unit to a first memory so as to transmit the first message unit to other processors through the first memory; wherein the number of data bits of the message header in the first message unit is the same as the bit width of the first memory.

[0018] According to another aspect of the present invention, there is provided an electronic device, comprising:

[0019] at least one processor; and

[0020] a memory communicatively connected to the at least one processor; wherein,

[0021] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to perform the data transmission method according to any embodiment of the present invention.

[0022] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data transmission method according to any embodiment of the present invention when executed.

[0023] The technical solution of the embodiment of the present invention is that after constructing the first message unit according to the first target instruction to be transmitted, the command field and data field of the first target instruction are respectively saved in the message header and the message body, and then the first message unit is transmitted to other processors through the first memory, thereby improving the information transmission efficiency between processors and simplifying the data transmission logic between processors. At the same time, the number of data bits of the message header in the first message unit is the same as the bit width of the first memory, so that the first memory can obtain the complete message header through one reading, and all data read by the first memory this time are derived from the message header, avoiding the occurrence of data reading and writing errors and improving the accuracy of transmitted data.

[0024] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1A This is a flow chart of a data transmission method provided by Embodiment 1 of the present invention;

[0027] Figure 1B This is a flow chart of a data transmission method provided in Example 1 of the present invention;

[0028] Figure 1C This is a flow chart of a data transmission method provided in Example 1 of the present invention;

[0029] Figure 2This is a flowchart of a data transmission method provided according to the second embodiment of the present invention;

[0030] Figure 3 This is a structural diagram of a data transmission device provided according to Embodiment 3 of the present invention;

[0031] Figure 4 is a schematic structural diagram of an electronic device for implementing the data transmission method according to an embodiment of the present invention; DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] Example 1

[0035] Figure 1A A flowchart of a data transmission method is provided for the first embodiment of the present invention. This embodiment is applicable to data transmission based on a constructed message unit through a memory. The method can be executed by a data transmission device. The data transmission device can be implemented in the form of hardware and / or software. The data transmission device can be configured in a chip, and the chip can be integrated into an electronic device. Figure 1A As shown, the method includes:

[0036] S101. Construct a first message unit according to a first target instruction to be transmitted; wherein, the first message unit includes a message header and a message body, the message header includes a command field of the first target instruction and a structure identifier of the message body, and the message body includes a data field of the first target instruction.

[0037] The instructions transmitted between processors are composed of a command field and a data field; wherein the command field indicates the type of operation to be performed by the instruction, that is, it indicates the nature of the operation that the instruction should perform, such as a read operation, a write operation, and a disk partition operation, etc. Different command fields are represented by different binary codes; the data field is the action entity of the command field, indicating the execution object, execution basis, or specific numerical operation amount and other parameter information of the command field. For example, for a read operation, the data field may include the read object and the read speed; for a write operation, the data field may include the write object and the write speed; for a disk partition operation, the data field may include the disk location and the disk capacity; in the embodiment of the present invention, there is no specific limitation on the types of the command field and the data field.

[0038] The message body stores the data field of the first target instruction. Based on the actual number of bits in the data field, the data field can be directly used as the message body, that is, the number of data bits in the message body is consistent with the number of data bits in the data field. In the message unit, the message header is located before the message body. The message header not only includes the command field in the instruction, but also marks the structural composition of the message body through specific identification information. For example, if the message body only includes the data field, the message header can indicate the actual number of bits of the above-mentioned data field through the message body bit identifier; if the message body includes other data in addition to the data field, the message header can indicate the specific number of bits of the data field through the data field bit identifier, and then indicate the starting position of the data field in the message body through the start bit identifier, and then determine the data field in the message body based on the starting position and the specific number of bits; or indicate the ending position of the data field in the message body through the end bit identifier, and then determine the data field based on the ending position and the specific number of bits; it can also indicate the specific position of the data field in the message body based on the data field start bit identifier and the data field end bit identifier.

[0039] The number of data bits of the message header is consistent with the data transmission bit width of the first memory, so that when the message header is written to the first memory, the first memory can obtain the complete message header through a single read, and all data read by the first memory this time comes from the message header. For example, the data transmission bit width of the first memory is 32 bits, and bits 0-15 of the message header store the command field of the first target instruction, and bits 16-31 store the structure identifier of the message body; in particular, in order to ensure the standardization and consistency of various components on the chip, the memories on the chip used to implement shared communication between processors are usually memories of the same model, so the bit width of each memory is usually the same; thus, after the first processor obtains the first target instruction to be transmitted, it can construct a message header of a specified number of bits based on the above-mentioned fixed bit width; if the bit widths of various memories on the chip used to implement shared communication between processors are different, after obtaining the first target instruction, the first processor determines the memory between the first processor and the recipient according to the recipient of the first target instruction, and uses the bit width of the memory as the number of data bits of the constructed message header. The memory in the embodiment of the present invention may include a display data RAM (DDRAM), a static random-access memory (SRAM), a first-in first-out (FIFO) memory, etc.

[0040] Optionally, in an embodiment of the invention, constructing the first message unit according to the first target instruction to be transmitted also includes: determining whether the number of data bits of the message body is an integer multiple of the bit width of the first memory; if the number of data bits of the message body is not an integer multiple of the bit width of the first memory, adding placeholder data in the message body so that the number of data bits of the message body is an integer multiple of the bit width of the first memory.

[0041] Specifically, if the number of data bits of the message body constructed according to the data field is exactly an integer multiple of the bit width of the first memory, it is obvious that the above message body can be directly placed in the message unit; if the number of data bits of the message body constructed according to the data field is not an integer multiple of the bit width of the first memory, then by adding placeholder data (for example, 0 value) at the end of the message body, it is ensured that the number of data bits of the message body is an integer multiple of the bit width of the first memory, and the structure identifier of the message body in the message header indicates the respective positions of valid data (that is, data field) and invalid data (that is, placeholder data); for example, the width of the first memory is 4 bytes (that is, 32 bits), and the current data bit number of the message body is 60 bits, then 4 bits of placeholder data (for example, binary "0000") are added to the back end of the message body to ensure that the data read by the first memory each time comes from the same message unit, thereby avoiding the first memory confusing data in different message units, resulting in read and write errors, and improving the accuracy of transmitted data.

[0042] S102: Send the first message unit to a first memory, so as to transmit the first message unit to other processors through the first memory; wherein the number of data bits of the message header in the first message unit is the same as the bit width of the first memory.

[0043] Since the hardware resources of the system on chip are limited, in order to save memory resources, in the embodiment of the present invention, each memory can be used as a shared memory between three or more processors, such as Figure 1B As shown, multiple processors act as data senders of the first memory (in this case, the data receiver may be one or more), or as Figure 1C As shown, multiple processors act as data receivers of the first memory (the data sender can be one or more in this case); when the first processor acts as the data sender of the first memory, if the first target instruction is a non-directional instruction, it can be executed by any other processor, then even if the first memory corresponds to multiple data receivers, the first processor can directly construct the first message unit according to the first target instruction; if the first target instruction is a directional instruction, that is, it is executed by one or more specified processors, when the first memory corresponds to multiple data receivers, the first processor needs to specify the identity information of the receiver in the first message unit.

[0044] Optionally, in an embodiment of the invention, the constructing of the first message unit according to the first target instruction to be transmitted further includes: obtaining a first receiver identifier that matches the first target instruction to be transmitted; constructing a first message unit according to the first target instruction and the first receiver identifier; wherein the message header of the first message unit includes the first receiver identifier. Specifically, after obtaining the first target instruction, if it is determined that the instruction needs to be executed by one or more specific processors, then the first processor needs to first obtain the receiver identifier of the instruction (i.e., the first receiver identifier) ​​and add the receiver identifier to the message header of the first message unit, so that other processors can determine the receiver information through the receiver identifier when obtaining the message unit, thereby realizing the sending of directional instructions based on shared memory, while saving memory hardware resources and ensuring the orderly issuance of directional instructions.

[0045] Optionally, in an embodiment of the invention, the method further includes: in response to obtaining a second message unit through a second memory, parsing the second message unit to obtain a message header and a message body of the second message unit; wherein the second message unit is constructed based on a second target instruction; and executing the second target instruction according to the message header and the message body of the second message unit. The first processor can act as a data sender, issuing instructions to other processors through the first memory, and can also act as a data receiver, receiving instructions issued by other processors through the second memory; when a second message unit issued by other processors is obtained through the second memory, the message header and the message body in the message unit are obtained by parsing the second message unit, and then the command field is obtained through the message header, and based on the structure identifier of the message body in the message header, the data field is extracted from the message body, and then based on the above-mentioned command field and data field, a response to the second target instruction is implemented. Through different memories, the first processor implements data sending and receiving respectively, which greatly expands the functionality of the first processor.

[0046] The technical solution of the embodiment of the present invention is that after constructing the first message unit according to the first target instruction to be transmitted, the command field and data field of the first target instruction are respectively saved in the message header and the message body, and then the first message unit is transmitted to other processors through the first memory, thereby improving the information transmission efficiency between processors and simplifying the data transmission logic between processors. At the same time, the number of data bits of the message header in the first message unit is the same as the bit width of the first memory, so that the first memory can obtain the complete message header through one reading, and all data read by the first memory this time are derived from the message header, avoiding the occurrence of data reading and writing errors and improving the accuracy of transmitted data.

[0047] Example 2

[0048] Figure 2This is a flowchart of a data transmission method provided by the second embodiment of the present invention. Based on the above embodiment, in this embodiment, after obtaining the second message unit, it is determined whether the recipient of the second message unit is the first processor. Figure 2 As shown, the method includes:

[0049] S201. In response to a bus-based hardware arbitration mechanism, obtain a second message unit through a second memory, parse the second message unit to obtain a message header and a message body of the second message unit; and execute S202.

[0050] When the second memory corresponds to multiple data receivers or multiple data senders, if shared communication is achieved through software shared memory, pipes or sockets and other communication mechanisms, in order to avoid multiple processors receiving messages or sending messages at the same time, it is necessary to avoid the above-mentioned conflicts by writing software-based mutual exclusion locks. However, the above-mentioned mutual exclusion operations will bring great losses to system performance. In the present application, each processor, whether serving as a data receiver or a data sender of the memory, is connected to the memory through a bus, and natural mutual exclusion is achieved based on the hardware arbitration mechanism of the on-chip bus, thereby avoiding communication conflicts between the processors without affecting the system performance.

[0051] S202. Determine whether the second recipient identifier in the second message unit is the same as the identifier of the first processor; if so, execute S203; if not, execute S204.

[0052] S203: Continue to obtain the message body in the second message unit.

[0053] S204. Determine, based on the second recipient that matches the second recipient identifier, whether there is a dedicated memory between the first processor and the second recipient; if so, execute S205; if not, execute S206.

[0054] S205: Send the second message unit to the dedicated memory, so as to transmit the second message unit to the second recipient through the dedicated memory.

[0055] The first processor obtains the second message unit, but the recipient of the second message unit is not the first processor. Obviously, the second memory includes at least two data recipients. Therefore, the second memory is a shared memory of three or more processors. When the message unit is transmitted in the shared memory, it cannot be ensured that the second message unit will be obtained by the second recipient in time, and it may also be obtained by other recipients first. Therefore, if there is a non-shared dedicated memory between the first processor and the second recipient, the first processor will send the second message unit directly to the second recipient through the dedicated memory, and switch from shared channel transmission to dedicated channel transmission, which obviously improves the transmission efficiency of the message unit.

[0056] Optionally, in an embodiment of the invention, the sending of the second message unit to the dedicated memory so as to transmit the second message unit to the second recipient through the dedicated memory includes: adjusting the data structure of the second message unit according to the bit width of the dedicated memory so that the number of data bits of the message header in the second message unit is the same as the bit width of the dedicated memory, and the number of data bits of the message body in the second message unit is an integer multiple of the bit width of the dedicated memory. When the first processor transmits the second message unit through the dedicated memory, the data structure of the second message unit is adjusted to adapt to the bit width of the dedicated memory, thereby further improving the data transmission efficiency between the first processor and the dedicated memory. At the same time, since the dedicated memory is a dedicated transmission channel between the first processor and the second recipient, the second recipient identifier in the message header of the second message unit can be deleted to reduce the amount of data in the message header. The data bits after the deletion of the data can also be filled with placeholder data.

[0057] S206: Send the second message unit to the second memory, so as to continue transmitting the second message unit to the second recipient through the second memory.

[0058] If there is no non-shared dedicated memory between the first processor and the second recipient, the second message unit is returned to the second memory, so that the second recipient obtains the message unit through the second memory.

[0059] The technical solution of the embodiment of the present invention realizes natural mutual exclusion between processors based on the hardware arbitration mechanism of the on-chip bus, avoiding communication conflicts between processors without affecting system performance. At the same time, by parsing the second message unit to obtain the message header and message body, when it is determined that the second recipient identifier does not match itself, the second message unit is transmitted to the second recipient through a dedicated memory, further improving the transmission efficiency of the message unit.

[0060] Example 3

[0061] Figure 3 This is a structural diagram of a data transmission device provided by the third embodiment of the present invention. Figure 3 As shown, the device includes:

[0062] A message unit construction module 301 is configured to construct a first message unit according to a first target instruction to be transmitted; wherein the first message unit includes a message header and a message body, the message header includes a command field of the first target instruction and a structure identifier of the message body, and the message body includes a data field of the first target instruction;

[0063] The message unit sending module 302 is used to send the first message unit to the first memory so as to transmit the first message unit to other processors through the first memory; wherein the number of data bits of the message header in the first message unit is the same as the bit width of the first memory.

[0064] The technical solution of the embodiment of the present invention is that after constructing the first message unit according to the first target instruction to be transmitted, the command field and data field of the first target instruction are respectively saved in the message header and the message body, and then the first message unit is transmitted to other processors through the first memory, thereby improving the information transmission efficiency between processors and simplifying the data transmission logic between processors. At the same time, the number of data bits of the message header in the first message unit is the same as the bit width of the first memory, so that the first memory can obtain the complete message header through one reading, and all data read by the first memory this time are derived from the message header, avoiding the occurrence of data reading and writing errors and improving the accuracy of transmitted data.

[0065] Optionally, the message unit construction module 301 is specifically used to determine whether the number of data bits of the message body is an integer multiple of the bit width of the first memory; if the number of data bits of the message body is not an integer multiple of the bit width of the first memory, placeholder data is added to the message body to make the number of data bits of the message body an integer multiple of the bit width of the first memory.

[0066] Optionally, the message unit construction module 301 is further specifically used to obtain a first recipient identifier that matches the first target instruction to be transmitted; construct a first message unit based on the first target instruction and the first recipient identifier; wherein the message header of the first message unit includes the first recipient identifier.

[0067] Optionally, the data transmission device further includes:

[0068] a message unit acquisition module, configured to, in response to acquiring a second message unit through a second memory, parse the second message unit to obtain a message header and a message body of the second message unit; wherein the second message unit is constructed based on a second target instruction;

[0069] The message unit execution module is used to execute the second target instruction according to the message header and message body of the second message unit.

[0070] Optionally, the message unit acquisition module specifically includes:

[0071] a message unit acquiring unit, configured to acquire a second message unit through a second memory in response to a bus-based hardware arbitration mechanism, and parse the second message unit to acquire a message header and a message body of the second message unit;

[0072] a receiver identification determination unit, configured to determine whether the second receiver identification in the second message unit is the same as the identification of the first processor;

[0073] A message body acquiring unit is configured to continue acquiring the message body in the second message unit if the second recipient identifier in the second message unit is the same as the identifier of the first processor.

[0074] Optionally, the message unit acquisition module further includes:

[0075] a dedicated memory determining unit, configured to determine, if the second recipient identifier in the second message unit is different from the identifier of the first processor, whether a dedicated memory exists between the first processor and the second recipient according to the second recipient matching the second recipient identifier;

[0076] a dedicated memory forwarding unit, configured to, if it is determined that a dedicated memory exists between the first processor and the second recipient, send the second message unit to the dedicated memory, so as to transmit the second message unit to the second recipient through the dedicated memory;

[0077] The second memory returning unit is configured to send the second message unit to the second memory if it is determined that no dedicated memory exists between the first processor and the second recipient, so as to continue transmitting the second message unit to the second recipient through the second memory.

[0078] Optionally, a dedicated memory forwarding unit is specifically used to adjust the data structure of the second message unit according to the bit width of the dedicated memory, so that the number of data bits of the message header in the second message unit is the same as the bit width of the dedicated memory, and the number of data bits of the message body in the second message unit is an integer multiple of the bit width of the dedicated memory.

[0079] The data transmission device provided in the embodiment of the present invention can execute the data transmission method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0080] Example 4

[0081] Figure 4 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0082] like Figure 4 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0083] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0084] The processor 11 may be any general-purpose and / or specialized processing component with processing and computing capabilities. Examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors for running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the data transmission method.

[0085] In some embodiments, the data transmission method may be implemented as a computer program that is tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the data transmission method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the data transmission method in any other suitable manner (e.g., by means of firmware).

[0086] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0087] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0088] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0089] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0090] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0091] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within a cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0092] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0093] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A data transmission method, characterized in that: Applied to a first processor, comprising: Constructing a first message unit according to the first target instruction to be transmitted; wherein the first message unit includes a message header and a message body, the message header includes a command field of the first target instruction and a structure identifier of the message body, and the message body includes a data field of the first target instruction; The first message unit is sent to a first memory, so as to transmit the first message unit to other processors through the first memory; wherein the number of data bits of the message header in the first message unit is the same as the bit width of the first memory.

2. The method according to claim 1, characterized in that The constructing of the first message unit according to the first target instruction to be transmitted further includes: Determining whether the number of data bits of the message body is an integer multiple of the bit width of the first memory; If the number of data bits of the message body is not an integer multiple of the bit width of the first memory, placeholder data is added to the message body to make the number of data bits of the message body an integer multiple of the bit width of the first memory.

3. The method according to claim 1, characterized in that The constructing of the first message unit according to the first target instruction to be transmitted further includes: Acquire a first recipient identifier that matches a first target instruction to be transmitted; A first message unit is constructed according to the first target instruction and the first recipient identifier; wherein a message header of the first message unit includes the first recipient identifier.

4. The method according to claim 1, wherein The method further comprises: In response to obtaining a second message unit through the second memory, parsing the second message unit to obtain a message header and a message body of the second message unit; wherein the second message unit is constructed based on the second target instruction; The second target instruction is executed according to the message header and message body of the second message unit.

5. The method according to claim 4, characterized in that The step of, in response to obtaining the second message unit through the second memory, parsing the second message unit to obtain a message header and a message body of the second message unit, includes: In response to a bus-based hardware arbitration mechanism, obtaining a second message unit through a second memory, and parsing the second message unit to obtain a message header and a message body of the second message unit; Determining whether the second recipient identifier in the second message unit is the same as the identifier of the first processor; If the second recipient identifier in the second message unit is the same as the identifier of the first processor, continue to obtain the message body in the second message unit.

6. The method according to claim 5, characterized in that After determining whether the second recipient identifier in the second message unit is the same as the identifier of the first processor, the method further includes: If the second recipient identifier in the second message unit is different from the identifier of the first processor, determining whether there is a dedicated memory between the first processor and the second recipient based on the second recipient matching the second recipient identifier; If it is determined that a dedicated memory exists between the first processor and the second recipient, sending the second message unit to the dedicated memory, so as to transmit the second message unit to the second recipient through the dedicated memory; If it is determined that no dedicated memory exists between the first processor and the second recipient, the second message unit is sent to the second memory, so as to continue to transmit the second message unit to the second recipient through the second memory.

7. The method according to claim 6, characterized in that The sending of the second message unit to the dedicated memory, so as to transmit the second message unit to the second recipient through the dedicated memory, comprises: According to the bit width of the dedicated memory, the data structure of the second message unit is adjusted so that the number of data bits of the message header in the second message unit is the same as the bit width of the dedicated memory, and the number of data bits of the message body in the second message unit is an integer multiple of the bit width of the dedicated memory.

8. A data transmission device, characterized in that: Applied to a first processor, comprising: a message unit construction module, configured to construct a first message unit according to a first target instruction to be transmitted; wherein the first message unit includes a message header and a message body, the message header includes a command field of the first target instruction and a structure identifier of the message body, and the message body includes a data field of the first target instruction; A message unit sending module is used to send the first message unit to a first memory so as to transmit the first message unit to other processors through the first memory; wherein the number of data bits of the message header in the first message unit is the same as the bit width of the first memory.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to perform the data transmission method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data transmission method according to any one of claims 1 to 7 when executed.

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