Semiconductor mesa device forming method

Abstract

A method for forming a semiconductor device may include providing a semiconductor substrate including an inner region of a first polarity and a surface layer disposed on the inner region, wherein the surface layer includes a second polarity opposite to the first polarity. The method may further include removing a surface portion of the semiconductor substrate using a saw, wherein a trench region is formed in the semiconductor substrate, and cleaning the trench region using a chemical process, wherein at least one mesa structure is formed in the semiconductor substrate.

Description

Technical Field

[0001] Embodiments relate to the field of semiconductor devices, and more particularly, to semiconductor devices using a mesa structure. Background Art

[0002] Today, semiconductor devices can employ mesa-type structures to form active devices. According to known methods, mesa structures can be used to electrically insulate semiconductor substrates comprising multiple layers of different polarities. For example, a semiconductor substrate may include an n-type region within an inner region and a p-type layer formed above the n-type region toward the surface of the semiconductor substrate. To form a mesa-type device, the perimeter of the mesa can be defined by photolithography to achieve electrical isolation of the substrate region and form the mesa. For example, a photoresist layer can be deposited on the substrate, and a mask or other device can be used to define the perimeter of the mesa within the photoresist layer. The photoresist layer can then be patterned to create exposed areas of the substrate to be etched. A subsequent wet etching process can be performed to remove the surface portion of the substrate defining the perimeter, thereby forming the mesa. The perimeter region can then be passivated, for example. This method of forming the mesa may involve multiple operations, including photoresist coating, mask alignment, development, overbake, and may involve WNDR, NBA, or quartz mask materials.

[0003] In view of the above considerations, improvements to the above-mentioned mesa process may be useful.

[0004] It is with respect to these and other considerations that the present disclosure is provided.

[0005] Main content

[0006] In one embodiment, a method for forming a semiconductor device is provided. The method may include providing a semiconductor substrate comprising an inner region of a first polarity and a surface layer disposed on the inner region, wherein the surface layer comprises a second polarity opposite to the first polarity. The method may further include removing a surface portion of the semiconductor substrate using a saw, wherein a trench region is formed in the semiconductor substrate, and cleaning the trench region using a chemical process, wherein at least one mesa structure is formed in the semiconductor substrate.

[0007] In another embodiment, a method of forming a semiconductor device may include providing a semiconductor substrate comprising an interior region of a first polarity and a surface layer disposed on the interior region, wherein the surface layer comprises a second polarity opposite to the first polarity. The method may also include using a saw to define a grid pattern in the semiconductor substrate, wherein the grid pattern comprises a trench region formed in an XY grid, wherein the trench region extends through the entire surface layer, wherein a plurality of mesas are formed in the surface layer, wherein a given mesa of the plurality of mesas is electrically insulated from other mesas of the plurality of mesas.

[0008] In yet another embodiment, a method for forming a semiconductor device is provided. The method may include providing a semiconductor substrate comprising an inner region of a first polarity, and a first surface layer arranged in the inner region on a first side of the semiconductor substrate, and a second surface layer arranged in the inner region on a second side of the semiconductor substrate opposite to the first side. Accordingly, the first surface layer and the second surface layer may include a second polarity opposite to the first polarity. The method may include removing a first surface portion of the semiconductor substrate on the first surface using a saw, and removing a second surface portion of the semiconductor substrate on the second surface using a saw. Accordingly, a first trench region may be formed in the semiconductor substrate on the first surface, and a second trench region may be formed in the semiconductor substrate on the second surface. The method may include cleaning the first trench region and the second trench region using a chemical process, wherein at least one mesa structure is formed in the semiconductor substrate on the first side, and at least one additional mesa structure is formed in the semiconductor substrate on the second side. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A and Figure 1B Side cross-sectional views of a substrate at different stages during the formation of a mesa device structure according to various embodiments of the present disclosure are shown.

[0010] Figure 1C Shown in Figure 1B A top plan view of the substrate at the stage of formation indicated in FIG.

[0011] Figure 2A and Figure 2B Side cross-sectional views of a substrate at different stages during the formation of a mesa device structure according to various embodiments of the present disclosure are shown.

[0012] Figure 3 An exemplary flow chart is depicted.

[0013] Figure 4 Another exemplary flow chart is depicted. DETAILED DESCRIPTION

[0014] The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. The embodiments should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey its scope to those skilled in the art. In the drawings, like numbers refer to like elements throughout.

[0015] In the following description and / or claims, the terms "on ...", "covering ...", "arranged on ...", and "above ..." may be used in the following description and claims. "On ...", "covering ...", "arranged on ...", and "above ..." may be used to indicate that two or more elements are in direct physical contact with each other. Additionally, the terms "on ...", "covering ...", "arranged on ...", and "above ..." may mean that two or more elements are not in direct contact with each other. For example, "above ..." may mean that one element is above another element and is not in contact with each other, and may have another one or more elements between the two elements. Additionally, although the scope of the claimed subject matter is not limited to this aspect, the term "and / or" may mean "and", it may mean "or", it may mean "exclusive or", it may mean "one", it may mean "some, but not all", it may mean "any one of the two", and / or it may mean "both".

[0016] In various embodiments, methods for forming a mesa-type semiconductor device including a transient voltage suppression (TVS) diode device are provided.

[0017] Figure 1A and Figure 1B Side cross-sectional views of the substrate 100 are shown at different stages during the formation of a mesa device structure 140 according to various embodiments of the present disclosure. Figure 1C Shown in Figure 1B 1 is a top plan view of substrate 100 at the stage of formation indicated in FIG.

[0018] exist Figure 1A, a substrate 100 is shown including an inner region 110 having a first polarity. For example, the substrate 100 can be an N-type substrate, wherein the inner region 110 is also n-type. A surface layer 112 is disposed on the inner region 110. The surface layer 112 includes a second polarity opposite to the first polarity of the inner region 110. For example, the surface layer 112 can be a P-type layer. The surface layer 112 can be formed using any suitable known method. The thickness and dopant concentration in the surface layer 112 can be selected based on the type of device to be formed from the mesa device structure 140.

[0019] For example, in the case of a TVS device, a suitable dopant concentration can be selected according to different non-limiting embodiments to generate a target breakdown voltage, such as 15V-20V or 30V-35V. Similarly, the thickness of the surface layer 112 can be selected to generate the desired electrical characteristics of the device to be formed. In some non-limiting embodiments, the thickness of the surface layer 112 can be in the range of 2 mils.

[0020] Steering Figure 1B , according to an embodiment of the present disclosure, a new operation for forming a mesa device structure is shown. In this operation, a saw device 120 is employed to form a trench region 130 in a surface region of a substrate 100. According to a non-limiting embodiment of the present disclosure, the saw device 120 can be a known type of saw and can, for example, employ a cutting blade 122 formed of metal, ceramic, carbide, diamond, or a combination thereof. The saw device 120 can be configured to generate a trench having a controllable and fixed depth within the substrate 100.

[0021] As shown in FIG1B , the formation of a trench region 130 can be used to electrically insulate a portion of the surface layer 112 to form a semiconductor device. In various embodiments, to achieve electrical insulation, the trench region 130 is defined by a trench depth d, where the trench depth d is at least as great as the thickness of the surface layer 112. For example, in some embodiments, the trench depth d can be at least 2 mils, while the trench width w can be on the order of several mils, such as 5 mils, 10 mils, or 20 mils. The embodiments are not limited in this context.

[0022] In order to define the mesa device structure 140, the saw device 120 can be configured to generate a two-dimensional pattern, such as a grid pattern, for the trench region 130. Figure 1CIn the example of FIG, an array of mesa device structures 140 is shown, wherein the device structures form a grid of rectangular mesas, each mesa being surrounded by a trench region 130 that forms a perimeter around the given mesa device structure. Because the trench region 130 extends at least through the entire surface layer 112, the surface layer 112 within a given mesa device structure is electrically isolated from a portion of the surface layer 112 within any other mesa device structure because the current must travel through the interior region 110 of opposite polarity. Figure 1C In the example of FIG. 1 , the trench region 130 may be formed by generating a series of saw marks along the X-axis and a series of saw marks along the Y-axis to form a grid pattern as shown.

[0023] According to embodiments of the present disclosure, as described in detail later with respect to further embodiments, further operations may be performed to complete the formation of the semiconductor device, including cleaning and passivation.

[0024] Figure 1A-1C An advantage of the method shown in is that mesa isolation can be achieved in essentially one operation, involving a saw cutting process that can be programmed to generate repeatable trench depths suitable for a given device formation.

[0025] Figure 2A and Figure 2B Side cross-sectional views of the substrate 200 are shown at different stages during the formation of a mesa device structure 240 according to various embodiments of the present disclosure.

[0026] exist Figure 2A , a substrate 200 including an inner region is shown, the semiconductor substrate including an inner region 210 having a first polarity. For example, the substrate 200 can be an N-type substrate, wherein the inner region 210 is also n-type. Alternatively, the substrate 200 can be a P-type substrate, wherein the inner region 210 is also p-type. A first surface layer 212 is arranged on the inner region 210. The first surface layer 212 includes a second polarity opposite to the first polarity of the inner region 210. For example, the first surface layer 212 can be a P-type layer. The first surface layer 212 can be formed using any suitable known method. The thickness and dopant concentration in the first surface layer 212 can be selected based on the type of device to be formed from the mesa device structure 240. The substrate 200 includes a second surface layer 216 arranged on the opposite side of the inner region 210, wherein the second surface layer 216 includes a second polarity opposite to the first polarity of the inner region 210. The substrate 200 further includes a first oxide layer 214 disposed above the first surface layer 212 and a second oxide layer 218 disposed above the second surface layer 216. Figure 2A2B, the substrate 200 can function as a bidirectional diode. In some non-limiting embodiments, the first surface layer 212 and the second surface layer 216 can have the same thickness and the same dopant concentration as each other, while in other embodiments, the thickness and / or dopant concentration of the first surface layer 212 and the second surface layer 216 can be different. For example, according to various embodiments, the first surface layer 212 and the second surface layer 216, as well as the first oxide layer 214 and the second oxide layer 218 can be formed in a single diffusion process to establish a base junction.

[0027] As for Figures 1A-1C In the embodiment, the thickness and dopant concentration of the first surface layer 212 may be selected according to the device application of the mesa device structure to be formed.

[0028] like Figure 2A As further depicted in FIG, a novel operation for forming a mesa device structure according to an embodiment of the present disclosure is shown. In this operation, a saw device 220 is employed to form a trench region 230 in a surface region of a substrate 100. According to non-limiting embodiments of the present disclosure, the saw device 220 can be a known type of saw and can, for example, employ a cutting blade (not shown) formed of metal, ceramic, carbide, diamond, or a combination thereof. The saw device 220 can be configured to generate a trench having a controllable and fixed depth within the substrate 200.

[0029] like Figure 2A As shown in FIG, the formation of the trench region 230 can be used to electrically insulate a portion of the surface layer 212 to form a semiconductor device. In various embodiments, to achieve electrical insulation, such as Figure 2B As shown in , the groove region 230 is defined by a groove depth d, wherein the groove depth d is at least as great as the thickness of the first surface layer 212. As with the previous embodiments, the groove thickness d can be at least 2 mils, while the groove width w can be on the order of several mils, such as 5 mils, 10 mils, or 20 mils. The embodiments are not limited in this context.

[0030] As about Figure 1C As generally described, in order to define the mesa device structure 240, the saw device 220 can be configured to generate a two-dimensional pattern, such as a grid pattern, for the trench region 230. Figure 2AAt this stage of the operation, the trench region 230 has been defined by the saw marks, and debris 232 formed as a byproduct of the saw marks may remain in the trench region 230, as well as in other surface areas of the substrate 200. The cleaning operation can be completed using a chemical process 234, which is schematically illustrated by arrows. In a non-limiting embodiment, the chemical process 234 is an MAE etch (the recipe for the MAE etch can be represented by a 2:1:1 (HF:HNO3:CH3COOH) mixture), wherein the MAE etch removes residual semiconductor debris and ionic contaminants from the surface of the trench region 230.

[0031] like Figure 2B As shown in FIG, after the formation of the trench 230 , further operations may include the formation of a passivation layer in the trench region 230 .

[0032] Figure 2A The advantage of embodiment 2B is that the formation of the mesa device structure only requires a saw cutting operation and a subsequent simple chemical etching process.

[0033] Despite Figure 2B Although not shown, according to various embodiments of the present disclosure, when a substrate, such as substrate 200, is formed into a bidirectional diode, the mesa device structure 240 can be formed on both sides of the substrate. In other words, the mesa device structure 240 can be formed on the upper surface 202 of the substrate 200, and the mesa device structure 240 can also be formed (using the second surface layer 216) on the lower surface 204 of the substrate 200. Such a process is carried out in the following Figure 4 This will be explained in further detail.

[0034] Figure 3 A flowchart 300 is depicted according to an embodiment of the present disclosure. At block 310, a semiconductor substrate, such as a silicon substrate, is provided. In some embodiments, the semiconductor substrate may be doped to a first conductivity type (first polarity) and at a suitable doping concentration for forming a device (e.g., a breakdown diode). As an example, the semiconductor substrate may be doped to have an N-type polarity.

[0035] At block 320, a surface layer of the second conductivity type is formed in a surface region on a main surface of the semiconductor substrate, wherein the surface layer and the inner portion of the semiconductor substrate define a p / n junction. For example, if the semiconductor substrate is doped to have an N-type polarity as a whole, a surface layer can be formed on the semiconductor substrate to define a P-type semiconductor layer, which is now arranged above the N-type inner portion of the semiconductor substrate. In some non-limiting embodiments, a second surface layer of the second conductivity type can be formed on the relative main surface of the semiconductor substrate. In such an embodiment, a second p / n junction can be formed between the inner portion of the semiconductor substrate and the second surface layer.

[0036] At block 330, a trench structure is formed in a surface region of the semiconductor substrate using a saw cutting process, wherein the trench structure extends at least to a depth of the p / n junction and wherein the trench structure encloses at least one mesa structure. In particular, the saw cutting process may be performed in such a manner that the trench structure forms a two-dimensional perimeter defining at least one mesa structure. In various embodiments, the saw cutting process may define a two-dimensional rectangular grid defining an array of mesa structures.

[0037] At block 340 , after the sawing process, a chemical etching process is performed to remove debris and clean the trench structure. The chemical etching process may be any suitable etching process known in the art, such as a MAE process.

[0038] Turning to block 350 , a passivation process is performed to passivate the trench structure.

[0039] Figure 4 Another exemplary flow chart 400 is depicted. At block 410, a semiconductor substrate of a first conductivity type is provided.

[0040] At block 420, a first surface layer of a second conductivity type is formed in the first surface of the semiconductor substrate, and a second surface layer of the second conductivity type is formed in the second surface of the semiconductor substrate. As such, the first semiconductor layer and the inner portion of the semiconductor substrate define a first p / n junction, and the second semiconductor layer and the inner portion of the semiconductor substrate define a second p / n junction.

[0041] At block 430 , a first trench structure is formed in the first surface of the semiconductor substrate using a saw process, wherein the first trench structure extends at least to a depth of the first p / n junction, and wherein the first trench structure surrounds at least one mesa structure on the first surface.

[0042] At block 440 , a second trench structure is formed in the second surface of the semiconductor substrate using a saw process, wherein the second trench structure extends at least to a depth of the second p / n junction and wherein the second trench structure encloses at least one additional mesa structure on the second surface.

[0043] At block 450 , a chemical etching process is performed to clean the first trench structure and the second trench structure. The chemical etching process may be any suitable etching process known in the art, such as a MAE process.

[0044] At block 460 , a passivation process is performed to passivate the first trench structure and the second trench structure. As such, a bidirectional diode device may be formed with mesa device structures on both sides of the semiconductor substrate.

[0045] Although the present embodiments have been disclosed with reference to specific embodiments, many modifications, substitutions, and changes may be made to the embodiments without departing from the field and scope of the present disclosure as defined in the appended claims. Therefore, the present embodiments are not intended to be limiting, and they have the full scope defined by the language of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, comprising: Providing a semiconductor substrate, the semiconductor substrate comprising an inner region of a first polarity, and a first surface layer disposed on the inner region on a first side of the semiconductor substrate, and a second surface layer disposed on the inner region on a second side of the semiconductor substrate opposite to the first side, wherein the first surface layer and the second surface layer comprise a second polarity opposite to the first polarity, wherein the first surface layer and the inner region on the first side of the semiconductor substrate define a first p / n junction, and the second surface layer and the inner region on the second side of the semiconductor substrate define a second p / n junction, wherein the first surface layer and the second surface layer are formed in a single diffusion process, the single diffusion process further forming a first oxide layer and a second oxide layer on the first surface layer and the second surface layer, respectively; removing a first surface portion of the semiconductor substrate on a first surface using a saw, and removing a second surface portion of the semiconductor substrate on a second surface using a saw, wherein a first trench region is formed in the semiconductor substrate on the first surface and extends at least to a depth of the first p / n junction, and a second trench region is formed in the semiconductor substrate on the second surface and extends at least to a depth of the second p / n junction; and The first trench region and the second trench region are cleaned using a chemical process, wherein at least one mesa structure is formed in the semiconductor substrate on the first side and at least one additional mesa structure is formed in the semiconductor substrate on the second side. 2 . The method of claim 1 , wherein the first trench region and the second trench region comprise a trench depth, wherein the trench depth is at least as great as a first thickness of the first surface layer and a second thickness of the second surface layer. The method of claim 2 , wherein the first thickness is equal to the second thickness.

4. The method of claim 2, wherein the groove depth is at least 2 mils. The method of claim 3 , wherein the groove width is between 5 mils and 50 mils. 6 . The method of claim 1 , wherein the first trench region and the second trench region are arranged in a grid pattern defining a plurality of mesas on the first side and on the second side.

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