Method of preparing patterned silicon substrates for epitaxial growth of iii-v semiconductors

Abstract

The application discloses a preparation method of a patterned silicon substrate for III-V group semiconductor epitaxial growth, which comprises the following steps: preparing a mask layer on a pre-acquired silicon substrate, obtaining the silicon substrate with the mask layer; etching the mask layer in the silicon substrate with the mask layer based on a preset pattern, forming a first groove; etching the silicon substrate in the silicon substrate with the mask layer based on the first groove, forming a second groove and exposing a 111 plane of silicon; and cleaning to remove the oxide in the second groove, thereby obtaining the patterned silicon substrate for III-V group semiconductor epitaxial growth. The patterned silicon substrate prepared by the method can be used for epitaxial growth of a III-V group semiconductor thin film of a single crystal, can effectively inhibit dislocations of a III-V group semiconductor / Si interface, has better crystallization of the III-V group semiconductor thin film, and greatly improves the overall quality.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a preparation method of a patterned silicon substrate for epitaxial growth of a III-V semiconductor. BACKGROUND

[0002] The contemporary semiconductor industry is seeking new methods for manufacturing integrated circuits to improve the performance of devices and reduce costs; among them, silicon integrated circuit technology is limited by process and physical problems in terms of integration, reliability, speed, power consumption, etc., and the traditional method of increasing integration by reducing device size has encountered a bottleneck, and devices with high mobility channels have become a research hotspot. Because III-V semiconductor materials have much higher electron mobility than Si, they are widely studied to replace Si channels to prepare high-mobility devices to improve device speed.

[0003] Epitaxial growth of high-quality III-V semiconductor thin films on Si substrates is a prerequisite for the preparation of Si-based high-mobility devices, but direct heteroepitaxial growth of high-quality III-V semiconductors, such as indium phosphide (InP), on Si substrates is challenging because the lattice mismatch and thermal expansion mismatch between InP and Si will result in a large number of dislocations during heteroepitaxy, which will reduce device performance; at the same time, because III-V semiconductors are polar, when grown on non-polar Si substrates, they will have anti-phase domains, anti-phase domain boundaries, and crystal defects, which will affect the quality of the epitaxial film.

[0004] In summary, how to perform heteroepitaxy of high-quality III-V semiconductors on Si substrates is a technical problem that needs to be solved. SUMMARY

[0005] The present application aims to provide a preparation method of a patterned silicon substrate for epitaxial growth of a III-V semiconductor, to solve one or more of the above technical problems. The patterned silicon substrate prepared by the method of the present application can be used to perform epitaxial growth of single-crystal III-V semiconductor thin films, effectively inhibiting dislocations at the III-V semiconductor / Si interface, and the crystalline condition of the III-V semiconductor thin film is good, the overall quality is greatly improved, and a prerequisite for the preparation of Si-based high-mobility devices is provided.

[0006] To achieve the above-mentioned purpose, the present application adopts the following technical scheme:

[0007] The present application provides a preparation method of a patterned silicon substrate for epitaxial growth of a III-V semiconductor, comprising the following steps:

[0008] A mask layer is prepared on a pre-acquired silicon substrate to obtain a silicon substrate with a mask layer; wherein the off-plane orientation of the pre-acquired silicon substrate is 001 and is obliquely cut to the 110 direction of silicon by 3-10 degrees;

[0009] The mask layer in the silicon substrate with the mask layer is etched based on a preset pattern to form a first groove; wherein the etching depth is the same as the thickness of the mask layer; the preset pattern comprises one or more of a strip-shaped pattern, a grid-shaped pattern and a round hole-shaped pattern;

[0010] The silicon substrate in the silicon substrate with the mask layer is etched based on the first groove to form a second groove and expose the 111 plane of silicon; wherein the second groove is a reverse pyramid type;

[0011] The second groove is cleaned to remove the oxide in the second groove to obtain a patterned silicon substrate for III-V semiconductor epitaxial growth.

[0012] The further improvement of the preparation method is that, after the patterned silicon substrate for III-V semiconductor epitaxial growth is obtained, the prepared patterned silicon substrate for III-V semiconductor epitaxial growth is stored in a vacuum cavity.

[0013] The further improvement of the preparation method is that the mask layer material is silicon oxide or silicon nitride.

[0014] The further improvement of the preparation method is that the thickness of the mask layer is 50-1000 nm.

[0015] The further improvement of the preparation method is that the direction of the strip-shaped pattern has an angle of 15 degrees with the 110 direction, the width of the strip-shaped groove is 0.5-2 microns, the different grooves are parallel to each other and the distance between the grooves is 2-3 microns.

[0016] The further improvement of the preparation method is that the grid-shaped pattern is a strip-shaped groove staggered in two directions, one direction of the strip-shaped groove has an angle of 15 degrees with the 110 direction, the other direction of the strip-shaped groove has an angle of 105-120 degrees with the 110 direction, the width of the groove is 0.5-2 microns, and the distance between the grooves is 2-3 microns.

[0017] The further improvement of the preparation method is that the round hole-shaped pattern is a continuous row of round holes, the round holes in the row are parallel to each other; the round holes in the row have an angle of 15 degrees with the 110 direction, the diameter of the round hole is 0.5-1 micron, and the distance between the round holes is 1-2 microns.

[0018] The further improvement of the preparation method is that, in the process of etching the silicon substrate in the silicon substrate with the mask layer based on the first groove, the etching solution used in the etching process is potassium hydroxide solution, and the etching temperature is 50-70 DEG C.

[0019] The further improvement of the preparation method is that, in the process of cleaning to remove the oxide in the second groove, the cleaning solution used in the cleaning process is hydrofluoric acid solution.

[0020] Compared with the prior art, the present application has the following beneficial effects:

[0021] The preparation method provided by the present application limits the III-V semiconductor to start growing from the groove, and stops the mismatch dislocation and the anti-phase domain boundary between the III-V semiconductor and Si on the wall of the insulating medium layer; the Si substrate with a special pattern (the groove width of which is sub-micron level) used can improve the quality of the III-V semiconductor grown on the substrate; the use of the inverted pyramid groove technology controls the III-V semiconductor to start growing from the 111 surface of Si, and provides a surface with a unique polarity, which can more effectively inhibit the dislocation of the III-V semiconductor / Si interface; and the use of the silicon substrate which is inclined to a special direction can inhibit the generation of the anti-phase domain. The patterned Si substrate prepared by the method of the present application can epitaxially grow a high-quality, less-defect single-crystal III-V semiconductor thin film thereon, and provides a prerequisite for preparing a Si-based high-mobility device. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following briefly introduces the drawings needed to be used in the embodiments or prior art description; obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0023] Figure 1 is a flowchart of a preparation method of a patterned silicon substrate for epitaxial growth of a III-V semiconductor according to an embodiment of the present application;

[0024] Figure 2 is a schematic diagram of a scanning electron microscope (SEM) secondary electron test result of a strip-shaped patterned substrate in a patterned substrate according to an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of a SEM secondary electron test result of a grid-shaped patterned substrate in a patterned substrate according to an embodiment of the present application;

[0026] Figure 4is a schematic diagram of SEM secondary electron test results of a round-hole-patterned substrate in a patterning substrate according to an embodiment of the present application;

[0027] Figure 5 is a schematic diagram of SEM secondary electron test results obtained after selective growth of indium phosphide (InP) in a strip-patterned substrate in an epitaxial growth step of a III-V semiconductor according to an embodiment of the present application; explanatory, based on Figure 5 It can be found that the selective growth of InP can be realized by using the patterning substrate according to the present application, and the growth of InP is limited in the Si trench;

[0028] Figure 6 is a schematic diagram of SEM secondary electron test results obtained after selective growth of InP in a grid-patterned substrate in an epitaxial growth step of a III-V semiconductor according to an embodiment of the present application; explanatory, based on Figure 6 It can be found that the selective growth of InP can be realized by using the patterning substrate according to the present application, and the growth of InP is limited in the Si trench;

[0029] Figure 7 is a schematic diagram of X-ray diffraction 2θ test results obtained after epitaxial growth of InP in a grid-patterned substrate according to an embodiment of the present application, in a strip-patterned substrate according to an embodiment of the present application, and in a common silicon substrate in an epitaxial growth step of a III-V semiconductor according to an embodiment of the present application; explanatory, based on Figure 7 It can be found that the FWHM of the 004 orientation peak of InP of the film grown on the grid-patterned substrate and the strip-patterned substrate is 0.22° and 0.20° respectively, which is lower than the FWHM of the 004 orientation peak of InP of the film grown on the common silicon substrate, i.e. 0.40°, which indicates that the epitaxial growth of III-V semiconductor film using the patterning substrate according to the present application can effectively inhibit the dislocation of the III-V semiconductor / Si interface, the crystallization of the III-V semiconductor film is better, and the overall quality is greatly improved. DETAILED DESCRIPTION

[0030] The present application will be further described below in conjunction with specific embodiments, which should be understood as merely illustrative of the present application but not used to limit the protection scope of the present application.

[0031] Following, the embodiments of the present application will be described in detail by specific examples, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of this specification. The present application can also be implemented or applied by other different embodiments, and various modifications or changes can be made to the details in this specification based on different views and applications without departing from the spirit of the present application.

[0032] It should be noted that the process equipment or device not specifically mentioned in the following examples is the conventional equipment or device in the art.

[0033] In addition, it should be understood that the one or more method steps mentioned in the present application do not exclude that there can be other method steps before and after the combination steps or other method steps can be inserted between the explicitly mentioned steps, unless otherwise specified; it should also be understood that the combination connection relationship between the one or more devices / apparatuses mentioned in the present application does not exclude that there can be other devices / apparatuses before and after the combination devices / apparatuses or other devices / apparatuses can be inserted between the two explicitly mentioned devices / apparatuses, unless otherwise specified. Moreover, unless otherwise specified, the numbering of each method step is only a convenient tool to identify each method step, and is not intended to limit the arrangement order of each method step or to limit the range of implementation of the present application, and the change or adjustment of the relative relationship without substantial change of the technical content is also regarded as the scope of implementation of the present application.

[0034] Please refer to Figure 1 The preparation method of the patterned silicon (Si) substrate for high-quality epitaxial growth of group III-V semiconductors according to an embodiment of the present application comprises the following steps:

[0035] Step 1: preparing a mask layer on the Si substrate; the off-plane orientation of the Si substrate in step 1 is 001, and the Si substrate is inclined to the 110 direction of Si by 3°-10°;

[0036] Step 2: etching the mask layer to form a groove, and patterning the substrate;

[0037] Step 3: etching the groove in the substrate to form an inverted-pyramid-shaped groove, and exposing the 111 plane of Si;

[0038] Step 4: cleaning the substrate and quickly placing it in a vacuum chamber for epitaxial growth of group III-V semiconductors.

[0039] In the embodiment of the present application, the mask layer material in step 1 includes but is not limited to silicon oxide and silicon nitride; the thickness of the mask layer is 50 nm-1000 nm.

[0040] In the embodiment of the present application, the pattern in step 2 has three kinds of strip, grid and round hole respectively. The strip pattern has an angle of 15° with the 110 direction, the width of the strip groove is 0.5-2 μm, and the distance between the grooves is 2-3 μm. The grid pattern has two directions of strip grooves which are interlaced with each other, one direction of the strip grooves has an angle of 15° with the 110 direction, and the other direction of the strip grooves has an angle of 105-120° with the 110 direction, the width of the grooves is 0.5-2 μm, and the distance between the grooves is 2-3 μm. The round hole pattern has continuous round holes in a row, and the round holes in the row are parallel to each other. The round holes in the row have an angle of 15° with the 110 direction, the diameter of the round hole is 0.5-1 μm, and the distance between the round holes is 1-2 μm.

[0041] In the embodiment of the present application, the patterning method in step 2 is to etch the mask layer on the surface according to the pattern, and the etching depth is the same as the thickness of the mask layer on the surface, i.e. the etching depth is 50-1000 nm.

[0042] In the embodiment of the present application, the etching solution used in the etching step in step 3 is potassium hydroxide (KOH) solution, the mass concentration of the KOH solution is 50-70%, the etching temperature is 50-70°C, and the etching time is 2-10 minutes.

[0043] In the embodiment of the present application, the cleaning solution used in the cleaning step in step 4 is hydrofluoric acid (HF) solution, the mass concentration of the HF solution is 0.2-1%, and the cleaning time is 15-60 seconds.

[0044] Embodiment 1

[0045] The present application provides a preparation method of a patterned silicon (Si) substrate for high-quality epitaxial growth of III-V group semiconductors, which comprises the following steps

[0046] Step 1: growing a mask layer on a silicon (Si) substrate, which is used as an insulating medium layer for selective epitaxial growth.

[0047] Step 2: etching the mask layer to form grooves and pattern the substrate.

[0048] Step 3: etching the substrate with potassium hydroxide (KOH) solution to form inverted-pyramid grooves and expose the 111 plane of Si.

[0049] Step 4: cleaning the substrate with hydrofluoric acid (HF) solution to remove the oxide in the grooves.

[0050] Step 5: Put the substrate into a vacuum chamber to prepare for epitaxial growth of monocrystalline III-V semiconductor thin film.

[0051] The method provided by the embodiment of the application has the following inventive points:

[0052] (1) The high aspect ratio trench confinement technology is used to confine the III-V semiconductor to start selective growth from the trench, and the mismatch dislocation between the III-V semiconductor and silicon (Si) and the reverse domain boundary are cut off on the wall of the mask layer.

[0053] (2) The optimized patterned Si substrate and submicron trench width are used to further improve the quality of the III-V semiconductor grown on the Si substrate by hetero-selective epitaxy.

[0054] (3) The potassium hydroxide (KOH) solution is used to etch in the Si trench to form an inverted pyramid type groove, which can further improve the aspect ratio and ensure that the III-V semiconductor is grown from the 111 plane of Si, thereby providing a surface with unique polarity, on which the III-V semiconductor has fewer defects, better crystallization, and better quality.

[0055] (4) The Si substrate is used to be inclined at a certain angle to the 110 direction, which can inhibit the generation of reverse domains.

[0056] Please refer to Figures 2 to 4 , the pattern of the patterned substrate in step 2 uses three types of patterns shown in Figure 2 , Figure 3 and Figure 4 , which are strip-shaped, grid-shaped and circular hole-shaped, respectively, wherein the meaning of 110 is the 110 direction of Si, and the meanings of the α angle, the β angle, C and D have been marked in the figure. The α angle of the strip-shaped pattern is 15°, the trench width is 0.5 μm-2 μm, and the trenches are parallel to each other, and the distance between them is 2 μm-3 μm; the α angle of the grid-shaped pattern is 15°, the β angle is 105°-120°, the trench width is 0.5 μm-2 μm, and the distance between the trenches is 2 μm-3 μm; the α angle of the circular hole-shaped pattern is 15°, and the β angle is 105°. The circular hole diameter is 0.5 μm-1 μm, and the circular hole spacing is 1 μm-2 μm.

[0057] Embodiment 2

[0058] The preparation method of the patterned silicon (Si) substrate for high-quality III-V semiconductor epitaxial growth provided by the embodiment of the application comprises the following steps:

[0059] 1) Prepare a 3-inch Si substrate with an off-plane orientation of 001 and an inclined angle of 4° to the 110 direction.

[0060] 2) Grow 50nm thick SiO2on the Si substrate using dry-wet-dry thermal oxidation method.

[0061] 3) Prepare a photoetch mask with a pattern as shown in FIG. 1, with the following parameters: grid, a = 15°, β = 105°, D = 0.5 μm, C = 3 μm. Figure 3

[0062] 4) Use a photoetch machine and the above mask to photoetch the Si substrate, and use dry etching to etch the Si substrate and form a groove with a special pattern, with an etching depth of 50 nm, to ensure that the surface SiO2is completely etched.

[0063] 5) Use a 60% KOH solution to etch the substrate at 60°C for 3 minutes to form an inverted pyramid shape, exposing the Si 111 plane. Then, use acetone, alcohol, and deionized water at room temperature to clean the substrate in an ultrasonic cleaning instrument for 5 minutes to remove residual KOH solution.

[0064] 6) Use a 0.5% HF solution to clean the prepared substrate at room temperature for 30 seconds to ensure that the surface oxide is completely removed. Then, use acetone, alcohol, and deionized water at room temperature to clean the substrate in an ultrasonic cleaning instrument for 5 minutes to remove residual HF solution.

[0065] 7) Put the prepared patterned substrate into a vacuum chamber to prepare for growth of a III-V semiconductor thin film. The III-V semiconductor thin film grown using the grid-shaped substrate is an indium phosphide (InP) thin film, and the method used is molecular beam epitaxy (MBE). After 1 hour of growth, selective growth of InP in the Si groove is achieved, and the scanning electron microscope (SEM) secondary electron test results are shown in FIG. 2. After increasing the growth time to 6 hours, film-to-film growth is achieved, as shown in FIG. 3. Figure 6 Figure 7 The X-ray diffraction 2θ test results of the InP 004 orientation peak of the InP thin film grown on the grid pattern substrate described in this embodiment are shown in FIG. 4, with a full width at half maximum (FWHM) of 0.20°, which is significantly lower than the full width at half maximum (FWHM) of 0.40° in the X-ray diffraction 2θ test results of the InP 004 orientation of an InP thin film grown on a common Si substrate under the same conditions, indicating that the patterned substrate proposed in this application can indeed inhibit the generation of dislocations and achieve better crystalline quality of the thin film when growing a III-V semiconductor thin film.

[0066] Example 3

[0067] ​​A preparation method of a patterned silicon (Si) substrate for high-quality III-V group semiconductor epitaxial growth, comprising the following steps:

[0068] 1) preparing a 3-inch Si substrate with an off-plane orientation of 001 and a 6° tilt to the 110 direction.

[0069] 2) growing a 50 nm thick SiO2 on the Si substrate using a dry-wet-dry thermal oxidation method.

[0070] 3) preparing a photoetching mask with a pattern as shown in Figure 2 , with the following specific parameters: strip-shaped, α of 15°, D of 1 μm, and C of 2 μm.

[0071] 4) using a photoetching machine and the above mask to perform photoetching on the Si substrate, using dry etching to etch the Si substrate and etch a groove with a special pattern, with an etching depth of 50 nm, to ensure that the surface SiO2 is completely etched.

[0072] 5) using a 60% KOH solution to immerse and etch the substrate at a temperature of 60 °C for 3 minutes to etch a reverse pyramid shape and expose the 111 plane of Si, and then using acetone, alcohol, and deionized water at room temperature to clean the substrate in an ultrasonic cleaning instrument for 5 minutes to remove residual KOH solution.

[0073] 6) using a 0.5% HF solution to immerse and clean the prepared substrate at room temperature for 30 seconds to ensure that the surface oxide is completely removed, and then using acetone, alcohol, and deionized water at room temperature to clean the substrate in an ultrasonic cleaning instrument for 5 minutes to remove residual HF solution.

[0074] 7) placing the prepared patterned substrate into a vacuum chamber to prepare for III-V group semiconductor film growth. The III-V group semiconductor film epitaxially grown using the strip-shaped substrate is an indium phosphide (InP) film, and the method used is molecular beam epitaxy (MBE). After 1 hour of growth, selective growth of InP in the Si groove can be achieved, and the secondary electron test result diagram of a scanning electron microscope (SEM) is as shown in Figure 5 . After increasing the growth time to 6 hours, film-to-patch growth can be achieved, Figure 7 , which is an X-ray diffraction 2θ test result diagram of the InP 004 orientation peak of the InP film grown on the strip pattern substrate described in the embodiment, with a full width at half maximum (FWHM) of 0.22°. Compared with an X-ray diffraction 2θ test result diagram of the InP 004 orientation peak of an InP film grown on a common silicon substrate under the condition that other conditions remain unchanged, Figure 7The full width at half maximum (FWHM) 0.40° is obviously reduced, which indicates that the patterned substrate provided by the application can obtain a thin film with better crystallization quality and can effectively inhibit the generation of dislocations when growing a III-V semiconductor thin film.

[0075] Embodiment 4

[0076] The preparation method of the patterned silicon substrate for epitaxial growth of a III-V semiconductor provided by the application comprises the following steps:

[0077] A mask layer is prepared on the pre-acquired silicon substrate to obtain a silicon substrate with a mask layer;

[0078] The mask layer in the silicon substrate with a mask layer is etched based on a preset pattern to form a first groove; the etching depth is the same as the thickness of the mask layer;

[0079] The silicon substrate in the silicon substrate with a mask layer is etched based on the first groove to form a second groove and expose the 111 plane of silicon; the second groove is in the form of an inverted pyramid;

[0080] The second groove is cleaned to remove the oxide in the second groove to obtain a patterned silicon substrate for epitaxial growth of a III-V semiconductor; the obtained patterned silicon substrate for epitaxial growth of a III-V semiconductor is stored in a vacuum chamber.

[0081] The out-of-plane orientation of the pre-acquired silicon substrate is 001 and is obliquely cut 3° to the 110 direction of silicon; the mask layer material is silicon oxide; and the thickness of the mask layer is 50 nm. In the process of etching the silicon substrate with a mask layer based on the first groove, the etching solution used during etching is potassium hydroxide solution, and the etching temperature is 50℃. In the process of cleaning to remove the oxide in the second groove, the cleaning solution used during cleaning is hydrofluoric acid solution.

[0082] The patterned silicon substrate adopts a strip-shaped pattern, the direction of the strip-shaped pattern has an angle of 15° with the 110 direction, the width of the strip-shaped groove is 0.5μm, the different grooves are parallel to each other and have a spacing of 2μm.

[0083] Embodiment 5

[0084] The preparation method of the patterned silicon substrate for epitaxial growth of a III-V semiconductor provided by the embodiment of the application is different from that of embodiment 4 only in that the out-of-plane orientation of the pre-acquired silicon substrate is 001 and is obliquely cut 5° to the 110 direction of silicon; the mask layer material is silicon oxide; and the thickness of the mask layer is 500 nm. In the process of etching the silicon substrate in the silicon substrate with a mask layer based on the first groove, the etching solution used during etching is potassium hydroxide solution, and the etching temperature is 60℃.

[0085] The patterned silicon substrate adopts a strip pattern, the width of the strip-shaped groove is 1 μm, and the different grooves are parallel to each other and have a distance of 2.5 μm.

[0086] Embodiment 6

[0087] The preparation method of the patterned silicon substrate for epitaxial growth of a III-V semiconductor according to the embodiment of the application is different from that of embodiment 4 only in that the out-of-plane orientation of the pre-acquired silicon substrate is 001 and is obliquely cut 10° to the 110 direction of silicon; the mask layer material is silicon oxide; and the thickness of the mask layer is 1000 nm. In the process of etching the silicon substrate in the silicon substrate provided with the mask layer based on the first groove, the etching solution used in the etching is potassium hydroxide solution, and the etching temperature is 70 °C.

[0088] The patterned silicon substrate adopts a strip pattern, the width of the strip-shaped groove is 2 μm, and the different grooves are parallel to each other and have a distance of 3 μm.

[0089] Embodiment 7

[0090] The preparation method of the patterned silicon substrate for epitaxial growth of a III-V semiconductor according to the embodiment of the application is different from that of embodiment 4 only in that the patterned silicon substrate adopts a grid pattern and a strip pattern; the grid pattern is two directions of interlaced strip-shaped grooves, the included angle between one direction of the strip-shaped grooves and the 110 direction is 15°, the included angle between the other direction of the strip-shaped grooves and the 110 direction is 105°, the width of the groove is 0.5 μm, and the distance between the grooves is 2 μm.

[0091] Embodiment 8

[0092] The preparation method of the patterned silicon substrate for epitaxial growth of a III-V semiconductor according to the embodiment of the application is different from that of embodiment 7 only in that the grid pattern is two directions of interlaced strip-shaped grooves, the included angle between one direction of the strip-shaped grooves and the 110 direction is 15°, the included angle between the other direction of the strip-shaped grooves and the 110 direction is 110°, the width of the groove is 1 μm, and the distance between the grooves is 2.5 μm.

[0093] Embodiment 9

[0094] The preparation method of the patterned silicon substrate for epitaxial growth of a III-V semiconductor according to the embodiment of the application is different from that of embodiment 7 only in that the grid pattern is two directions of interlaced strip-shaped grooves, the included angle between one direction of the strip-shaped grooves and the 110 direction is 15°, the included angle between the other direction of the strip-shaped grooves and the 110 direction is 120°, the width of the groove is 2 μm, and the distance between the grooves is 3 μm.

[0095] Example 10

[0096] The preparation method of the patterned silicon substrate for epitaxial growth of III-V semiconductor according to the embodiment of the present application is different from that of Example 4 only in that the patterned silicon substrate adopts a circular hole pattern; the circular hole pattern is a continuous row of circular holes, and the circular holes in the row are parallel to each other; the angle between the row of circular holes and the 110 direction is 15°, the diameter of the circular hole is 0.5 μm, and the distance between the circular holes is 1 μm.

[0097] Example 11

[0098] The preparation method of the patterned silicon substrate for epitaxial growth of III-V semiconductor according to the embodiment of the present application is different from that of Example 10 only in that the circular hole pattern is a continuous row of circular holes, and the circular holes in the row are parallel to each other; the angle between the row of circular holes and the 110 direction is 15°, the diameter of the circular hole is 0.8 μm, and the distance between the circular holes is 1.5 μm.

[0099] Example 12

[0100] The preparation method of the patterned silicon substrate for epitaxial growth of III-V semiconductor according to the embodiment of the present application is different from that of Example 10 only in that the circular hole pattern is a continuous row of circular holes, and the circular holes in the row are parallel to each other; the angle between the row of circular holes and the 110 direction is 15°, the diameter of the circular hole is 1 μm, and the distance between the circular holes is 2 μm.

[0101] The embodiment of the present application specifically provides a preparation method of a patterned silicon (Si) substrate for epitaxial growth of high-quality III-V semiconductor, which comprises the following steps: 1) preparing a Si substrate with a 001 out-of-plane orientation and a 3°-10° tilt to the 110 direction; 2) preparing a mask layer of a material including but not limited to silicon oxide or silicon nitride on the Si substrate, and the thickness of the mask layer is 50 nm-1000 nm;

[0102] 3) etching the Si substrate covered with the mask according to a special pattern to form a groove, the etching depth being the same as the thickness of the mask layer, and the groove width being 0.5-2 μm; 4) etching the Si substrate using a 50-70% KOH solution at a temperature of 50-70 °C for 2-10 minutes to form a reverse-pyramid-shaped groove exposing the 111 plane of Si; 5) cleaning the substrate using a 0.2-1% HF solution at room temperature for 15-60 seconds to remove the residual oxide on the surface; and 6) placing the prepared patterned substrate into a vacuum chamber for hetero-epitaxial growth of a III-V semiconductor thin film. The III-V semiconductor thin film epitaxially grown on the patterned Si substrate prepared by the above method can effectively inhibit the dislocation of the III-V semiconductor / Si interface, the crystallization of the III-V semiconductor thin film is better, and the overall quality is greatly improved, thereby providing a prerequisite for preparing a Si-based high-mobility device.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application but not to limit it, and although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the specific embodiments of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and any modification or equivalent replacement without departing from the spirit and scope of the present application should be covered in the protection scope of the claims of the present application.

Claims

1. A method for preparing a patterned silicon substrate for epitaxial growth of a Ill-nitride semiconductor, characterized in that, The method comprises the following steps: Preparation of a mask layer on a pre-acquired silicon substrate to obtain a silicon substrate with a mask layer; wherein the out-of-plane orientation of the pre-acquired silicon substrate is 001 and is inclined to the 110 direction of silicon by 3°-10°; Etching the mask layer in the silicon substrate with a mask layer based on a preset pattern to form a first groove; wherein the etching depth is the same as the thickness of the mask layer; the preset pattern comprises one or more of a strip-shaped, grid-shaped and circular hole-shaped pattern; Based on the first groove, etching the silicon substrate in the silicon substrate with a mask layer to form a second groove and expose the 111 plane of silicon; wherein the second groove is a reverse pyramid type; Cleaning to remove the oxide in the second groove to obtain a patterned silicon substrate for III-V semiconductor epitaxial growth; The strip-shaped pattern has an angle of 15° with the 110 direction, the width of the strip-shaped groove is 0.5-2 μm, the grooves are parallel to each other and have a distance of 2-3 μm; the grid-shaped pattern is a strip-shaped groove in two directions that are interlaced with each other, one of the directions has an angle of 15° with the 110 direction, the other of the directions has an angle of 105°-120° with the 110 direction, the width of the groove is 0.5-2 μm, and the distance between the grooves is 2-3 μm; the circular hole-shaped pattern is a continuous row of circular holes, the circular holes in the row are parallel to each other, the row of circular holes has an angle of 15° with the 110 direction, the diameter of the circular hole is 0.5-1 μm, and the distance between the circular holes is 1-2 μm.

2. The method of claim 1, wherein the patterned silicon substrate is prepared by a method comprising: After the patterned silicon substrate for III-V semiconductor epitaxial growth is obtained, the method further comprises: storing the obtained patterned silicon substrate for III-V semiconductor epitaxial growth in a vacuum chamber. ​ 3. The method of claim 1, wherein the patterned silicon substrate is prepared by a method comprising: providing a silicon wafer; forming a patterned mask on the silicon wafer; and etching the silicon wafer to form a plurality of patterned silicon structures. The mask layer material is silicon oxide or silicon nitride.

4. The method of claim 1, wherein the patterned silicon substrate is prepared by a method comprising: The thickness of the mask layer is 50-1000 nm. ​ 5. The method of claim 1, wherein the patterned silicon substrate is prepared by a method comprising: a) providing a silicon wafer; b) forming a patterned mask on the silicon wafer; c) etching the silicon wafer to form a patterned silicon substrate; and d) removing the patterned mask. In the process of etching the silicon substrate in the silicon substrate with a mask layer based on the first groove, The etching solution used in the etching process is a potassium hydroxide solution, and the etching temperature is 50-70 °C.

6. The method of claim 1, wherein the patterned silicon substrate is prepared by a method comprising: providing a silicon wafer; forming a patterned mask on the silicon wafer; etching the silicon wafer to form a patterned silicon substrate. In the process of cleaning to remove the oxide in the second groove, the cleaning solution used in the cleaning process is a hydrofluoric acid solution.

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