Semiconductor structure and method of manufacturing the same

Abstract

Semiconductor structures are provided. The semiconductor structures can include a transistor structure that can include a gate region disposed above an upper surface of a substrate and extending substantially in a first direction perpendicular to the upper surface of the substrate; a first source / drain region located above the upper surface of the substrate; a second source / drain region located above the upper surface of the substrate; and a channel region extending vertically in the first direction between the first source / drain region and the second source / drain region, wherein the channel region includes an oxide semiconductor material. In the first direction, the gate region covers sidewalls of the channel region. Embodiments of the present application also relate to methods of manufacturing semiconductor structures.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of manufacturing the same. Background Technology

[0002] As technology advances, the minimum size of circuit elements that can be fabricated in integrated circuit chips (ICs) continues to shrink. Therefore, the demand for increasing the number of circuit elements in ICs of the same or smaller size is constantly increasing. One way to increase the density of circuit elements in ICs is to fabricate circuit elements in multiple layers of the IC. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor structure, including: a transistor structure comprising: a gate region disposed above an upper surface of a substrate, wherein the gate region extends substantially in a first direction perpendicular to the upper surface of the substrate; a first source / drain region located above the upper surface of the substrate; a second source / drain region located above the upper surface of the substrate; and a channel region extending perpendicularly in the first direction between the first source / drain region and the second source / drain region, wherein the channel region comprises an oxide semiconductor material; wherein, along the first direction, the gate region covers the sidewalls of the channel region.

[0004] Some other embodiments of this application provide a semiconductor structure, including: a first transistor structure and a second transistor structure, each including: a gate region disposed above an upper surface of a substrate and extending substantially in a first direction perpendicular to the upper surface of the substrate; a first source / drain region; a second source / drain region; and a channel region extending substantially in the first direction between the first source / drain region and the second source / drain region, wherein the channel region comprises an oxide semiconductor material; wherein, along the first direction, the gate region of the first transistor structure substantially covers a first sidewall of the channel region of the first transistor structure, wherein, along the first direction, the gate region of the second transistor structure substantially covers a second sidewall of the channel region of the second transistor structure, wherein the gate region of the first transistor structure is electrically isolated from the gate region of the second transistor structure; wherein the gate region of the first transistor structure and the gate region of the second transistor structure are located between the first source / drain region of the first transistor structure and the first source / drain region of the second transistor structure.

[0005] Further embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: forming a first source / drain region; forming a first dielectric layer over the first source / drain region; forming a first trench by removing a portion of the first dielectric layer that substantially does not cover the first source / drain region; forming a channel region in the first trench; forming a gate dielectric region in the first trench that contacts the channel region; filling the first trench with a second dielectric material; forming a second trench by removing a portion of the second dielectric material and exposing the gate dielectric region; filling the second trench to form a gate region; forming a second dielectric layer over the first dielectric layer and the gate region; removing a portion of the second dielectric layer and the first dielectric layer to expose the channel region; and forming a second source / drain region that contacts the channel region. Attached Figure Description

[0006] Aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1D Several schematic diagrams of exemplary transistor structures according to some embodiments of the present invention are shown.

[0008] Figures 2A to 2B , Figures 3A to 3B , Figures 4A to 4B , Figures 5A to 5B , Figures 6A to 6B , Figures 7A to 7B , Figures 8A to 8B , Figures 9A to 9B , Figures 10A to 10B , Figures 11A to 11B , Figures 12A to 12B , Figures 13A to 13B , Figures 14A to 14B , Figures 15A to 15B , Figures 16A to 16C , Figures 17A to 17C , Figures 18A to 18C , Figures 19A to 19B , Figures 20A to 20B , Figures 21A to 21B , Figures 22A to 22B , Figures 23A to 23B , Figures 24A to 24B and Figures 25A to 25B A semiconductor structure is shown to illustrate exemplary steps for manufacturing a transistor structure according to some embodiments of the present invention.

[0009] Figure 26A and Figure 26B Exemplary dimensions of various structural components of a transistor structure according to some embodiments of the present invention are shown.

[0010] Figure 27A A schematic diagram of an exemplary transistor structure array according to some embodiments of the present invention is shown.

[0011] Figure 27B (Including portions (a) and (b)) show schematic diagrams of memory arrays according to some embodiments of the present invention.

[0012] Figures 27C to 27D A schematic diagram of an exemplary semiconductor structure according to some embodiments of the present invention is shown.

[0013] Figure 28A and Figure 28B Exemplary transistor structures according to some embodiments of the present invention are shown.

[0014] Figure 29 A schematic diagram of an exemplary semiconductor structure according to some embodiments of the present invention is shown.

[0015] Figure 30A and Figure 30B An exemplary flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present invention is shown.

[0016] Figure 31 A schematic diagram illustrating a vertical layer arrangement of a semiconductor device related to an embodiment of the present invention is shown. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0019] In some embodiments, for a first direction and a second direction, the terms "substantially along," "substantially parallel," or "substantially orthogonal" refer to the first direction within an angle of deviation (such as 5°, 10°, and 15°) from a reference direction. For "substantially along" or "substantially parallel," the reference direction is the second direction, and for "substantially orthogonal," the reference direction is at 90° to the second direction. Other methods for determining whether the first direction is "substantially along," "substantially parallel," or "substantially orthogonal" to the second direction are within the scope of this invention. For example, the ratio of the angle of deviation of the first direction from the first reference direction to the angle of deviation of the second direction from the second reference direction is greater than a percentage such as 85%, 90%, 95%, etc. For "substantially along" or "substantially parallel," the first reference direction is the same as the second reference direction, and for "substantially orthogonal," the first reference direction is at 90° to the second reference direction. In another instance, the difference between the angle of deviation of the first direction from the first reference direction and the angle of deviation of the second direction from the second reference direction is less than a percentage such as 5%, 10%, and 15% of the angle of deviation of the second direction from the second reference direction.

[0020] It should be understood that, in this invention, a pattern / layer / structure / surface / direction substantially perpendicular to another pattern / layer / structure / surface / direction means that the two patterns / layers / structures / surfaces / directions are perpendicular to each other, or that the two patterns / layers / structures / surfaces / directions are intended to be configured to be perpendicular to each other, but may not be perfectly perpendicular due to design, manufacturing, or measurement errors / margins caused by non-ideal manufacturing and measurement conditions. Such a description should be readily recognizable to those skilled in the art.

[0021] In this invention, forming two layers / patterns / structures at different levels means that, taking into account variations / errors caused by, for example, surface roughness, the two layers / patterns / structures have different distances from a reference plane (e.g., the surface of a substrate), upon which a semiconductor device is formed.

[0022] In this invention, a layer, pattern, or structure extending in one direction means that the dimension of the layer, pattern, or structure in the direction of extension is greater than the dimension of the layer, pattern, or structure in another direction substantially perpendicular to the direction of extension.

[0023] In this invention, the phrase “one of A, B and C” means “A, B and / or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean an element from A, an element from B and an element from C, unless otherwise stated.

[0024] In this invention, the phrase "layers / patterns / structures formed of substantially the same material" means that the layers / patterns / structures are formed of the same material or that the layers / patterns / structures are initially formed of the same material but may later be doped with impurities of the same or different types and of the same or different concentrations to realize a semiconductor device. Such a description should be readily apparent to those skilled in the art.

[0025] In this invention, expressions such as "about" and "approximately" preceding a value indicate that the value is exactly the same as described or within a certain range of the described value, taking into account design errors / margins, manufacturing errors / margins, measurement errors, etc. Such descriptions should be recognizable to those skilled in the art.

[0026] Furthermore, it should be understood that when a component is referred to as "connected to" or "coupled to" another component, it can be directly connected to or coupled to another component, or there can be intermediate components.

[0027] In this invention, not every layer of a unit or layout is depicted in the accompanying drawings. Those skilled in the art will understand that a unit or layout may include more layers to achieve the function of the unit, and these layers are omitted only for the sake of description.

[0028] Figure 31 A cross-sectional view showing a vertical layer arrangement of a semiconductor device in relation to an embodiment of the present invention is displayed. Figure 31 The specific cross-section of the semiconductor device or structure described elsewhere in this invention may not necessarily be shown.

[0029] In the substrate layer, channel structures (such as fin structures) and source / drain structures can be formed. In the gate layer, gate structures (such as gate electrodes and gate dielectric layers) can be formed. A local interconnect wiring layer M0 is located above the gate layer and / or the source / drain structures. A first via layer is located above the gate layer, and a first via can be formed in the first via layer. Metal interconnects can be formed in the first metal layer M1. Vias can be formed in the second via layer to electrically connect components in layers M0 and M1. Metal interconnects can be formed in the second metal layer M2. The number of metal layers (x represents Mx) can be greater than 2, and in some embodiments, up to 15-20.

[0030] Application-specific integrated circuits (ASICs) can be manufactured on semiconductor wafers (such as silicon wafers) using semiconductor manufacturing processes. These processes can be divided into front-end processing (FEOL) and back-end processing (BEOL).

[0031] In the context of this invention, FEOL processing refers to the steps and processes associated with forming transistors in or directly on a semiconductor substrate. In the context of this invention, BEOL processing may include steps and processes associated with the formation of interconnects and passivations (e.g., elements for interconnecting transistors formed in the FEOL processing). In the context of this invention, BEOL processing may refer to the formation of layer M1 and layers above M1.

[0032] Some FEOL processes may require relatively high temperatures. For example, annealing performed after certain types of doping processes may reach temperatures of 1000°C or even higher. High temperatures may prevent the use of some materials in FEOL processes.

[0033] In contrast, the lower processing temperatures may be sufficient for common manufacturing steps employed in BEOL processes (such as deposition), thus allowing BEOL processes to have a lower temperature budget than FEOL processes. This lower temperature budget allows the use of materials that are unsuitable for FEOL processes due to temperature limitations.

[0034] Specialized semiconductor manufacturing processes can be used to manufacture different types of integrated circuits. For example, ASICs contain many logic gates, while memory chips mainly contain memory cells; therefore, specialized processes can be developed to manufacture them. That is, an ASIC may still contain a certain number of memory cells to store data for logic gate operations. Therefore, it is not uncommon to use logic processes to manufacture memory cells embedded in ASICs.

[0035] Two common types of memory are Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). A single DRAM cell can use as few as one transistor and one capacitor ("1T1C" configuration), while a single SRAM cell can use more than one transistor, such as six, eight, or ten. Because the technological trend is to squeeze as many transistors as possible into the same amount of substrate area in an ASIC, DRAM can have an advantage over SRAM in terms of cell size.

[0036] The transistors (often called "access transistors") embedded in the 1T1C DRAM cell of the ASIC can still be manufactured using logic processes that are rapidly evolving to continuously reduce the minimum usable transistor size and increase the number of transistors that can be accommodated in the same die size.

[0037] However, because DRAM access transistors are formed using the FEOL process, these transistors may compete with transistors in logic circuits for the same semiconductor substrate area. Therefore, it would be advantageous to provide transistor structures suitable for use as DRAM access transistors placed on a semiconductor substrate. That is, it would be advantageous to provide transistor structures that can be fabricated using steps and processes available in the BEOL process.

[0038] It is also advantageous to keep gate-induced drain leakage (GIDL) and other types of drain leakage in such transistor structures at relatively low levels to reduce power consumption.

[0039] Providing transistor structures with reduced coverage areas would also be advantageous.

[0040] Providing a transistor structure whose performance remains stable over a wide operating temperature range would also be advantageous.

[0041] The subject matter of the invention will now be explained in more detail with reference to the accompanying drawings.

[0042] Figures 1A to 1D Several schematic diagrams of an exemplary transistor structure 1 according to some embodiments of the present invention are shown. Figure 1A A three-dimensional view is shown. Figure 1B A cross-sectional view along cutting line 1B-1B is shown. Figure 1C A top view along the cutting line 1C-1C is shown. Figure 1D A three-dimensional view along the cutting line 1B-1B is shown.

[0043] exist Figure 1B cross-sectional view and Figure 1C The top view uses cross-sectional lines to better illustrate some, but not all, components of transistor structure 1. Figure 1A Section lines are not used in the 3D drawing to avoid visual clutter. Figure 1D In the cross-sectional view of some components, section lines are used on the sides, but not on the other sides, to achieve optimal clarity. The fact that some components are not represented using section line patterns does not necessarily mean that they share any relationship. Moreover, the absence of section line patterns in a component does not necessarily mean that it is empty.

[0044] The transistor structure 1 includes a gate region 10, source / drain regions 12a and 12b, source / drain regions 14a and 14b, channel regions 16a and 16b, and gate dielectric regions 18a and 18b.

[0045] The gate region 10 extends substantially in the Z direction, such as Figure 1B As shown. The gate region 10 may also extend substantially in another direction, such as the Y direction, as shown. Figure 1CAs shown in the diagram. Gate dielectric region 18a is located between gate region 10 and channel region 16a. Gate dielectric region 18b is located between gate region 10 and channel region 16b. Gate dielectric regions 18a and 18b can prevent conductive connection between gate region 10 and channel regions 16a and 16b, respectively.

[0046] Source / drain regions 12a and 14a are in contact with channel region 16a. Depending on the voltage applied during operation, one of the source / drain regions 12a and 14a can become the source region, and the other can become the drain region. If a sufficient voltage is applied to the gate region 10, a current channel can be established in the channel region 16a between the source / drain regions 12a and 14a. Current can flow substantially in the current channel of channel region 16a in the Z direction.

[0047] Similarly, if a sufficient voltage is applied to the gate region 10, a current channel can be established in the channel region 16b between the source / drain regions 12b and 14b.

[0048] Advantageously, forming the transistor channel primarily in the Z direction, rather than in the X or Y direction, reduces the coverage area of ​​the transistor structure 1 in the XY plane. This allows for the placement of more transistor structures within the same unit area in the XY plane. This can also help save substrate space.

[0049] Advantageously, gate region 10 can be shared by two channel regions 16a and 16b (e.g., by two transistors). This helps to reduce the XY coverage area of ​​each transistor.

[0050] like Figure 1B As shown, gate region 10 substantially covers the entire channel regions 16a and 16b. That is, gate region 10 can cover the entire length of the current channel. Therefore, gate region 10 can provide improved control over the current channel formed in channel regions 16a and 16b. In other words, the spatial relationship between gate region 10 and channel regions 16a and 16b can help reduce or eliminate poorly controlled or uncontrolled areas in channel regions 16a and 16b. Improved control can help reduce unwanted current leakage. Improved control can help improve the transistor's on / off ratio.

[0051] The dimensions and shapes of gate region 10, source / drain regions 12a, 12b, 14a and 14b, channel regions 16a and 16b, and gate dielectric regions 18a and 18b are not limited to those of other regions. Figures 1A to 1DThose shown in the diagram. These dimensions and shapes can be adjusted. For example, while the source / drain regions 12a, 12b, 14a, and 14b are shown as having a rectangular shape in the XY plane, other shapes are also possible, such as circular or elliptical.

[0052] like Figure 1B As shown, source / drain regions 12a and 12b can extend in the +Z direction from adjacent channel regions 16a and 16b to the outer surfaces perpendicularly across channel regions 16a and 16b. In other words, the top surfaces of source / drain regions 12a and 12b may not be coplanar with channel regions 16a and 16b.

[0053] like Figure 1B As shown, source / drain regions 14a and 14b can extend in the -Z direction from adjacent channel regions 16a and 16b to the outer surfaces perpendicularly across channel regions 16a and 16b. In other words, the bottom surfaces of source / drain regions 14a and 14b may not be coplanar with channel regions 16a and 16b.

[0054] Although the channel region 16a shown has substantially the same length in the Z direction as the gate dielectric region 18a, other relative lengths are also possible. Similarly, substantially identical Z lengths between the channel region 16b and the gate dielectric region 18b are also exemplary.

[0055] The transistor structure 1 may also include an etch stop layer 30, dielectric regions 32a and 32b, dielectric regions 34a and 34b, dielectric layer 36, dielectric regions 50a and 50b, and dielectric regions 52a and 52b.

[0056] Dielectric regions 32a and 32b may be part of a dielectric layer. Dielectric regions 32a and 32b may provide electrical isolation between circuit elements on different sides of dielectric regions 32a and 32b. For example, dielectric regions 32a and 32b may isolate source / drain regions 14a and 14b from other circuit elements that may be present next to or around transistor structure 1.

[0057] Dielectric regions 34a and 34b may be part of a dielectric layer. Dielectric regions 34a and 34b may provide electrical isolation between circuit elements on different sides of dielectric regions 34a and 34b. For example, dielectric regions 34a and 34b may isolate channel regions 16a and 16b from other circuit elements that may be present next to or around transistor structure 1.

[0058] Dielectric layer 36 can provide electrical isolation for other circuit elements. For example, dielectric layer 36 can provide source / drain regions 12a and 12b that are isolated from each other.

[0059] Etching stop layer 30 can also be applied to, for example, stack 90 ( Figure 1D Electrical isolation is provided between the transistor structure 1 (as shown in the diagram) and the components below the etch stop layer 30. Furthermore, during the formation of the transistor structure 1, the etch stop layer 30 can prevent over-etching that could damage the underlying layers (e.g., conductive regions 40a and 40b and / or dielectric layer 42).

[0060] Similarly, dielectric regions 50a, 50b, 52a, and 52b may be part of one or more dielectric layers and provide electrical isolation. For example, dielectric regions 50a, 50b, 52a, and 52b may isolate source / drain regions 12a, 12b, 14a, and 14b from other circuit elements that may be present next to or around transistor structure 1, such as those close to transistor structure 1 in the Y direction.

[0061] In some embodiments, the semiconductor structure may include a plurality of transistor structures 1 arranged in an array. Dielectric regions 32a, 32b, 34a, 34b, 50a, 50b, 52a, and 52b effectively isolate the channel regions 16a and 16b of one transistor structure from other transistor structures. Furthermore, within transistor structure 1, channel regions 16a and 16b are also isolated from each other. Isolation of channel regions 16a and 16b can help reduce or eliminate poorly controlled or uncontrolled areas in the channel regions. Improved control can help reduce unwanted current leakage. Improved control can help improve the transistor's on / off ratio.

[0062] The transistor structure 1 may also include conductive regions 40a and 40b and a dielectric layer 42. Conductive regions 40a and 40b may be conductive contacts, such as vias or conductive interconnects. Conductive regions 40a and 40b can connect circuit elements (such as source / drain regions 14a and 14b) in the stack 90 to circuit elements in other layers of the integrated circuit.

[0063] Although Figures 1A to 1D It is not explicitly shown, but a semiconductor substrate may exist beneath transistor structure 1.

[0064] Transistor structure 1 is formed in the BEOL portion of an integrated circuit. Transistor structure 1 may be formed in or above a layer that is M1. In the exemplary description, the constituent parts of the stack 90 of transistor structure 1 are located within a metal layer, such as M1 and M2; however, this is not a limitation of the invention.

[0065] In an embodiment where transistor structure 1 is used as an access transistor for a DRAM cell, gate region 10 may be part of a word line. In an embodiment, conductive regions 40a and 40b may each be part of a bit line for a DRAM cell. In an embodiment, charge storage devices (such as capacitors in different layers) may be connected to the source / drain regions 12a and 12b of transistor structure 1.

[0066] Advantageously, in applications where transistor structure 1 is used as an access transistor for DRAM cells, the ability to place transistor structure 1 within the BEOL section allows for more space on the semiconductor substrate for logic circuitry. This capability also enables under-array CMOS (CuA) integration, where more logic circuitry fabricated in the FEOL section can be placed beneath a memory array fabricated in the BEOL section.

[0067] Advantageously, DRAM implemented using transistor structure 1 can achieve a unit cell area that is competitive with other types of memory (such as SRAM) in more advanced technology nodes.

[0068] Advantageously, because the channel regions 16a and 16b of transistor structure 1 have improved isolation from other circuit elements, DRAM with access transistors implemented using transistor structure 1 may be less susceptible to or even immune to line hammer attacks.

[0069] The components of transistor structure 1 may include or be made of a variety of materials.

[0070] Gate region 10 may include titanium nitride (TiN), tungsten (W), molybdenum (Mo), other suitable materials, compounds and / or alloys thereof, and any suitable combinations thereof. These materials can reduce the temperature used to fabricate gate region 10. These materials can be used in processes (e.g., deposition) compatible with BEOL processing to fabricate gate region 10.

[0071] The source / drain regions 12a, 12b, 14a, and 14b may comprise W, copper (Cu), TiN, Mo, ruthenium (Ru), other suitable materials, their compounds and / or alloys, and any suitable combinations thereof. These materials can reduce the temperature required to fabricate the source / drain regions 12a, 12b, 14a, and 14b (e.g., deposition) compared to other methods of fabricating source / drain regions (such as ion implantation). The processes used to fabricate the source / drain regions 12a, 12b, 14a, and 14b using these materials are compatible with BEOL processing.

[0072] Channel regions 16a and 16b may comprise one or more oxide semiconductor materials. Channel regions 16a and 16b may comprise: indium tin oxide (ITO); indium tungsten oxide (IWO); indium gallium zinc oxide (IGZO); titanium oxide (TiO); I x G y Z z MO, wherein M includes at least one of Ti, aluminum (Al), cerium (Ce) or tin (Sn), wherein x, y, and z are each greater than 0 and less than 1; compounds thereof; and any suitable combination thereof. Oxide semiconductor materials can be formed as single-layer or multi-layer structures.

[0073] The aforementioned materials, which are suitable for channel regions 16a and 16b, can be used in processes (e.g., deposition) compatible with BEOL processing for manufacturing channel regions 16a and 16b. The temperatures used to manufacture channel regions made of these oxide semiconductor materials can be low enough to make them compatible with BEOL processing.

[0074] The choice of materials for the gate region 10, source / drain regions 12a, 12b, 14a and 14b, and channel regions 16a and 16b allows for transistor formation without doping or implantation, thereby achieving a reduced process temperature.

[0075] Gate dielectric regions 18a and 18b may comprise oxides and / or high-k materials. Gate dielectric regions 18a and 18b may comprise AlO. x HfO x HfLaO, HfSiO, LaO, other suitable materials and their compounds, and any suitable combinations thereof.

[0076] In some embodiments, the surfaces of the channel regions 16a and 16b facing the gate dielectric regions 18a and 18b can be treated with a surface treatment configured to improve material stability. This treatment can improve the transistor's on / off ratio. A ratio of less than 10 can be achieved over a certain temperature range. -15 The leakage current of A, and this range can be as high as about 200°C. Surface treatments can include oxygen or N2O annealing, treatment using fluorine (Cl) doping, or oxygen plasma treatment. The temperature range for these treatments can be from room temperature (plasma) to about 400°C, which is within the BEOL thermal budget limit temperature.

[0077] Annealing may be performed during the fabrication of transistor structure 1. An exemplary upper temperature limit is approximately 400°C, approximately 500°C, or other similar values.

[0078] Because the gate region 10, source / drain regions 12a, 12b, 14a and 14b, channel regions 16a and 16b, and gate dielectric regions 18a and 18b of transistor structure 1 can be formed by deposition, a transistor thus manufactured can be called a thin-film transistor (TFT). However, the expression "thin" should not be interpreted as limiting the size or thickness of any of the constituent components of such a transistor.

[0079] Figures 2A to 25B A semiconductor structure is shown to illustrate exemplary steps for manufacturing a transistor structure according to some embodiments of the present invention. Unless otherwise stated, Figures 2A to 25B In this diagram, figures ending in "A" represent 3D views, and figures ending in "B" represent cross-sectional views along the cutting line shown in the corresponding figure ending in "A". Figures ending in "C" (if present) represent another figure.

[0080] refer to Figure 2A and Figure 2B An etch stop layer 30x may be fabricated (e.g., deposited) on dielectric layer 42. Conductive regions 40a and 40b may be present or embedded in dielectric layer 42. Dielectric layer 42 may be a metal layer, such as M1. Etch stop layer 30x may be located in a different metal layer, such as M2.

[0081] refer to Figure 3A and Figure 3B One or more portions of the etch stop layer 30x can be removed (by means of etching) to become the etch stop layer 30. The etch stop layer 30 may include recesses 60a and 60b. Recesses 60a and 60b may expose conductive regions 40a and 40b in the dielectric layer 42.

[0082] refer to Figure 4A and Figure 4B A layer of source / drain material 14x may be formed (e.g., deposited) on or above the etch stop layer 30. The source / drain material 14x may be filled with... Figure 3A and Figure 3B The grooves 60a and 60b are shown. The source / drain material 14x may include W, Cu, TiN, Mo, Ru, other suitable materials, their compounds and / or alloys, and any suitable combination thereof.

[0083] refer to Figure 5A and Figure 5B A portion of the source / drain material 14x can be removed (e.g., by a planarization technique such as chemical mechanical polishing (CMP)) to expose the etch stop layer 30. Removal can also create separated source / drain regions 14a1 and 14b1. A portion of the etch stop layer 30 may or may not be removed.

[0084] refer to Figure 6A and Figure 6B A layer of dielectric material 32x may be formed (e.g., deposited) on or above the etch stop layer 30 and the source / drain regions 14a1 and 14b1. The dielectric material 32x may provide electrical isolation and, for example, moisture isolation.

[0085] refer to Figure 7A and Figure 7B One or more portions of dielectric material 32x can be removed (by means of etching) to form dielectric layer 32y. Dielectric layer 32y may include recesses 61a and 61b. Recesses 61a and 61b may expose source / drain regions 14a1 and 14b1. Recesses 61a and 61b may or may not expose etch stop layer 30.

[0086] refer to Figure 8A and Figure 8B A layer of source / drain material 14y can be formed (e.g., deposited) on or above the dielectric layer 32y. The source / drain material 14y can be filled with... Figure 7A and Figure 7B The grooves 61a and 61b are shown. The source / drain material 14y may include W, Cu, TiN, Mo, Ru, other suitable materials, their compounds and / or alloys, and any suitable combination thereof. The source / drain materials 14x and 14y may be different or substantially identical.

[0087] refer to Figure 9A and Figure 9B A portion of the source / drain material 14y can be removed (e.g., by CMP) to expose the dielectric layer 32y. The deposition and subsequent partial removal of the source / drain material 14y can create separated source / drain regions 14a and 14b. The source / drain materials 14x and 14y can be different from each other; in this case, each of the source / drain regions 14a and 14b can include two portions, one of which is... Figure 7A and Figure 7B The source / drain regions 14a1 and 14b1 are shown.

[0088] Depending on the hardness of the different materials being polished, the polished surface is not necessarily perfectly flat. For example, slight grooves or protrusions may exist in the source / drain regions, depending on whether the source / drain material is softer or harder than the surrounding dielectric material.

[0089] refer to Figure 10A and Figure 10BA layer of dielectric material 34x may be formed (e.g., deposited) on or above the dielectric layer 32y and the source / drain regions 14a and 14b. The dielectric material 34x may provide electrical isolation and, for example, moisture isolation. The thickness of the dielectric material 34x may be chosen to be any suitable value. As previously mentioned in this invention, components are not necessarily drawn to scale. For clarity of discussion, some of the components shown may be scaled.

[0090] refer to Figure 11A and Figure 11B One or more portions of dielectric material 34x can be removed (by means of etching) to form dielectric regions 34a and 34b. Trench 62 is shown to exist between dielectric regions 34a and 34b. Trench 62 may expose etch stop layer 30 and source / drain regions 14a and 14b.

[0091] like Figure 11B As shown, trench 62 has a width X and a height H. The width X can be between about 20 nanometers (nm) and about 90 nm, between about 30 nm and about 80 nm, between about 40 nm and about 70 nm, between about 30 nm and about 60 nm, or any other suitable value. The height H can be less than about 100 nm, between about 10 nm and about 90 nm, between about 20 nm and about 80 nm, between about 30 nm and about 70 nm, between about 40 nm and about 60 nm, or any other suitable value. The aspect ratio of trench 62 can be any suitable value. In an embodiment, the aspect ratio of trench 62 can be about 1.

[0092] refer to Figure 12A and Figure 12B A layer of channel material 16X may be formed (e.g., deposited) in or on trench 62 and on etch stop layer 30. Channel material 16X may be formed to initially contact source / drain regions 14a and 14b. Channel material 16X may comprise one or more oxide semiconductor materials. Oxide semiconductor materials may include ITO; IWO; IGZO; TiO; I x G y Z zMO, where M includes at least one of Ti, Al, Ce, or Sn, where x, y, and z are each greater than 0 and less than 1; compounds thereof; and any suitable combination thereof. The channel material 16X can be formed by atomic layer deposition (ALD). ALD helps achieve a high level of conformality over 3D structures while maintaining the quality of the material, i.e., its composition. The thickness of the channel material 16X can be between about 3 nm and about 20 nm, between about 5 nm and about 15 nm, between about 7 nm and about 12 nm, or in other suitable ranges. Reducing the thickness of the channel material 16X can help shrink transistor structures including the channel material 16X and thus contribute to higher transistor densities.

[0093] refer to Figure 13A and Figure 13B One or more portions of the channel material 16X can be removed (e.g., by etching) to form channel regions 16a and 16b and expose dielectric regions 34a and 34b. Removal can be performed by anisotropic etching. In an embodiment, portions of the channel material 16X not located within the trench 62 can be removed.

[0094] The etch stop layer 30 can be resistant to the etchant used to etch the channel material 16X, thereby protecting the area beneath the etch stop layer 30 (such as the dielectric layer 42), which may not necessarily be resistant to the etchant used to etch the channel material 16X. The etch stop layer 30 can increase the flexibility in selecting the etchant to etch the channel material 16X.

[0095] In one embodiment, anisotropic etching of the channel material 16X can cause the corner 16r of the channel region 16a to become a curve. The curved corner can also appear in the channel region 16b.

[0096] In this embodiment, the portion of the channel material 16X located at the bottom of the trench 62 is removed, but the portion of the XY surfaces covering the dielectric regions 34a and 34b is not removed. The unremoved portion can then be removed by other measures such as planarization.

[0097] refer to Figure 14A and Figure 14B A layer of gate dielectric material 18X may be formed (e.g., deposited) in trench 62, on or above etch stop layer 30, and / or formed to cover channel regions 16a and 16b. Gate dielectric material 18X may be formed to initiate contact with channel regions 16a and 16b. Gate dielectric material 18X may include oxides and / or high-k materials. Gate dielectric material 18X may include AlO2. x HfO xHfLaO, HfSiO, LaO, other suitable materials and their compounds, and any suitable combinations thereof.

[0098] In one embodiment, the gate dielectric material 18X is formed immediately after the channel regions 16a and 16b are formed. In another embodiment, the surfaces of the channel regions 16a and 16b facing the gate dielectric material 18X may be treated. Surface treatment may include oxygen or N₂O annealing, treatment using fluorine (Cl) doping, or oxygen plasma treatment. The temperature range for these treatments can range from room temperature (plasma) to approximately 400°C, which is within the BEOL thermal budget limit temperature.

[0099] refer to Figure 15A and Figure 15B One or more portions of the gate dielectric material 18X can be removed (e.g., by etching) to become gate dielectric regions 18a and 18b and expose dielectric regions 34a and 34b and / or etch stop layer 30. Removal can be performed by anisotropic etching. In an embodiment, portions of the gate dielectric material 18X not located within trench 62 can be removed.

[0100] refer to Figure 16A , Figure 16B and Figure 16C One or more portions of dielectric regions 34a and 34b, dielectric regions 32a and 32b, channel regions 16a and 16b, and gate dielectric regions 18a and 18b can be removed (e.g., by etching). Thus, a recess 63 can be formed. Figure 16C As exemplarily shown in the side view, the groove 63 can be considered as the result of two “slicing” cuts.

[0101] If formed Figures 2A to 15B In the intermediate structure array shown, the groove 63 can also be considered as a trench between these structures. In such an embodiment, the groove 63 can reserve space for the future introduction of dielectric material. Such a dielectric material can improve the isolation between channel regions 16a and 16b and channel regions in adjacent transistor structures in the array.

[0102] refer to Figure 17A , Figure 17B and Figure 17C A layer of dielectric material 50x can be formed (e.g., deposited). The dielectric material 50x can cover the etch stop layer 30, dielectric regions 32a and 32b, dielectric regions 34a and 34b, channel regions 16a and 16b, and / or gate dielectric regions 18a and 18b. The dielectric material 50x can fill trench 62. Figure 17C This is an exemplary perspective view along cut lines 17B-17B to better illustrate the possible location of dielectric material 50x and its spatial relationship with other structural components.

[0103] refer to Figure 18A , Figure 18B and Figure 18C A portion of the dielectric material 50x (e.g., by CMP) can be removed to expose dielectric regions 32a and 32b, channel regions 16a and 16b, and gate dielectric regions 18a and 18b. The exposed portions of the structure may also have been removed by a CMP process. Figure 18C This is an exemplary perspective view along cutting lines 18B-18B to better illustrate the result of this removal step.

[0104] refer to Figure 19A and Figure 19B One or more portions of the dielectric material 50x can be removed (by means of etching) to form a trench 64. The trench 64 can expose the etch stop layer 30 and the gate dielectric regions 18a and 18b.

[0105] refer to Figure 20A and Figure 20B A 10x layer of gate material can be formed (e.g., deposited) to fill the gap. Figure 19A and Figure 19B The trench 64 shown is an example. The gate material 10x may include TiN, W, Mo, other suitable materials, their compounds and / or alloys, and any suitable combination thereof.

[0106] refer to Figure 21A and Figure 21B A portion of the gate material 10x can be removed (e.g., by CMP) to expose dielectric regions 34a, 34b, 50a, 50b, 52a and 52b, channel regions 16a and 16b, and gate dielectric regions 18a and 18b. Removal of the gate material 10x creates gate region 10.

[0107] refer to Figure 22A and Figure 22B A layer of dielectric material 36x may be formed (e.g., deposited) on or above the gate region 10, channel regions 16a and 16b, gate dielectric regions 18a and 18b and / or dielectric regions 34a and 34b. The dielectric material 36x may provide electrical isolation and, for example, moisture isolation.

[0108] refer to Figure 23A and Figure 23B One or more portions of dielectric material 36x can be removed (e.g., by etching) to become dielectric layer 36. One or more portions of dielectric regions 34a and 34b can also be removed. This allows the formation of grooves 65a and 65b. Grooves 65a and 65b can expose channel regions 16a and 16b.

[0109] refer to Figure 24A and Figure 24BA layer of source / drain material 12x may be formed (e.g., deposited) on or above dielectric layer 36. The source / drain material 12x may be filled with… Figure 23A and Figure 23B The grooves 65a and 65b are shown. The source / drain material 12x may include W, Cu, TiN, Mo, Ru, other suitable materials, their compounds and / or alloys, and any suitable combination thereof. The source / drain material 12x may begin to contact the channel regions 16a and 16b.

[0110] refer to Figure 25A and Figure 25B A portion of the source / drain material 12x can be removed (e.g., by CMP) to expose the dielectric layer 36. The deposition of the source / drain material 12x and subsequent partial removal can create separated source / drain regions 12a and 12b. Figure 25A It shows the relationship with Figure 1A The transistor structure shown is exactly the same as transistor structure 1, and is provided for the reader's convenience.

[0111] Figure 26A and Figure 26B Exemplary dimensions of various structural components of a transistor structure according to some embodiments of the present invention are shown. The dimensions shown herein may be exemplary minimum dimensions.

[0112] In some embodiments, gate region 10 may have a first size 2602 (e.g., a first width). In some embodiments, the first size 2602 may have an exemplary minimum size of about 30 nm in the X direction and / or about 30 nm in the Z direction. In other embodiments, the first size 2602 may be less than 30 nm in the X direction and / or Z direction. In some embodiments, source / drain regions 12a, 12b, 14a, and 14b may have a second size 2604 (e.g., a second width) in the X direction, a third size 2606 in the Y direction, and a fourth size 2612 in the Z direction. In some embodiments, the second size 2604 may have an exemplary minimum size of about 15 nm in the X direction, and the third size 2606 may have an exemplary minimum size of about 20 nm in the Y direction, and / or the fourth size 2612 may have an exemplary minimum size of about 10 nm in the Z direction. In other embodiments, the second size 2604, the third size 2606, and the fourth size 2612 may be smaller than these sizes. In some embodiments, channel regions 16a and 16b may have an exemplary minimum size of about 5 nm in the X direction, about 20 nm in the Y direction, and / or about 30 nm in the Z direction. In other embodiments, the exemplary minimum size of channel regions 16a and 16b may be smaller than these sizes. In some embodiments, gate dielectric regions 18a and 18b may have an exemplary minimum size of about 5 nm in the X direction, about 20 nm in the Y direction, and / or about 30 nm in the Z direction. In other embodiments, the exemplary minimum size of gate dielectric regions 18a and 18b may be smaller than these sizes. In some embodiments, the channel length 2610 of the transistor structure may be about 10 nm. In some embodiments, the channel width of the transistor structure may have an exemplary minimum size of about 20 nm. In other embodiments, the exemplary minimum sizes of the channel length and channel width may be smaller than these sizes. In some embodiments, dielectric regions 50a, 50b, 52a, and 52b may have an exemplary minimum size 2608 of about 5 nm in the Y direction. In some embodiments, each of the dielectric regions 32a, 32b, 34a, 34b and the dielectric layer 36 may have a minimum dimension of about 5 nm in at least one of the X, Y, and Z directions. For example, in some embodiments, dielectric region 32b may have a minimum dimension of about 5 nm in the X direction. In other embodiments, exemplary minimum dimensions of dielectric regions 32a, 32b, 34a, 34b and the dielectric layer 36 may be smaller than these dimensions.

[0113] Figures 2A to 26BThe exemplary process shown may involve less etching than the comparative embodiments. For example, during the formation of the source / drain regions, grooves and / or trenches are first etched, and then the source / drain regions are formed by deposition. The exemplary process flow of the present invention can reduce the chance of damaging the source / drain regions when etching other structures.

[0114] Fewer etching steps can also be advantageous in BEOL processing, as etching of metals commonly found in BEOL is often more difficult to control.

[0115] The exemplary process flow of this invention can achieve the formation of transistor structures without using doping or implantation steps. This helps reduce the maximum temperature in the process flow, as annealing after doping and implantation may require higher temperatures. In some embodiments, the maximum temperature in the process flow is about 400 degrees Celsius. This temperature range allows the use of oxide semiconductor materials such as IGZO.

[0116] Figure 27A A top view of an exemplary transistor structure array according to some embodiments of the present invention is shown. The array may be a memory array of paired transistors. The transistor pairs may share a word line WL. Each transistor has two source / drain regions S / D, one shown in the top view and the other shown below. Bit lines BL may be provided in the array. Each bit line may be connected to more than one transistor.

[0117] Source / drain region S / D at Figure 27A The figure is shown as having a circular shape, but this is not a limitation of the invention. Other shapes, such as rectangular shapes, are also possible.

[0118] The various parts of the transistor structure, the word lines WL and bit lines BL of the array, can be arranged in different layers. In a top view, the word lines WL and bit lines BL can be shown as intersecting in a non-perpendicular manner.

[0119] Figure 27B A schematic diagram of a memory array according to some embodiments of the present invention is shown.

[0120] Figure 27B (In section (a)) four transistor pairs 4 are shown, each comprising transistors 4a and 4b. Word line 46 may be connected to the gate terminals of transistors 4a and 4b. Bit line 44 may be connected to the source / drain terminals of transistors 4a and 4b. Word line 46 and bit line 44 may be arranged in different layers. In a plan view, word line 46 and bit line 44 may intersect each other at an angle not of 90 degrees. In some embodiments, the arrangement of transistor pair 4 and word line 46 conforms to the main axis of one layer; while the arrangement of bit line 44 (in another layer) does not conform to the main axis of one layer.

[0121] Figure 27B An embodiment of bit line 44a is shown in section (b). The layout of bit line 44a can also be made of several straight line segments with 90-degree turns. This can help reduce the lithographic challenges in manufacturing tilted layout structures.

[0122] Figure 27C The following are some embodiments of the invention shown. Figure 27A The diagram shows a cross-sectional view of an exemplary memory cell structure with cut lines 27C-27C. A transistor structure similar to transistor structure 1 described above can be arranged in layer metal N. The transistor structure can be connected to layer metal N+1 via vias 21c and 21d, where capacitor structures 70a and 70b can be present. An air gap 71 can exist between capacitor structures 70a and 70b. The transistor structure can be connected to layer metal N-1 via vias 21a and 21b, where conductive contacts 40c and 40d can be present.

[0123] In some embodiments, Figure 27C The memory cell structure shown is a DRAM cell structure. The transistor structure in layer N can be an access transistor. Conductive contacts 40c and 40d can form bit lines. The gate region of the transistor structure can form a word line. Capacitor structures 70a and 70b can form an information storage device.

[0124] Figure 27D A cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present invention is shown.

[0125] The semiconductor structure is shown as including a memory array region 2a and a logic region 2b. The memory array region 2a may include, for example, a memory array region 2a. Figure 27C The memory cells shown are those shown. Logic region 2b may include conductive interconnects and vias 72a, 72b, 72c, 72d, and 72e. The semiconductor structure shown may be located within the BEOL portion of the die. The semiconductor structure shown indicates that the transistor structure provided in this invention can be embedded in the BEOL layer and is adjacent to and / or surrounded by conductive interconnects in logic region 2b of the BEOL layer.

[0126] Figure 28A and Figure 28B Exemplary transistor structures according to some embodiments of the present invention are shown.

[0127] Figure 28A The transistor structure shown is similar to Figure 1AThe transistor structure shown is different in that it has a dielectric region 38 for the two transistors and two separate gate regions 10a and 10b. The dielectric region 38 may contact the dielectric layer 36 and may be made of similar or different materials. The dielectric region 38 helps to provide additional isolation for the channel regions 16a and 16b.

[0128] Figure 28B The transistor structure shown is similar to Figure 28A The transistor structure shown is different from the one described above. Differences include the presence of additional control regions 19a and 19b, and additional gate dielectric regions 18a1 and 18b1. The materials of the additional control regions 19a and 19b can be similar to those of the gate region 10 and / or the source / drain regions 12a, 12b, 14a, and 14b. The materials of the additional gate dielectric regions 18a1 and 18b1 can be similar to those of the gate dielectric regions 18a and 18b. The additional control regions 19a and 19b can help reduce the drain current-gate voltage profile (i.e., Id) of the transistor structure. d -V g The amount of swing in the curve can help increase the switching ratio. By adding additional control regions 19a and 19b, the electric field generated by, for example, gate regions 10a and 10b can help improve transistor performance.

[0129] Figure 29 A perspective view of an exemplary semiconductor structure 3 according to some embodiments of the present invention is shown.

[0130] Semiconductor structure 3 is shown as including array 3a, which may include several transistor structures (four in this example). The boundaries between transistor structures 1a, 1b, 1c, and 1d are shown as dashed lines, but the transistor structures may actually be continuous. Array 3a can be connected to other circuit components in other layers, such as integrated circuits, via conductive paths 22 and 24. Conductive paths 22 and 24 may be vias. Via 24 can connect array 3a to layer 3b having bit line 44.

[0131] Figure 30A and Figure 30B A flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present invention is shown.

[0132] In step S3001, a first source / drain region can be formed. In step S3003, a first dielectric layer can be formed over the first source / drain region. In step S3005, a first groove can be formed by removing a portion of the first dielectric layer that does not substantially cover the first source / drain region. In step S3007, a channel region can be formed in the first groove. In step S3009, a gate dielectric region can be formed in the first groove, and the gate dielectric region can contact the channel region. In step S3011, the first groove can be filled with a second dielectric material.

[0133] In step S3013, a second trench can be formed by removing a portion of the second dielectric material and exposing the gate dielectric region. In step S3015, the second trench can be filled to form the gate region. In step S3017, a second dielectric layer can be formed over the first dielectric layer and the gate region. In step S3019, portions of the second dielectric layer and the first dielectric layer can be removed to expose the channel region. In step S3021, a second source / drain region in contact with the channel region can be formed.

[0134] This invention discloses an improved transistor structure. Due to its materials and novel process flow, the transistor structure is fully compatible with BEOL processing. The transistor structure allows DRAM cells to be fully embedded within the BEOL layer. The vertical shape reduces the coverage area. Improved channel isolation reduces leakage and contributes to safety. The improved process flow involves less etching and can contribute to higher yields.

[0135] Any embodiment described herein may be used alone or in any combination. One or more embodiments included within this specification may also include embodiments that are only partially mentioned or implied in this brief overview or summary, or that are not mentioned or implied at all. While the various embodiments may arise from various deficiencies in the prior art, which may be discussed or implied in one or more places in the specification, the embodiments do not necessarily solve any of these deficiencies. In other words, different embodiments may solve different deficiencies that may be discussed in this specification. Some embodiments may only partially solve some or only one of the deficiencies that may be discussed in the specification, and some embodiments may not solve any of these deficiencies.

[0136] It should be understood that not all advantages need to be discussed herein, no particular advantage is necessary for all embodiments or instances, and other embodiments or instances may provide different advantages.

[0137] According to aspects of the present invention, a semiconductor structure is provided. The semiconductor structure may include a transistor structure, which may include: a gate region disposed above an upper surface of a substrate, wherein the gate region extends substantially in a first direction perpendicular to the upper surface of the substrate; a first source / drain region located above the upper surface of the substrate; a second source / drain region located above the upper surface of the substrate; and a channel region extending perpendicularly in the first direction between the first source / drain region and the second source / drain region, wherein the channel region comprises an oxide semiconductor material. Along the first direction, the gate region covers the sidewalls of the channel region.

[0138] In an embodiment, the first source / drain region may include at least one of tungsten (W), copper (Cu), titanium nitride (TiN), molybdenum (Mo), or ruthenium (Ru). In an embodiment, the second source / drain region may include at least one of W, Cu, TiN, Mo, or Ru. In an embodiment, the semiconductor structure includes a capacitor electrically connected to the first source / drain region or the second source / drain region; in such an embodiment, the transistor structure may be located in an Mx layer, where x is an integer greater than or equal to 1, and the capacitor may be located in a My layer, where y is an integer greater than or equal to 1, wherein y may be different from x. In an embodiment, the transistor structure is a first transistor structure, and the semiconductor structure may include a second transistor structure. The second transistor structure may include: a gate region extending substantially in a first direction; a channel region extending substantially in the first direction, wherein the channel region includes an oxide semiconductor material; a first source / drain region; and a second source / drain region. Along the first direction, the gate region may substantially cover the entire channel region. The gate region of the first transistor structure may be electrically connected to the gate region of the second transistor structure. In an embodiment, the transistor structure may include a word line, and the gate region of the first transistor structure and the gate region of the second transistor structure may be part of the word line. In an embodiment, the semiconductor structure may include a bit line, and the word line may extend in a second direction, and the bit line may extend in a third direction, and the second direction may be substantially non-perpendicular to the third direction. In an embodiment, at least one of the gate region, the first source / drain region, and the second source / drain region may be formed by deposition.

[0139] According to aspects of the present invention, a semiconductor structure is provided. The semiconductor structure may include a first transistor structure and a second transistor structure. Each transistor may include: a gate region disposed above an upper surface of a substrate and extending substantially in a first direction perpendicular to the upper surface of the substrate; a first source / drain region; a second source / drain region; and a channel region extending substantially in the first direction between the first source / drain region and the second source / drain region, wherein the channel region comprises an oxide semiconductor material. Along the first direction, the gate region of the first transistor structure substantially covers a first sidewall of the channel region of the first transistor structure. Along the first direction, the gate region of the second transistor structure substantially covers a second sidewall of the channel region of the second transistor structure. The gate region of the first transistor structure may be electrically isolated from the gate region of the second transistor structure. The gate region of the first transistor structure and the gate region of the second transistor structure may be located between the first source / drain region of the first transistor structure and the first source / drain region of the second transistor structure.

[0140] In one embodiment, the gate region of the first transistor structure and the gate region of the second transistor structure may each include a first end and a second end, and the first end of the gate region of the first transistor structure and the first end of the gate region of the second transistor structure may be substantially coplanar in a plane substantially perpendicular to the first direction. In another embodiment, the second end of the gate region of the first transistor structure and the second end of the gate region of the second transistor structure may be substantially coplanar in a plane substantially perpendicular to the first direction.

[0141] According to an aspect of the present invention, a method for manufacturing a semiconductor structure is provided. The method may include: forming a first source / drain region; forming a first dielectric layer over the first source / drain region; forming a first trench by removing a portion of the first dielectric layer that substantially does not cover the first source / drain region; forming a channel region in the first trench; forming a gate dielectric region in the first trench that contacts the channel region; filling the first trench with a second dielectric material; forming a second trench by removing a portion of the second dielectric material and exposing the gate dielectric region; filling the second trench to form a gate region; forming a second dielectric layer over the first dielectric layer and the gate region; removing a portion of the second dielectric layer and the first dielectric layer to expose the channel region; and forming a second source / drain region that contacts the channel region.

[0142] In an embodiment, forming a first source / drain region may include depositing metal or a metal compound. In an embodiment, forming a second source / drain region may include depositing metal or a metal compound. In an embodiment, the method may include forming an etch stop layer. In an embodiment, forming the first source / drain region may include: forming a trench in the etch stop layer; and depositing source / drain material in the trench of the etch stop layer. In an embodiment, the method may include removing a portion of the gate dielectric region, the channel region, and the first dielectric layer to expose the etch stop layer.

[0143] Some embodiments of this application provide a semiconductor structure, including: a transistor structure comprising: a gate region disposed above an upper surface of a substrate, wherein the gate region extends substantially in a first direction perpendicular to the upper surface of the substrate; a first source / drain region located above the upper surface of the substrate; a second source / drain region located above the upper surface of the substrate; and a channel region extending perpendicularly in the first direction between the first source / drain region and the second source / drain region, wherein the channel region comprises an oxide semiconductor material; wherein, along the first direction, the gate region covers the sidewalls of the channel region.

[0144] In some embodiments, the oxide semiconductor material includes indium tin oxide, indium tungsten oxide, indium gallium zinc oxide, titanium oxide, or I... x G y Z zAt least one of M, wherein M comprises at least one of titanium, aluminum, cerium, or tin, and wherein x, y, and z are each greater than 0 and less than 1. In some embodiments, the gate region comprises at least one of titanium nitride, tungsten, or molybdenum. In some embodiments, along the first direction, the first source / drain region is located between the substrate and the second source / drain region; the first source / drain region has a position closer to the bottom surface of the substrate than the bottom surface of the channel region. In some embodiments, along the first direction, the first source / drain region is located between the substrate and the second source / drain region; the second source / drain region extends along the first direction beyond the uppermost surface of the channel region. In some embodiments, the transistor structure is a first transistor structure, and the semiconductor structure further includes a second transistor structure, the second transistor structure including: a second gate region extending substantially in the first direction; a second channel region extending substantially in the first direction, wherein the second channel region includes an oxide semiconductor material; a third source / drain region; and a fourth source / drain region; wherein, along the first direction, the second gate region substantially covers the entire second channel region; and the gate region of the first transistor structure is electrically connected to the second gate region of the second transistor structure. In some embodiments, the semiconductor structure further includes: a word line, wherein the gate region of the first transistor structure and the second gate region of the second transistor structure are part of the word line. In some embodiments, the transistor structure further includes: an additional channel region extending substantially in the first direction, wherein the additional channel region comprises an oxide semiconductor material; a third source / drain region; and a fourth source / drain region; wherein, along the first direction, the gate region substantially covers the entire additional channel region; wherein the first source / drain region and the second source / drain region are in contact with the channel region; wherein the third source / drain region and the fourth source / drain region are in contact with the additional channel region. In some embodiments, the first source / drain region and the second source / drain region are located on a first side of the gate region, wherein the third source / drain region and the fourth source / drain region are located on opposite second sides of the gate region. In some embodiments, in a plan view, the first source / drain region and the second source / drain region are separated from the third source / drain region and the fourth source / drain region by the gate region. In some embodiments, the first source / drain region, the second source / drain region, the third source / drain region, and the fourth source / drain region form a transistor pair that shares the gate region.

[0145] Some other embodiments of this application provide a semiconductor structure, including: a first transistor structure and a second transistor structure, each including: a gate region disposed above an upper surface of a substrate and extending substantially in a first direction perpendicular to the upper surface of the substrate; a first source / drain region; a second source / drain region; and a channel region extending substantially in the first direction between the first source / drain region and the second source / drain region, wherein the channel region comprises an oxide semiconductor material; wherein, along the first direction, the gate region of the first transistor structure substantially covers a first sidewall of the channel region of the first transistor structure, wherein, along the first direction, the gate region of the second transistor structure substantially covers a second sidewall of the channel region of the second transistor structure, wherein the gate region of the first transistor structure is electrically isolated from the gate region of the second transistor structure; wherein the gate region of the first transistor structure and the gate region of the second transistor structure are located between the first source / drain region of the first transistor structure and the first source / drain region of the second transistor structure.

[0146] In some embodiments, the gate region of the first transistor structure and the gate region of the second transistor structure are located between the second source / drain region of the first transistor structure and the second source / drain region of the second transistor structure. In some embodiments, the gate region of the first transistor structure and the gate region of the second transistor structure have substantially the same length along the first direction.

[0147] Further embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: forming a first source / drain region; forming a first dielectric layer over the first source / drain region; forming a first trench by removing a portion of the first dielectric layer that substantially does not cover the first source / drain region; forming a channel region in the first trench; forming a gate dielectric region in the first trench that contacts the channel region; filling the first trench with a second dielectric material; forming a second trench by removing a portion of the second dielectric material and exposing the gate dielectric region; filling the second trench to form a gate region; forming a second dielectric layer over the first dielectric layer and the gate region; removing a portion of the second dielectric layer and the first dielectric layer to expose the channel region; and forming a second source / drain region that contacts the channel region.

[0148] In some embodiments, forming the channel region in the first groove includes depositing an oxide semiconductor material. In some embodiments, forming the channel region in the first groove includes anisotropically etching the oxide semiconductor material. In some embodiments, forming the gate dielectric region in contact with the channel region in the first groove includes depositing a gate dielectric material. In some embodiments, the gate dielectric material includes a high-k dielectric material. In some embodiments, forming the gate dielectric region in contact with the channel region in the first groove includes anisotropically etching the gate dielectric material.

[0149] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising: Transistor structure, including: A gate region is disposed above the upper surface of the substrate, wherein the gate region extends substantially in a first direction perpendicular to the upper surface of the substrate; The first source / drain region is located above the upper surface of the substrate; The second source / drain region is located above the upper surface of the substrate; and A channel region is laterally located between the outermost edge of the first source / drain region and the outermost outer wall of the gate region facing the channel region, wherein the channel region extends vertically in the first direction between the first source / drain region and the second source / drain region, wherein the channel region comprises an oxide semiconductor material; Wherein, along the first direction, the gate region covers the sidewall of the channel region.

2. The semiconductor structure according to claim 1, wherein, The oxide semiconductor material includes indium tin oxide, indium tungsten oxide, indium gallium zinc oxide, titanium oxide, or I. x G y Z z At least one of MO, wherein M includes at least one of titanium, aluminum, cerium or tin, and wherein x, y and z are each greater than 0 and less than 1.

3. The semiconductor structure according to claim 1, wherein, The gate region includes at least one of titanium nitride, tungsten, or molybdenum.

4. The semiconductor structure according to claim 1, wherein: Along the first direction, the first source / drain region is located between the substrate and the second source / drain region; The first source / drain region has a bottom surface closer to the bottom surface of the substrate than the bottom surface of the channel region.

5. The semiconductor structure according to claim 1, wherein: Along the first direction, the first source / drain region is located between the substrate and the second source / drain region; The second source / drain region extends along the first direction beyond the uppermost surface of the channel region.

6. The semiconductor structure according to claim 1, wherein: The transistor structure is a first transistor structure. The semiconductor structure further includes a second transistor structure, the second transistor structure comprising: The second gate region extends substantially in the first direction; The second channel region extends substantially in the first direction, wherein the second channel region comprises an oxide semiconductor material; Third source / drain region; and Fourth source / drain region; Wherein, along the first direction, the second gate region substantially covers the entire second channel region; and The gate region of the first transistor structure is electrically connected to the second gate region of the second transistor structure.

7. The semiconductor structure according to claim 6, further comprising: A word line, wherein the gate region of the first transistor structure and the second gate region of the second transistor structure are part of the word line.

8. The semiconductor structure according to claim 1, wherein, The transistor structure also includes: An additional channel region extends substantially in the first direction, wherein the additional channel region comprises an oxide semiconductor material; Third source / drain region; and Fourth source / drain region; Along the first direction, the gate region substantially covers the entire additional channel region; The first source / drain region and the second source / drain region are in contact with the channel region. The third source / drain region and the fourth source / drain region are in contact with the additional channel region.

9. The semiconductor structure according to claim 8, wherein, The first source / drain region and the second source / drain region are located on a first side of the gate region, wherein the third source / drain region and the fourth source / drain region are located on opposite second sides of the gate region.

10. The semiconductor structure according to claim 8, wherein, In the plan view, the first source / drain region and the second source / drain region are separated from the third source / drain region and the fourth source / drain region by the gate region.

11. The semiconductor structure according to claim 8, wherein, The first source / drain region, the second source / drain region, the third source / drain region, and the fourth source / drain region form a transistor pair that shares the gate region.

12. A semiconductor structure, comprising: The first transistor structure and the second transistor structure respectively include: A gate region is disposed above the upper surface of the substrate and extends substantially in a first direction perpendicular to the upper surface of the substrate; First source / drain region; Second source / drain region; and A channel region extends substantially in the first direction between the first source / drain region and the second source / drain region, wherein the channel region comprises an oxide semiconductor material; Wherein, along the first direction, the gate region of the first transistor structure substantially covers the first sidewall of the channel region of the first transistor structure. Wherein, along the first direction, the gate region of the second transistor structure substantially covers the second sidewall of the channel region of the second transistor structure. Wherein, the gate region of the first transistor structure is electrically isolated from the gate region of the second transistor structure; The gate region of the first transistor structure and the gate region of the second transistor structure are located between the first source / drain region of the first transistor structure and the first source / drain region of the second transistor structure.

13. The semiconductor structure according to claim 12, wherein, The gate region of the first transistor structure and the gate region of the second transistor structure are located between the second source / drain region of the first transistor structure and the second source / drain region of the second transistor structure.

14. The semiconductor structure according to claim 12, wherein, The gate region of the first transistor structure and the gate region of the second transistor structure have substantially the same length along the first direction.

15. A method for manufacturing a semiconductor structure, comprising: Forming the first source / drain region; A first dielectric layer is formed on the first source / drain region; The first groove is formed by removing a portion of the first dielectric layer that does not substantially cover the first source / drain region. A channel region is formed in the first groove; A gate dielectric region in contact with the channel region is formed in the first groove; The first groove is filled with a second dielectric material; The second groove is formed by removing a portion of the second dielectric material and exposing the gate dielectric region; Fill the second groove to form a gate region; A second dielectric layer is formed over the first dielectric layer and the gate region; Remove portions of the second dielectric layer and the first dielectric layer to expose the channel region; as well as A second source / drain region is formed in contact with the channel region, wherein the channel region is laterally located between the outermost edge of the first source / drain region and the outermost wall of the gate region facing the channel region.

16. The method according to claim 15, wherein, Forming the channel region in the first groove includes depositing an oxide semiconductor material.

17. The method according to claim 16, wherein, Forming the channel region in the first groove includes anisotropic etching of the oxide semiconductor material.

18. The method according to claim 16, wherein, Forming the gate dielectric region in the first groove that contacts the channel region includes depositing gate dielectric material.

19. The method according to claim 18, wherein, The gate dielectric material includes a high-k dielectric material.

20. The method according to claim 18, wherein, Forming the gate dielectric region in the first groove that contacts the channel region includes anisotropic etching of the gate dielectric material.

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