Semiconductor packaging method and semiconductor packaging structure

Abstract

This application provides a semiconductor packaging method and a semiconductor packaging structure. In this application, the semiconductor packaging structure includes: a pre-wiring substrate, a first intermediate packaging structure, a second intermediate packaging structure, a first encapsulation layer, a first dielectric layer, and a heat sink. The first and second intermediate packaging structures are located on and electrically connected to the pre-wiring substrate. The first intermediate packaging structure includes a first die and a first heat dissipation layer, and the second intermediate packaging structure includes a second die and a second heat dissipation layer. The first encapsulation layer is located on the side of the pre-wiring substrate closest to the first and second intermediate packaging structures. The heat sink is located on the side of the first and second intermediate packaging structures furthest from the pre-wiring substrate and is connected to both the first and second heat dissipation layers. In this embodiment, the heat sink enables common heat dissipation of the first and second intermediate packaging structures, improving the heat dissipation performance of the semiconductor packaging structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor packaging method and semiconductor packaging structure. Background Technology

[0002] In related technologies, semiconductor packaging structures generate heat during operation. If the generated heat is not dissipated in time, it will have an adverse effect on the working efficiency and lifespan of the semiconductor packaging structure.

[0003] Therefore, how to dissipate the heat generated by the semiconductor packaging structure in a timely manner is a technical problem that needs to be solved. Summary of the Invention

[0004] This application provides a semiconductor packaging method and a semiconductor packaging structure that can dissipate heat generated by the semiconductor packaging structure in a timely manner.

[0005] This application provides a semiconductor packaging structure, including:

[0006] Pre-wired substrate, having pre-wired lines;

[0007] A first intermediate package structure and a second intermediate package structure are located on the pre-wiring substrate. The first intermediate package structure and the second intermediate package structure are electrically connected to the pre-wiring lines. The first intermediate package structure includes a first die and a first heat dissipation layer. The first die includes a front side and a back side, with the front side and back side facing each other. The front side of the first die faces the pre-wiring substrate, and the first heat dissipation layer is located on the back side of the first die. The second intermediate package structure includes a second die and a second heat dissipation layer. The second die includes a front side and a back side, with the front side and back side facing each other. The front side of the second die faces the pre-wiring substrate, and the second heat dissipation layer is located on the back side of the second die.

[0008] The first encapsulation layer is located on the side of the pre-wiring substrate close to the first intermediate package structure and the second intermediate package structure, and at least covers the side of the first intermediate package structure and the side of the second intermediate package structure.

[0009] The heat sink is located on the side of the first intermediate packaging structure and the second intermediate packaging structure away from the pre-wired substrate, and is connected to the first heat dissipation layer and the second heat dissipation layer respectively.

[0010] In one embodiment, the thickness of the first intermediate packaging structure is the same as the thickness of the second intermediate packaging structure;

[0011] The first surface of the first intermediate packaging structure away from the pre-wiring substrate is flush with the second surface of the second intermediate packaging structure away from the pre-wiring substrate.

[0012] In one embodiment, the semiconductor package structure further includes a first dielectric layer, which is located on the side of the first encapsulation layer near the pre-wiring substrate and at least covers the side of the pre-wiring substrate.

[0013] The pre-wiring substrate further includes a first electrical connection point located on the side of the pre-wiring substrate away from the heat sink, and the pre-wiring substrate exposes the first electrical connection point.

[0014] In one embodiment, the first die includes a first silicon substrate, a first bonding pad, and a first protective layer. The first silicon substrate includes a front side and a back side. The front side of the first silicon substrate faces the pre-wiring substrate. The first bonding pad is located on the front side of the first silicon substrate. The first protective layer is located on the front side of the first silicon substrate. The first protective layer includes a first protective layer opening for exposing the first bonding pad.

[0015] The first intermediate package structure further includes a second encapsulation layer, a first electrical connection portion, and a first wiring layer. The second encapsulation layer is located on the side of the first heat dissipation layer near the first die and at least covers the side of the first die. The first electrical connection portion is located in the opening of the first protective layer. The first wiring layer is located on the side of the first protective layer away from the first heat dissipation layer and on the side of the second encapsulation layer away from the first heat dissipation layer. The first solder pad is electrically connected to the pre-wired line via the first electrical connection portion and the first wiring layer.

[0016] In one embodiment, the second die includes a second silicon substrate, a second bonding pad, and a second protective layer. The second silicon substrate includes a front side and a back side. The front side of the second silicon substrate faces the pre-wiring substrate. The second bonding pad is located on the front side of the second silicon substrate. The second protective layer is located on the front side of the second silicon substrate. The second protective layer includes a second protective layer opening for exposing the second bonding pad.

[0017] The second intermediate package structure further includes a third encapsulation layer, a second electrical connection portion, and a second wiring layer. The third encapsulation layer is located on the side of the second heat dissipation layer near the second die and at least covers the side of the second die. The second electrical connection portion is located in the opening of the second protective layer. The second wiring layer is located on the side of the second protective layer away from the second heat dissipation layer and on the side of the third encapsulation layer away from the second heat dissipation layer. The second solder pad is electrically connected to the pre-wired line via the second electrical connection portion and the second wiring layer.

[0018] This application also provides a semiconductor packaging method, which includes:

[0019] A first intermediate packaging structure and a second intermediate packaging structure are placed on a first carrier board. The first intermediate packaging structure includes a first die and a first heat dissipation layer. The first die includes a front side and a back side, with the front side and back side facing each other and the front side of the first die facing the first carrier board. The first heat dissipation layer is located on the back side of the first die. The second intermediate packaging structure includes a second die and a second heat dissipation layer. The second die includes a front side and a back side, with the front side and back side facing each other and the front side of the second die facing the first carrier board. The second heat dissipation layer is located on the back side of the second die.

[0020] A first encapsulation layer is formed, which is located on the side of the first carrier board close to the first intermediate package structure and the second intermediate package structure, and at least covers the side of the first intermediate package structure and the side of the second intermediate package structure. The first heat dissipation layer and the second heat dissipation layer are exposed from the first encapsulation layer.

[0021] Remove the first carrier plate;

[0022] A pre-wiring substrate is applied to the first encapsulation layer, with the front side of the first die facing the pre-wiring substrate and the front side of the second die facing the pre-wiring substrate. The pre-wiring substrate has pre-wiring lines, and the first intermediate package structure and the second intermediate package structure are electrically connected to the pre-wiring lines, respectively.

[0023] A heat sink is applied to the first encapsulation layer. The heat sink is located on the side of the first intermediate package structure and the second intermediate package structure away from the pre-wired substrate, and is connected to the first heat sink layer and the second heat sink layer, respectively.

[0024] In one embodiment, the pre-wiring substrate further includes a first electrical connection point located on the side of the pre-wiring substrate away from the heat sink; the pre-wiring substrate exposes the first electrical connection point.

[0025] After applying the pre-wired substrate to the first encapsulation layer, the method further includes:

[0026] A first dielectric layer is formed, which is located on the side of the first encapsulation layer near the pre-wiring substrate and at least covers the side of the pre-wiring substrate.

[0027] In one embodiment, before placing the first intermediate packaging structure and the second intermediate packaging structure on the first carrier board, the method further includes:

[0028] The first bare die is packaged to obtain the first intermediate package structure, and the second bare die is packaged to obtain the second intermediate package structure.

[0029] In one embodiment, the first die includes a first silicon substrate, a first bonding pad, and a first protective layer. The first silicon substrate includes a front side and a back side. The front side of the first silicon substrate faces the pre-wiring substrate. The first bonding pad is located on the front side of the first silicon substrate. The first protective layer is located on the front side of the first silicon substrate. The first protective layer includes a first protective layer opening for exposing the first bonding pad.

[0030] The first intermediate packaging structure further includes a second encapsulation layer, a first electrical connection portion, and a first wiring layer;

[0031] The process of encapsulating the first bare die to obtain the first intermediate package structure includes:

[0032] The first die is placed on the second carrier plate, with the front side of the first die facing the second carrier plate;

[0033] A second encapsulation layer is formed, which is located on the side of the second carrier plate close to the first die, at least covering the side of the first die and exposing the back of the first die;

[0034] Remove the second carrier plate;

[0035] A first electrical connection portion and a first wiring layer are formed. The first electrical connection portion is located in the opening of the first protective layer. The first wiring layer is located on the side of the first protective layer away from the back of the first die and on the side of the second encapsulation layer away from the back of the first die. The first solder pad is electrically connected to the first wiring layer via the first electrical connection portion. The first wiring layer is used to electrically connect to the pre-wired lines.

[0036] A first heat dissipation layer is formed, which is located on the back side of the first die and on the side of the second encapsulation layer away from the front side of the first die.

[0037] In one embodiment, the second die includes a second silicon substrate, a second bonding pad, and a second protective layer. The second silicon substrate includes a front side and a back side. The front side of the second silicon substrate faces the pre-wiring substrate. The second bonding pad is located on the front side of the second silicon substrate. The second protective layer is located on the front side of the second silicon substrate. The second protective layer includes a second protective layer opening for exposing the second bonding pad.

[0038] The second intermediate packaging structure also includes a third encapsulation layer, a second electrical connection portion, and a second wiring layer;

[0039] The process of encapsulating the second bare die to obtain the second intermediate package structure includes:

[0040] The second bare die is placed on the third carrier plate, with the front side of the second bare die facing the third carrier plate;

[0041] A third encapsulation layer is formed, which is located on the side of the third carrier plate closer to the second die, at least covering the side of the second die and exposing the back of the second die;

[0042] Remove the third carrier plate;

[0043] A second electrical connection portion and a second wiring layer are formed. The second electrical connection portion is located in the opening of the second protective layer. The second wiring layer is located on the side of the second protective layer away from the back of the second die and on the side of the third encapsulation layer away from the back of the second die. The second solder pad is electrically connected to the second wiring layer via the second electrical connection portion. The second wiring layer is used to electrically connect to the pre-wired lines.

[0044] A second heat dissipation layer is formed, which is located on the back side of the second die and on the side of the third encapsulation layer away from the front side of the second die.

[0045] In this embodiment, when the semiconductor package structure includes a first intermediate package structure and a second intermediate package structure, the first intermediate package structure includes a first die and a first heat dissipation layer, and the second intermediate package structure includes a second die and a second heat dissipation layer. The first heat dissipation layer is located on the back side of the first die, and the second heat dissipation layer is located on the back side of the second die. The first heat dissipation layer is used to dissipate heat from the first intermediate package structure, and the second heat dissipation layer is used to dissipate heat from the second intermediate package structure. Furthermore, the semiconductor package structure also includes a heat sink, which is located on the side of the first intermediate package structure and the second intermediate package structure away from the pre-wiring substrate, and is connected to the first heat dissipation layer and the second heat dissipation layer respectively. In this way, the heat sink can achieve common heat dissipation of the first intermediate package structure and the second intermediate package structure, thereby improving the heat dissipation performance of the semiconductor package structure. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of this application.

[0047] Figure 2 This is a top view of a pre-wiring substrate according to an embodiment of this application.

[0048] Figure 3This is a cross-sectional view of a pre-wiring substrate according to an embodiment of this application.

[0049] Figure 4 This is a schematic flowchart illustrating a semiconductor packaging method according to an embodiment of this application.

[0050] Figure 5 This is a schematic diagram of the structure of a first bare die according to an embodiment of this application.

[0051] Figure 6 This is a schematic diagram of the structure of a second bare die according to an embodiment of this application.

[0052] Figure 7 This is a schematic flowchart illustrating a method for preparing a first bare wafer according to an embodiment of this application.

[0053] Figures 8-12 This is a schematic diagram of the intermediate structure produced during the preparation of the first bare wafer, according to an embodiment of this application.

[0054] Figure 13 A schematic flowchart of a method for preparing a first intermediate packaging structure according to an embodiment of this application.

[0055] Figures 14-22 This is a schematic diagram of the intermediate structure generated during the preparation of the first intermediate packaging structure according to an embodiment of this application.

[0056] Figure 23 A schematic flowchart of a method for preparing a second intermediate transition structure according to an embodiment of this application.

[0057] Figures 24-31 This is a schematic diagram of an intermediate structure generated during the fabrication of a semiconductor packaging structure according to an embodiment of this application. Detailed Implementation

[0058] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0059] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0060] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0061] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0062] Embodiments of this application provide a semiconductor package structure 1. The semiconductor package structure 1 is a chip package. This semiconductor package structure can be applied to electronic devices, such as mobile phones, computers, etc. Figure 1 As shown, the semiconductor package structure 1 includes a pre-wiring substrate 11, a first intermediate package structure 12, a second intermediate package structure 13, a first encapsulation layer 14, a first dielectric layer 15, and a heat sink 16.

[0063] In this embodiment, by providing a pre-formed pre-wiring substrate 11, the pre-wiring substrate 11 can be tested before packaging, thus avoiding the use of known defective pre-wiring substrates 11. Moreover, since the pre-wiring substrate 11 is a pre-fabricated substrate, its fabrication process is independent of the packaging process of the semiconductor packaging structure 1, which can save packaging time in the entire packaging process.

[0064] In this embodiment, as Figure 1As shown, the pre-wiring substrate 11 has a first electrical connection point 111, a second electrical connection point 112, a third electrical connection point 113, and pre-wiring lines 114. The first electrical connection point 111, the second electrical connection point 112, and the third electrical connection point 113 are electrically connected to the pre-wiring lines 114. The first electrical connection point 111 is located on the side of the pre-wiring substrate 11 away from the heat sink 16, and the surface of the pre-wiring substrate 11 away from the heat sink 16 is flush with the surface of the pre-wiring substrate 11 away from the heat sink 16. The second electrical connection point 112 is located on the side of the pre-wiring substrate 11 near the first intermediate package structure 12 and is used for electrical connection to the first intermediate package structure 12. The third electrical connection point 113 is located on the side of the pre-wiring substrate 11 near the second intermediate package structure 13 and is used for electrical connection to the second intermediate package structure 13.

[0065] In this embodiment, as Figure 2 As shown, the pre-wiring substrate 11 may include at least one pre-wiring unit 115, for example, one, two, four, or other number of pre-wiring units 115. Each pre-wiring unit 115 may have the same structure, but is not limited thereto. Figure 3 As shown, each pre-wiring unit 115 may include a first electrical connection point 111, a second electrical connection point 112, a third electrical connection point 113, and a pre-wiring line 114.

[0066] In this embodiment, the electrical connection between the first intermediate package structure 12 and the second intermediate package structure 13 is achieved through the pre-wiring substrate 11. Since the pre-wiring substrate 11 includes complex multiple circuits, it can realize complex wiring between the first intermediate package structure 12 and the second intermediate package structure 13.

[0067] In this embodiment, as Figure 1 As shown, the thickness of the first intermediate packaging structure 12 is the same as the thickness of the second intermediate packaging structure 13. Therefore, when the first intermediate packaging structure 12 and the second intermediate packaging structure 13 are placed on the pre-wiring substrate 11, the first surface of the first intermediate packaging structure 12 away from the pre-wiring substrate 11 is flush with the second surface of the second intermediate packaging structure 13 away from the pre-wiring substrate 11.

[0068] In this embodiment, as Figure 1 As shown, the first intermediate package structure 12 is located on the pre-wiring substrate 11 and is electrically connected to the pre-wiring line 114. The first intermediate package structure 12 includes a first die 121, a second encapsulation layer 122, a first electrical connection portion 123, a first wiring layer 124, a second dielectric layer 125, and a first heat dissipation layer 126.

[0069] In this embodiment, as Figure 1As shown, the first die 121 includes a front side and a back side, with the front side and back side of the first die 121 facing each other. The front side of the first die 121 is the active side, the front side of the first die 121 faces the pre-wiring substrate 11, and the back side of the first die 121 faces the first heat dissipation layer 126.

[0070] In this embodiment, as Figure 1 As shown, the first die 121 includes a first silicon substrate (not shown), a first bonding pad 1211 and a first protective layer 1212. The first silicon substrate includes a front side and a back side. The front side of the first silicon substrate faces the pre-wiring substrate 11. The first bonding pad 1211 is located on the front side of the first silicon substrate and is used for electrical connection with the outside world. The first protective layer 1212 is located on the front side of the first silicon substrate and includes a first protective layer opening (not shown) for exposing the first bonding pad 1211.

[0071] In this embodiment, the first protective layer 1212 is made of an insulating material, and the first protective layer 1212 can protect the active surface of the first bare die 121 during the molding process. The first protective layer 1212 may include one or more layers of insulating material. The material of the first protective layer 1212 may be ABF (Ajinomoto buildup film), PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material, or other materials with similar properties, or any combination of the above materials.

[0072] In this embodiment, as Figure 1 As shown, the second encapsulation layer 122 is located on the side of the first heat dissipation layer 126 closest to the first bare die 121, and at least covers the side of the first bare die 121. The second encapsulation layer 122 can be a polymer, resin, or a composite material of resin and polymer. For example, the second encapsulation layer 122 can be a resin with fillers, or other materials with similar properties. The second encapsulation layer 122 can be formed by plastic material molding methods such as injection molding, thermoforming, and transfer molding.

[0073] In this embodiment, as Figure 1As shown, the first electrical connection portion 123 is connected to the first wiring layer 124 and can be integrally formed. The first wiring layer 124 is electrically connected to the pre-wiring line 114, that is, the first solder pad 1211 is electrically connected to the pre-wiring line 114 via the first electrical connection portion 123 and the first wiring layer 124. The material of the first electrical connection portion 123 is the same as the material of the first wiring layer 124, both being conductive materials, for example, both being metallic materials, such as copper. When the materials of the first electrical connection portion 123 and the first wiring layer 124 are metallic materials, the first electrical connection portion 123 and the first wiring layer 124 can be formed by metal sputtering, electrolytic plating, or electrodeless plating. The first electrical connection portion 123 and the first wiring layer 124 can be formed in the same metal deposition process.

[0074] In this embodiment, as Figure 1 As shown, the first electrical connection portion 123 is located in the opening of the first protective layer, and the first wiring layer 124 is located on the side of the first protective layer 1212 away from the first heat dissipation layer 126 and on the side of the second encapsulation layer 122 away from the first heat dissipation layer 126.

[0075] In this embodiment, as Figure 1 As shown, the first wiring layer 124 includes a first conductive trace 1241 and a first conductive protrusion 1242. The first conductive trace 1241 is located on the side of the first protective layer 1212 away from the first heat dissipation layer 126 and on the side of the second encapsulation layer 122 away from the first heat dissipation layer 126. The first conductive protrusion 1242 is located on the side of the first conductive trace 1241 away from the first heat dissipation layer 126, and is exposed from the second dielectric layer 125, and is connected to the second electrical connection point 112 of the pre-wiring substrate 11. It should be noted that in other embodiments, the first intermediate packaging structure 12 may include multiple wiring layers.

[0076] In this embodiment, as Figure 1 As shown, the second dielectric layer 125 is located on the side of the first protective layer 1212 away from the first heat dissipation layer 126 and on the side of the first wiring layer 124 away from the first heat dissipation layer 126. In other words, the second dielectric layer 125 is located on the side of the first protective layer 1212 away from the first heat dissipation layer 126 and on the side of the first conductive trace 1241 away from the first heat dissipation layer 126.

[0077] In this embodiment, the second dielectric layer 125 may include one or more layers of insulating material, and the material of the first protective layer 1212 may be ABF (Ajinomoto buildup film), PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar properties, or any combination of the above materials.

[0078] In this embodiment, the material of the first heat dissipation layer 126 is a thermally conductive material, for example, the material of the first heat dissipation layer 126 is a metal material, for example, the material of the first heat dissipation layer 126 is copper, but it is not limited to this.

[0079] In this embodiment, as Figure 1 As shown, the second intermediate package structure 13 is located on the pre-wiring substrate 11 and is electrically connected to the pre-wiring lines 114. The second intermediate package structure 13 includes a second die 131, a third encapsulation layer 132, a second electrical connection portion 133, a second wiring layer 134, a third dielectric layer 135, and a second heat dissipation layer 136.

[0080] In this embodiment, as Figure 1 As shown, the second die 131 includes a front side and a back side, with the front side and back side of the second die 131 facing each other. The front side of the second die 131 is the active side, the front side of the second die 131 faces the pre-wiring substrate 11, and the back side of the second die 131 faces the second heat dissipation layer 136.

[0081] In this embodiment, as Figure 1 As shown, the second die 131 includes a second silicon substrate (not shown), a second bonding pad 1311, and a second protective layer 1312. The second silicon substrate includes a front side and a back side. The front side of the second silicon substrate faces the pre-wiring substrate 11. The second bonding pad 1311 is located on the front side of the second silicon substrate. The second protective layer 1312 is located on the front side of the second silicon substrate. The second protective layer 1312 includes a second protective layer opening (not shown) for exposing the second bonding pad 1311.

[0082] In this embodiment, the second protective layer 1312 is made of an insulating material. The second protective layer 1312 can protect the active surface of the second die 131 during the molding process. The second protective layer 1312 may include one or more layers of insulating material. The material of the second protective layer 1312 may be ABF (Ajinomoto buildup film), PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar properties, or any combination of the above materials.

[0083] In this embodiment, as Figure 1 As shown, the third encapsulation layer 132 is located on the side of the second heat dissipation layer 136 closest to the second bare die 131, and at least covers the side of the second bare die 131. The third encapsulation layer 132 can be a polymer, resin, or a composite material of resin and polymer. For example, the third encapsulation layer 132 can be a resin with fillers, or other materials with similar properties. The third encapsulation layer 132 can be formed by plastic material molding methods such as injection molding, thermoforming, and transfer molding.

[0084] In this embodiment, as Figure 1 As shown, the second electrical connection portion 133 is connected to the second wiring layer 134 and can be integrally formed. The second wiring layer 134 is electrically connected to the pre-wiring line 114, that is, the second solder pad 1311 is electrically connected to the pre-wiring line 114 via the second electrical connection portion 133 and the second wiring layer 134. The material of the second electrical connection portion 133 is the same as the material of the second wiring layer 134, both being conductive materials, for example, both being metallic materials, such as copper. When the materials of the second electrical connection portion 133 and the second wiring layer 134 are metallic materials, the second electrical connection portion 133 and the second wiring layer 134 can be formed by metal sputtering, electrolytic plating, or electrodeless plating. The second electrical connection portion 133 and the second wiring layer 134 can be formed in the same metal deposition process.

[0085] In this embodiment, as Figure 1 As shown, the second electrical connection portion 133 is located in the opening of the second protective layer, and the second wiring layer 134 is located on the side of the second protective layer 1312 away from the second heat dissipation layer 136 and on the side of the third encapsulation layer 132 away from the second heat dissipation layer 136.

[0086] In this embodiment, as Figure 1 As shown, the second wiring layer 134 includes a second conductive trace 1341 and a second conductive protrusion 1342. The second conductive trace 1341 is located on the side of the second protective layer 1312 away from the second heat dissipation layer 136 and on the side of the third encapsulation layer 132 away from the second heat dissipation layer 136. The second conductive protrusion 1342 is located on the side of the second conductive trace 1341 away from the second heat dissipation layer 136, and is exposed from the third dielectric layer 135, and is connected to the third electrical connection point 113 of the pre-wiring substrate 11. It should be noted that in other embodiments, the second intermediate package structure 13 may include multiple wiring layers.

[0087] In this embodiment, as Figure 1 As shown, the third dielectric layer 135 is located on the side of the second protective layer 1312 away from the second heat dissipation layer 136 and on the side of the second wiring layer 134 away from the second heat dissipation layer 136. Alternatively, the third dielectric layer 135 is located on the side of the second protective layer 1312 away from the second heat dissipation layer 136 and on the side of the second conductive trace 1341 away from the second heat dissipation layer 136.

[0088] In this embodiment, the material of the second heat dissipation layer 136 is a thermally conductive material, for example, the material of the second heat dissipation layer 136 is a metal material, for example, the material of the second heat dissipation layer 136 is copper, but it is not limited to this.

[0089] In this embodiment, as Figure 1As shown, the thickness of the first intermediate package structure 12 is the same as the thickness of the second intermediate package structure 13. Therefore, when the first intermediate package structure 12 and the second intermediate package structure 13 are placed on the pre-wiring substrate 11, the first surface of the first intermediate package structure 12 away from the pre-wiring substrate 11 and the second surface of the second intermediate package structure 13 away from the pre-wiring substrate 11 are flush. This facilitates the placement of the heat sink 16 on the first heat dissipation layer 126 and the second heat dissipation layer 136, and enables the first heat dissipation layer 126 and the second heat dissipation layer 136 to be connected to the heat sink 16 respectively. Furthermore, the heat dissipated by the first intermediate package structure 12 and the second intermediate package structure 13 can be conducted away through the first heat dissipation layer 126, the second heat dissipation layer 136, and the heat sink 16, thereby improving the heat dissipation performance of the semiconductor package structure 1.

[0090] In this embodiment, as Figure 1 As shown, the first encapsulation layer 14 is located on the side of the pre-wiring substrate 11 near the first intermediate package structure 12 and the second intermediate package structure 13, and at least covers the side surface of the first intermediate package structure 12 and the side surface of the second intermediate package structure 13. The first encapsulation layer 14 can be a polymer, resin, or a composite material of resin and polymer. For example, the first encapsulation layer 14 can be a resin with fillers, or other materials with similar properties.

[0091] In this embodiment, as Figure 1 As shown, the heat sink 16 is located on the side of the first intermediate package structure 12 and the second intermediate package structure 13 away from the pre-wiring substrate 11, and is connected to the first heat dissipation layer and the second heat dissipation layer respectively. The material of the heat sink 16 is a thermally conductive material, such as a metal material, such as copper. In this way, the heat sink 16 can achieve common heat dissipation of the first intermediate package structure 12 and the second intermediate package structure 13, thereby improving the heat dissipation performance of the semiconductor package structure 1.

[0092] In this embodiment, the first dielectric layer 15 is located on the side of the first encapsulation layer 14 closest to the pre-wiring substrate 11, and at least covers the side surface of the pre-wiring substrate 11. The first dielectric layer 15 may include one or more layers of insulating material. The material of the first dielectric layer 15 may be ABF (Ajinomoto buildup film), PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material, or other materials with similar properties, or any combination of the above materials.

[0093] In this embodiment, when the semiconductor package structure 1 includes a first intermediate package structure 12 and a second intermediate package structure 13, the first intermediate package structure 12 includes a first die 121 and a first heat dissipation layer 126, and the second intermediate package structure 13 includes a second die 131 and a second heat dissipation layer 136. The first heat dissipation layer 126 is located on the back side of the first die 121, and the second heat dissipation layer 136 is located on the back side of the second die 131. The first heat dissipation layer 126 is used to dissipate heat from the first intermediate package structure 12, and the second heat dissipation layer 136 is used to dissipate heat from the second intermediate package structure 13. Furthermore, the semiconductor package structure 1 also includes a heat sink 16, which is located on the side of the first intermediate package structure 12 and the second intermediate package structure 13 away from the pre-wiring substrate 11, and is connected to the first heat dissipation layer 126 and the second heat dissipation layer 136 respectively. In this way, the heat sink 16 can achieve common heat dissipation of the first intermediate package structure 12 and the second intermediate package structure 13, thereby improving the heat dissipation performance of the semiconductor package structure 1.

[0094] Embodiments of this application also provide a semiconductor packaging method for preparing the above-described semiconductor packaging structure 1. For example... Figure 4 As shown, the semiconductor packaging method includes the following steps 401 to 409:

[0095] In step 401, a first bare die 121 and a second bare die 131 are prepared.

[0096] In this embodiment, as Figure 5 As shown, the first die 121 includes a first silicon substrate 1213, a first bonding pad 1211, a first insulating layer 1214, and a first protective layer 1212. The first silicon substrate 1213 includes a front side and a back side. The front side of the first silicon substrate 1213 is the active side, and circuitry, the first bonding pad 1211, and the first insulating layer 1214 are disposed on the front side of the first silicon substrate 1213. The first bonding pad 1211 is exposed from the first insulating layer 1214 to make electrical connections with the outside. The first protective layer 1212 is located on the first bonding pad 1211 and the first insulating layer 1214, and the first protective layer 1212 includes a first protective layer opening 1217 to expose the first bonding pad 1211.

[0097] In this embodiment, as Figure 6As shown, the second die 131 includes a second silicon substrate 1313, a second bonding pad 1311, a second insulating layer 1314, and a second protective layer 1312. The second silicon substrate 1313 includes a front side and a back side. The front side of the second silicon substrate 1313 is the active side, and circuitry, the second bonding pad 1311, and the second insulating layer 1314 are disposed on the front side of the second silicon substrate 1313. The second bonding pad 1311 is exposed from the second insulating layer 1314 to make electrical connections with the outside. The second protective layer 1312 is located on the second bonding pad 1311 and the second insulating layer 1314, and the second protective layer 1312 includes a second protective layer opening 1317 to expose the second bonding pad 1311.

[0098] In this embodiment, as Figure 7 As shown, the method for preparing the first bare wafer 121 includes the following steps 701-705:

[0099] In step 701, a first wafer 1215 is provided.

[0100] In this embodiment, as Figures 8-9 As shown, the first wafer 1215 has a front side B1 and a back side B2. The front side B1 of the first wafer 1215 is the active side, and circuitry, a first solder pad 1211, and a first insulating layer 1214 are disposed on the front side B1 of the first wafer 1215. The first solder pad 1211 is exposed from the first insulating layer 1214 to make electrical connections with the outside world.

[0101] In step 702, a first protective layer 1212 is formed on the front side of the first wafer 1215.

[0102] In this embodiment, as Figure 10 As shown, a first protective layer 1212 is formed on the front side of the first wafer 1215. The first protective layer 1212 can be applied by lamination, spin coating, printing, molding or other suitable methods, but is not limited thereto.

[0103] In step 703, the back side of the first wafer 1215 is thinned.

[0104] In this embodiment, a grinding device can be used to grind the back side of the first wafer 1215 to reduce the thickness of the first wafer 1215.

[0105] In step 704, a first protective layer opening 1217 is formed, resulting in a first intermediate transition structure 1101.

[0106] In this embodiment, as Figure 11 As shown, a laser drilling process can be used to drill holes in the first protective layer 1212 to obtain an opening 1217 in the first protective layer, thereby exposing the first solder pad 1211. Of course, other processes can also be used to prepare the opening 1217 in the first protective layer.

[0107] In step 705, the first intermediate transition structure 1101 is cut to obtain the first bare die 121.

[0108] In this embodiment, as Figure 12 As shown, the first intermediate transition structure 1101 can be cut along the cutting path to obtain the following result: Figure 5 The first bare die 121 is shown. The cutting slit can be located on the first intermediate transition structure 1101 at a position corresponding to the first cutting line 1201.

[0109] It should be noted that in other embodiments, the back side of the first wafer 1215 can be thinned first and then cut to form the first protective layer opening 1217.

[0110] In this embodiment, the method for preparing the second die 131 is similar to the method for preparing the first die 121, and will not be described again here.

[0111] In step 402, the first die 121 is packaged to obtain the first intermediate package structure 12, and the second die 131 is packaged to obtain the second intermediate package structure 13.

[0112] In this embodiment, as Figure 13 As shown, the method for preparing the first intermediate packaging structure 12 includes the following steps 1301 to 1307:

[0113] In step 1301, the first die 121 is placed on the second carrier plate 1401 with the front side of the first die 121 facing the second carrier plate 1401.

[0114] In this embodiment, as Figure 14 As shown, the first bare die 121 can be placed and mounted on the second carrier plate 1401 according to a predetermined arrangement. The first protective layer opening 1217 on the first protective layer 1212 of the first bare die 121 faces the second carrier plate 1401. Figure 15 As shown, multiple first bare wafers 121 can be placed on the second carrier plate 1401 according to a predetermined arrangement. Alternatively, a single first bare wafer 121 can be placed on the second carrier plate 1401 according to a predetermined arrangement. It should be noted that the number of first bare wafers 121 arranged on the second carrier plate 1401 can be determined based on the type and size of the first bare wafers 121 and the size of the second carrier plate 1401.

[0115] In this embodiment, during the process of placing and mounting the first bare die 121 onto the second carrier plate 1401, the second carrier plate 1401 can be photographed first to obtain a first image. The second carrier plate 1401 is provided with a first alignment mark, which is used to identify the arrangement position of the first bare die 121. Then, the first image is processed to determine the position information of the arrangement position. Next, a robotic arm picks up the first bare die 121 with the first protective layer opening 1217 on the first protective layer 1212 facing downwards. Then, a photograph is taken of the front of the first bare die 121 to obtain a second image. The second image is then processed based on the first protective layer opening 1217 in the second image. The position of the first bare die 121 is determined; then, it is determined whether the position of the first bare die 121 corresponds to the arrangement position of the first bare die 121 in the direction perpendicular to the second carrier plate 1401. If they do not correspond, the position of the first bare die 121 is adjusted in the direction parallel to the second carrier plate 1401 so that the position of the first bare die 121 corresponds to the arrangement position of the first bare die 121 in the direction perpendicular to the second carrier plate 1401. When the position of the first bare die 121 corresponds to the arrangement position of the first bare die 121 in the direction perpendicular to the second carrier plate 1401, the second carrier plate 1401 is moved toward the first bare die 121 until the first bare die 121 is mounted on the second carrier plate 1401. In this embodiment, during the process of placing and mounting the first die 121 onto the second carrier board 1401, the first protective layer opening 1217 is used as an alignment pattern feature, which allows the first die 121 to be arranged more accurately on the second carrier board 1401, thereby improving the packaging yield.

[0116] In step 1302, a second encapsulation layer 122 is formed. The second encapsulation layer 122 is located on the side of the second carrier plate 1401 close to the first die 121, covering at least the side of the first die 121 and exposing the back of the first die 121.

[0117] In this embodiment, as Figure 16 As shown, a first molding compound 1601 can be formed on the second carrier plate 1401 on the side near the first die 121. The first molding compound 1601 can cover the side and back of the first die 121, and the thickness of the first molding compound 1601 is greater than the thickness of the first die 121. Figure 17 As shown, the thickness of the first molding layer 1601 is then reduced to expose the back side of the first die 121, resulting in the second molding layer 122. Alternatively, the second molding layer 122 can be formed directly.

[0118] In this embodiment, the second encapsulation layer 122 can be formed by plastic material molding methods such as injection molding, hot pressing, and transfer molding.

[0119] In step 1303, the second carrier plate 1401 is removed.

[0120] In this embodiment, as Figure 18 As shown, the second carrier plate 1401 is removed to expose the first protective layer opening 1217 on the first protective layer 1212 of the first die 121.

[0121] In step 1304, a first electrical connection portion 123 and a first wiring layer 124 are formed. The first electrical connection portion 123 is located in the opening 1217 of the first protective layer, and the first wiring layer 124 is located on the side of the first protective layer 1212 away from the back surface of the first die 121 and on the side of the second encapsulation layer 122 away from the back surface of the first die 121. The first solder pad 1211 is electrically connected to the first wiring layer 124 via the first electrical connection portion 123, and the first wiring layer 124 is used for electrical connection with the pre-wired line 114.

[0122] In this embodiment, the first wiring layer 124 includes a first conductive trace 1241 and a first conductive protrusion 1242; the first conductive trace 1241 is located on the side of the first protective layer 1212 away from the back surface of the first die 121 and on the side of the second encapsulation layer 122 away from the back surface of the first die 121, and the first conductive protrusion 1242 is located on the side of the first conductive trace 1241 away from the back surface of the first die 121.

[0123] In this embodiment, as Figure 19 As shown, a first electrical connection portion 123 is formed by filling the first protective layer opening 1217 with conductive material, and a first wiring layer 124 is formed. The formation of the first wiring layer 124 includes forming a first conductive trace 1241 and forming a first conductive protrusion 1242 at the electrical connection point of the first conductive trace 1241 or at the position corresponding to the first pad 1211.

[0124] In this embodiment, the first electrical connection portion 123 and the first wiring layer 124 can be formed by methods such as metal sputtering, electrolytic plating, or electrodeless plating. The first electrical connection portion 123 and the first wiring layer 124 can be formed in the same metal deposition process.

[0125] In step 1305, a second dielectric layer 125 is formed. The second dielectric layer 125 is located on the side of the first protective layer 1212 away from the back of the first die 121 and on the side of the first wiring layer 124 away from the back of the first die 121, and exposes the first conductive protrusion 1242.

[0126] In this embodiment, as Figure 20As shown, a second dielectric layer 125 can be formed on the side of the first protective layer 1212 away from the back surface of the first die 121 and on the side of the first wiring layer 124 away from the back surface of the first die 121. The surface of the second dielectric layer 125 away from the first die 121 can be flush with the surface of the first conductive protrusion 1242 away from the first die 121 to expose the first conductive protrusion 1242. Of course, when forming the second dielectric layer 125, the second dielectric layer 125 can also cover the first conductive protrusion 1242, and then the second dielectric layer 125 can be thinned to expose the first conductive protrusion 1242.

[0127] In this embodiment, the second dielectric layer 125 can be applied by lamination, spin coating, printing, molding or other suitable methods.

[0128] In step 1306, a first heat dissipation layer 126 is formed to obtain a second intermediate transition structure 2101. The first heat dissipation layer 126 is located on the back side of the first die 121 and on the side of the second encapsulation layer 122 away from the front side of the first die 121.

[0129] In this embodiment, as Figure 21 As shown, a first heat dissipation layer 126 is formed on the back side of the first die 121 and on the side of the second encapsulation layer 122 away from the front side of the first die 121, resulting in a second intermediate transition structure 2101.

[0130] In this embodiment, the first heat dissipation layer 126 can be formed by physical or chemical deposition, or a metal component can be applied to the back side of the first bare die 121 to serve as the first heat dissipation layer 126.

[0131] In step 1307, the second intermediate transition structure 2101 is cut to obtain the first intermediate packaging structure 12.

[0132] In this embodiment, as Figure 22 As shown, the second intermediate transition structure 2101 can be cut along the second cutting line 2201 to obtain the first intermediate packaging structure 12.

[0133] In this embodiment, as Figure 23 As shown, the preparation method of the second intermediate transition structure 2101 includes the following steps 2301 to 2307:

[0134] In step 2301, the second die 131 is placed on the third carrier plate with the front side of the second die 131 facing the third carrier plate.

[0135] In step 2302, a third encapsulation layer 132 is formed. The third encapsulation layer 132 is located on the side of the third carrier plate close to the second die 131, covering at least the side of the second die 131 and exposing the back of the second die 131.

[0136] In step 2303, the third carrier board is removed.

[0137] In step 2304, a second electrical connection portion 133 and a second wiring layer 134 are formed. The second electrical connection portion 133 is located in the opening 1317 of the second protective layer. The second wiring layer 134 is located on the side of the second protective layer 1312 away from the back surface of the second die 131 and on the side of the third encapsulation layer 132 away from the back surface of the second die 131. The second solder pad 1311 is electrically connected to the second wiring layer 134 via the second electrical connection portion 133. The second wiring layer 134 is used for electrical connection with the pre-wired line 114.

[0138] In this embodiment, the second wiring layer 134 includes a second conductive trace 1341 and a second conductive protrusion 1342; the second conductive trace 1341 is located on the side of the second protective layer 1312 away from the back surface of the second die 131 and on the side of the third encapsulation layer 132 away from the back surface of the second die 131, and the second conductive protrusion 1342 is located on the side of the second conductive trace 1341 away from the back surface of the second die 131.

[0139] In step 2305, a third dielectric layer 135 is formed. The third dielectric layer 135 is located on the side of the second protective layer 1312 away from the back of the second die 131 and on the side of the second wiring layer 134 away from the back of the second die 131, and exposes the second conductive protrusion 1342.

[0140] In step 2306, a second heat dissipation layer 136 is formed to obtain a third intermediate transition structure. The second heat dissipation layer 136 is located on the back side of the second die 131 and on the side of the third encapsulation layer 132 away from the front side of the second die 131.

[0141] In step 2307, the third intermediate transition structure is cut to obtain the second intermediate packaging structure 13.

[0142] In this embodiment, steps 2301 to 2307 are similar to the corresponding steps in steps 1301 to 1307, and will not be described again here.

[0143] In step 403, the first intermediate packaging structure 12 and the second intermediate packaging structure 13 are placed on the first carrier board 2401. The first intermediate packaging structure 12 includes a first die 121 and a first heat dissipation layer 126. The first die 121 includes a front side and a back side, with the front side and back side of the first die 121 facing each other and the front side of the first die 121 facing the first carrier board 2401. The first heat dissipation layer 126 is located on the back side of the first die 121. The second intermediate packaging structure 13 includes a second die 131 and a second heat dissipation layer 136. The second die 131 includes a front side and a back side, with the front side and back side of the second die 131 facing each other and the front side of the second die 131 facing the first carrier board 2401. The second heat dissipation layer 136 is located on the back side of the second die 131.

[0144] In this embodiment, as Figure 24 As shown, the first intermediate packaging structure 12 and the second intermediate packaging structure 13 can be placed on the first carrier board 2401 according to a predetermined arrangement. The front side of the first die 121 faces the first carrier board 2401, and the front side of the second die 131 also faces the first carrier board 2401. Figure 25 As shown, multiple first intermediate packaging structures 12 and multiple second intermediate packaging structures 13 can be placed on the first carrier board 2401 according to a predetermined arrangement. Each first intermediate packaging structure 12 and each second intermediate packaging structure 13 forms a group. Alternatively, a single first intermediate packaging structure 12 and a single second intermediate packaging structure 13 can be placed on the first carrier board 2401 according to a predetermined arrangement. It should be noted that the number of first intermediate packaging structures 12 and the number of second intermediate packaging structures 13 arranged on the first carrier board 2401 can be determined based on the type of first intermediate packaging structure 12, the type of second intermediate packaging structure 13, the size of the first intermediate packaging structure 12, the size of the second intermediate packaging structure 13, and the size of the first carrier board 2401.

[0145] In this embodiment, the method of placing the first intermediate packaging structure 12 on the first carrier board 2401 according to the predetermined arrangement position is similar to the method of placing the second intermediate packaging structure 13 on the first carrier board 2401 according to the predetermined arrangement position. To avoid redundancy, the method of placing the first intermediate packaging structure 12 on the first carrier board 2401 according to the predetermined arrangement position will be described below as an example.

[0146] In this embodiment, during the process of placing the first intermediate packaging structure 12 on the first carrier 2401 according to a predetermined arrangement, the first carrier 2401 can be photographed first to obtain a third image. The first carrier 2401 is provided with a second alignment mark, which is used to identify the arrangement position of the first intermediate packaging structure 12. Then, the third image is processed to determine the position information of the first intermediate packaging structure 12. Next, a robotic arm picks up the first intermediate packaging structure 12 with the first conductive protrusion 1242 facing downwards. Then, a fourth image is obtained by photographing the side of the first intermediate packaging structure 12 with the first conductive protrusion 1242. The fourth image is then processed based on the position of the first conductive protrusion 1242 in the fourth image. The position of the first intermediate packaging structure 12 is determined; then, it is determined whether the position of the first intermediate packaging structure 12 corresponds to the arrangement position of the first intermediate packaging structure 12 in the direction perpendicular to the first carrier board 2401. If they do not correspond, the position of the first intermediate packaging structure 12 is adjusted in the direction parallel to the first carrier board 2401 so that the position of the first intermediate packaging structure 12 corresponds to the arrangement position of the first intermediate packaging structure 12 in the direction perpendicular to the first carrier board 2401. When the position of the first intermediate packaging structure 12 corresponds to the arrangement position of the first intermediate packaging structure 12 in the direction perpendicular to the first carrier board 2401, the first carrier board 2401 is moved toward the first intermediate packaging structure 12 until the first intermediate packaging structure 12 is mounted on the first carrier board 2401. In this embodiment, during the process of placing and mounting the first intermediate packaging structure 12 onto the first carrier board 2401, the first conductive protrusion 1242 is used as an alignment pattern feature, which allows the first intermediate packaging structure 12 to be arranged more accurately on the first carrier board 2401, thereby improving the packaging yield.

[0147] In step 404, a first encapsulation layer 14 is formed. The first encapsulation layer 14 is located on the side of the first carrier board 2401 close to the first intermediate packaging structure 12 and the second intermediate packaging structure 13, and at least covers the side of the first intermediate packaging structure 12 and the side of the second intermediate packaging structure 13. The first heat dissipation layer 126 and the second heat dissipation layer 136 are exposed from the first encapsulation layer 14.

[0148] In this embodiment, as Figure 26As shown, a first encapsulation layer 14 can be formed on the side of the first carrier board 2401 near the first intermediate packaging structure 12 and the second intermediate packaging structure 13. The first encapsulation layer 14 covers the side of the first intermediate packaging structure 12 and the side of the second intermediate packaging structure 13, and the first heat dissipation layer 126 and the second heat dissipation layer 136 are exposed from the first encapsulation layer 14. In other embodiments, a second molding layer can also be formed on the side of the first carrier board 2401 near the first intermediate packaging structure 12 and the second intermediate packaging structure 13. The second molding layer covers the side of the first intermediate packaging structure 12 and the side of the first intermediate packaging structure 12 away from the first carrier board 2401. The second molding layer also covers the side of the second intermediate packaging structure 13 and the side of the second intermediate packaging structure 13 away from the first carrier board 2401. Then, the second molding layer is thinned to obtain the first encapsulation layer 14, so that the first heat dissipation layer 126 and the second heat dissipation layer 136 are exposed from the first encapsulation layer 14.

[0149] In this embodiment, the first encapsulation layer 14 can be formed by plastic material molding methods such as injection molding, hot pressing, and transfer molding.

[0150] In step 405, the first carrier plate 2401 is removed.

[0151] In this embodiment, as Figure 27 As shown, the first carrier plate 2401 is removed to expose the first conductive protrusion 1242 and the second conductive protrusion 1342.

[0152] In step 406, a pre-wiring substrate 11 is applied to the first encapsulation layer 14, with the front side of the first die 121 facing the pre-wiring substrate 11 and the front side of the second die 131 facing the pre-wiring substrate 11. The pre-wiring substrate 11 has pre-wiring lines 114, and the first intermediate packaging structure 12 and the second intermediate packaging structure 13 are electrically connected to the pre-wiring lines 114.

[0153] In this embodiment, as Figure 28 As shown, a pre-wiring substrate 11 is applied to a first encapsulation layer 14. The front side of a first die 121 faces the pre-wiring substrate 11, and the front side of a second die 131 faces the pre-wiring substrate 11. The pre-wiring substrate 11 has pre-wiring lines 114. A first intermediate package structure 12 and a second intermediate package structure 13 are electrically connected to the pre-wiring lines 114. The first conductive protrusion 1242 of the first intermediate package structure 12 is connected to the second electrical connection point 112 of the pre-wiring substrate 11, and the second conductive protrusion 1342 of the second intermediate package structure 13 is connected to the third electrical connection point 113 of the pre-wiring substrate 11. The second electrical connection point 112 and the third electrical connection point 113 are electrically connected to the pre-wiring lines 114.

[0154] In this embodiment, the second electrical connection point 112 of the pre-wiring substrate 11 can be electrically connected to the first conductive protrusion 1242 of the first intermediate package structure 12 by soldering, and the third electrical connection point 113 of the pre-wiring substrate 11 can be electrically connected to the second conductive protrusion 1342 of the second intermediate package structure 13 by soldering.

[0155] In step 407, a first dielectric layer 15 is formed. The first dielectric layer 15 is located on the side of the first encapsulation layer 14 close to the pre-wiring substrate 11 and at least covers the side of the pre-wiring substrate 11.

[0156] In this embodiment, as Figure 29 As shown, a first dielectric layer 15 is formed on the side of the first encapsulation layer 14 near the pre-wiring substrate 11, and the first dielectric layer 15 covers the side of the pre-wiring substrate 11.

[0157] In this embodiment, the first dielectric layer 15 can be applied by lamination, spin coating, printing, molding or other suitable methods.

[0158] In step 408, the heat sink 16 is applied to the first encapsulation layer 14 to obtain the third intermediate transition structure 3001. The heat sink 16 is located on the side of the first intermediate encapsulation structure 12 and the second intermediate encapsulation structure 13 away from the pre-wired substrate 11, and is connected to the first heat dissipation layer 126 and the second heat dissipation layer 136 respectively.

[0159] In this embodiment, as Figure 30 As shown, a heat sink 16 is applied to the side of the first intermediate packaging structure 12 and the second intermediate packaging structure 13 away from the pre-wiring substrate 11, and the heat sink 16 is connected to the first heat dissipation layer 126 and the second heat dissipation layer 136 respectively.

[0160] In step 409, the third intermediate transition structure 3001 is cut to obtain the semiconductor package structure 1.

[0161] In this embodiment, as Figure 31 As shown, the third intermediate transition structure 3001 is cut according to the third cutting line 3101 to obtain the semiconductor packaging structure 1.

[0162] In this embodiment, when the semiconductor package structure 1 includes a first intermediate package structure 12 and a second intermediate package structure 13, the first intermediate package structure 12 includes a first die 121 and a first heat dissipation layer 126, and the second intermediate package structure 13 includes a second die 131 and a second heat dissipation layer 136. The first heat dissipation layer 126 is located on the back side of the first die 121, and the second heat dissipation layer 136 is located on the back side of the second die 131. The first heat dissipation layer 126 is used to dissipate heat from the first intermediate package structure 12, and the second heat dissipation layer 136 is used to dissipate heat from the second intermediate package structure 13. Furthermore, the semiconductor package structure 1 also includes a heat sink 16, which is located on the side of the first intermediate package structure 12 and the second intermediate package structure 13 away from the pre-wiring substrate 11, and is connected to the first heat dissipation layer 126 and the second heat dissipation layer 136 respectively. In this way, the heat sink 16 can achieve common heat dissipation of the first intermediate package structure 12 and the second intermediate package structure 13, thereby improving the heat dissipation performance of the semiconductor package structure 1.

[0163] Furthermore, the first intermediate packaging structure 12 and the second intermediate packaging structure 13 are repackaged to form a PIP (Package in Package) packaging structure. A pre-wiring substrate 11 is used to rewire the components between the first intermediate packaging structure 12 and the second intermediate packaging structure 13. Since the pre-wiring substrate 11 includes complex multi-circuit circuits, these pre-wiring substrates 11 with complex multi-circuit circuits rewire the components between the first intermediate packaging structure 12 and the second intermediate packaging structure 13, improving the performance of the entire packaging structure. In addition, replacing the fine wiring in the rewiring layer with the pre-wiring substrate 11 with complex multi-circuit circuits reduces the probability of short circuits, increases product yield, and reduces process complexity. In this way, a PIP packaging structure with complex circuitry can also be formed.

[0164] In this embodiment, the functions of the first intermediate packaging structure 12 and the second intermediate packaging structure 13 may be different. The first intermediate packaging structure 12 and the second intermediate packaging structure 13 with different functions are packaged in one packaging structure to achieve a specific function. This is called a multi-chip module (MCM), which has advantages such as small size, compact structure, high reliability, high performance and multi-functionality.

[0165] In this application, the hardware structure embodiments and method embodiments can complement each other without conflict. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0166] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor packaging method, characterized by, The semiconductor packaging method comprises: placing a first intermediate packaging structure and a second intermediate packaging structure on a first carrier plate, the first intermediate packaging structure comprising a first die and a first heat dissipation layer, the first die comprising a front surface and a back surface, the front surface and the back surface of the first die being opposite to each other, the front surface of the first die facing the first carrier plate, and the first heat dissipation layer being located at the back surface of the first die; the second intermediate packaging structure comprising a second die and a second heat dissipation layer, the second die comprising a front surface and a back surface, the front surface and the back surface of the second die being opposite to each other, the front surface of the second die facing the first carrier plate, and the second heat dissipation layer being located at the back surface of the second die; forming a first encapsulation layer on a side of the first carrier plate close to the first intermediate packaging structure and the second intermediate packaging structure, the first encapsulation layer at least covering side surfaces of the first intermediate packaging structure and the second intermediate packaging structure, and the first heat dissipation layer and the second heat dissipation layer being exposed from the first encapsulation layer; removing the first carrier plate; applying a pre-wiring substrate on the first encapsulation layer, the front surface of the first die facing the pre-wiring substrate, the front surface of the second die facing the pre-wiring substrate, the pre-wiring substrate having pre-wiring lines, and the first intermediate packaging structure and the second intermediate packaging structure being electrically connected to the pre-wiring lines, respectively; applying a heat sink on the first encapsulation layer, the heat sink being located on a side of the first intermediate packaging structure and the second intermediate packaging structure away from the pre-wiring substrate, and being connected to the first heat dissipation layer and the second heat dissipation layer, respectively.

2. The semiconductor packaging method of claim 1, wherein, The pre-wiring substrate further comprises a first electrical connection point located on a side of the pre-wiring substrate away from the heat sink; The pre-wiring substrate exposes the first electrical connection point; After the pre-wiring substrate is applied on the first encapsulation layer, the method further comprises: forming a first dielectric layer on a side of the first encapsulation layer close to the pre-wiring substrate, the first dielectric layer at least covering side surfaces of the pre-wiring substrate.

3. The semiconductor packaging method of claim 1, wherein Before the first intermediate packaging structure and the second intermediate packaging structure are placed on the first carrier plate, the method further comprises: packaging the first die to obtain the first intermediate packaging structure, and packaging the second die to obtain the second intermediate packaging structure.

4. The semiconductor packaging method of claim 3, wherein, The first die comprises a first silicon substrate, a first solder pad, and a first protective layer, the first silicon substrate comprising a front surface and a back surface, the front surface of the first silicon substrate facing the pre-wiring substrate, the first solder pad being located on the front surface of the first silicon substrate, and the first protective layer being located on the front surface of the first silicon substrate, the first protective layer comprising a first protective layer opening for exposing the first solder pad; The first intermediate packaging structure further comprises a second encapsulation layer, a first electrical connection part, and a first wiring layer. The packaging of the first die to obtain the first intermediate packaging structure comprises: placing the first die on a second carrier plate, the front surface of the first die facing the second carrier plate; forming a second encapsulation layer on a side of the second carrier plate close to the first die, covering at least a side of the first die and exposing a back of the first die; removing the second carrier plate; forming a first electrical connection part in the first protective layer opening and a first wiring layer on a side of the first protective layer away from the back of the first die and on a side of the second encapsulation layer away from the front of the first die, the first soldering pad being electrically connected to the first wiring layer through the first electrical connection part, the first wiring layer being configured to be electrically connected to the pre-wiring circuit; forming a first heat dissipation layer on the back of the first die and on a side of the second encapsulation layer away from the front of the first die.

5. The semiconductor packaging method of claim 3, wherein, The second die includes a second silicon substrate, a second soldering pad, and a second protective layer, the second silicon substrate including a front and a back, the front of the second silicon substrate facing the pre-wiring substrate, the second soldering pad being on the front of the second silicon substrate, and the second protective layer being on the front of the second silicon substrate, the second protective layer including a second protective layer opening configured to expose the second soldering pad. The second intermediate packaging structure further includes a third encapsulation layer, a second electrical connection part, and a second wiring layer. The packaging of the second die to obtain the second intermediate packaging structure includes: placing the second die on a third carrier plate, the front of the second die facing the third carrier plate; forming a third encapsulation layer on a side of the third carrier plate close to the second die, covering at least a side of the second die and exposing a back of the second die; removing the third carrier plate; forming a second electrical connection part in the second protective layer opening and a second wiring layer on a side of the second protective layer away from the back of the second die and on a side of the third encapsulation layer away from the front of the second die, the second soldering pad being electrically connected to the second wiring layer through the second electrical connection part, the second wiring layer being configured to be electrically connected to the pre-wiring circuit; forming a second heat dissipation layer on the back of the second die and on a side of the third encapsulation layer away from the front of the second die.

6. A semiconductor package structure, comprising: The semiconductor packaging structure is prepared by the semiconductor packaging method according to any one of claims 1 to 5, including: a pre-wiring substrate having a pre-wiring circuit. The first intermediate packaging structure and the second intermediate packaging structure are located on the pre-wiring substrate, and the first intermediate packaging structure and the second intermediate packaging structure are respectively electrically connected with the pre-wiring circuit; the first intermediate packaging structure comprises a first die and a first heat dissipation layer, the first die comprises a front surface and a back surface, the front surface and the back surface of the first die are opposite, the front surface of the first die faces the pre-wiring substrate, and the first heat dissipation layer is located on the back surface of the first die; the second intermediate packaging structure comprises a second die and a second heat dissipation layer, the second die comprises a front surface and a back surface, the front surface and the back surface of the second die are opposite, the front surface of the second die faces the pre-wiring substrate, and the second heat dissipation layer is located on the back surface of the second die; A first encapsulation layer is located on one side of the pre-wiring substrate close to the first intermediate packaging structure and the second intermediate packaging structure, and at least covers the side surface of the first intermediate packaging structure and the side surface of the second intermediate packaging structure; A heat sink is located on one side of the first intermediate packaging structure and the second intermediate packaging structure away from the pre-wiring substrate, and is connected with the first heat dissipation layer and the second heat dissipation layer respectively.

7. The semiconductor package structure of claim 6, wherein, The thickness of the first intermediate packaging structure is the same as the thickness of the second intermediate packaging structure; The first surface of the first intermediate packaging structure away from the pre-wiring substrate is flush with the second surface of the second intermediate packaging structure away from the pre-wiring substrate.

8. The semiconductor package structure of claim 6, wherein, Further comprising a first dielectric layer, the first dielectric layer is located on one side of the first encapsulation layer close to the pre-wiring substrate, and at least covers the side surface of the pre-wiring substrate; The pre-wiring substrate further comprises a first electrical connection point, the first electrical connection point is located on one side of the pre-wiring substrate away from the heat sink, and the pre-wiring substrate exposes the first electrical connection point.

9. The semiconductor package structure of claim 6, wherein, The first die comprises a first silicon substrate, a first solder pad and a first protective layer, the first silicon substrate comprises a front surface and a back surface, the front surface of the first silicon substrate faces the pre-wiring substrate, the first solder pad is located on the front surface of the first silicon substrate, and the first protective layer is located on the front surface of the first silicon substrate, the first protective layer comprises a first protective layer opening, and the first protective layer opening is used to expose the first solder pad; The first intermediate packaging structure further comprises a second encapsulation layer, a first electrical connection part and a first wiring layer, the second encapsulation layer is located on one side of the first heat dissipation layer close to the first die, and at least covers the side surface of the first die; the first electrical connection part is located in the first protective layer opening, the first wiring layer is located on one side of the first protective layer away from the first heat dissipation layer and one side of the second encapsulation layer away from the first heat dissipation layer; the first solder pad is electrically connected with the pre-wiring circuit through the first electrical connection part, the first wiring layer and the pre-wiring circuit.

10. The semiconductor package structure of claim 6, wherein, The second die comprises a second silicon substrate, a second solder pad and a second protective layer, the second silicon substrate comprises a front surface and a back surface, the front surface of the second silicon substrate faces the pre-wiring substrate, the second solder pad is located on the front surface of the second silicon substrate, the second protective layer is located on the front surface of the second silicon substrate, and the second protective layer comprises a second protective layer opening for exposing the second solder pad; The second intermediate packaging structure further comprises a third encapsulation layer, a second electrical connection part and a second wiring layer, the third encapsulation layer is located on the side of the second heat dissipation layer close to the second die and at least covers the side surface of the second die; the second electrical connection part is located in the second protective layer opening, and the second wiring layer is located on the side of the second protective layer away from the second heat dissipation layer and on the side of the third encapsulation layer away from the second heat dissipation layer; and the second solder pad is electrically connected through the second electrical connection part, the second wiring layer and the pre-wiring circuit.

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