Semiconductor device and method of forming the same

Abstract

Embodiments of the present invention provide a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a gate, a source / drain region, a first dielectric layer, an etch stop layer, a second dielectric layer, an additional dielectric layer, a conductive contact, and a bit line. The gate is on the substrate. The source / drain region is in the substrate and is laterally adjacent to the gate. The first dielectric layer is over the gate. The etch stop layer is on the first dielectric layer. The second dielectric layer is on the etch stop layer. The additional dielectric layer is in the second dielectric layer and the etch stop layer. The conductive contact passes through the first dielectric layer and is electrically connected to the source / drain region. The bit line passes through the second dielectric layer, the etch stop layer, and the additional dielectric layer, and is electrically connected to the conductive contact.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device and a method of forming the same BACKGROUND

[0002] A flash memory device has a bit line and a conductive contact, the bit line overlying the conductive contact and electrically coupled to a source / drain region of a select gate through the conductive contact. Typically, a top surface width of the conductive contact is formed to be larger than a bottom surface width of the bit line to facilitate alignment and contact of the bit line to the conductive contact. However, as the size of the flash memory design continues to shrink, shorting between the conductive contact and an adjacent bit line overlying the conductive contact is prone to occur. Therefore, how to avoid or reduce the shorting problem between the conductive contact and the bit line becomes a problem to be solved in the art. SUMMARY

[0003] Embodiments of the present application provide a flash memory device and a method of forming the same, which can avoid shorting between a conductive contact and a bit line.

[0004] Embodiments of the present application provide a semiconductor device, which includes a substrate, a gate, a source / drain region, a first dielectric layer, an etch stop layer, a second dielectric layer, an additional dielectric layer, a conductive contact, and a bit line. The gate is on the substrate. The source / drain region is in the substrate and laterally adjacent to the gate. The first dielectric layer is over the gate. The etch stop layer is on the first dielectric layer. The second dielectric layer is on the etch stop layer. The additional dielectric layer is in the second dielectric layer and the etch stop layer. The conductive contact passes through the first dielectric layer and is electrically connected to the source / drain region. The bit line passes through the second dielectric layer, the etch stop layer, and the additional dielectric layer, and is electrically connected to the conductive contact.

[0005] Embodiments of the present application provide a method of forming a semiconductor device, which includes forming a first dielectric layer; forming an etch stop layer on the first dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer and the etch stop layer to form an opening in the second dielectric layer and the etch stop layer; forming an additional dielectric layer in the opening; forming a patterned mask layer on the second dielectric layer and the additional dielectric layer; performing an etching process according to the patterned mask layer to remove some portions of the second dielectric layer, the additional dielectric layer, the etch stop layer, and the first dielectric layer, and form a bit line trench and a via; removing the patterned mask layer; and filling a conductive material in the bit line trench and the via to form a bit line in the bit line trench and a conductive contact in the via.

[0006] In summary, the present application forms an opening in the etch stop layer interposed in the dielectric layer and fills the opening with a dielectric material. Then, a single etch process is used to simultaneously form the bit line trench and the via in the dielectric layer and the etch stop layer. After that, a conductive material is formed in the bit line trench and the via to simultaneously form the bit line and the conductive contact. The conductive contact formed by this method is self-aligned with the bit line, and the top width of the conductive contact is not greater than the bottom width of the bit line. Therefore, the shorting problem between the conductive contact and other bit lines adjacent to the bit line above the conductive contact can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 shows a semiconductor device according to some embodiments of the present application;

[0008] Figure 2A shows a cross-sectional view of a semiconductor device according to some embodiments of the present application taken along the line I-I' of Figure 1 ;

[0009] Figure 2B shows a cross-sectional view of a semiconductor device according to some embodiments of the present application taken along the line II-II' of Figure 1 ;

[0010] Figures 3-8A , Figure 8B shows a cross-sectional view and a corresponding plan view or top view of a plurality of intermediate steps of a manufacturing method of a bit line and a conductive contact of a semiconductor device according to some embodiments;

[0011] Figure 4B , Figure 5B , Figure 7B , Figure 8B are plan views along the line A-A' of Figure 4A , Figure 5A , Figure 7A , Figure 8A respectively, and Figure 4A , Figure 5A , Figure 7A , Figure 8A are cross-sectional views taken along the line B-B' of Figure 4B , Figure 5B , Figure 7B , Figure 8B respectively;

[0012] Figure 6B is a top view of Figure 6A , and Figure 6A is a cross-sectional view taken along the line B-B' of Figure 6B . DETAILED DESCRIPTION

[0013] Figure 1 shows a semiconductor device 500 according to some embodiments of the present application.Figure 2A The following are some embodiments of the invention. Figure 1 A cross-sectional view of semiconductor device 500 taken by line I-I'. Figure 2B The following are some embodiments of the invention. Figure 1 A cross-sectional view of semiconductor device 500 taken from line II-II'.

[0014] Reference Figure 1 , Figure 2A as well as Figure 2B In some embodiments, the semiconductor device 500 may be or may include a memory device, such as a flash memory device. Figure 2A and Figure 2B As shown, the semiconductor device 500 includes a substrate 10. The substrate 10 is, for example, a semiconductor substrate, a semiconductor compound, or a semiconductor alloy. For example, the semiconductor substrate may include a silicon substrate. The silicon substrate may be an undoped silicon substrate or a doped silicon substrate. A doped silicon substrate may be an N-type doped silicon substrate or a P-type doped silicon substrate.

[0015] Substrate 10 includes multiple isolation structures 8 (in) Figure 2B (shown) and the active region 9 defined by the isolation structure 8. The material of the isolation structure 8 includes an insulating material, such as silicon oxide. In some embodiments, the isolation structure 8 may include a shallow trench isolation (STI) structure.

[0016] In some embodiments, such as Figure 2A As shown, a plurality of gate structures 15 and 18 are disposed on the active region 9 of the substrate 10. Gate structure 15 may include a tunneling dielectric layer 11, a floating gate 12, an inter-gate dielectric layer 13, and a control gate 14. Gate structure 18 includes, for example, a gate dielectric layer 16 and a select gate 17. Gate structure 18 may also be referred to as a select gate structure. In some embodiments, gate structure 18 includes gate structures 18a and 18b, and a plurality of gate structures 15 may be located between gate structures 18a and 18b. The materials of the floating gate 12, control gate 14, and select gate 17 may respectively include polysilicon, metal, or metal alloys, such as copper, aluminum, tungsten, or alloys thereof. The materials of the tunneling dielectric layer 11, the inter-gate dielectric layer 13, and the gate dielectric layer 16 respectively include suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0017] A plurality of source / drain regions 19 are disposed in the substrate 10 and are located at the sides of the plurality of gate structures 15 and 18. Some of the source / drain regions 19 can be located between the select gate structures 15 and the gate structures 18 and serve as common source / drain regions for the gate structures 15 and 18. The source / drain regions 19 can be doped regions disposed in the substrate 10 and can include P-type dopants or N-type dopants. P-type dopants include, for example, boron, and N-type dopants include, for example, phosphorus or arsenic.

[0018] In some embodiments, a dielectric layer 100 is disposed on the substrate 10. The material of the dielectric layer 100 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The dielectric layer 100 covers the sidewalls and top surfaces of the gate structures 15 and 18 and can be a single layer or a multi-layer structure. Conductive contacts 101 and 22 are embedded in the dielectric layer 100 and are electrically connected to the source / drain regions 19 of the gate structures 18a and 18b, respectively. The conductive contacts 101 and 22 can also be referred to as source / drain contacts. In some embodiments, a source line SL is disposed on the conductive contact 22 and is electrically connected to the source / drain regions 19 of the gate structure 18b through the conductive contact 22.

[0019] A dielectric layer 102, an etch stop layer 103, a dielectric layer 104, and a dielectric layer 106 Figure 2B are disposed on the dielectric layer 100. A bit line BL and a conductive contact 112 are embedded in the dielectric layer 102, the etch stop layer 103, the dielectric layer 104, and the dielectric layer 106 and are electrically connected to the conductive contact 101. In embodiments of the present application, the bit line BL and the conductive contact 112 are integrally formed, and there is no interface between the bit line BL and the conductive contact 112. The method of formation and structural features of the bit line BL and the conductive contact 112 will be described in detail below.

[0020] In some embodiments, the control gates 14 serve as word lines WL, and the select gates 17 serve as select gate lines SG. The select gate lines SG can include select gate lines SGD and SGS. For example, the select gate 17 in the gate structure 18a can serve as a select gate line SGD, and the select gate 17 in the gate structure 18b can serve as a select gate line SGS.

[0021] Reference is made to Figure 1 and Figure 2AIn some embodiments, the plurality of select gate lines SGS and SGD are disposed side-by-side with the plurality of word lines WL and can extend parallel to each other in direction Dl. The plurality of word lines WL can be located between the select gate lines SGS and the select gate lines SGD. The source lines SL are connected to the source / drain regions 19 at the side of the select gate lines SGS and can extend in direction Dl. In some embodiments, the bit lines BL are located above the select gate lines SGS and the word lines WL and extend in direction D2. The direction Dl and the direction D2 are, for example, parallel to the top surface of the substrate 10, and the direction D2 can be perpendicular to the direction Dl. The conductive contacts 112 are located below the bit lines BL and extend from the bottom of the bit lines BL to the conductive contacts 101 in direction D3. The direction D3 is, for example, perpendicular to the top surface of the substrate 10.

[0022] Figure 3 , Figure 4A , Figures 4B-8A , Figure 8B are cross-sectional views and corresponding plan or top views of a plurality of intermediate steps of a method of fabricating a bit line BL and a conductive contact 112 in a semiconductor device 500 according to some embodiments of the present disclosure. For brevity and clarity, Figures 3-8A Figure 8B only a portion of the semiconductor device 500 is shown, and some components (e.g., the substrate 10, the gate structures 15 / 18, etc.) are omitted in Figures 3-8A Figure 8B .

[0023] Referring to Figure 3 , in some embodiments, a dielectric layer 100 is formed on the substrate 10 Figure 2A . The method of forming the dielectric layer 100 can include a suitable deposition process, such as chemical vapor deposition (CVD). The conductive contacts 101 are formed in the dielectric layer 100. The conductive contacts 101 pass through the dielectric layer 100 to electrically connect with the source / drain regions 19 Figure 2A in the substrate located below the dielectric layer 100. The material of the conductive contacts 101 can include a metal or a metal alloy, such as copper, tungsten, aluminum, an alloy thereof, or a combination thereof. In some embodiments, the formation of the conductive contacts 101 can include the following processes: the dielectric layer 100 is patterned by a photolithography and etching process to form a via in the dielectric layer 100, and then a metal material is formed on the dielectric layer 100 using a suitable deposition process (e.g., CVD, physical vapor deposition (PVD)) to fill the via. After that, a planarization process is used to remove the excess metal material above the top surface of the dielectric layer 100. The metal material remaining in the via forms the conductive contacts 101. In some embodiments, the top surface of the conductive contacts 101 is substantially flush with the top surface of the dielectric layer 100.​​

[0024] Still referring to Figure 3 In some embodiments, dielectric layer 102, etch stop layer 103, and dielectric layer 104 are formed in sequence on dielectric layer 100 and conductive contacts 101, respectively, using suitable deposition processes (e.g., CVD). The materials of dielectric layer 102 and dielectric layer 104 are similar to the material of dielectric layer 100, and can be the same as or different from each other. The material of etch stop layer 103 is different from the materials of dielectric layer 102 and 104. For example, etch stop layer 103 comprises a dielectric material such as silicon nitride, silicon oxynitride, or the like. In some embodiments, the materials of dielectric layer 102 and 104 comprise silicon oxide, while the material of etch stop layer 103 comprises silicon nitride.

[0025] In some embodiments, a patterned mask layer 105 is formed on dielectric layer 104. Patterned mask layer 105 comprises, for example, a patterned photoresist. Patterned mask layer 105 has a plurality of mask openings 105a that expose portions of the top surface of dielectric layer 104. In some embodiments, the plurality of mask openings 105a are located at corresponding locations directly above conductive contacts 101, and the size (e.g., width, area) of mask openings 105a is greater than the top dimension of corresponding conductive contacts 101.

[0026] Referring to Figure 4A Dielectric layer 104, etch stop layer 103, and / or dielectric layer 102 are patterned to form openings OP. The patterning comprises an etching process using patterned mask layer 105 as an etching mask to remove portions of dielectric layer 104, etch stop layer 103, and / or dielectric layer 102 exposed by mask openings 105a, and form openings OP in dielectric layer 104, etch stop layer 103, and / or dielectric layer 102. In other words, openings 105a of patterned mask layer 105 are transferred into dielectric layer 104, etch stop layer 103, and / or dielectric layer 102 to form openings OP.

[0027] The opening OP extends at least through the dielectric layer 104 and the etch stop layer 103, and in some embodiments can further extend into the dielectric layer 102. In some embodiments, the etching process stops in the dielectric layer 102 such that a bottom surface of the opening OP exposes the dielectric layer 102 and is below a topmost surface of the dielectric layer 102. In some other embodiments, the etching process stops at the etch stop layer 103 is removed and a top surface of the dielectric layer 102 is just exposed, i.e., the etching process can not remove the dielectric layer 102 and a bottom surface of the opening OP can be substantially flush with a bottom surface of the etch stop layer 103. In other words, sidewalls of the opening OP expose the dielectric layer 104, the etch stop layer 103, and / or the dielectric layer 102. A bottom surface of the opening OP exposes the dielectric layer 102. In some embodiments, the opening OP has sloped sidewalls and has a dimension (e.g., width) that gradually decreases from top to bottom, but the present disclosure is not limited as such. In alternative embodiments, the opening OP can have substantially vertical sidewalls, i.e., the opening OP can have a uniform dimension (e.g., width) from top to bottom.

[0028] Figure 4B A plan view along line A-A' of Figure 4A , i.e., a top view of the etch stop layer 103 is shown. Figure 4A is a cross-sectional view taken along line B-B' of Figure 4B . As shown in Figure 4B , a plurality of openings 103a are located in the etch stop layer 103. The openings 103a are portions of the openings OP defined by sidewalls of the etch stop layer 103. In some embodiments, the plurality of openings 103a can be arranged in an array and two adjacent rows of the openings 103a can be staggered with respect to each other. In other words, the etch stop layer 103 is opened and has a plurality of openings 103a defined by sidewalls thereof.

[0029] Referring to Figure 4A and Figure 5AThe patterned mask layer 105 is removed, and a dielectric layer 106 is filled in the openings OP. The dielectric layer 106 can also be referred to as an additional dielectric layer. The material of the dielectric layer 106 is similar to the material of the dielectric layers 104, 102, and can be the same or different from the material of the dielectric layers 104 / 102, and different from the material of the etch stop layer 103. In some embodiments, the dielectric layer 106 comprises silicon oxide. The formation of the dielectric layer 106 can include the following processes: after the patterned mask layer 105 is removed, a dielectric material is formed using a suitable deposition process (e.g., CVD), which can be formed to fill the openings OP and cover the top surface of the dielectric layer 104. In some embodiments, a planarization process (e.g., a chemical mechanical polishing (CMP) process) is then performed to remove the dielectric material on the top surface of the dielectric layer 104, and the dielectric material remaining in the openings OP forms the dielectric layer 106. In some embodiments, the top surface of the dielectric layer 106 is substantially flush with the top surface of the dielectric layer 104. However, the present application is not limited thereto. In some alternative embodiments, the planarization process does not completely remove the dielectric material on the top surface of the dielectric layer 104, such that the dielectric layer 106 fills the openings OP and extends to cover the top surface of the dielectric layer 104.

[0030] Figure 5B A plan view along line A-A' of Figure 5A , i.e., an upper view of the etch stop layer 103 and part of the dielectric layer 106. Figure 5A is a cross-sectional view along line B-B' of Figure 5B . Referring to Figure 5A and Figure 5B , the dielectric layer 106 is on the dielectric layer 102, and is laterally surrounded by the dielectric layer 104, the etch stop layer 103, and / or the dielectric layer 102. The sidewall of the dielectric layer 106 is in contact with the dielectric layer 104, the etch stop layer 103, and / or the dielectric layer 102, and the bottom surface of the dielectric layer 106 is in contact with the dielectric layer 102. In other words, the openings 103a of the etch stop layer 103 that are opened are filled by the dielectric layer 106.

[0031] Referring to Figure 6AA mask layer 108 is formed on the dielectric layers 104 and 106. In some embodiments, the mask layer 108 is formed by a multi-patterning process, such as a self-aligned double patterning (SADP) process. For example, the mask layer 108 is formed by the following process: a plurality of photoresist patterns are formed on the dielectric layers 104 and 106 by a photolithography process. A hard mask layer is then formed on the dielectric layers 104 / 106 to cover the plurality of photoresist patterns. Thereafter, a back-etching process is performed to remove portions of the hard mask layer, leaving the hard mask layer covering the sidewalls of the photoresist patterns to form spacer walls of the photoresist patterns. The photoresist patterns are then removed, and the spacer walls constitute the mask layer 108.

[0032] Figure 6B is a top view of Figure 6A is a top view of Figure 6B is a top view of Figure 6A is a cross-sectional view taken along line B-B’ of

[0033] Referring to Figure 6A and Figure 6B , the mask layer 108 has a plurality of mask openings 108a. In some embodiments, the plurality of openings 108a are, for example, a plurality of trenches extending in parallel along a direction D2. Each opening 108a exposes a portion of a top surface of the dielectric layer 106 and a portion of a top surface of the dielectric layer 104, and a portion of the opening 108a is directly above the opening 103a of the etch stop layer 103 and the conductive contact 101. In other words, the opening 108a overlaps the opening 103a of the etch stop layer 103 and the conductive contact 101 in a direction D3. In some embodiments, a width of the opening 108a is no greater than (e.g., less than or substantially equal to) a width of the opening 103a. Herein, the width of the opening 108a and the width of the opening 103a refer to their widths in the direction D1.

[0034] Referring to Figure 7A , the dielectric layer 104, the dielectric layer 106, the etch stop layer 103, and the dielectric layer 102 are patterned to form trenches 109a and via holes 109b. The patterning includes performing an etching process using the mask layer 108 as an etching mask to remove some portions of the dielectric layer 104, the dielectric layer 106, the etch stop layer 103, and the dielectric layer 102 exposed by the openings 108a, and to form a plurality of openings 109. In some embodiments, each opening 109 includes a trench 109a and a via hole 109b that are in spatial communication with each other. The trench 109a can also be referred to as a bit line trench.

[0035] The plurality of trenches 109a extend parallel to each other along a direction D2, and the plurality of via holes 109b respectively extend downward from the bottom of the trenches 109a in a direction D3 to expose the top surface of the conductive contacts 101. The trenches 109a include a first portion FP and a second portion SP adjacent to and in communication with each other. The first portion FP extends at least through the dielectric layer 104 and the etch stop layer 103, and in some embodiments can further extend into the dielectric layer 102. The bottom surface of the first portion FP exposes the dielectric layer 102. The second portion SP is in spatial communication with the via holes 109b and extends through the dielectric layer 106 and the dielectric layer 102 to expose the top surface of the conductive contacts 101.

[0036] In some embodiments, the formation of the openings 109 includes removing some portions of the dielectric layer 104, the etch stop layer 103, and the dielectric layer 102 exposed by the mask openings 108a to form the first portion FP of the trenches 109a. The formation of the openings 109 also includes removing the portions of the dielectric layer 106 and the dielectric layer 102 thereunder exposed by the mask openings 108a to form the second portion SP of the trenches 109a and the via holes 109b. In some embodiments, the etchant used in the etching process has a high etch selectivity of the dielectric layers 106, 104, 102 (e.g., silicon oxide) to the etch stop layer 103 (e.g., silicon nitride). For example, the etching process has substantially the same etch rate for the dielectric layers 106 / 104 / 102, and has a first etch rate. The etching process has a second etch rate for the etch stop layer 103, and the second etch rate can be much lower than the first etch rate.

[0037] In the etching process, since the first portion FP of the trenches 109a requires removal of the etch stop layer 103, while the second portion SP of the trenches 109a and the via holes 109b do not require removal of the etch stop layer 103, the etching process removes the dielectric layers 106 and 102 at a faster etch rate to form the second portion BP of the trenches 109a and the deeper via holes 109b downward at the same time the etch stop layer 103 is removed to form the first portion FP of the trenches 109a. In some embodiments, at the time the etching process is stopped, the via holes 109b extend to expose the top surface of the conductive contacts 101, while the trenches 109a extend to expose the dielectric layer 102. The bottom surface of the trenches 109a can be substantially flush with the bottom surface of the etch stop layer 103 or below the topmost surface of the dielectric layer 102.

[0038] Figure 7B A plan view along line A-A' of Figure 7A is shown. Figure 7A is a cross-sectional view taken along line B-B' of Figure 7B is shown. Figure 7A and Figure 7BAs shown, portions of the dielectric layer 106 embedded in the etch stop layer 103 are removed. In some embodiments, the width Wl of the trench 109a is smaller than the width W2 of the dielectric layer 106, and the remaining portions of the dielectric layer 106 are located on opposite sides of the trench 109a and can be spaced apart by the trench 109a. The second portion SP of the trench 109a is located in the dielectric layer 106 and is defined at least by the sidewalls of the dielectric layer 106.

[0039] Referring to Figure 8A , the mask layer 108 is removed, and bit lines BL and conductive contacts 112 are formed in the trenches 109a and the via holes 109b. In some embodiments, the materials of the bit lines BL and the conductive contacts 112 can include metals or metal alloys, such as copper, aluminum, tungsten, alloys thereof, or combinations thereof. In some embodiments, the formation of the bit lines BL and the conductive contacts 112 includes the following processes: after the mask layer 108 is removed, a suitable deposition process, such as CVD / PVD, is used to form a conductive material on the dielectric layer 104 / 106 to fill the trenches 109a and the via holes 109b, and then a planarization process, such as CMP, is used to remove the excess portions of the conductive material above the top surfaces of the dielectric layer 104 / 106, leaving the conductive material in the trenches 109a to form the bit lines BL and leaving the conductive material in the via holes 109b to form the conductive contacts 112. In some embodiments, the top surfaces of the bit lines BL are substantially planar with the top surfaces of the dielectric layer 106 and the dielectric layer 104.

[0040] Figure 8B A plan view along Figure 8A line A-A' is shown. Figure 8A A cross-sectional view along Figure 8B line B-B' is shown.

[0041] Referring to Figure 8A and Figure 8B , in some embodiments, a plurality of bit lines BL extend along a direction D2 parallel to each other. The conductive contacts 112 are located between the bit lines BL and the conductive contacts 101 to electrically connect the bit lines BL to the conductive contacts 101. Each bit line BL includes a first portion 113a and a second portion 113b. The first portion 113a is located in the dielectric layer 104, the etch stop layer 103, and / or the dielectric layer 102. In some embodiments, the bottom surface of the first portion 113a is in contact with the dielectric layer 102 and can be substantially planar with or lower than the bottom surface of the etch stop layer 103 (or planar with or lower than the top surface of the dielectric layer 102). The sidewalls of the first portion 113a are in physical contact with the dielectric layer 104, the etch stop layer 103, and / or the dielectric layer 102. The second portion 113b of the bit line BL is located in the dielectric layer 106 and can further extend into the dielectric layer 102. The bottom surface of the second portion 113b is in contact with the dielectric layer 106, and the sidewalls of the second portion 113b are in physical contact with the dielectric layer 106. Figure 8AThe second portion 113b is substantially flush with the bottom surface of the first portion 113a and in contact with the conductive contact 112. The sidewall of the second portion 113b is surrounded by and in physical contact with the dielectric layer 106. In some embodiments, the second portion 113b is spaced apart from the dielectric layer 104 and the etch stop layer 103 by the dielectric layer 106 therebetween. The bottom surface of the bit line 113 can be higher than, substantially flush with, or lower than the bottom surface of the dielectric layer 106. The conductive contact 112 is embedded in the dielectric layer 102 and laterally surrounded by the dielectric layer 102. In some embodiments, the conductive contact 112 is embedded in both the dielectric layer 102 and the dielectric layer 106 and its sidewall is in contact with both the dielectric layers 102 and 106.

[0042] The bit line BL is integrally formed with the conductive contact 112. There is no interface between the bit line BL and the conductive contact 112. The top width Wt of the conductive contact 112 is not greater than the bottom width Wb of the bit line BL. In some embodiments, the top width Wt of the conductive contact 112 is substantially equal to the bottom width Wb of the bit line. It is noted that the top width Wt of the conductive contact 112 and the bottom width Wb of the bit line BL referred to herein are the width thereof in the direction Dl.

[0043] In embodiments of the present application, the bit line trench and the via are formed by one etching process, followed by filling the conductive material in the bit line trench and the via to simultaneously form the bit line and the conductive contact. In this way, the bit line and the conductive contact are integrally formed, which can avoid or reduce the risk of short circuit between the conductive contact and the bit line adjacent thereto. In addition, the etching process and the depth of the via can be better controlled by adjusting the thickness of the etch stop layer.

[0044] Although the present application has been disclosed in its embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, and the scope of protection of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: a substrate; a gate over the substrate; a source / drain region in the substrate laterally adjacent to the gate; a first dielectric layer over the gate; an etch stop layer over the first dielectric layer; a second dielectric layer over the etch stop layer; an additional dielectric layer in the second dielectric layer, the etch stop layer, and the first dielectric layer, wherein the additional dielectric layer extends through the second dielectric layer and the etch stop layer and into the first dielectric layer, wherein sidewalls of the additional dielectric layer are in contact with the first dielectric layer, the etch stop layer, and the second dielectric layer, and a bottom surface of the additional dielectric layer connected to the sidewalls is in contact with the first dielectric layer; a conductive contact through the first dielectric layer and electrically connected to the source / drain region; and a bit line through the second dielectric layer, the etch stop layer, and the additional dielectric layer and extending into the first dielectric layer and electrically connected to the conductive contact, wherein the bit line comprises: a first portion in the first dielectric layer, the second dielectric layer, and the etch stop layer, wherein a bottom surface of the first portion is in contact with the first dielectric layer, and sidewalls of the first portion are in physical contact with the second dielectric layer, the etch stop layer, and the first dielectric layer; and a second portion in the additional dielectric layer and the first dielectric layer, sidewalls of the second portion are surrounded by and in physical contact with the additional dielectric layer, and wherein the second portion is connected to the first portion and overlies the conductive contact, wherein the second portion is spaced apart from the second dielectric layer and the etch stop layer by the additional dielectric layer, wherein the bit line is monolithically formed with the conductive contact, and there is no interface between the bit line and the conductive contact, wherein the bit line extends in a first direction, a top width of the conductive contact is no greater than a bottom width of the bit line in a second direction, the second direction is perpendicular to the first direction.

2. The semiconductor device of claim 1, further comprising: an inner dielectric layer between the first dielectric layer and the substrate, covering sidewalls and a top surface of the gate; and a source / drain contact in the inner dielectric layer and connected to the source / drain region, wherein the conductive contact is electrically connected to the source / drain region through the source / drain contact.

3. A method of forming a semiconductor device, comprising: forming a first dielectric layer; forming an etch stop layer over the first dielectric layer; forming a second dielectric layer over the etch stop layer; patterning the first dielectric layer, the second dielectric layer, and the etch stop layer to form an opening in the second dielectric layer, the etch stop layer, and the first dielectric layer, wherein the opening extends into the first dielectric layer, and a bottom surface of the opening is higher than a bottom surface of the first dielectric layer; forming an additional dielectric layer in the opening; forming a patterned mask layer over the second dielectric layer and the additional dielectric layer; ​ ​ ​ performing an etching process according to the patterned mask layer, wherein the etching process comprises: removing a portion of the second dielectric layer, a portion of the etch stop layer under the second dielectric layer, and a portion of the first dielectric layer under the etch stop layer to form a first portion of a bit line trench, wherein a bottom surface of the first portion exposes the first dielectric layer; and removing a portion of the additional dielectric layer and a portion of the first dielectric layer under the additional dielectric layer to form a second portion of the bit line trench and a via under the second portion, wherein the second portion and the via are in spatial communication with each other and pass through the additional dielectric layer and the first dielectric layer, wherein a sidewall of the remaining additional dielectric layer is in contact with the first dielectric layer, the etch stop layer, and the second dielectric layer, and a bottom surface of the remaining additional dielectric layer connected to the sidewall is in contact with the first dielectric layer; removing the patterned mask layer; and filling the first portion of the bit line trench, the second portion of the bit line trench, and the via with a conductive material to form a bit line in the bit line trench and a conductive contact in the via, wherein the bit line and the conductive contact are integrally formed, and there is no interface between the bit line and the conductive contact, wherein the bit line extends in a first direction, a top width of the conductive contact is not greater than a bottom width of the bit line in a second direction, and the second direction is perpendicular to the first direction.

4. The method of claim 3, wherein the patterned mask layer has a mask opening to expose a portion of the second dielectric layer and a portion of the additional dielectric layer, and the mask opening is disposed directly above the portion of the additional dielectric layer embedded in the etch stop layer.

5. The method of claim 4, wherein a width of the mask opening is less than a width of the portion of the additional dielectric layer.

6. The method of claim 3, wherein the bit line is electrically connected to a source / drain contact through the conductive contact, and the source / drain contact is connected to a source / drain region of a select gate.

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