Method of manufacturing a semiconductor device

Abstract

The present disclosure provides a method of manufacturing a semiconductor device. A semiconductor device and a method for manufacturing the semiconductor device. The method includes the following steps: forming a stacked structure including a lower-level sacrificial layer above a semiconductor substrate; forming a slit that penetrates the stacked structure and exposes the lower-level sacrificial layer; forming spacers on sidewalls of the slit; forming a horizontal recess by removing the lower-level sacrificial layer; forming a conductive material in each of the horizontal recesses; etching the conductive material to form source-channel contact portions respectively filling the horizontal recesses, and forming a separation groove between the source-channel contact portions; and forming an etch barrier material filling the separation groove.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device. Background Art

[0002] Manufacturing electronic devices such as semiconductor devices requires gap-fill for three-dimensional (3D) structures or high aspect ratio structures. For example, when manufacturing vertical semiconductor devices, gap-fill of high aspect ratio structures is performed. Summary of the Invention

[0003] According to one embodiment, a method for manufacturing a semiconductor device may include the steps of: forming a stacked structure including a lower-level sacrificial layer above a semiconductor substrate; forming a slit that penetrates the stacked structure and exposes the lower-level sacrificial layer; forming spacers on sidewalls of the slit; forming a horizontal recess by removing the lower-level sacrificial layer; forming a conductive material in each of the horizontal recesses; etching the conductive material to form source-channel contact portions respectively filling the horizontal recesses, and forming a separation groove between the source-channel contact portions; and forming an etch barrier material filling the separation groove.

[0004] According to one embodiment, a method for manufacturing a semiconductor device may include the steps of: forming a lower-level stack including a sacrificial source layer above a semiconductor substrate and an upper-level stack above the lower-level stack, in which a plurality of insulating layers and a plurality of sacrificial layers are alternately stacked; forming a plurality of vertical channel structures, each of the plurality of vertical channel structures including a channel layer that penetrates the upper-level stack and the lower-level stack; forming a slit that divides the upper-level stack into a first alternately stacked body and a second alternately stacked body; expanding the slit by partially etching the lower-level stack to expose the sacrificial source layer; forming spacers on sidewalls of the slit; forming a horizontal recess extending from the slit by removing the sacrificial source layer; forming source-channel contact portions respectively filling the horizontal recesses, and a separation groove between the source-channel contact portions; and forming an etch barrier material filling the separation groove.

[0005] According to one embodiment, a semiconductor device may include: a source-level stack including a first horizontal recess and a second horizontal recess; a gate stack including a gate electrode and an insulating layer above the source-level stack; a vertical channel including a channel layer that penetrates the gate stack and the source-level stack; source-channel contact portions respectively filling the first horizontal recess and the second horizontal recess; and a separation groove located between the source-channel contact portions, wherein the source-channel contact portions may include embedded voids, and an exposed side of the source-channel contact portions may be oxide-free, and the source-channel contact portions are exposed through the separation groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 and Figure 2 are diagrams illustrating a vertical semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 and Figure 17 are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0008] The various embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams that are ideal schematic diagrams of the present disclosure. Therefore, the structure of the drawings may be modified due to manufacturing techniques and / or tolerances. The embodiments of the present disclosure are not limited to the specific structures shown in the drawings, but include any changes in the structures that can be produced according to the manufacturing process. In addition, any regions and region shapes shown in the drawings are schematic diagrams, intended to illustrate specific examples of the regional structures of the respective elements, and are not intended to limit the scope of the embodiments.

[0009] The various embodiments of the present disclosure provide a method for manufacturing a semiconductor device capable of improving reliability.

[0010] In the present disclosure, voids or seams in the source-channel contact portion can be prevented or mitigated by forming an etch barrier material containing carbon.

[0011] The present disclosure can improve the reliability and yield of semiconductor devices by preventing or mitigating the erosion of voids or seams in the source-channel contact portion.

[0012] Figure 1 and Figure 2 are diagrams showing a vertical semiconductor device according to an embodiment. Figure 2 is a cross-sectional view taken along line A-A’ of Figure 1 .

[0013] Referring to Figure 1 and Figure 2, the vertical semiconductor device 100 may include a 3D structure NAND. The vertical semiconductor device 100 may include a semiconductor substrate 101, a source level stack 110 on the semiconductor substrate 101, and a plurality of gate stacks 120 on the source level stack 110. The source level stack 110 may include source layers 102 and 103 and a plurality of source channel contacts 104.

[0014] The gate stack 120 may be a stack including a gate electrode. In each gate stack 120, an insulating layer 105 and a gate electrode 106 may be alternately stacked. The insulating layer 105 at the lowest height among the insulating layers 105 may be thicker than the other insulating layers among the insulating layers 105. The insulating layer 105 may include silicon oxide. The gate electrode 106 may include a metal-based material. The gate electrode 106 may include tungsten or a stack of titanium nitride and tungsten. The gate electrode 106 may be referred to as a word line.

[0015] The vertical semiconductor device 100 may further include a vertical channel structure 130 that penetrates the gate stack 120 and the source level stack 110. Each vertical channel structure 130 may include a memory layer, a channel layer 134, and a core insulating layer 135. The core insulating layer 135 may fill the space inside the channel layer 134. The memory layer may surround the outer wall of the channel layer 134. The memory layer may be a stacked structure including a blocking layer 131, a charge trapping layer 132, and a tunnel insulating layer 133. The tunnel insulating layer 133 may be formed on the channel layer 134. The charge trapping layer 132 may be formed on the tunnel insulating layer 133. The blocking layer 131 may be formed on the charge trapping layer 132. The blocking layer 131 and the tunnel insulating layer 133 may include silicon oxide. The charge trapping layer 132 may include silicon nitride. The memory layer may have an oxide-nitride-oxide (ONO) structure. The channel layer 134 may include a polysilicon layer. The channel layer 134 may have a cylindrical shape including an internal space. The outer wall of the channel layer 134 may be surrounded by the memory layer. The internal space of the channel layer 134 may be completely filled by the core insulating layer 135. The core insulating layer 135 may include silicon oxide or silicon nitride. The charge trapping layer 132 may be referred to as a charge storage layer or a data storage layer. The charge trapping layer 132 may be formed of a charge trapping material.

[0016] The lower part of the vertical channel structure 130 may penetrate the source level stack 110. The upper part of the vertical channel structure 130 may penetrate the gate stack 120. The vertical semiconductor device 100 may further include a slit 140 between the gate stacks 120. The slit 140 may be spaced apart from the vertical channel structure 130. The slit 140 may have a trench shape. Adjacent gate stacks 120 may be spaced apart by the slit 140.

[0017] A detailed description of the source electrode level stack 110 is as follows.

[0018] The source electrode level stack 110 may include source electrode layers 102 and 103 and a source electrode channel contact portion 104 between the source electrode layers 102 and 103. The source electrode layers 102 and 103 may include a lower source electrode layer 102 and an upper source electrode layer 103, respectively. The vertical channel structure 130 may penetrate the lower source electrode layer 102 and the upper source electrode layer 103.

[0019] The source electrode level stack 110 may further include a horizontal recess 106. The horizontal recess 106 may be defined between the lower source electrode layer 102 and the upper source electrode layer 103. Adjacent horizontal recesses 106 may be spaced apart by a separation groove 107. The separation groove 107 may extend vertically from a slit 140. The slit 140 may penetrate the upper source electrode layer 103. Adjacent upper source electrode layers 103 may be spaced apart from each other by the slit 140. Adjacent source electrode channel contact portions 104 may be spaced apart from each other by the separation groove 107. The source electrode channel contact portion 104 may be formed in each of the horizontal recesses 106. The source electrode channel contact portion 104 may be formed between the lower source electrode layer 102 and the upper source electrode layer 103. The source electrode channel contact portion 104 may fill the horizontal recess 106. The lower source electrode layer 102 and the upper source electrode layer 103 may be made of the same material (e.g., a semiconductor material such as polysilicon). The source electrode channel contact portion 104 may include a semiconductor material such as polysilicon.

[0020] Each source electrode channel contact portion 104 may include a void 104V. The separation groove 107 may be formed between adjacent source electrode channel contact portions 104. The voids 104V may be spaced apart from each other by the separation groove 107. The separation groove 107 and the slit 140 may be vertically connected. The side wall of the separation groove 107 may include a rounded side wall.

[0021] The source electrode channel contact portion 104 may include a phosphorus-doped polysilicon layer. In another embodiment, the source electrode channel contact portion 104 may include a phosphorus-doped epitaxial silicon layer.

[0022] As described above, the channel layer 134 and the source electrode channel contact portion 104 may be in direct contact with each other. The void 104V may be included in the source electrode channel contact portion 104. The void 104V may be referred to as an embedded void. The rounded side wall of the source electrode channel contact portion 104 may be oxide-free.

[0023] Figures 3 to 17 It is a diagram illustrating a method of manufacturing a vertical semiconductor device according to an embodiment. Hereinafter, Figures 3 to 17 may be alongFigure 1 Cross-sectional view taken along line A-A'.

[0024] As Figure 3 shown, a stacked structure may be formed on a semiconductor substrate 11. The stacked structure may include a lower level stack and an upper level stack. The lower level stack may include a lower source layer 12, an upper source layer 16, liner layers 13 and 15, and a sacrificial source layer 14. The sacrificial source layer 14 may be formed between the lower source layer 12 and the upper source layer 16. The liner layer 13 may be formed between the sacrificial source layer 14 and the lower source layer 12. The liner layer 15 may be formed between the sacrificial source layer 14 and the upper source layer 16. The lower source layer 12, the sacrificial source layer 14, and the upper source layer 16 may be made of the same material. The liner layers 13 and 15 may be made of a material different from that of the lower source layer 12, the sacrificial source layer 14, and the upper source layer 16. The lower source layer 12, the sacrificial source layer 14, and the upper source layer 16 may have an etching selectivity with respect to the liner layers 13 and 15. The lower source layer 12, the sacrificial source layer 14, and the upper source layer 16 may include a semiconductor material. The liner layers 13 and 15 may include an insulating material. The lower source layer 12, the sacrificial source layer 14, and the upper source layer 16 may include polysilicon. The liner layers 13 and 15 may include silicon oxide. The liner layers 13 and 15 may be thinner than the lower source layer 12, the sacrificial source layer 14, and the upper source layer 16. For example, the liner layer 13 may be thinner than any one of the lower source layer 12, the sacrificial source layer 14, and the upper source layer 16. For example, the liner layer 15 may be thinner than any one of the lower source layer 12, the sacrificial source layer 14, and the upper source layer 16.

[0025] The upper-level stack may include an insulating layer 17 and a sacrificial layer 18 stacked on the upper source electrode layer 16. In the upper-level stack, the insulating layer 17 and the sacrificial layer 18 may be alternately stacked. The insulating layer 17 and the sacrificial layer 18 may be alternately stacked several times. The insulating layer 17 and the sacrificial layer 18 may be made of different materials. The insulating layer 17 may have an etching selectivity with respect to the sacrificial layer 18. The insulating layer 17 may include silicon oxide, and the sacrificial layer 18 may include silicon nitride. The insulating layer 17 and the sacrificial layer 18 may have the same thickness. The insulating layer 17 and the sacrificial layer 18 may be thicker than the cushion layers 13 and 15. For example, the insulating layer 17 may be thicker than any one of the cushion layers 13 and 15. For example, the sacrificial layer 18 may be thicker than any one of the cushion layers 13 and 15. The insulating layer 17 and the sacrificial layer 18 may be thinner than the lower source electrode layer 12 and the upper source electrode layer 16. For example, the insulating layer 17 may be thinner than any one of the lower source electrode layer 12 and the upper source electrode layer 16. For example, the sacrificial layer 18 may be thinner than any one of the lower source electrode layer 12 and the upper source electrode layer 16. Among the insulating layers 17, the insulating layer 17 at the lowest height may be thicker than the other insulating layers 17 among the insulating layers 17. For example, as Figure 3 shown, the insulating layer 17 at the lowest height is thicker than the other insulating layers 17 among the insulating layers 17.

[0026] The insulating layer 17 and the sacrificial layer 18 may be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0027] The sacrificial source electrode layer 14 may be referred to as a lower-level sacrificial layer or a source electrode-level sacrificial layer. The sacrificial layer 18 may be referred to as an upper-level sacrificial layer or a gate-level sacrificial layer. As will be described later, the sacrificial source electrode layer 14 may be replaced by a source channel contact portion. The sacrificial layer 18 may be replaced by a gate electrode.

[0028] As Figure 4 shown, a vertical opening 19 may be formed. The insulating layer 17, the sacrificial layer 18, the upper source electrode layer 16, the cushion layers 13 and 15, the sacrificial source electrode layer 14, and the lower source electrode layer 12 may be etched to form the vertical opening 19.

[0029] The vertical opening 19 may be formed perpendicular to the surface of the semiconductor substrate 11. The vertical opening 19 may have a shape that penetrates the insulating layer 17 and the sacrificial layer 18. The vertical opening 19 may extend to penetrate the upper source electrode layer 16, the cushion layers 13 and 15, the sacrificial source electrode layer 14, and the lower source electrode layer 12. Although not shown, when observed in a plan view, a plurality of vertical openings 19 may be formed and the plurality of vertical openings 19 may have a hole array structure. When the vertical opening 19 is formed, the surface of the semiconductor substrate 11 may be partially recessed. In another embodiment, the vertical opening 19 may be referred to as a "vertical recess", a "vertical hole", or a "channel hole".

[0030] As Figure 5 shown, the vertical channel structure 20 can be formed in the vertical opening 19. The vertical channel structure 20 can fill the vertical opening 19. The vertical channel structure 20 can be referred to as a "columnar structure".

[0031] The vertical channel structure 20 can include a memory layer, a channel layer 24, and a core insulating layer 25. The memory layer can have a stacked structure including a barrier layer 21, a charge trapping layer 22, and a tunnel insulating layer 23. The barrier layer 21 and the tunnel insulating layer 23 can include oxides. The charge trapping layer 22 can include nitrides. The memory layer can have an oxide-nitride-oxide (ONO) structure. The channel layer 24 can include a semiconductor material or an oxide semiconductor material. The channel layer 24 can include polysilicon or InGaZnO (IGZO). The channel layer 24 can have a cylindrical shape including an internal space. The memory layer can surround the outer wall of the channel layer 24. The internal space of the channel layer 24 can be completely or partially filled by the core insulating layer 25. The core insulating layer 25 can include silicon oxide or silicon nitride.

[0032] As Figure 6 shown, the slit 26 can be formed. The slit 26 can be formed by etching the insulating layer 17 and the sacrificial layer 18. To form the slit 26, the insulating layer 17 and the sacrificial layer 18 can be etched, and the upper source electrode layer 16 can be etched subsequently. The bottom surface of the slit 26 can penetrate the upper source electrode layer 16. The slit 26 can also be referred to as a trench. When viewed from a top view, the slit 26 can have a linear shape extending in any direction. The slit 26 can be formed perpendicular to the surface of the semiconductor substrate 11. The slit 26 can be referred to as a vertical slit.

[0033] With the formation of the slit 26, the upper-level laminate including the insulating layer 17 and the sacrificial layer 18 can be divided into a plurality of alternating laminates. For example, the upper-level laminate can be divided into a first alternating laminate M1 and a second alternating laminate M2 by the slit 26. In each of the first alternating laminate M1 and the second alternating laminate M2, a plurality of insulating layers 17 and a plurality of sacrificial layers 18 can be alternately laminated. A plurality of vertical channel structures 20 can penetrate the first alternating laminate M1 and the second alternating laminate M2.

[0034] As Figure 7 shown, the spacer 27 can be formed on the sidewalls of the slit 26. The spacer 27 can include at least one of spacer materials. The spacer 27 can include an oxide, a nitride, or a combination thereof. For example, the spacer 27 can include a nitride-oxide-nitride laminate (i.e., a nitride-oxide-nitride (NON) structure).

[0035] As Figure 8As shown, the spacer 27 can be used as a barrier to etch the liner layer 15 and the sacrificial source layer 14. The liner layer 13 and the lower source layer 12 can be left unetched.

[0036] Next, the sacrificial source layer 14 can be selectively removed through the slit 26. Accordingly, the horizontal recesses 28A and 28B can be formed. The horizontal recesses 28A and 28B can extend from the slit 26. The horizontal recesses 28A and 28B can be formed between the liner layers 13 and 15 by removing the sacrificial source layer 14 via a dip-out process. The horizontal recesses 28A and 28B can be parallel to the surface of the semiconductor substrate 11. When the sacrificial source layer 14 is removed, the liner layers 13 and 15 can be left unremoved due to the etching selectivity. The horizontal recesses 28A and 28B can be formed between the lower source layer 12 and the upper source layer 16. When the sacrificial source layer 14 is removed, the lower source layer 12 and the upper source layer 16 can be left unremoved. A wet etching can be applied to remove the sacrificial source layer 14. Since the sacrificial source layer 14 includes a polysilicon layer, the wet etching can include a chemical capable of etching the polysilicon layer.

[0037] The horizontal recesses 28A and 28B can expose the lower outer wall of the vertical channel structure 20. The lower outer wall of the vertical channel structure 20 can be part of the blocking layer 21. The horizontal recesses 28A and 28B can have a shape surrounding the lower outer wall of the vertical channel structure 20.

[0038] As Figure 9 shown, the liner layers 13 and 15 can be removed. Accordingly, the volume of the horizontal recesses 28A and 28B can be increased. As indicated by the reference numerals “29A” and “29B”, the horizontal recesses with an enlarged volume can be formed. Hereinafter, the horizontal recesses with an enlarged volume will be referred to as the horizontal recesses 29A and 29B.

[0039] Next, the lower outer wall of the vertical channel structure 20 can be partially removed through the horizontal recesses 29A and 29B. For example, a part of the memory layers (i.e., the blocking layer 21, the charge trapping layer 22, and the tunnel insulating layer 23) can be removed through the horizontal recesses 29A and 29B. Accordingly, the lower outer wall of the channel layer 24 of the vertical channel structure 20 can be exposed. In another embodiment, when the blocking layer 21, the charge trapping layer 22, and the tunnel insulating layer 23 are additionally etched, an undercut may be formed between the channel layer 24 and the lower source layer 12 and between the channel layer 24 and the upper source layer 16.

[0040] Through the series of processes described above, the horizontal recesses 29A and 29B can expose the lower outer wall of the channel layer 24.

[0041] The horizontal recesses 29A and 29B may have a first surface that is parallel to the semiconductor substrate 11. The slit 26 may extend from the horizontal recesses 29A and 29B and have a second surface that is perpendicular to the surface of the semiconductor substrate 11. That is, a gap-fill target structure including the horizontal recesses 29A and 29B having the first surface and the slit having the second surface may be formed on the semiconductor substrate 11. The first surface may be provided by the channel layer 24, the lower source layer 12, and the upper source layer 16. In one embodiment, the first surface may be provided by the memory layer, the lower source layer 12, and the upper source layer 16. The second surface may be provided by the spacer 27. The first surface may be the surface of a silicon layer, and the second surface may be the surface of an insulating material.

[0042] As Figure 10 shown, a source contact layer 30 may be formed. The source contact layer 30 may be formed by a process of depositing a semiconductor material. The semiconductor material may include a polysilicon layer. The source contact layer 30 may fill the horizontal recesses 29A and 29B and may be conformally formed on the spacer 27. The source contact layer 30 may not fill the slit 26. The source contact layer 30 may include seams or voids 30V. That is, the source contact layer 30 may be formed of a semiconductor material embedded in the voids. In one embodiment, the source contact layer 30 may include a conductive material.

[0043] As Figure 11 shown, the source contact layer 30 may be selectively removed to form source-channel contact portions 31A and 31B that respectively fill the horizontal recesses 29A and 29B. The source contact layer 30 may be selectively removed using wet etching. After the wet etching, the corresponding side surfaces of the source-channel contact portions 31A and 31B may be exposed.

[0044] Adjacent source-channel contact portions 31A and 31B may be spaced apart from each other by a separation groove 32. The separation groove 32 and the slit 26 may be connected to each other. The corresponding side surfaces of the adjacent source-channel contact portions 31A and 31B may be exposed by the separation groove 32.

[0045] Through the series of processes described above, the horizontal recesses 29A and 29B may be filled by the source-channel contact portions 31A and 31B, respectively. The source-channel contact portions 31A and 31B may not be formed in the slit 26. The source-channel contact portions 31A and 31B may include voids 30V. The source-channel contact portions 31A and 31B may directly contact the channel layer 24 of the vertical channel structure 20. The corresponding side surfaces of the source-channel contact portions 31A and 31B exposed by the separation groove 32 may be oxide-free. Here, oxide-free may refer to a surface on which no oxide is formed. In one embodiment, the source-channel contact portions 31A and 31B may include a conductive material.

[0046] The lower source electrode layer 12, the upper source electrode layer 16, and the source electrode channel contact portions 31A and 31B may form a source electrode layer stack.

[0047] As Figure 12 shown, an etch barrier material 33 may be formed to cover the corresponding side surfaces of the source electrode channel contact portions 31A and 31B exposed through the isolation grooves 32. The etch barrier material 33 may gap-fill the isolation grooves 32. For example, after forming an etch barrier material layer (not shown) to fill the isolation grooves 32 and the slits 26, the etch barrier material layer may be etched back in-situ to form the etch barrier material 33.

[0048] The etch barrier material 33 may prevent or mitigate the exposure of the source electrode channel contact portions 31A and 31B in subsequent processes. The etch barrier material 33 may protect the source electrode channel contact portions 31A and 31B from the subsequent removal process of the spacer 27. That is, the etch barrier material 33 may prevent or mitigate the erosion of the exposed surfaces of the source electrode channel contact portions 31A and 31B and the voids 30V.

[0049] The etch barrier material 33 may include a void-free carbon-based material. The etch barrier material 33 may include a void-free carbon layer. The carbon-based material as the etch barrier material 33 has excellent gap-filling characteristics, and thus the isolation grooves 32 can be filled with the etch barrier material 33 without voids. In another embodiment, the etch barrier material 33 may include a material having high selectivity with respect to subsequent wet etching in addition to the carbon layer. The etch barrier material 33 may include a material that is not etched during the wet etching of the spacer 27. For example, when the spacer 27 includes silicon nitride, the etch barrier material 33 may be a material having high selectivity with respect to the wet etching of silicon nitride. When the spacer 27 includes silicon oxide, the etch barrier material 33 may be a material having high selectivity with respect to the wet etching of silicon oxide.

[0050] As a comparative example, when the etch barrier material 33 is conformally and thinly formed on the sidewalls of the isolation grooves 32, there may be limitations in protecting the voids 30V of the source electrode channel contact portions 31A and 31B during subsequent wet etching. As another comparative example, when there are seams or voids in the etch barrier material 33, it is difficult to block the path of the wet chemicals in the subsequent wet etching process.

[0051] As a comparative example, the oxide covering the void 30V can be formed on the respective sides of the source channel contacts 31A and 31B by selective oxidation without forming the etch barrier material 33. However, since the oxide cannot obtain sufficient selectivity with respect to highly selective phosphoric acid (HSP) in the subsequent wet etching, a path is formed that penetrates into the source channel contacts 31A and 31B.

[0052] In the present embodiment, since the etch barrier material 33 has excellent gap filling characteristics and gap fills the isolation grooves 32 without voids, the exposure of the void 30V during the subsequent process can be prevented or reduced. Since the etch barrier material 33 has high selectivity with respect to the subsequent wet chemicals, the void 30V can be prevented or reduced from being eroded.

[0053] The upper surface of the etch barrier material 33 can be at a height that covers at least the bottom of the spacer 27. The etch barrier material 33 can have a height that does not expose the lower source layer 12, the upper source layer 16, and the source channel contacts 31A and 31B. The top surface of the etch barrier material 33 and the top surface of the upper source layer 16 can be at the same height.

[0054] As a method of forming the etch barrier material 33, a deposition-etch-deposition (DED) method can be used. The method of forming the etch barrier material 33 according to the DED method can repeat the process of forming the etch barrier material layer and etching the etch barrier material layer. For example, instead of filling the isolation grooves 32 and the slits 26 with a carbon layer in one deposition process, the carbon layer deposition process and the etching process of the carbon layer can be repeated to selectively fill the isolation grooves 32.

[0055] The respective voids 30V of the source channel contacts 31A and 31B can be covered by the etch barrier material 33. The respective sides of the source channel contacts 31A and 31B that contact the etch barrier material 33 can be oxide-free.

[0056] As Figure 13 shown, a part of the spacer 27 can be removed. Wet etching using wet chemicals can be performed to remove the spacer 27. For example, when the spacer 27 includes silicon nitride, highly selective phosphoric acid (HSP) can be used to remove the spacer 27.

[0057] As described above, when the spacer 27 is removed, the source channel contacts 31A and 31B can be protected by the etch barrier material 33. For example, the etch barrier material 33 can block the path through which the wet chemical penetrates. In particular, since the etch barrier material 33 made of a carbon-based material has excellent gap filling characteristics, the path through which the wet chemical may be introduced can be blocked fundamentally. Even if the source channel contacts 31A and 31B include voids 30V, the voids 30V can be fundamentally prevented from being affected by the wet chemical through the etch barrier material 33.

[0058] The spacer 27' with a reduced height can be partially retained on the upper sidewalls of the etch barrier material 33.

[0059] As Figure 14 and Figure 15 shown, the sacrificial layer 18 can be replaced with the gate electrode 35 through the slit 26. For example, the sacrificial layer 18 can be removed to form a gate recess 34 between the insulating layers 17. Subsequently, the gate electrode 35 can be filled in the gate recess 34. The gate electrode 35 can include tungsten, titanium nitride, or a combination thereof.

[0060] As the gate electrode 35 is formed, a first gate stack M11 and a second gate stack M12 can be formed. The first gate stack M11 and the second gate stack M12 can be an alternating stack in which the gate electrode 35 and the insulating layer 17 are alternating. The first gate stack M11 and the second gate stack M12 can be spaced apart from each other through the slit 26. A plurality of vertical channel structures 20 can penetrate the first gate stack M11 and the second gate stack M12. The source channel contacts 31A and 31B can be disposed below the first gate stack M11 and the second gate stack M12. The channel layers 24 of the vertical channel structures 20 of the first gate stack M11 and the second gate stack M12 can be connected to the source channel contacts 31A and 31B.

[0061] As Figure 16 shown, a capping spacer 36 can be formed on the sidewalls of the slit 26 (i.e., the sidewalls on one side of the gate electrode 35). The capping spacer 36 can include silicon oxide, silicon nitride, silicon carbonitride, or a combination thereof.

[0062] Next, the etch barrier material 33 can be removed. The etch barrier material 33 can be removed through an oxygen stripping process. Since the carbon layer used as the etch barrier material 33 is removed through the oxygen stripping process, erosion of the source channel contacts 31A and 31B and the voids 30V can be avoided.

[0063] As Figure 17As shown, the common source line 37 filling the slit 26 may be formed on the covering spacer 36. The common source line 37 may include polysilicon, tungsten, titanium nitride, or a combination thereof.

[0064] The above-described embodiments are not limited by the above-described embodiments and the drawings. Those of ordinary skill in the art will readily understand that various substitutions, changes, or modifications can be made thereto without departing from the scope of the present disclosure.

[0065] Cross-reference to related applications

[0066] This application claims priority to Korean Patent Application No. 10-2021-0042011, filed on Mar. 31, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a stacked structure including a lower-level sacrificial layer above a semiconductor substrate; Forming a slit that penetrates the stacked structure and exposes the lower-level sacrificial layer; Forming spacers on sidewalls of the slit; Forming a horizontal recess by removing the lower-level sacrificial layer; Forming a conductive material in each of the horizontal recesses; Etching the conductive material to form source-channel contact portions respectively filling the horizontal recesses, and forming separation grooves between the source-channel contact portions; And Forming an etch barrier material that fills the separation grooves without voids.

2. The method according to claim 1, the method further comprising the step of removing the spacers.

3. The method according to claim 1, wherein, The etch barrier material fills the separation grooves until a height at least covering bottoms of the spacers.

4. The method according to claim 1, wherein The etch barrier material includes a void-free carbon-based material.

5. The method according to claim 1, wherein The etch barrier material includes a void-free carbon layer.

6. The method according to claim 1, wherein The step of forming the etch barrier material that fills the separation grooves includes the following steps: Forming an etch barrier material layer on sidewalls of the slit by filling the separation grooves; and Etching the etch barrier material layer to form the etch barrier material retained in the separation grooves.

7. The method according to claim 1, wherein The step of forming the etch barrier material that fills the separation grooves includes the following steps: Forming an etch barrier material layer on sidewalls of the slit and sidewalls of the separation grooves; and Etching the etch barrier material layer, wherein the steps of forming the etch barrier material layer and etching the etch barrier material layer are repeated.

8. The method according to claim 1, wherein The conductive material includes polysilicon.

9. The method according to claim 1, wherein Both the conductive material and the source-channel contact portions include voids.

10. The method according to claim 1, the method further comprising the following steps: Performing in-situ back etching such that an upper surface of the formed etch barrier material is at a height covering at least bottoms of the spacers.

11. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a lower-level stack including a sacrificial source layer above a semiconductor substrate and an upper-level stack above the lower-level stack, in which a plurality of insulating layers and a plurality of sacrificial layers are alternately stacked; Forming a plurality of vertical channel structures, each of the plurality of vertical channel structures including a channel layer that penetrates the upper-level stack and the lower-level stack; Forming a slit that divides the upper-level stack into a first alternating stack and a second alternating stack; Partially etching the lower-level stack to expose the sacrificial source layer to expand the slit; Forming spacers on sidewalls of the slit; Forming a horizontal recess extending from the slit by removing the sacrificial source layer; Forming source-channel contact portions respectively filling the horizontal recesses and separation grooves between the source-channel contact portions; And Forming an etch barrier material that fills the separation grooves without voids.

12. The method according to claim 11, the method further comprising the step of removing the spacers.

13. The method according to claim 11, wherein, The etch barrier material fills the isolation groove until it covers at least the height of the bottom of the spacer.

14. The method according to claim 11, wherein, The etch barrier material includes a void-free carbon-based material.

15. The method according to claim 11, wherein, The etch barrier material includes a void-free carbon layer.

16. The method according to claim 11, wherein, The step of forming the etch barrier material that fills the isolation groove includes the following steps: Forming an etch barrier material layer on the sidewalls of the slit by filling the isolation groove; and Etching the etch barrier material layer to form the etch barrier material retained in the isolation groove.

17. The method according to claim 11, wherein, The step of forming the etch barrier material that fills the isolation groove includes the following steps: Forming an etch barrier material layer on the sidewalls of the slit and the sidewalls of the isolation groove; and Etching the etch barrier material layer, wherein the steps of forming the etch barrier material layer and etching the etch barrier material layer are repeated.

18. The method according to claim 11, wherein, The source-channel contact portion includes polysilicon.

19. The method according to claim 11, wherein, The source-channel contact portions all include voids.

20. The method according to claim 11, wherein, The step of forming the source-channel contact portion and the isolation groove includes the following steps: Filling a conductive material in the horizontal recess; and Selectively etching the conductive material, wherein the conductive material includes voids provided in each of the horizontal recesses.

21. According to the method of claim 11, after the step of forming the horizontal recess, the method further comprises the following steps: The channel layer of the vertical channel structure is exposed through the horizontal recess.

22. The method according to claim 21, wherein, The exposed channel layer is directly connected to the source-channel contact portion.

23. According to the method of claim 12, after the step of removing the spacer, the method further includes a step of removing the etch barrier material.

24. According to the method of claim 11, after the step of removing the spacer, the method further includes the following steps: Replacing the sacrificial layer of the first alternating stack and the second alternating stack with a gate electrode; Forming a cover spacer disposed above the etch barrier material and covering the sidewalls of the slit; And Removing the etch barrier material.

25. The method according to claim 11, wherein, The etch barrier material has a height that prevents the source-channel contact portion from being exposed through the slit.

26. According to the method of claim 11, the method further includes the following steps: Performing in-situ back etching such that the upper surface of the formed etch barrier material is at a height covering at least the bottom of the spacer.

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