Display panel and display terminal

Abstract

The application discloses a display panel and a display terminal. The display panel comprises a display area, a fan-out area and a bending area. The fan-out area is located between the display area and the bending area. The display panel comprises a substrate, a plurality of data lines, a plurality of first signal lines located in the fan-out area, a plurality of second signal lines, a plurality of third signal lines and a plurality of fourth signal lines. The plurality of data lines are arranged on the substrate, and the data lines are located in the display area. One first signal line is connected with one data line. One second signal line is connected with one data line. The plurality of third signal lines, one third signal line is connected with one data line. One fourth signal line is connected with one data line. The first signal lines, the second signal lines, the third signal lines and the fourth signal lines are arranged in different layers.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a spliced display panel and a display terminal. BACKGROUND

[0002] With the development trend of extreme full screen, the frame of the display panel is getting narrower and narrower, and the screen-to-body ratio is getting higher and higher, bringing a more extreme experience to consumers.

[0003] However, with the increase of the screen ratio, the number of data lines included in the display panel increases sharply, and the space required for the data lines in the lower frame part of the display panel increases, so that the effective display area AA domain becomes smaller. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display terminal, which are used for reducing the lower frame of the display panel and improving the screen-to-body ratio of the display area.

[0005] The embodiments of the present application disclose a display panel, which comprises a display area, a fan-out area and a bending area, the fan-out area is located between the display area and the bending area, and the display panel comprises:

[0006] a substrate;

[0007] a plurality of data lines, which are arranged on the substrate and located in the display area;

[0008] a plurality of first signal lines, which are located in the fan-out area, and one first signal line is connected with one data line;

[0009] a plurality of second signal lines, which are located in the fan-out area, and one second signal line is connected with one data line;

[0010] a plurality of third signal lines, which are located in the fan-out area, and one third signal line is connected with one data line;

[0011] a plurality of fourth signal lines, which are located in the fan-out area, and one fourth signal line is connected with one data line; wherein

[0012] The first signal lines, the second signal lines, the third signal lines and the fourth signal lines are arranged in different layers.

[0013] Optionally, in some embodiments provided by the present application, the fan-out area comprises a first fan-out area and a second fan-out area, and the first fan-out area is located on both sides of the second fan-out area; wherein

[0014] The plurality of first signal lines and the plurality of second signal lines are extended from the first fan-out area to the second fan-out area.

[0015] The third signal lines and the fourth signal lines are arranged in the second fan-out area and in the first direction.

[0016] Optionally, in some embodiments provided in the present application, the first signal line comprises a first line segment and a second line segment, part of the first line segment is located in the first fan-out area, the second line segment is located in the second fan-out area, and the second line segment extends in the first direction.

[0017] Optionally, in some embodiments provided in the present application, the second signal line comprises a third line segment and a fourth line segment, part of the third line segment is located in the first fan-out area, the fourth line segment is located in the second fan-out area, and the fourth line segment extends in the first direction.

[0018] Optionally, in some embodiments provided in the present application, in the direction from the second fan-out area to the first fan-out area, the second line segment and the fourth line segment are arranged between the third signal lines and the fourth signal lines in sequence, and one of the second line segment and the fourth line segment is arranged between two adjacent third signal lines and fourth signal lines.

[0019] Optionally, in some embodiments provided in the present application, the display area comprises a first side, a second side and a third side, the first side and the second side are connected by the third side, the third side is arc-shaped, and the data lines corresponding to the third side are connected with the first signal line and the second signal line.

[0020] The extension directions of the first line segment and the third line segment are the same as the extension direction of the third side.

[0021] Optionally, in some embodiments provided in the present application, the data lines comprise first data lines and second data lines, the first data lines are located on both sides of the second data lines, the first data lines correspond to the third side, part of the first data lines are connected with the first signal line, and the other part of the first data lines are connected with the second signal line.

[0022] Optionally, in some embodiments provided in the present application, the first signal line and the second signal line are alternately connected with the first data lines.

[0023] Optionally, in some embodiments provided in the present application, the third signal line and the fourth signal line are alternately connected with the second data lines.

[0024] Optionally, in some embodiments provided in the present application, the display panel further comprises:

[0025] a shielding metal layer disposed on the substrate, the first signal traces being located on the shielding metal layer;

[0026] a first metal layer disposed on a side of the shielding metal layer away from the substrate, the third signal traces being located on the first metal layer;

[0027] a second metal layer disposed on a side of the first metal layer away from the substrate, the fourth signal traces being located on the second metal layer;

[0028] a third metal layer disposed on a side of the second metal layer away from the first metal layer, the second signal traces being located on the third metal layer.

[0029] Optionally, in some embodiments provided in the present application, the fan-out area comprises a first fan-out area and a second fan-out area, the first fan-out area being located on two sides of the second fan-out area; wherein

[0030] the first signal traces, the second signal traces and the third signal traces are extended from the first fan-out area to the second fan-out area;

[0031] the fourth signal traces are located in the second fan-out area and arranged in a first direction.

[0032] Optionally, in some embodiments provided in the present application, the first signal traces, the second signal traces and the third signal traces are arranged alternately.

[0033] Optionally, in some embodiments provided in the present application, the first signal traces comprise connected first trace segments and second trace segments, the second signal traces comprise connected third trace segments and fourth trace segments, and the third signal traces comprise connected fifth trace segments and sixth trace segments; wherein

[0034] the first trace segments, the third trace segments and the fifth trace segments are extended from the first fan-out area to the second fan-out area, the second trace segments, the fourth trace segments and the sixth trace segments are located in the second fan-out area, and the second trace segments, the fourth trace segments and the sixth trace segments are extended in the first direction.

[0035] Optionally, in some embodiments provided in the present application, along a direction from the second fan-out area to the first fan-out area, the second trace segment, the fourth trace segment and the sixth trace segment are arranged in sequence between a plurality of fourth signal traces, and one of the second trace segment, the fourth trace segment and the sixth trace segment is arranged between two adjacent fourth signal traces.

[0036] Optionally, in some embodiments provided in the present application, the display panel further comprises:

[0037] a shielding metal layer arranged on the substrate, the fourth signal trace being located in the shielding metal layer;

[0038] a first metal layer arranged on a side of the shielding metal layer away from the substrate and insulated from the shielding metal layer, the second signal trace being located in the first metal layer;

[0039] a second metal layer arranged on a side of the first metal layer away from the substrate and insulated from the first metal layer, the third signal trace being located in the second metal layer;

[0040] a third metal layer arranged on a side of the second metal layer away from the first metal layer and insulated from the second metal layer, the first signal trace being located in the third metal layer.

[0041] Optionally, in some embodiments provided in the present application, the display panel further comprises a first active layer and a second active layer, the first active layer being arranged on a side of the shielding metal layer away from the substrate and insulated from the shielding metal layer, and the second active layer being arranged on a side of the second metal layer away from the first metal layer and insulated from the second metal layer; wherein

[0042] the first active layer is a low-temperature polysilicon active layer, and the second active layer is a metal oxide active layer.

[0043] Optionally, in some embodiments provided in the present application, the shielding metal layer further comprises a shielding metal line, the shielding metal line being located in the display area.

[0044] Optionally, in some embodiments provided in the present application, the display panel further comprises a fourth metal layer arranged on a side of the third metal layer away from the second metal layer, the data line being located in the fourth metal layer.

[0045] Optionally, in some embodiments provided in the present application, a height of the second fan-out area in the first direction is less than or equal to 600 microns.

[0046] Accordingly, this application embodiment also provides a display terminal, which includes the above-mentioned display panel and housing, with the display panel disposed within the housing.

[0047] This application provides a display panel and a display terminal. The display panel includes a display area, a fan-out area, and a bending area. The fan-out area is located between the display area and the bending area. The display panel includes a substrate, multiple data lines, multiple first signal lines, multiple second signal lines, multiple third signal lines, and multiple fourth signal lines located in the fan-out area. The multiple data lines are disposed on the substrate and are located in the display area. A first signal line is connected to a data line. A second signal line is connected to a data line. A third signal line is connected to a data line. A fourth signal line is connected to a data line. The first, second, third, and fourth signal lines are disposed in different layers. In this application embodiment, because the first, second, third, and fourth signal lines are disposed in different layers, the number of signal lines disposed in the same film layer can be reduced. With the distance between adjacent first and second signal traces and the distance between third and fourth signal traces remaining unchanged, the display panel of this embodiment can reduce the area occupied by the fan-out region, thereby reducing the bottom bezel of the display panel and increasing the screen ratio of the display area. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A schematic diagram of a display panel provided in an embodiment of this application;

[0050] Figure 2 This is a first planar schematic diagram of a display panel provided in an embodiment of this application;

[0051] Figure 3 For along Figure 2 A schematic diagram of a cross-sectional structure of the fan-out region cut off in the AA direction;

[0052] Figure 4 For along Figure 2 A schematic diagram of a cross-sectional structure of the display area cut off in the BB direction;

[0053] Figure 5 This is a second planar schematic diagram of a display panel provided in an embodiment of this application;

[0054] Figure 6For along Figure 5 A schematic diagram of a cross-sectional structure of the fan-out region cut off in the CC direction;

[0055] Figure 7 This is a schematic plan view of a display terminal provided in an embodiment of this application. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Please refer to the figures in the drawings, where the same component symbols represent the same components. The following description is based on the specific embodiments of this application shown, and should not be considered as limiting other specific embodiments not detailed herein. The term "embodiment" as used in this specification means example, illustration, or illustration.

[0057] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0058] This application provides a splicing display panel. The following provides a detailed description of each. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0059] Please refer to Figure 1 , Figure 1This is a schematic diagram of a display panel provided in an embodiment of this application. In known technologies, the left, right, and top bezels of display panels can be made very narrow (e.g., less than 1mm wide). However, the bending radius *a* of the bending area BA of the bottom bezel, the fitting accuracy of the back panel during bending, and the wiring in the fan-out area all contribute to an excessively wide bottom bezel, hindering the development of a narrow bottom bezel. The inventors have discovered that this problem arises because the bottom bezel of the display panel typically has denser wiring, making its structure more complex than other bezels. Known wiring methods usually employ diagonal routing, where the connecting lines from the bending area BA are diagonally routed in the fan-out area FA to connect the data lines of the display area AA. In the display area AA, there are usually many data lines, and this number increases rapidly with increasing resolution; for example, at a 1080*2340 resolution, there are 2160 data lines. When using the existing technology for diagonal wiring, in order to prevent short circuits between connecting lines, the width of the bottom border needs to be increased, that is, the b value will be very large (greater than 1mm), which is not conducive to achieving a narrow bottom border.

[0060] This application provides a display panel, which includes a display area, a fan-out area, and a bending area. The fan-out area is located between the display area and the bending area. The display panel includes a substrate, multiple data lines, multiple first signal lines, multiple second signal lines, multiple third signal lines, and multiple fourth signal lines located in the fan-out area. The multiple data lines are disposed on the substrate and are located in the display area. A first signal line is connected to a data line. A second signal line is connected to a data line. Multiple third signal lines are connected to a data line. A fourth signal line is connected to a data line. The first, second, third, and fourth signal lines are disposed in different layers. In this application embodiment, because the first, second, third, and fourth signal lines are disposed in different layers, the number of signal lines disposed in the same film layer can be reduced. With the distance between adjacent first and second signal traces and the distance between adjacent third and fourth signal traces remaining unchanged, the display panel of this embodiment can reduce the area occupied by the fan-out region, thereby reducing the bottom bezel of the display panel and increasing the screen ratio of the display area.

[0061] The display panel provided in this application will be described in detail below through specific embodiments.

[0062] Please combine Figure 2 , Figure 3 and Figure 4 , Figure 2 This is a first planar schematic diagram of a display panel provided in an embodiment of this application. Figure 3 For along Figure 2 A schematic diagram of a cross-sectional structure of the fan-out region taken along the AA direction.Figure 4 For along Figure 2 This application provides a cross-sectional view of a display area taken along the BB direction. The display panel 100 includes a display area AA, a fan-out area FA, and a bending area BA. The fan-out area FA is located between the display area AA and the bending area BA. The fan-out area FA includes a first fan-out area FA1 and a second fan-out area FA2. The first fan-out area FA1 is located on both sides of the second fan-out area FA2. The second fan-out area FA2 is a rectangular region, one side of which forms the lower border of the display panel 100. The first fan-out area FA1 is the region within the fan-out area FA excluding the second fan-out area FA2. The display panel 100 includes a substrate 10, multiple data lines 101, multiple first signal lines 103, multiple second signal lines 104, multiple third signal lines 105, and multiple fourth signal lines 106. The data lines 101 are disposed on the substrate 10 and are located in the display area AA. The multiple data lines 101 extend along a first direction X and are arranged along a second direction Y. A first signal trace 103 is connected to a data line 101, extending from a first fan-out area FA1 to a second fan-out area FA2. A second signal trace 104 is connected to a data line 101, extending from the first fan-out area FA1 to the second fan-out area FA2. A third signal trace 105 is connected to a data line 101, located in the second fan-out area FA2, and extending along a first direction X. A fourth signal trace 106 is connected to a data line, located in the second fan-out area FA2, and extending along the first direction X. The first signal trace 103, second signal trace 104, third signal trace 105, and fourth signal trace 106 are arranged on different layers.

[0063] In this application, since the first signal trace 103, the second signal trace 104, the third signal trace 105, and the fourth signal trace 106 are disposed in different layers—that is, the first signal trace 103 and the second signal trace 104 located in the first fan-out region FA1 are disposed in different film layers, and the third signal trace 105 and the fourth signal trace 106 located in the second fan-out region FA2 are disposed in different film layers—the number of signal traces disposed in the same film layer can be reduced. Therefore, compared with the prior art where the first signal trace 103 and the second signal trace 104 are disposed in the same film layer, and the third signal trace 105 and the fourth signal trace 106 are disposed in the same layer, this embodiment, by disposing of the first signal trace 103, the second signal trace 104, the third signal trace 105, and the fourth signal trace 106 in different layers, can reduce the area occupied by the first fan-out region FA1 of the display panel 100 while keeping the distance between adjacent first signal traces 103 and second signal traces 104 unchanged. Specifically, the distance of the first fan-out area FA1 along the first direction X can be reduced, that is, the distance of the lower border where the first fan-out area FA1 is located along the first direction X can be reduced, thereby enabling the display panel 100 to achieve a narrow bezel design.

[0064] Specifically, the display area AA is used to realize the display function of the display panel 100. A pixel circuit composed of thin-film transistors is disposed in the display area AA to drive the light-emitting elements on the substrate 10 to emit light. Multiple data lines 101 extending along the first direction X in the display area AA are used to transmit data voltage to the pixel circuit.

[0065] The multiple data lines 101 include multiple first-type data lines 101a and multiple second-type data lines 101b. The first-type data lines 101a are located on both sides of the multiple second-type data lines 101b. The first-type data lines 101a extend along a first direction X to the corner bezel between the two sides of the display panel 100, and the second-type data lines 101b extend along the first direction X to the lower bezel of the display panel 100. A portion of the first-type data lines 101a are connected to a first signal trace 103, and another portion of the first-type data lines 101a are connected to a second signal trace 104. A portion of the second-type data lines 101b are connected to a third signal trace 105, and another portion of the second-type data lines 101b are connected to a fourth signal trace 106.

[0066] Specifically, the first signal trace 103 and the second signal trace 104 are alternately connected to the first type of data line 101a. The third signal trace 105 and the fourth signal trace 106 are alternately connected to the second type of data line 101b.

[0067] The first signal trace 103 and part of the second signal trace 104 are arranged between multiple third signal traces 105 and fourth signal traces 106.

[0068] The first signal trace 103 and the second signal trace 104 are arranged alternately. The third signal trace 105 and the fourth signal trace 106 are arranged alternately. This reduces the vertical routing space for the signal traces in the fan-out area FA.

[0069] Specifically, a first signal trace 103 includes a connected first trace segment 1031 and a second trace segment 1032. A portion of the first trace segment 1031 is located in a first fan-out area FA1. The second trace segment 1032 is located in a second fan-out area FA2, and extends along a first direction X. A second signal trace 104 includes a third trace segment 1041 and a fourth trace segment 1042. A portion of the third trace segment 1041 is located in the first fan-out area FA1. The fourth trace segment 1042 is located in the second fan-out area FA2, and extends along a first direction X.

[0070] It should be noted that, in the embodiments of this application, the second trace segment 1032 and the fourth trace segment 1042 are traces parallel to the third signal trace 105 and the fourth signal trace 106, the first trace segment 1031 is the trace of the first signal trace 103 other than the second trace segment 1032, and the third trace segment 1041 is the trace of the second signal trace 104 other than the fourth trace segment 1042.

[0071] Along the direction from the second fan-out area FA2 to the first fan-out area FA1, the second trace segment 1032 and the fourth trace segment 1042 are sequentially arranged between multiple third signal traces 105 and fourth signal traces 106, and one of the second trace segment 1032 and the fourth trace segment 1042 is provided between two adjacent third signal traces 105 and fourth signal traces 106. That is, in this embodiment, only one trace segment is provided between two adjacent third signal traces 105 and fourth signal traces 106, and the second trace segment 1032 and the fourth trace segment 1042 are arranged sequentially to prevent the distance between adjacent second trace segments 1032 and fourth trace segments 1042 along the second direction Y from being too narrow and short-circuiting, thereby improving the stability of the display panel 100.

[0072] In some embodiments, the display area AA includes a first side a1, a second side a2, and a third side a3. The first side a1 and the second side a2 are connected through the third side a3, which is arc-shaped. The data line 101 of the display area AA corresponding to the third side a3 is connected to the first signal line 103 and the second signal line 104. Multiple first-type data lines 101a correspond to the third side a3. The extension directions of the first line segment 1031 and the third line segment 1041 are the same as the extension direction of the third side a3. The second line segment 1032 and the fourth line segment 1042 are alternately arranged between the third signal line 105 and the fourth signal line 106.

[0073] In this embodiment, the first trace segment 1031 and the third trace segment 1041 extend along the third side a3 into the first sector area FA1, and the second trace segment 1032 and the fourth trace segment 1042 are alternately arranged between the third signal trace 105 and the fourth signal trace 106. Therefore, the distance of the first sector area FA1 along the first direction X is further reduced. Furthermore, the second trace segment 1032 and the fourth trace segment 1042 are alternately interspersed between the third signal trace 105 and the fourth signal trace 106, making full use of the space between the third signal trace 105 and the fourth signal trace 106, and preventing the second trace segment 1032 and the fourth trace segment 1042 from accumulating in the first sector area FA1, which could cause a short circuit.

[0074] In some embodiments, the height of the second fan-out region FA2 in the first direction X is less than or equal to 600 micrometers. For example, the height of the second fan-out region FA2 in the first direction X can be any one of 600 micrometers, 500 micrometers, 400 micrometers, 300 micrometers, 200 micrometers, 100 micrometers, or 50 micrometers.

[0075] In this embodiment, by placing the signal traces connecting the data line 101 on four different film layers, the number of signal traces placed on the same film layer can be reduced. Therefore, compared with the prior art where the first signal trace 103 and the second signal trace 104 are placed on the same film layer, and the third signal trace 105 and the fourth signal trace 106 are placed on the same layer, this embodiment places the first signal trace 103, the second signal trace 104, the third signal trace 105, and the fourth signal trace 106 on different layers. While maintaining the same distance between adjacent first signal traces 103 and second signal traces 104, the display panel 100 of this embodiment can reduce the area occupied by the first fan-out area FA1. Specifically, the distance of the first fan-out area FA1 along the first direction X can be reduced, that is, the distance of the lower bezel containing the first fan-out area FA1 along the first direction X can be reduced, thereby enabling the display panel 100 to achieve a narrow bezel design.

[0076] Please continue to refer to this. Figure 2 and Figure 3The display panel also includes a shielding metal layer BSM, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4. The shielding metal layer BSM is disposed on the substrate 10, and a first signal trace 103 is located on the shielding metal layer BSM. The first metal layer M1 is disposed on the side of the shielding metal layer BSM away from the substrate 10 and is insulated from the shielding metal layer BSM. A third signal trace 105 is located on the first metal layer M1. The second metal layer M2 is disposed on the side of the first metal layer M1 away from the substrate 10 and is insulated from the first metal layer M1. A fourth signal trace 106 is located on the second metal layer M2. The third metal layer M3 is disposed on the side of the second metal layer M2 away from the first metal layer M1 and is insulated from the second metal layer M2. A second signal trace 104 is located on the third metal layer M3.

[0077] In some embodiments, the shielding metal layer BSM further includes a shielding metal line 1033, which is located in the display area AA. In this embodiment, since the shielding metal layer BSM includes the first signal trace and the shielding metal line 1033, meaning the shielding metal layer BSM including the first signal trace and the shielding metal line 1033 can be formed in the same process, this application does not require adding an additional film layer to set the first signal trace, nor does it require adding a mask. That is, it utilizes the original process of the display panel to achieve the arrangement of multiple signal traces, thereby reducing the distance of the first fan-out area FA1 along the first direction X, reducing the distance of the lower bezel along the first direction X, and increasing the screen-to-body ratio of the display area of ​​the display panel.

[0078] The display panel 100 also includes a barrier layer 11, a buffer layer 12, a first active layer AL1, a first gate insulating layer 13, a second gate insulating layer 14, a first interlayer dielectric layer 15, a second active layer AL2, a third gate insulating layer 16, a second interlayer dielectric layer 17, a first planarization layer 18, and a second planarization layer 19.

[0079] Among them, the barrier layer 11 covers the shielding metal layer BSM.

[0080] The buffer layer 12 is disposed on the side of the barrier layer 11 away from the substrate 10. The material of the buffer layer 12 includes, but is not limited to, silicon-containing oxides, nitrides, or oxynitrides.

[0081] The first active layer AL1 is disposed on the side of the shielding metal layer BSM away from the substrate 10 and is insulated from the shielding metal layer BSM. Specifically, the first active layer AL1 is disposed on the side of the buffer layer 12 away from the substrate 10. The first active layer AL1 is a low-temperature polycrystalline silicon active layer.

[0082] The first gate insulating layer 13 is disposed on the side of the first active layer AL1 away from the substrate 10. The first metal layer M1 is disposed on the first gate insulating layer 13 away from the first active layer AL1, and the first metal layer M1 includes the first gate GE1 and the third signal trace 105.

[0083] The second gate insulating layer 14 is disposed on the side of the first gate insulating layer 13 away from the buffer layer 12, and the second gate insulating layer 14 covers the first metal layer M1. The second metal layer M2 is disposed on the second gate insulating layer 14, and the second metal layer M2 includes the second gate GE2 and the second signal trace 1042.

[0084] The second gate insulating layer 14 disposed on the first interlayer dielectric layer 15 is away from the first gate insulating layer 13 and covers the second metal layer M2.

[0085] The second active layer AL2 is disposed on the side of the second metal layer M2 away from the first metal layer M1, and is insulated from the second metal layer M2. Specifically, the second active layer AL2 is disposed on the side of the first interlayer dielectric layer 15 away from the second gate insulating layer 14. The second active layer AL2 is a metal oxide active layer.

[0086] The third gate insulating layer 16 is disposed on the side of the first interlayer dielectric layer 15 away from the second gate insulating layer 14. The third metal layer M3 is disposed on the side of the third gate insulating layer 16 away from the second gate insulating layer 14, and the third metal layer M3 includes the second signal trace 104 and the third gate GE3.

[0087] The second interlayer dielectric layer 17 is disposed on the side of the third gate insulating layer 16 away from the first interlayer insulating layer. The fourth metal layer M4 is disposed on the side of the second interlayer dielectric layer 17 away from the third gate insulating layer 16. The fourth metal layer M4 includes a first source S1, a first drain D1, a contact electrode TE, a second source S2, a second drain D2, and a data line 101. The first source and first drain are connected to the first active layer AL1 via vias. The second source S2 and second drain D2 are connected to the second active layer AL2 via vias. The first active layer AL1 and the second source S2 are connected via the contact electrode TE.

[0088] In some embodiments, the display panel 100 further includes a fifth metal layer M5, which is disposed on the side of the first planarization layer 18 away from the second interlayer dielectric layer 17. Data lines may also be located on the fifth metal layer M5. The fifth metal layer M5 also includes a connection electrode NE, which is used to connect the first drain electrode D1 and the light-emitting functional layer of the display panel 100 to drive the display panel to emit light.

[0089] Please combine Figure 5 and Figure 6 ,Figure 5 This is a second planar schematic diagram of a display panel provided in an embodiment of this application. Figure 6 For along Figure 5 A cross-sectional structural diagram of the fan-out region cut in the CC direction, the display panel 100 provided in this application embodiment and Figure 2 The difference in the provided display panel 100 is that multiple first signal traces 103, multiple second signal traces 104 and multiple third signal traces 105 extend from the first fan-out area FA1 to the second fan-out area FA2, and multiple fourth signal traces 106 are located in the second fan-out area FA2 and are arranged along the first direction X.

[0090] A first signal trace 103, a second signal trace 104, and a third signal trace 105 are alternately arranged.

[0091] The first signal trace 103 includes a first trace segment 1031 and a second trace segment 1032 connected together. The second signal trace 104 includes a third trace segment 1041 and a fourth trace segment 1042 connected together. The third signal trace 105 includes a fifth trace segment 1051 and a sixth trace segment 1052 connected together. The first trace segment 1031, the third trace segment 1041, and the fifth trace segment 1051 extend from the first fan-out area FA1 to the second fan-out area FA2. The second trace segment 1032, the fourth trace segment 1042, and the sixth trace segment 1052 are alternately arranged between the fourth signal trace 106, and the second trace segment 1032, the fourth trace segment 1042, and the sixth trace segment 1052 extend along the first direction X.

[0092] It should be noted that, in the embodiments of this application, the second trace segment 1032, the fourth trace segment 1042 and the sixth trace segment 1052 are traces parallel to the fourth signal trace 106, the first trace segment 1031 is the trace of the first signal trace 103 other than the second trace segment 1032, the third trace segment 1041 is the trace of the second signal trace 104 other than the fourth trace segment 1042, and the fifth trace segment 1051 is the trace of the third signal trace 105 other than the sixth trace segment 1052.

[0093] In some implementations, along the direction from the second fan-out area FA2 to the first fan-out area FA1, the second trace segment 1032, the fourth trace segment 1042, and the sixth trace segment 1052 are sequentially arranged between multiple fourth signal traces 106, and one of the second trace segment 1032, the fourth trace segment 1042, and the sixth trace segment 1052 is provided between two adjacent fourth signal traces 106. That is, in the embodiments of this application, only one trace segment is provided between two adjacent fourth signal traces 106, and the second trace segment 1032, the fourth trace segment 1042, and the sixth trace segment 1052 are arranged sequentially to prevent the distance between adjacent second trace segments 1032, fourth trace segments 1042, and sixth trace segments 1052 along the second direction Y from being too narrow and short-circuiting, thereby improving the stability of the display panel 100.

[0094] In some embodiments, a portion of the first type of data line 101a is connected to the first signal trace 103, a portion of the first type of data line 101a is connected to the second signal trace 104, and a portion of the first type of data line 101a is connected to the third signal trace 105. The second type of data line 101b is connected to the fourth signal trace 106.

[0095] Among them, a first signal trace 103, a second signal trace 104 and a third signal trace segment 105 are alternately connected to the first type of data line 101a.

[0096] In this embodiment, the first signal trace 103 is located in the third metal layer M3. The second signal trace 104 is located in the first metal layer M1. The third signal trace 105 is located in the second metal layer M2. The fourth signal trace 106 is located in the shielding metal layer BSM.

[0097] In this application, since the first signal trace 103, the second signal trace 104, the third signal trace 105, and the fourth signal trace 106 are disposed in different layers, that is, the first signal trace 103, the second signal trace 104, and the third signal trace located in the first fan-out area FA1 are disposed in different film layers, the number of signal traces disposed in the same film layer can be reduced. Therefore, compared with the prior art in which the first signal trace 103 and the second signal trace 104 are disposed in the same film layer, and the third signal trace 105 and the fourth signal trace 106 are disposed in the same layer, this embodiment, by disposing of the first signal trace 103, the second signal trace 104, the third signal trace 105, and the fourth signal trace 106 in different layers, can further reduce the area occupied by the first fan-out area FA1 while keeping the distance between adjacent first signal traces 103, the second signal trace 104, and the third signal trace 105 unchanged. Specifically, the distance of the first fan-out area FA1 along the first direction X can be reduced, that is, the distance of the lower border where the first fan-out area FA1 is located along the first direction X can be reduced, thereby enabling the display panel 100 to achieve a narrow bezel design.

[0098] Accordingly, please refer to Figure 7 , Figure 7 This is a plan view of a display terminal provided in an embodiment of this application. This application also provides a display terminal 1000, which includes a display panel 100 and a housing 200, with the display panel 100 disposed within the housing 200.

[0099] The display panel 100 is the same as described above.

[0100] The display terminal 1000 can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0101] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area, a fan-out area, and a bending area, wherein the fan-out area is located between the display area and the bending area. substrate; Multiple data lines are disposed on the substrate, and the data lines are located in the display area; Multiple first signal traces are located in the fan-out area, and one of the first signal traces is connected to one of the data lines; Multiple second signal traces are located in the fan-out area, and one of the second signal traces is connected to one of the data lines; Multiple third signal traces are located in the fan-out area, and one of the third signal traces is connected to one of the data lines; Multiple fourth signal traces are located in the fan-out area, and one of the fourth signal traces is connected to one of the data lines; wherein The first signal trace, the second signal trace, the third signal trace, and the fourth signal trace are disposed on different layers; The fan-out area includes a first fan-out area and a second fan-out area, with the first fan-out area located on both sides of the second fan-out area; multiple first signal traces and multiple second signal traces extend from the first fan-out area to the second fan-out area, and multiple third signal traces and multiple fourth signal traces are located in the second fan-out area and arranged along a first direction; The first signal trace includes a first trace segment and a second trace segment, a portion of the first trace segment is located in the first fan-out area, the second trace segment is located in the second fan-out area, and the second trace segment extends along the first direction; the second signal trace includes a third trace segment and a fourth trace segment, a portion of the third trace segment is located in the first fan-out area, the fourth trace segment is located in the second fan-out area, and the fourth trace segment extends along the first direction; Along the direction from the second fan-out area to the first fan-out area, the second trace segment and the fourth trace segment are arranged sequentially between multiple third signal traces and fourth signal traces, and one of the second trace segment and the fourth trace segment is provided between two adjacent third signal traces and fourth signal traces.

2. The display panel according to claim 1, characterized in that, The display area includes a first side, a second side, and a third side. The first side and the second side are connected through the third side. The third side is arc-shaped. The data line of the display area corresponding to the third side is connected to the first signal trace and the second signal trace. The extension direction of the first trace segment and the third trace segment is the same as the extension direction of the third side.

3. The display panel according to claim 2, characterized in that, The multiple data lines include multiple first-type data lines and multiple second-type data lines. The multiple first-type data lines are located on both sides of the multiple second-type data lines. The multiple first-type data lines correspond to the third side. A portion of the first-type data lines are connected to the first signal trace, and another portion of the first-type data lines are connected to the second signal trace.

4. The display panel according to claim 3, characterized in that, The first signal trace and the second signal trace are alternately connected to the first type of data line.

5. The display panel according to claim 3, characterized in that, The third signal trace and the fourth signal trace are alternately connected to the second type of data line.

6. The display panel according to claim 1, characterized in that, The display panel also includes: A shielding metal layer is disposed on the substrate, and the first signal trace is located in the shielding metal layer; A first metal layer is disposed on the side of the shielding metal layer away from the substrate and is insulated from the shielding metal layer; the third signal trace is located on the first metal layer. The second metal layer is disposed on the side of the first metal layer away from the substrate and is insulated from the first metal layer. The fourth signal trace is located in the second metal layer. A third metal layer is disposed on the side of the second metal layer away from the first metal layer and is insulated from the second metal layer, and the second signal trace is located on the third metal layer.

7. The display panel according to claim 6, characterized in that, The display panel further includes a first active layer and a second active layer. The first active layer is disposed on the side of the shielding metal layer away from the substrate and is insulated from the shielding metal layer. The second active layer is disposed on the side of the second metal layer away from the first metal layer and is insulated from the second metal layer. in The first active layer is a low-temperature polycrystalline silicon active layer, and the second active layer is a metal oxide active layer.

8. The display panel according to claim 7, characterized in that, The shielding metal layer also includes shielding metal wires, which are located in the display area.

9. The display panel according to claim 7, characterized in that, The display panel further includes a fourth metal layer disposed on the side of the third metal layer away from the second metal layer, and the data line is located on the fourth metal layer.

10. The display panel according to claim 1, characterized in that, The height of the second fan-out region in the first direction is less than or equal to 600 micrometers.

11. A display panel, characterized in that, The display panel includes a display area, a fan-out area, and a bending area, wherein the fan-out area is located between the display area and the bending area. substrate; Multiple data lines are disposed on the substrate, and the data lines are located in the display area; Multiple first signal traces are located in the fan-out area, and one of the first signal traces is connected to one of the data lines; Multiple second signal traces are located in the fan-out area, and one of the second signal traces is connected to one of the data lines; Multiple third signal traces are located in the fan-out area, and one of the third signal traces is connected to one of the data lines; Multiple fourth signal traces are located in the fan-out area, and one of the fourth signal traces is connected to one of the data lines; wherein The first signal trace, the second signal trace, the third signal trace, and the fourth signal trace are disposed on different layers; The fan-out area includes a first fan-out area and a second fan-out area, wherein the first fan-out area is located on both sides of the second fan-out area; wherein Multiple first signal traces, multiple second signal traces, and multiple third signal traces extend from the first fan-out area to the second fan-out area; Multiple fourth signal traces are located in the second fan-out area and arranged along the first direction; a first signal trace, a second signal trace, and a third signal trace are alternately arranged.

12. The display panel according to claim 11, characterized in that, The first signal trace includes a first trace segment and a second trace segment connected together; the second signal trace includes a third trace segment and a fourth trace segment connected together; the third signal trace includes a fifth trace segment and a sixth trace segment connected together. in The first, third, and fifth trace segments extend from the first fan-out area to the second fan-out area. The second, fourth, and sixth trace segments are located in the second fan-out area and extend along the first direction.

13. The display panel according to claim 12, characterized in that, Along the direction from the second fan-out area to the first fan-out area, the second trace segment, the fourth trace segment, and the sixth trace segment are arranged sequentially between multiple fourth signal traces, and one of the second trace segment, the fourth trace segment, and the sixth trace segment is provided between two adjacent fourth signal traces.

14. The display panel according to claim 11, characterized in that, The display panel also includes: A shielding metal layer is disposed on the substrate, and the fourth signal trace is located in the shielding metal layer; A first metal layer is disposed on the side of the shielding metal layer away from the substrate and is insulated from the shielding metal layer; the second signal trace is located on the first metal layer. The second metal layer is disposed on the side of the first metal layer away from the substrate and is insulated from the first metal layer; the third signal trace is located in the second metal layer. A third metal layer is disposed on the side of the second metal layer away from the first metal layer and is insulated from the second metal layer, and the first signal trace is located on the third metal layer.

15. The display panel according to claim 14, characterized in that, The display panel further includes a first active layer and a second active layer. The first active layer is disposed on the side of the shielding metal layer away from the substrate and is insulated from the shielding metal layer. The second active layer is disposed on the side of the second metal layer away from the first metal layer and is insulated from the second metal layer. in The first active layer is a low-temperature polycrystalline silicon active layer, and the second active layer is a metal oxide active layer.

16. The display panel according to claim 15, characterized in that, The shielding metal layer also includes shielding metal wires, which are located in the display area.

17. The display panel according to claim 15, characterized in that, The display panel further includes a fourth metal layer disposed on the side of the third metal layer away from the second metal layer, and the data line is located on the fourth metal layer.

18. The display panel according to claim 11, characterized in that, The height of the second fan-out region in the first direction is less than or equal to 600 micrometers.

19. A display terminal, characterized in that, The display terminal includes a display panel and a housing as described in any one of claims 1 to 18, wherein the display panel is disposed within the housing.

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