A planar power device and a method of manufacturing the same

Abstract

The application belongs to the technical field of semiconductors, and provides a planar power device and a preparation method thereof. The planar power device comprises a semiconductor substrate, an N-type well region, a P-type well region, a gate oxide layer, a gate metal layer, a source region, an isolation region, a drain region and an inversion layer. The N-type well region and the P-type well region are both located on the semiconductor substrate; the gate oxide layer is located on the N-type well region and the P-type well region; the gate metal layer is located on the gate oxide layer; the source region is in contact with the gate oxide layer; the isolation region is arranged between the drain region and the gate oxide layer; the inversion layer is arranged between the N-type well region and the drain region; and the doping type of the inversion layer is different from the doping type of the drain region. By arranging the inversion layer between the drain region and the N-type well region, the withstand voltage capacity of the planar power device can be improved without increasing the size of the planar power device, thereby solving the problems of the existing planar power device, such as large size and poor withstand voltage performance.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a planar power device and a preparation method thereof. BACKGROUND

[0002] Power devices have a wide range of applications in many fields due to their special properties of withstand voltage, such as magnetic disk drives, automotive electronics and the like. It is known that planar power devices have the advantage of low manufacturing cost compared to vertical devices, but the withstand voltage and device performance cannot be considered at the same time. The withstand voltage capability of the existing planar power device is improved by increasing the distance between the source and the drain, which also improves the on-resistance of the drain. However, in the trend of miniaturization of power devices, simply relying on increasing the distance between the drain and the source to improve the withstand voltage performance of the power device greatly limits the development of power devices.

[0003] Therefore, the existing planar power device has the problems of large size and poor withstand voltage performance. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a planar power device and a preparation method thereof, which can solve the problems of large size and poor withstand voltage performance of the existing planar power device.

[0005] The first aspect of the present application provides a planar power device, which comprises:

[0006] a semiconductor substrate;

[0007] an N-type well region and a P-type well region, the N-type well region and the P-type well region are in contact and are located on the semiconductor substrate;

[0008] a gate oxide layer located on the N-type well region and the P-type well region;

[0009] a gate metal layer located on the gate oxide layer;

[0010] a source region located on the P-type well region and in contact with the gate oxide layer;

[0011] an isolation region, a drain region and an inversion layer, the isolation region, the drain region and the inversion layer are provided on the N-type well region, the isolation region is provided between the drain region and the gate oxide layer, the inversion layer is provided between the N-type well region and the drain region, and the inversion layer is in contact with the isolation region;

[0012] wherein the doping type of the inversion layer is different from the doping type of the drain region.

[0013] In one embodiment, the inversion layer comprises: a first inversion region and a second inversion region.

[0014] The first inversion region and the second inversion region are respectively arranged at edge regions of the N-type well region, and the first inversion region and the second inversion region do not contact each other.

[0015] In one embodiment, the sum of the widths of the first inversion region and the second inversion region is less than the width of the drain region.

[0016] In one embodiment, the width of each of the first inversion region and the second inversion region ranges from 10% to 30% of the width of the drain region.

[0017] In one embodiment, the length of each of the first inversion region and the second inversion region is greater than the length of the drain region.

[0018] In one embodiment, the thickness of each of the first inversion region and the second inversion region is less than the thickness of the drain region.

[0019] In one embodiment, the first inversion region and the second inversion region are symmetrically arranged.

[0020] In one embodiment, the N-type well region and the P-type well region have the same width, and the N-type well region and the P-type well region have the same thickness.

[0021] A second aspect of the embodiments of the present application provides a preparation method of a planar power device, comprising:

[0022] providing a semiconductor substrate;

[0023] forming an N-type well region and a P-type well region on the semiconductor substrate in sequence; wherein the N-type well region and the P-type well region contact each other;

[0024] forming a source region on the P-type well region;

[0025] forming an inversion layer, an isolation region, and a drain region on the N-type well region; the inversion layer is located between the drain region and the N-type well region;

[0026] forming a gate oxide layer on the N-type well region, the P-type well region, the source region, and the isolation region, and forming a gate metal layer on the gate oxide layer;

[0027] wherein the isolation region is arranged between the drain region and the gate oxide layer, the inversion layer is arranged between the N-type well region and the drain region, the inversion layer contacts the isolation region, and the doping type of the inversion layer is different from the doping type of the drain region.

[0028] In one embodiment, the forming the inversion layer on the N-type well region comprises:

[0029] Defining the position of the inversion layer on the N-type well region by using a mask plate, wherein the inversion layer is located at the edge region of the N-type well region;

[0030] Implanting P-type doping ions into the N-type well region under the cover of the mask plate to form the inversion layer in the N-type well region, wherein the inversion layer comprises: a first inversion region and a second inversion region, the first inversion region and the second inversion region are respectively arranged at the edge region of the N-type well region, and the first inversion region and the second inversion region do not contact each other.

[0031] The beneficial effects of the embodiments of the present application compared with the prior art are: by setting the N-type well region and the P-type well region on the semiconductor substrate, and setting the inversion layer on the N-type well region, wherein the inversion layer is located between the N-type well region and the drain region, and the inversion layer contacts the isolation region, wherein the doping type of the inversion layer is different from the doping type of the drain region. The main inventive concept of the present application is to set the inversion layer between the drain region and the N-type well region, which can improve the withstand voltage capability of the planar power device without increasing the size of the planar power device, and solves the problems of large size and poor withstand voltage performance of the existing planar power device. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a structure schematic diagram of a planar power device provided by one embodiment of the present application;

[0033] Figure 2 is a top view structure schematic diagram of a planar power device provided by one embodiment of the present application;

[0034] Figure 3 is a flowchart of a preparation method of a planar power device provided by one embodiment of the present application;

[0035] Figure 4 is a schematic diagram after forming the N-type well region and the P-type well region provided by one embodiment of the present application;

[0036] Figure 5 is a schematic diagram after forming the source region provided by one embodiment of the present application;

[0037] Figure 6 is a schematic diagram after forming the drain region and the isolation region provided by one embodiment of the present application;

[0038] Figure 7 is a schematic diagram after forming the gate oxide layer and the gate metal layer provided by one embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the technical problems, technical solutions and beneficial effects to be solved in the present application clearer, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application and not to limit the present application.

[0040] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0041] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0042] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is one or more than one, unless otherwise explicitly and specifically limited.

[0043] Power devices have a wide range of applications in many fields due to their special properties of withstand voltage, such as magnetic disk drive, automotive electronics and the like. It is well known that planar power devices have the advantage of low manufacturing cost compared to vertical devices, but their withstand voltage and device performance cannot be considered at the same time. The withstand voltage of the existing planar power device is improved by increasing the distance between the source and the drain, which also improves the on-resistance of the drain. However, in the trend of miniaturization of power devices, simply relying on increasing the distance between the drain and the source to improve the withstand voltage performance of the power device greatly limits the development of the power device.

[0044] Therefore, the existing planar power device has the problems of large size and poor withstand voltage performance.

[0045] In order to solve the above technical problems, the embodiments of the present application provide a planar power device, which refers to Figure 1As shown in the figure, the planar power device comprises a semiconductor substrate 10, an N-type well region 20, a P-type well region 30, a gate oxide layer 40, a gate metal layer 50, a source region 60, an isolation region 70, a drain region 80, and a reverse type layer 90.

[0046] Specifically, the N-type well region 20 and the P-type well region 30 are in contact and are both located on the semiconductor substrate 10; the gate oxide layer 40 is located on the N-type well region 20 and the P-type well region 30; the gate metal layer 50 is located on the gate oxide layer 40; the source region 60 is located on the P-type well region 30 and is in contact with the gate oxide layer 40; the isolation region 70, the drain region 80, and the reverse type layer 90 are provided on the N-type well region 20, the isolation region 70 is provided between the drain region 80 and the gate oxide layer 40, the reverse type layer 90 is provided between the N-type well region 20 and the drain region 80, and the reverse type layer 90 is in contact with the isolation region 70; wherein the doping type of the reverse type layer 90 is different from the doping type of the drain region 80.

[0047] In this embodiment, the planar power device needs different withstand voltage for different application scenarios, and the existing planar power device generally increases the distance between the source region 60 and the drain region 80 to improve the withstand voltage capability of the planar power device when high withstand voltage is needed. However, such operation greatly increases the volume of the planar power device, not only causing material waste, but also not ideal withstand voltage effect. The embodiment of the present application sets the reverse type layer 90 on the N-type well region 20, wherein the reverse type layer 90 is provided between the N-type well region 20 and the drain region 80, and the reverse type layer 90 is in contact with the isolation region 70, and the doping type of the reverse type layer 90 is different from the doping type of the drain region 80. By setting the reverse type layer 90 at the lower end edge part of the drain region 80, the withstand voltage capability of the planar power device can be improved.

[0048] In this embodiment, the reverse type layer 90 is located at the lower end edge part of the drain region 80, and TCAD (Technology Computer Aided Design, semiconductor process simulation and device simulation tool) simulation and experiments show that the electric field and stress of the device edge (10%-30%) are the largest, and when the reverse bias is increased, the breakdown effect occurs in this edge region first, which limits the withstand voltage of the device. In this embodiment, the reverse type layer 90 is provided in the region of the planar power device where the breakdown effect is prone to occur, because the doping type of the reverse type layer 90 is different from the doping type of the drain region 80, so the breakdown effect can be greatly alleviated, the electric field and stress of the planar power device are reduced, and because the reverse type layer 90 is only provided in the edge part of the planar power device, the performance of the middle region of the planar power device is retained, the performance of the device is maximally retained, and the withstand voltage capability of the device is improved.

[0049] In the embodiment, the P-type well region 30 is also provided with a P-type doped region 100, wherein the P-type doped region 100 is doped with P-type ions and is lightly doped.

[0050] In the embodiment, the N-type well region 20 and the P-type well region 30 are in contact and are both located on the semiconductor substrate 10. Specifically, the P-type well region 30 is in the shape of "L" and the N-type well region 20 is in the shape of ladder. The P-type doped region 100 and the source region 60 are arranged in parallel and are located in the "L" shape of the P-type well region 30. The P-type doped region 100 and the source region 60 have the same height and fill the vacancy of the "L" shape of the P-type well region 30 after being arranged in the "L" shape of the P-type well region 30, so that the gate oxide layer 40 can be arranged in parallel on the N-type well region 20 and the P-type well region 30, thereby ensuring the stability of the planar power device. The inversion layer 90 is located in the first step of the ladder shape of the N-type well region 20 and fills the first step. The isolation region 70 and the drain region 80 are arranged in parallel and are located on the inversion layer 90 and the second step of the ladder shape of the N-type well region 20, and fill the second step. It can be understood that the first step of the ladder shape of the N-type well region 20 is only located below the edge of the drain region 80. The inversion layer 90 arranged in the first step can greatly alleviate the breakdown effect of the power device, reduce the electric field and stress of the planar power device, while retaining the performance of the middle region of the planar power device, thereby maximizing the performance of the device and improving the withstand voltage capability of the device. After being filled, the N-type well region 20, the P-type well region 30, the source region 60, the isolation region 70, the drain region 80 and the inversion layer 90 can make the gate oxide layer 40 arranged in parallel on the N-type well region 20 and the P-type well region 30, thereby ensuring the stability of the planar power device.

[0051] In one embodiment, the inversion layer 90 is doped with P-type ions and is lightly doped, and the drain region 80 is doped with N-type ions and is heavily doped.

[0052] In one embodiment, as shown in FIG. 1, the inversion layer 90 includes a first inversion region 91 and a second inversion region 92. Figure 2

[0053] ​Specifically, the first inversion region 91 and the second inversion region 92 are respectively located in the edge region of the N-type well region 20, and the first inversion region 91 and the second inversion region 92 do not contact each other. In this embodiment, the first inversion region 91 is located in the edge region of the first end of the N-type well region 20, and the second inversion region 92 is located in the edge region of the second end of the N-type well region 20. It can be understood that the first inversion region 91 is located below the edge region of the first end of the drain region 80, and the second inversion region 92 is located below the edge region of the second end of the drain region 80. This operation only sets the inversion region in the areas where the first and second ends of the drain region 80 are prone to breakdown, which can solve the problem of the breakdown effect easily occurring at the edge of the power device. The first inversion region 91 and the second inversion region 92 do not contact each other. It can be understood that the first inversion region 91 and the second inversion region 92 are only set in the edge region of the N-type well region 20, and not in the middle region of the N-type well region 20. This operation alleviates the breakdown effect of the power device, reduces the electric field and stress of the planar power device, and at the same time preserves the performance of the middle region of the planar power device, thus maximizing the preservation of the device's performance and improving the device's withstand voltage capability.

[0054] In one embodiment, the sum of the widths of the first inversion region 91 and the second inversion region 92 is less than the width of the drain region 80. Specifically, in this embodiment, the first inversion region 91 and the second inversion region 92 only need to be provided at the edge of the power device where the breakdown effect is likely to occur, while retaining the high-efficiency part of the middle section of the power device. Therefore, the sum of the widths of the first inversion region 91 and the second inversion region 92 is less than the width of the drain region 80, so as to minimize the impact of the increased first inversion region 91 and the second inversion region 92 on the performance of the middle region of the power device, and maximize the preservation of the device performance while improving the device's withstand voltage.

[0055] In one embodiment, reference Figure 2 As shown, the width W1 of the first inversion region 91 and the second inversion region 92 are both 10%-30% of the width W2 of the drain region 80.

[0056] Specifically, the first inversion region 91 and the second inversion region 92 are located between the N-type well region 20 and the drain region 80. Through TCAD simulation and experiments, this application has determined that the electric field and stress are greatest at the edge (10%-30%) of the power device. When the reverse bias voltage is increased, this edge region is the first to experience a breakdown effect, limiting the device's withstand voltage. Therefore, by keeping the width W1 of the first inversion region 91 and the second inversion region 92 within 10%-30% of the width W2 of the drain region 80, the problem of breakdown at the edge of the power device can be solved. Simultaneously, the performance of the power device in the middle region is preserved, maximizing the preservation of power device performance while improving the device's withstand voltage. Furthermore, this application's improvement in the withstand voltage of the power device is not achieved by increasing the distance between the source region 60 and the drain region 80. Therefore, this application's planar power device also solves the problem of improving withstand voltage while achieving miniaturization.

[0057] In one embodiment, the width W1 of both the first inversion region 91 and the second inversion region 92 is 10% of the width W2 of the drain region 80. By setting the width W1 of both the first inversion region 91 and the second inversion region 92 to be 10% of the width W2 of the drain region 80, the performance of the power device can be maintained to the maximum extent, and the withstand voltage capability of the power device can also be improved.

[0058] In one embodiment, reference Figure 2 As shown, the lengths L1 of the first inversion region 91 and the second inversion region 92 are both greater than the length L2 of the drain region 80.

[0059] In this embodiment, since the drain region 80 is prone to breakdown at the edge region of the N-type well region 20, the lengths L1 of the first inversion region 91 and the second inversion region 92 are both greater than the length L2 of the drain region 80. This ensures that the first inversion region 91 and the second inversion region 92 completely surround the drain region 80 at the point where they contact the drain region 80 at the edge region of the N-type well region 20. That is, the entire edge region of the drain region 80 is separated from the N-type well region 20 by the first inversion region 91 and the second inversion region 92. The first inversion region 91 and the second inversion region 92 are used to improve the withstand voltage capability of the edge region of the power device, thereby improving the withstand voltage capability of the entire power device.

[0060] In one embodiment, reference Figure 1 As shown, the thickness H1 of the first inversion region 91 and the second inversion region 92 is smaller than the thickness H2 of the drain region 80.

[0061] In the embodiment, because the doping type of the inversion layer 90 is different from the doping type of the drain region 80, the first inversion region 91 and the second inversion region 92 are arranged, which increases the on-resistance of the power device, and further affects the performance of the power device. Through a large number of experiments, it is found that the thickness H1 of the first inversion region 91 and the second inversion region 92 is less than the thickness H2 of the drain region 80, which can reduce the influence of the first inversion region 91 and the second inversion region 92 on the power device as much as possible, and further improve the withstand voltage of the power device.

[0062] In an embodiment, the first inversion region 91 and the second inversion region 92 are symmetrically arranged. Specifically, the first inversion region 91 is arranged at the lower side of the edge region of the first end of the drain region 80, and the second inversion region 92 is arranged at the lower side of the edge region of the second end of the drain region 80. The first inversion region 91 and the second inversion region 92 are arranged at the two ends of the drain region 80, respectively. In this way, the inversion region is arranged only at the positions where the breakdown effect is prone to occur at the first end and the second end of the drain region 80, which can solve the problem that the breakdown effect is prone to occur at the edge of the power device.

[0063] In an embodiment, the width of the N-type well region 20 is the same as the width of the P-type well region 30, and the thickness of the N-type well region 20 is the same as the thickness of the P-type well region 30. In the embodiment, the width and the thickness of the N-type well region 20 and the P-type well region 30 are the same, which does not need to extend the distance between the drain region 80 and the source region 60 to improve the withstand voltage of the power device, and further reduces the size of the power device, so that the power device is more miniaturized.

[0064] In an embodiment, the planar power device further comprises a gate inversion layer 90. The gate inversion layer 90 is arranged between the gate oxide layer 40 and the N-type well region 20 and the P-type well region 30. The doping type of the gate inversion layer 90 is different from the doping type of the gate metal layer 50. It can be understood that the gate inversion layer 90 comprises a first gate inversion region and a second gate inversion region. The first gate inversion region and the second gate inversion region are arranged at the edge region of the gate oxide layer 40, the N-type well region 20, and the P-type well region 30. That is, the first gate inversion region is arranged below the first end of the gate oxide layer 40 and contacts the N-type well region 20 and the P-type well region 30, and the second gate inversion region is arranged below the second end of the gate oxide layer 40 and contacts the N-type well region 20 and the P-type well region 30. Because the breakdown effect is prone to occur at the edge region of the power device, the first gate inversion region and the second gate inversion region can solve the problem that the breakdown effect is prone to occur at the edge of the power device.

[0065] In an embodiment, the width of the first gate inversion region and the width of the second gate inversion region are in the range of 10%-30% of the width of the gate metal region.

[0066] In one embodiment, the planar power device further comprises at least one of: a gate redundancy region, a drain redundancy region, and a source redundancy region.

[0067] Specifically, the gate redundancy region is arranged on the gate oxide layer 40 and located at both ends of the gate metal layer 50; the material of the gate redundancy region is different from that of the gate metal layer 50; the drain redundancy region is arranged on the N-type well region 20 and located at both ends of the drain region 80 and in contact with the drain region 80 and the isolation region 70 respectively; the material of the drain redundancy region is different from that of the drain region 80; and the source redundancy region is arranged on the P-type well region 30 and located at both ends of the source region 60 and in contact with the source region 60 and the P-type doped region 100 respectively; the material of the source redundancy region is different from that of the source region 60.

[0068] In the embodiment, the planar power device comprises at least one of: a gate redundancy region, a drain redundancy region, and a source redundancy region. It can be understood that any one of the gate redundancy region, the drain redundancy region, and the source redundancy region can be included, or two or all of them can be included. Specifically, the gate redundancy region is arranged on the gate oxide layer 40 and located at both ends of the gate metal layer 50; the material of the gate redundancy region is different from that of the gate metal layer 50. It can be understood that the gate redundancy region is arranged at the region where the breakdown effect is prone to occur at both ends of the gate metal layer 50, i.e. the region of 10%-30% of the edge of the gate metal layer 50; by setting the material of the gate redundancy region to be different from that of the gate metal layer 50, the region where the gate redundancy region is arranged cannot work due to the absence of the gate metal layer 50, so that the breakdown effect of the edge region of the planar power device is greatly reduced, the electric field and stress of the planar power device are reduced, and since the gate redundancy region is only arranged at both ends of the gate metal layer 50, the performance of the middle region of the planar power device is retained, the performance of the device is maximally retained, and the withstand voltage of the power device is improved.

[0069] In the embodiment, the source redundant region is arranged on the P-type well region 30 and located at both ends of the source region 60 and contacts the source region 60 and the P-type doped region 100 respectively; wherein the material of the source redundant region is different from the material of the source region 60. It can be understood that the source redundant region is arranged at the region where the breakdown effect is easy to occur at both ends of the source region 60, that is, the region of 10%-30% of the edge of the source region 60, and by arranging the material of the source redundant region to be different from the material of the source region 60, the region where the source redundant region is arranged cannot work due to the absence of the source region 60, so that the breakdown effect of the edge region of the planar power device is greatly reduced, the electric field and stress of the planar power device are reduced, and at the same time, the performance of the middle region of the planar power device is retained, the performance of the device is maximally retained, and the withstand voltage capability of the power device is improved.

[0070] In the embodiment, the drain redundant region is arranged on the N-type well region 20 and located at both ends of the drain region 80 and contacts the drain region 80 and the isolation region 70 respectively; wherein the material of the drain redundant region is different from the material of the drain region 80; it can be understood that the drain redundant region is arranged at the region where the breakdown effect is easy to occur at both ends of the drain region 80, that is, the region of 10%-30% of the edge of the drain region 80, and by arranging the material of the drain redundant region to be different from the material of the drain region 80, the region where the drain redundant region is arranged cannot work due to the absence of the drain region 80, so that the breakdown effect of the edge region of the planar power device is greatly reduced, the electric field and stress of the planar power device are reduced, and at the same time, the performance of the middle region of the planar power device is retained, the performance of the device is maximally retained, and the withstand voltage capability of the power device is improved.

[0071] The embodiment of the present application also provides a preparation method of a planar power device, as shown in Figure 3 the figure, comprising steps S10-S50, specifically,

[0072] Step S10: providing a semiconductor substrate 10;

[0073] Step S20: as shown in Figure 4 the figure, sequentially forming an N-type well region 20 and a P-type well region 30 on the semiconductor substrate 10; wherein the N-type well region 20 and the P-type well region 30 contact;

[0074] Step S30: as shown in Figure 5 the figure, forming a source region 60 on the P-type well region 30;

[0075] Step S40: as shown in Figure 6 the figure, forming an inversion layer 90, an isolation region 70 and a drain region 80 on the N-type well region 20; the inversion layer 90 is located between the drain region 80 and the N-type well region 20;

[0076] Step S50: Refer to Figure 7 As shown in FIG. 1, a gate oxide layer 40 is formed on the N-type well region 20, the P-type well region 30, the source region 60 and the isolation region 70, and a gate metal layer 50 is formed on the gate oxide layer 40. The isolation region 70 is arranged between the drain region 80 and the gate oxide layer 40, the inversion layer 90 is arranged between the N-type well region 20 and the drain region 80, and the inversion layer 90 is in contact with the isolation region 70. The doping type of the inversion layer 90 is different from the doping type of the drain region 80.

[0077] In this embodiment, the inversion layer 90 is formed on the N-type well region 20. The inversion layer 90 is arranged between the N-type well region 20 and the drain region 80, and the inversion layer 90 is in contact with the isolation region 70. The doping type of the inversion layer 90 is different from the doping type of the drain region 80. By arranging the inversion layer 90 at the lower end edge portion of the drain region 80, the withstand voltage capability of the planar power device can be improved.

[0078] Specifically, the inversion layer 90 is arranged at the lower end edge portion of the drain region 80. In TCAD (Technology Computer Aided Design, a semiconductor process simulation and device simulation tool) simulation and experiments, it is known that the electric field and stress at the edge (10%-30%) of the device are the largest. When the reverse bias is increased, the breakdown effect occurs first at this edge region, which limits the withstand voltage of the device. In this embodiment, the inversion layer 90 is arranged at the portion of the planar power device where the breakdown effect is prone to occur. Because the doping type of the inversion layer 90 is different from the doping type of the drain region 80, the breakdown effect can be greatly alleviated, the electric field and stress of the planar power device are reduced, and the performance of the middle region of the planar power device is retained, thereby maximizing the performance of the device and improving the withstand voltage capability of the device.

[0079] In one embodiment, the inversion layer 90 is formed on the N-type well region 20, including:

[0080] A mask plate is used to define the position of the inversion layer 90 on the N-type well region 20. The inversion layer 90 is arranged at the edge region of the N-type well region 20. P-type doping ions are implanted into the N-type well region 20 under the cover of the mask plate to form the inversion layer 90 in the N-type well region 20. The inversion layer 90 includes a first inversion region 91 and a second inversion region 92. The first inversion region 91 and the second inversion region 92 are arranged at the edge region of the N-type well region 20, respectively, and the first inversion region 91 and the second inversion region 92 do not contact each other.

[0081] In the embodiment, the first inversion region 91 is arranged at the edge region of the first end of the N-type well region 20, and the second inversion region 92 is arranged at the edge region of the second end of the N-type well region 20. It can be understood that the first inversion region 91 is arranged at the lower edge of the edge region of the first end of the drain region 80, and the second inversion region 92 is arranged at the lower edge of the edge region of the second end of the drain region 80. In this way, the inversion region is arranged only at the positions where the breakdown effect is prone to occur at the first end and the second end of the drain region 80, so that the problem that the breakdown effect is prone to occur at the edge region of the power device can be solved. The first inversion region 91 and the second inversion region 92 do not contact each other. It can be understood that the first inversion region 91 and the second inversion region 92 are arranged only at the edge region of the N-type well region 20, and are not arranged at the middle region of the N-type well region 20. In this way, the breakdown effect of the power device is alleviated, the electric field and the stress of the planar power device are reduced, the performance of the middle region of the planar power device is retained, the performance of the device is maximally retained, and the withstand voltage capability of the device is improved.

[0082] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in a certain embodiment can be referred to the related description of other embodiments.

[0083] The units described as separate components can or can not be physically separate, and the components displaying data as units can or can not be physical units, i.e., can be located in one place or distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0084] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A planar power device, characterized in that, The planar power device includes: Semiconductor substrate; An N-type well region and a P-type well region, wherein the N-type well region and the P-type well region are in contact and both are located on the semiconductor substrate; A gate oxide layer is located on the N-type well region and the P-type well region; A gate metal layer is located on the gate oxide layer; The source region is located on the P-type well region and is in contact with the gate oxide layer; An isolation region, a drain region, and an inversion layer are provided on the N-type well region. The isolation region is located between the drain region and the gate oxide layer, and the inversion layer is located between the N-type well region and the drain region, and the inversion layer is in contact with the isolation region. The doping type of the inversion layer is different from the doping type of the drain region; The inversion layer includes: a first inversion region and a second inversion region; The first inversion region and the second inversion region are respectively located only in the edge region of the N-type well region, and the first inversion region and the second inversion region do not contact each other.

2. The planar power device as described in claim 1, characterized in that, The sum of the widths of the first inversion region and the second inversion region is less than the width of the drain region.

3. The planar power device as described in claim 2, characterized in that, The widths of the first inversion region and the second inversion region are both 10%-30% of the width of the drain region.

4. The planar power device as described in claim 1, characterized in that, The lengths of both the first inversion region and the second inversion region are greater than the length of the drain region.

5. The planar power device as described in claim 1, characterized in that, The thicknesses of the first inversion region and the second inversion region are both less than the thickness of the drain region.

6. The planar power device as described in claim 1, characterized in that, The first inversion region and the second inversion region are symmetrically arranged.

7. The planar power device as described in claim 1, characterized in that, The N-type well region and the P-type well region have the same width and the same thickness.

8. A method for fabricating a planar power device, characterized in that, include: Provide semiconductor substrates; An N-type well region and a P-type well region are sequentially formed on the semiconductor substrate; wherein the N-type well region and the P-type well region are in contact. A source region is formed on the P-type well region; An inversion layer, an isolation region, and a drain region are formed on the N-type well region; the inversion layer is located between the drain region and the N-type well region. A gate oxide layer is formed on the N-type well region, the P-type well region, the source region, and the isolation region, and a gate metal layer is formed on the gate oxide layer. The isolation region is located between the drain region and the gate oxide layer, the inversion layer is located between the N-type well region and the drain region, and the inversion layer is in contact with the isolation region. The doping type of the inversion layer is different from that of the drain region. The formation of an inversion layer on the N-type well region includes: The location of the inversion layer is defined on the N-type well region using a mask, wherein, The inversion layer is located in the edge region of the N-type well region; P-type doped ions are implanted into the N-type well region under the cover of the mask plate to form the inversion layer in the N-type well region. The inversion layer includes a first inversion region and a second inversion region. The first inversion region and the second inversion region are respectively disposed only in the edge region of the N-type well region, and the first inversion region and the second inversion region do not contact each other.

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