Method for removing isolation layer at corner between semiconductor light emitting device and growth substrate

Abstract

The present application provides a semiconductor light-emitting device and a method for manufacturing the same, the method comprising forming a plurality of light-emitting diode structures having sidewall P-N junctions on a growth substrate, and forming an isolation layer on the light-emitting diode structure, wherein the LED structure has a corner at the intersection of the epitaxial structure and the growth substrate. The method also comprises forming an etchable covering channel layer on the isolation layer, forming a patterned protective layer on the covering channel layer, forming an etching channel in the covering channel layer using a first etching process, and etching the isolation layer using a second etching process to remove the corner of the isolation layer. After the second etching process, the isolation layer covers the sidewall P-N junction. The method may also comprise bonding the growth substrate to a carrier, and separating the growth substrate from the light-emitting diode structure using a laser lift-off process.

Description

Technical Field

[0001] The present application relates to the fabrication of semiconductor light emitting devices (LEDs), and more particularly to a method for fabricating semiconductor light emitting devices (LEDs), wherein a corner isolation layer is formed and removed on a growth substrate. Background Art

[0002] In the manufacture of semiconductor light emitting devices (LEDs), an epitaxial structure can be formed by using a growth substrate (e.g., a wafer including a sapphire substrate). An exemplary (LED) epitaxial structure may include: an undoped GaN layer formed on the wafer; an N-type GaN layer; a single or multiple quantum well layers; and a P-type GaN layer. A light emitting device (LED) can be formed on the wafer by selectively removing several layers of the (LED) epitaxial structure and exposing the sapphire substrate. For example, the sapphire substrate can be exposed in a selected pattern in the street region of the wafer to separate each light emitting device (LED). For a semiconductor light emitting device (LED) chip having a polygonal profile, each (LED) chip is spatially separated from an adjacent (LED) chip by a street region having a crisscross pattern.

[0003] This application relates to a method for manufacturing a semiconductor light emitting device (LED) in which an isolation layer is formed on an epitaxial structure and selectively removed from a corner of the epitaxial structure closest to a growth substrate. This application also allows for novel semiconductor light emitting devices (LEDs) manufactured using this method. Summary of the Invention

[0004] A method for manufacturing a semiconductor light emitting device (LED) includes the steps of forming a plurality of light emitting diode (LED) structures on a growth substrate. The light emitting diode (LED) structure includes a plurality of epitaxial structures having a plurality of sidewalls, wherein the sidewalls have a plurality of sidewall PN junctions. In several exemplary embodiments, the light emitting diode (LED) structure includes a plurality of dual-pad light emitting diode (LED) structures in the form of wafers, and a plurality of vertical light emitting diode (VLED) structures. In addition, the epitaxial structure may include an undoped layer (e.g., u-GaN), an N-type layer (e.g., n-GaN), a plurality of active layers (e.g., SQW or MQW), and a P-type layer (e.g., p-GaN). In some embodiments, the epitaxial structure may include a plurality of mesa surrounding structures for recessing the sidewall PN junctions.

[0005] The method also includes the step of forming an isolation layer on the light-emitting diode (LED) structure (including on the sidewall PN junction). The isolation layer includes a plurality of corners located at the intersection of the epitaxial structure and the growth substrate. In an exemplary embodiment, the growth substrate includes a wafer comprising a plurality of light-emitting diode (LED) structures and having a plurality of boundaries separating the individual light-emitting diode (LED) structures. The isolation layer can be formed on the light-emitting diode (LED) structure to a uniform thickness using a compliant deposition process and can cover the boundaries or leave the boundaries open.

[0006] After forming the isolation layer, an etchable cover channel layer may be formed on the isolation layer. The cover channel layer may comprise an etchable material, such as metal or oxide.

[0007] After forming the covering channel layer, a patterned protection layer may be formed on the covering channel layer. The patterned protection layer may include a patternable material such as photoresist, which has a plurality of openings aligned with the corners of the isolation layer.

[0008] After forming the patterned protective layer, a first etching process can be used to form a plurality of etched channels in the cover channel layer, wherein an etchant is passed through the openings in the patterned protective layer to etch away portions of the cover channel layer. The etched channels are located at the corners and can be shaped and dimensioned to surround the corners for removal using a second chemical etching step. For example, the cover channel layer can comprise a metal, and the first etching process can comprise a wet chemical etching process.

[0009] After forming the etch channel, the isolation layer can be removed from the corners by etching the isolation layer using a second etching process. For example, the isolation layer may comprise an oxide (e.g., SiO2) and the second etching process may comprise a buffered oxide etch (BOE etch). During this step, the isolation layer is removed only at the corners, leaving the isolation layer at the sidewall PN junction intact. In one exemplary embodiment, the etch channel is formed so that the isolation layer only isolates the sidewalls of the P-type layer, the sidewalls of the active layer, and a portion of the sidewalls of the N-type layer.

[0010] After etching the isolation layer, the covering channel layer and the patterned protection layer can be removed. Depending on the materials, the layers can be removed using conventional techniques.

[0011] The method may also include bonding the growth substrate to a carrier having a flexible polymer material thereon. In one exemplary embodiment, the bonding step may be performed by flip-chip bonding the LED structure to the carrier. The method may also include a laser lift-off (LLO) step, in which the growth substrate and the LED structure are separated using a laser lift-off (LLO) process.

[0012] In an alternative embodiment of this method, a capping channel layer is not formed on the isolation layer. Instead, a patterned protective layer is formed directly on the isolation layer. A first etching process then removes the isolation layer within the boundaries of the growth substrate, and a second etching process removes the corners of the isolation layer and forms a plurality of undercut sidewall structures on the sidewalls of the epitaxial structure.

[0013] A semiconductor light emitting device (LED) manufactured using this method or an alternative embodiment method includes an isolation layer covering the sidewall PN junction, the sidewall of the P-type layer, the sidewall of the active layer and a portion of the sidewall of the N-type layer, leaving an exposed undoped layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0015] Figure 1 An enlarged schematic cross-sectional view of a dual-pad semiconductor light emitting device (LED) structure is shown before a laser lift-off (LLO) step of the method and after forming an isolation layer with a corner.

[0016] Figure 2A The diagram is an enlarged schematic cross-sectional view of a plurality of dual-pad semiconductor light emitting device (LED) structures, showing the LED structures on a growth substrate, wherein an isolation layer does not extend into the boundary region.

[0017] Figure 2B The diagram is an enlarged schematic cross-sectional view of a plurality of dual-pad semiconductor light emitting device (LED) structures, showing the LED structures on a growth substrate, wherein an isolation layer extends into the boundary region.

[0018] Figure 3Ais an enlarged schematic cross-sectional view of a vertical light emitting diode (VLED) structure before a laser lift-off (LLO) step of the method and after forming an isolation layer with a corner.

[0019] Figure 3B is an enlarged schematic cross-sectional view of a vertical light emitting diode (VLED) structure having a mesa-enclosing structure before a laser lift-off (LLO) step of the method and after forming an isolation layer having a corner.

[0020] Figure 4 FIG2 is an enlarged schematic cross-sectional view of a plurality of vertical light emitting diode (VLED) structures on a growth substrate with an isolation layer extending into the boundary region thereof.

[0021] Figure 5A The enlarged schematic cross-sectional view shows the steps of the method for forming an isolation layer on a plurality of vertical light emitting diode (VLED) structures on a growth substrate.

[0022] Figure 5B An enlarged schematic cross-sectional view showing steps of the method for forming an isolation layer on a plurality of vertical light emitting diode (VLED) structures having a plurality of mesa-enclosing structures on a growth substrate.

[0023] Figure 6 An enlarged schematic cross-sectional view showing the steps of the method for forming a covering channel layer on the isolation layer.

[0024] Figure 7 An enlarged schematic cross-sectional view showing the steps of the method for forming a patterned protection layer on the capping channel layer.

[0025] Figure 8 An enlarged schematic cross-sectional view showing steps of the method for forming an etched channel using a first chemical etch process.

[0026] Figure 9 An enlarged schematic cross-sectional view showing the step of the method of etching the isolation layer using a second chemical etching process.

[0027] Figure 10 An enlarged schematic cross-sectional view showing the steps of this method for removing the capping channel layer and the patterned protective layer.

[0028] Figure 11 An enlarged schematic cross-sectional view showing steps of the method for bonding a growth substrate to a carrier having an elastic polymer material thereon.

[0029] Figure 12An enlarged schematic cross-sectional view showing a laser lift-off (LLO) step of the method, wherein the growth substrate is separated from the dual-pad semiconductor light emitting device (LED) structure.

[0030] Figure 13 The figure is an enlarged schematic cross-sectional view showing a semiconductor light emitting device (LED) manufactured using the method.

[0031] Figures 14 to 17 An enlarged schematic cross-sectional view showing an alternative embodiment method for manufacturing a semiconductor light emitting device (LED), in which a patterned protective layer can be directly deposited on an isolation layer, and a first etching process is used to etch the isolation layer to remove material in the boundary region, and a second etching process is used to etch the isolation layer to form a plurality of undercut sidewall structures.

[0032] Figures 18 to 23 An enlarged schematic cross-sectional view showing steps of the method for manufacturing a semiconductor light emitting device (LED).

[0033] Figures 24 to 27 An enlarged schematic cross-sectional view showing steps of an alternative embodiment method for manufacturing a semiconductor light emitting device (LED).

[0034] Figures 28 to 30 An enlarged schematic cross-sectional view showing a laser lift-off (LLO) step of this method or an alternative embodiment method for manufacturing a semiconductor light emitting device (LED).

[0035] Figure 31A It is a plan view of a carrier having a plurality of semiconductor light emitting device (LED) structures manufactured using this method or an alternative embodiment method.

[0036] Figure 31B To show the structure of a single semiconductor light emitting device (LED) along Figure 31A A cross-sectional view taken along section line 31A-31A.

[0037] Figures 32 to 35 An enlarged schematic cross-sectional view showing an implementation of a conventional laser lift-off (LLO) process.

[0038] Figure 36A FIG. 1 is a plan view of a carrier having a plurality of semiconductor light emitting device (LED) structures thereon fabricated using a conventional laser lift-off (LLO) process.

[0039] Figure 36B To show the structure of a single semiconductor light emitting device (LED) on a carrier along Figure 36A A cross-sectional view taken along section line 36A-36A.

[0040] Explanation of symbols:

[0041] z: height

[0042] 100, 100E: Light-emitting diode (LED) structure

[0043] 100A, 100B, 100C, 100D: Vertical light-emitting diode (VLED) structure

[0044] 101, 101A, 101B, 101C, 101D, 101E, 101PA: Isolation layer

[0045] 101a: sidewall isolation layer

[0046] 102PA: Sapphire growth substrate

[0047] 102, 102A, 102B, 102C, 102D, 102PA: Growth substrate

[0048] 111, 111A, 111B, 111C, 111E, 111PA: Corner

[0049] 112: epitaxial structure

[0050] 120, 120A: undoped layer

[0051] 122, 122A: N-type layer

[0052] 124, 124A, 124E: Active layer

[0053] 126, 126A, 126E: P-type layer

[0054] 128: N-type conductive layer

[0055] 130, 130A, 130B: P-type conductive layer

[0056] 132: p-pad

[0057] 134:n-pad

[0058] 136, 136A, 136E, 136PA: Boundary Road Area

[0059] 136EX: Exposed Boundary Area

[0060] 138, 138B: Sidewall PN junction

[0061] 138A:PN junction

[0062] 138C: Sidewall PN junction

[0063] 140, 140A, 140B, 140C: Sidewall

[0064] 142, 142C: Cover channel layer

[0065] 144, 144C: Patterned protective layer

[0066] 146, 146C: Etched channel

[0067] 148:Carrier

[0068] 150: Elastic polymer material

[0069] 152: Corner area

[0070] 154:Semiconductor light emitting device (LED)

[0071] 156E: Patterned protective layer

[0072] 158:Laser Beam

[0073] 201, 201B, 201D: Tabletop enclosure structure

[0074] 311: Undercut sidewall etching structure

[0075] 311E: Undercut sidewall structure DETAILED DESCRIPTION

[0076] Those skilled in the art will understand that when an element is referred to as being "on another element," it can be directly on the other element or intervening elements may be present. However, the term "directly" means that there are no intervening elements. Furthermore, while the terms "first," "second," and "third" are used to describe various elements, the elements should not be limited to these terms. Furthermore, unless otherwise defined, all terms are intended to have the same meaning as commonly understood by those skilled in the art.

[0077] See also Figure 1 , illustrating several initial steps in a method for fabricating a semiconductor light emitting device (LED). The method includes forming a plurality of light emitting diode (LED) structures 100 on a growth substrate 102 and forming an isolation layer 101 on the LED structures 100. The LED structures 100 have a plurality of corners 111 proximal to the growth substrate 102. Ideally, the corners 111 are perpendicular, but depending on the deposition process, the angles of the corners 111 may be greater than or less than 90 degrees.

[0078] In one exemplary embodiment, the growth substrate 102 may comprise sapphire, and the light-emitting diode (LED) structure 100 may comprise a plurality of dual-pad (LED) chips. Each LED structure 100 includes: an undoped layer 120, such as u-GaN; an N-type layer 122, such as n-GaN; a plurality of active layers 124, such as SQW or MQW; a P-type layer 126, such as p-GaN; an N-type conductive layer 128, such as a metal; a P-type conductive layer 130, such as a metal; a p-pad 132, such as a metal; and an n-pad 134, such as a metal.

[0079] Each light emitting diode (LED) structure 100 can be configured as a direct bandgap compound semiconductor light emitting diode (LED) structure formed by using several semiconductor processes. For example, the epitaxial structure 112 is grown on the growth substrate 102 by using several semiconductor processes, which includes the growth of an undoped layer 120 (such as a u-GaN layer), an N-type layer 122 (such as a Si-doped GaN layer), the active layer 124 (such as several quantum wells), and a P-type layer 126 (such as a Mg-doped GaN layer). However, the materials are only examples, and the epitaxial structure 112 can be composed of other direct bandgap compound semiconductor light emitting diode materials grown on the growth substrate 102. For example, the emission wavelength of semiconductor light can be determined by the bandgap energy of a direct bandgap semiconductor compound. The different direct bandgap energies of semiconductor light emitting materials can be selected from III-V compound semiconductors, such as In. x Ga 1-x N, GaN, Al x Ga 1-x N、In x Ga 1-x As, InGaP, GaAs, GaAsP, InP, (Al x Ga 1-x ) y In 1-y P, GaP.

[0080] The isolation layer 101 may comprise a continuous layer of a dielectric material (e.g., SiO2, Si3N4, Al2O3, or TiO2) formed to a uniform thickness using a suitable deposition process (e.g., CVD, PECVD, spin-on, or deposition via a nozzle). A representative thickness of the isolation layer 101 may be from 2000 Å (angstroms) to 500 μm. Figure 1As shown, the isolation layer 101 can be deposited on a top portion of the P-type layer 126 and on the sidewalls of the P-type layer 126. In addition, the isolation layer 101 can be deposited on the sidewalls of the active layer 124, on the sidewalls of the N-type layer 122, on the sidewalls of the undoped layer 120, and on a portion of the exposed growth substrate 102 in the boundary region 136. It is also noted that the corner 111 of the isolation layer 101 is located between the undoped layer 120 and the surface of the growth substrate 102 of the sidewall 140 of the light emitting diode (LED) structure 100. In addition, the isolation layer 101 is conformally deposited at a right angle on the corner 111 and can be deposited on any portion of the boundary region 136 or on the entire boundary region 136.

[0081] Another example Figure 1 As shown, a mesa enclosure structure 201 can be formed to provide a spacing between the sidewall PN junction 138 and the sidewall 140 of the LED structure 100. This spacing serves to extend the length of the isolation layer 101. Using the mesa enclosure structure 201, the isolation layer 101 extends from several vertical connections on the sidewall 140 of the LED structure 100 to a horizontal connection on the mesa enclosure structure 201, and then becomes a vertical connection at the sidewall PN junction 138. Different orientations of the isolation layer 101 can be provided by using different chemical etching speeds.

[0082] like Figure 2A As shown, the growth substrate 102 may include a plurality of light emitting diode (LED) structures 100 separated by the boundary region 136 . Figure 2A and Figure 2B Two different structures of the isolation layer 101 on the growth substrate 102 are shown. Figure 2A In FIG. 1 , the isolation layer 101 does not continue to enter the boundary region 136. Figure 2B In the embodiment, the isolation layer 101 continues to enter the boundary region 136 .

[0083] Figure 1 、 Figure 2A and Figure 2BThe LED structure 100 shown has the construction of a conventional flip-chip light-emitting diode (FCLED). In each LED structure 100, a P-type conductive layer 130 can be bonded to the P-type layer 126 using several conductive layers (e.g., a P-type ohmic contact layer), along with several additional p-metal layers (if desired). For example, a P-type ohmic contact layer can include ITO, Ni, Ag, Au, Pt, Pd, or alloys of these metals. P-type conductive layer 130 can include Cr, Ni, Al, Au, Cu, Ti, W, tin, or alloys of these metals. N-type conductive layer 128 can include Cr, Al, Ti, Ni, Au, or alloys of these metals. P-pad 132 can be conductive to the P-type layer 126, while n-pad 134 can be conductive to the N-type layer 122.

[0084] See also Figure 3A , a vertical light emitting diode (VLED) structure 100A has the structure of a vertical light emitting diode (VLED) wafer. The vertical light emitting diode (VLED) structure 100A includes an undoped layer 120A, an N-type layer 122A, an active layer 124A, and a P-type layer 126A, substantially as shown. As before, according to the current method, an isolation layer 101A having a plurality of corners 111A has been formed on the P-type layer 126A and on a portion of the growth substrate 102A, substantially as previously described. Figure 3A In the vertical light emitting diode (VLED) structure 100A, the isolation layer 101A may also be formed on the sidewall 140A of the vertical light emitting diode (VLED) structure 100A and the sidewall of the PN junction 138A.

[0085] See also Figure 3B A vertical light emitting diode (VLED) structure 100B has a structure of a vertical light emitting diode (VLED) wafer on a growth substrate 102B, which is essentially the vertical light emitting diode (VLED) structure 100A ( Figure 3A However, the vertical light emitting diode (VLED) structure 100B also includes a mesa surrounding structure 201B, which is essentially the mesa surrounding structure 201 ( Figure 1 ) is constructed. Using the tabletop enclosing structure 201 ( Figure 1 ) and 201B( Figure 3B ), a sidewall PN junction 138B is separated from the sidewall 140B of the vertical light emitting diode (VLED) structure 100B. As before, an isolation layer 101B having a corner 111B has been formed on the sidewall 140B of the VLED wafer, on the mesa surrounding structure 201B, and on the sidewall PN junction 138B. Figure 3A and Figure 3B In the embodiment, a P-type conductive layer 130A ( Figure 3A )、130B( Figure 3B ) may include ITO, Ni, Ag, Au, Pt, Pd or alloys thereof. Figure 4 In FIG. 1 , a plurality of vertical light emitting diode (VLED) structures 100A have been formed on a growth substrate 102A, and the isolation layer 101A does not continue to enter the boundary region 136A.

[0086] See also Figures 5A to 10 , showing further steps in this method for manufacturing a semiconductor light emitting device (LED). Figure 5A In the embodiment, an isolation layer 101C has been formed on a plurality of vertical light emitting diode (VLED) structures 100C on a growth substrate 102C, and includes a plurality of corners 111C at the intersections of the vertical light emitting diode (VLED) structures 100C and the growth substrate 102C, substantially as described previously. Figure 5B In another embodiment, an isolation layer 101D is formed on a plurality of vertical light emitting diode (VLED) structures 100D having a plurality of mesa-surrounding structures 201D on a growth substrate 102D. The isolation layer 101C ( Figure 5A ) or isolation layer 101D( Figure 5B ) is conformally formed on the vertical light emitting diode (VLED) structure 100C to a uniform thickness. Figure 5A As shown, the isolation layer 101C covers the sidewall 140C including a plurality of sidewall PN junctions 138C and maintains the isolation of the vertical light emitting diode (VLED) structures 100D from each other on the growth substrate 102C.

[0087] See also Figure 6 After forming the isolation layer 101C, an etchable cover channel layer 142C may be formed on the isolation layer 101C. The cover channel layer 142C may include an etchable material including a metal (eg, Ti) or an oxide (eg, SiO2).

[0088] See also Figure 7 After forming the cover channel layer 142C, a patterned protection layer 144C may be formed on the cover channel layer 142C. The patterned protection layer 144C may include a patternable material such as photoresist.

[0089] See also Figure 8After forming the patterned protective layer 144C, a plurality of etched channels 146C may be formed in the cover channel layer 142C using a first chemical etching process. The etched channels 146C are located above the corners 111C and may have dimensions that are shaped and sized, such as a height z above the growth substrate 102C, to surround the corners 111C for removal using a second chemical etching step. The patterned protective layer 144C includes a plurality of openings formed using photolithography that determine the location, shape, and size of the etched channels 146C. In an exemplary embodiment, the first chemical etching process may be performed using an etching chemical solution for metals to provide selective wet etching to remove portions of a cover channel layer 142C comprising a metal (e.g., Ti).

[0090] See also Figure 9 After forming the etched channel 146C, the isolation layer 101C can be etched using a second chemical etching process to remove the corner 111C of the isolation layer 101C. In one exemplary embodiment, the isolation layer 101C can include SiO2, and the second chemical etching process can be performed using a BOE etch. Note that during this step, the isolation layer 101C is only removed at the corner 111C, leaving the isolation layer 101C covering the sidewall PN junction 138C.

[0091] In another embodiment, the isolation layer 101C may comprise Si3N4, and the capping channel layer 142C may comprise SiO2. For a BOE chemical etch, the etching rate of Si3N4 is slower than that of SiO2 (for example, etching SiO2 to 500 nm in BOE takes only seconds, while etching Si3N4 to 500 nm in BOE takes minutes). Therefore, during the first etching process, the SiO2 capping channel layer 142C can be removed faster than the Si3N4 isolation layer 101C, thereby forming an etched channel 146C. By etching in the same BOE solution for a longer period of time, the Si3N4 isolation layer 101C at the corner 111C can be removed. Note that this method only removes the isolation layer 101C at the corner 111C, leaving the isolation layer 101C at the sidewall PN junction 138C protected and unetched.

[0092] In some embodiments, for example, a mesa-surrounding structure 201B ( Figure 3B ) of a vertical light emitting diode (VLED) structure 100B ( Figure 3B ), and having a plurality of table-surrounding structures 201D ( Figure 5B ) of a plurality of vertical light emitting diode (VLED) structures 100D ( Figure 5B ), the table surrounding structure 201B ( Figure 3A) or 201D( Figure 5B ) provides a structural function to slow down the etching speed / rate. In the embodiment described, the covering channel layer 142C ( Figure 7 ) and the isolation layer 101B ( Figure 3B ) or 101D( Figure 5B ) has a transition direction of etching from a vertical direction to a horizontal direction. The mesa surrounding structure 201B ( Figure 3B ) or 201D( Figure 5B ) utilizes the concept of etching rate having different etching speeds / rates in different directions for a target etching layer. For some applications, if necessary, the mesa surrounding structure 201B ( Figure 3B ) or 201D( Figure 5B ) can be manufactured into several mesa structures (similar to steps) as a geometric control of the etching conditions.

[0093] See also Figure 10 After etching the isolation layer 101C, the covering channel layer 142C and the patterned protection layer 144C may be removed. Depending on the materials, the layers may be removed using conventional techniques.

[0094] See also Figure 11 The method may also include bonding the growth substrate 102 to a carrier 148 having a resilient polymer material 150 thereon. This bonding step is part of a laser lift-off (LLO) process, which will be described further below. The bonding step may be performed by flip-chip wafer bonding the light emitting diode (LED) structure 100 to the carrier 148.

[0095] See also Figure 12 , the method may also include a laser lift-off (LLO) step, in which the growth substrate 102 is separated from the light emitting diode (LED) structure 100 by using a laser lift-off process. U.S. Publication No. US 2021 / 0066541 by Chu et al., which is incorporated herein by reference, discloses a laser lift-off process (LLO) and the above-mentioned bonding step. In one embodiment, the corner 111 of the isolation layer 101 has been removed. The original isolation layer 101 on the corner area 152 cannot be damaged so that a portion of the isolation layer is peeled off (not shown) and remains on the growth substrate 102. In addition, the current (LLO) step transfers the light emitting diode (LED) structure 100 to the carrier 148 without damaging the isolation layer 101 on the sidewall PN junction 138 ( Figure 1 This results in a robust light emitting diode (LED) structure 100 for various applications. In addition, the lane region 136 of the carrier 148 remains clean (free of isolation residues).

[0096] See also Figure 13 , shows a semiconductor light emitting device (LED) 154 manufactured using this method. The semiconductor light emitting device (LED) 154 includes an isolation layer 101 covering a sidewall PN junction 138. In addition, the isolation layer 101 covers a sidewall ( Figure 1 ), a side wall of the active layer 124 ( Figure 1 ) and a sidewall of the N-type layer 122 ( Figure 1 ) portion, leaving the undoped layer 120 ( Figure 1 In some cases, the isolation layer 101 covers a sidewall of the P-type layer 126 , a sidewall of the active layer 124 , a sidewall of the N-type layer 122 , and a portion of the undoped layer 120 , leaving the rest of the undoped layer 120 exposed.

[0097] See also Figures 14 to 17 , shows an alternative embodiment method for removing an isolation layer 101E in the boundary region of a growth substrate 102E and forming an undercut sidewall structure 311E. Figure 14 In the embodiment, a patterned protection layer 156E has been deposited and patterned to cover the plurality of light emitting diode (LED) structures 100E and portions of the isolation layer 101E on the boundary region 136E of the growth substrate 102E. Figure 15 Portions of the isolation layer 101E on the street region 136E are shown removed by a dry etching process or a chemical etching process. For applications requiring anisotropic structures, a dry etching process can be used to remove the isolation layer 101E on the street region 136E. Figure 16 and Figure 17 The undercut sidewall structure 311E is shown formed by wet etching to remove portions of the isolation layer 101E on the lane region 136E. A wet chemical solution such as BOE can be applied to initiate wet etching on portions of the isolation layer 101E on the exposed sidewalls of the light emitting diode (LED) structure 100E. By controlling the etching time and avoiding the isolation layer 101E from contacting the active layer 124 ( Figure 1 ) is over-etched to form an undercut sidewall structure 311E. Figure 16 The undercut sidewall structure 311E is shown. In addition, the isolation layer 101E is etched at the corner 111E, but the isolation layer 101E still covers a portion of the N-type layer 122E, the active layer 124E, and the P-type layer 126E. This feature improves reliability and prevents current leakage in the light-emitting diode (LED) structure 100E. Figure 17 , the patterned protection layer 156E has been removed.

[0098] Example (method)

[0099] See also Figures 18 to 23 A further implementation of this method is shown in an example. Figure 18 In the embodiment, a covering channel layer 142 has been conformally deposited on the light emitting diode (LED) structure 100 ( Figure 1 The isolation layer 101 comprises SiO2 (5000A), and the capping channel layer 142 comprises Ti (2000A). Figure 19 A patterned protection layer 144 composed of photoresist is shown and is patterned to cover the light emitting diode (LED) structure 100 . Figure 20 A first etching process (eg, diluted BOE) is shown to remove a portion of the capping channel layer 142 and form an etched channel 146. Note that the SiO2 spacer layer 101 at the corner 111 is partially removed by the first etching (eg, diluted BOE). Figure 21 It shows a second etching process performed in the same diluted BOE solution. The Ti capping channel layer 142 is further etched, and the isolation layer 101 at the corner 111 has been removed. Figure 22 The patterned protective layer 144 is shown to have been removed. Figure 23 The Ti capping channel layer 142 is shown having been removed / etched using a Ti etchant (ie, does not etch SiO2). Note that the corner 111 of the LED structure does not have the isolation layer 101.

[0100] Example (alternative embodiment method)

[0101] See also Figures 24 to 27 , a further embodiment of the alternative embodiment method is shown in an example. Figure 24 In FIG. 1 , a patterned protection layer 144 covers the light emitting diode (LED) structure 100 and a portion of the isolation layer 101 on the boundary region 136 of the growth substrate 102. The isolation layer 101 is exposed in an exposed boundary region 136EX. Figure 25 In the embodiment, a dry etching process may be used to etch the exposed isolation layer 101 located at the exposed channel region 136EX. Figure 26 As shown, a wet chemical solution such as BOE can be applied to wet etch starting from the exposed sidewall spacer layer 101a. The wet chemical solution is configured to etch the spacer layer 101 under the patterned protection layer 144. The etching time is controlled to avoid over-etching the spacer layer 101 to the active layer 124. Figure 26 An undercut sidewall etch structure 311 is also shown, and the isolation layer 101 is removed at the corner 111. However, the isolation layer 101 still covers a portion of the N-type layer 122, the active layer 124, and the P-type layer 126. Figure 27 In FIG. 1 , the patterned protection layer 144 has been removed.

[0102] Example (One embodiment of the laser lift-off (LLO) process)

[0103] See also Figures 28 to 30 , showing a further implementation of the laser lift-off (LLO) process. Figure 28 As shown, corners 111 of the isolation layer 101 have been removed from the light emitting diode (LED) structure 100 using this method or an alternative embodiment method. Figure 29 A laser beam 158 is shown for performing the LLO process. Figure 30 It is shown that there is no isolation residue (ie, no SiO 2 residue on the growth substrate 102 in the street region 136 , and no SiO 2 stripped residue on the elastic polymer material 150 in the street region 136 ). Figure 31A and Figure 31B The lack of SiO2 residue on the support 148 is also shown.

[0104] Example (Prior Art Laser Lift Off (LLO) Process)

[0105] See also Figures 32 to 36A , showing an implementation of a prior art laser lift-off (LLO) process for manufacturing a prior art light emitting diode (LED) structure 100PA. Figure 32 A conventional flip-chip wafer light emitting diode (LED) structure 100PA is shown on a sapphire growth substrate 102PA. After conventional wafer processing, a portion of an isolation layer 101PA remains on the street area 136PA and the corner 111PA. Figure 33 The conventional flip-chip LED structure 100PA is shown in wafer form on a growth substrate 102PA. The conventional flip-chip LED structure 100PA is flipped over and bonded to a carrier 148 comprising an elastic polymer material 150. A corner 111PA of the isolation layer 101PA remains on the boundary region 136PA of the growth substrate 102PA. Figure 34 A laser beam 158, carrier 148, and elastic polymer material 150 (as previously described) are shown for performing a (LLO) process. Figure 35 It is shown that there may be isolation residues (such as SiO 2 residues) on the growth substrate 102PA in the boundary area 136PA and stripped isolation residues (such as SiO 2 residues) on the elastic polymer material 150 in the boundary area 136PA. Figure 36A and Figure 36B Also shown are isolation residues (e.g., SiO2 residues) on the elastomeric polymer material 150 of the carrier 148. The present method eliminates the isolation residues to provide a more reliable and robust light emitting diode (LED) structure 100 ( Figure 2A ).

[0106] Although some exemplary embodiments and examples have been discussed above, those skilled in the art will recognize certain modifications, permutations, additions, and sub-combinations thereof. It is therefore intended that the scope of protection of the claims of this application be interpreted to include all such modifications, permutations, additions, and sub-combinations as fall within their true spirit and scope.

Claims

1. A method for manufacturing a semiconductor light-emitting device, characterized in that: Include: forming a plurality of light-emitting diode structures on a growth substrate, wherein the plurality of light-emitting diode structures include a plurality of epitaxial structures having a plurality of sidewalls, and the plurality of epitaxial structures include an undoped layer, an N-type layer, an active layer, and a P-type layer; forming an isolation layer on the plurality of light-emitting diode structures, including on the plurality of sidewalls of the plurality of epitaxial structures, wherein the isolation layer includes a plurality of corners between the undoped layer and the growth substrate; forming an etchable covering channel layer on the isolation layer; forming a patterned protection layer on the covering channel layer, wherein the covering channel layer has a plurality of openings aligned with the plurality of corners of the isolation layer; Etching a plurality of channels in the cover channel layer using a first etching process, wherein a first etchant is passed through the plurality of openings in the patterned protection layer to etch away portions of the cover channel layer; etching the isolation layer using a second etching process to remove the corners of the isolation layer, wherein a second etchant passes through the channels to remove the corners, leaving portions of the isolation layer covering sidewalls of the P-type layers, sidewalls of the active layers, and sidewalls of the N-type layers; and The patterned protection layer and the covering channel layer are removed.

2. The manufacturing method according to claim 1, wherein The capping channel layer comprises a metal, the first etching process comprises wet chemical etching of the metal, the isolation layer comprises an oxide, and the second etching process comprises buffered oxide etching.

3. The manufacturing method according to claim 1, wherein: The method further includes bonding the growth substrate to a carrier and using a laser lift-off process to separate the growth substrate from the plurality of light-emitting diode structures, wherein the carrier has an elastic polymer material on it.

4. The manufacturing method according to claim 1, wherein: The growth substrate includes a plurality of boundaries separating the plurality of light-emitting diode structures, and after the isolation layer is formed, the isolation layer covers the plurality of boundaries.

5. The manufacturing method according to claim 1, wherein: The growth substrate includes a plurality of boundaries separating the plurality of light-emitting diode structures, and after the isolation layer is formed, the isolation layer only partially covers the plurality of boundaries.

6. The manufacturing method according to claim 1, wherein: The plurality of epitaxial structures include a plurality of mesa enclosure structures configured to slow down an etching speed / rate during the second etching process.

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