Voltage regulating circuit and electronic device
By introducing a protection circuit into the voltage regulation circuit, the problem of logic disorder caused by the power-down of the timing control module is solved, the boost module is protected, and the reliability of the voltage regulation circuit is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- VIVO MOBILE COMM CO LTD
- Filing Date
- 2022-07-20
- Publication Date
- 2026-05-15
AI Technical Summary
When a mobile terminal is powered off or restarted, some switching devices in the existing voltage regulation circuit may be directly turned on due to control logic disorder, causing a short circuit to ground in the system power supply, burning out the switching devices in the voltage regulation circuit, and leading to circuit failure.
By introducing a protection circuit into the voltage regulation circuit, the protection circuit protects the boost module when the timing control module is powered down, avoiding logic disorder caused by the power-down of the timing control module and ensuring the normal operation of the voltage regulation circuit.
This effectively avoids damage to the boost module switching devices caused by the power-down of the timing control module, thus improving the reliability of the voltage regulation circuit.
Smart Images
Figure CN115149787B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic technology, specifically relating to a voltage regulation circuit and an electronic device. Background Technology
[0002] With the development of technology, electronic devices such as mobile terminals are becoming more and more functional and integrated, and power consumption issues are becoming more and more prominent. Power amplifiers are the main power-consuming components in mobile terminals, so reducing the power consumption of power amplifiers has become a key technology for extending the lifespan of mobile devices.
[0003] In related technologies, to reduce the power consumption of power amplifiers, mobile terminals typically employ Average Power Tracking (APT) technology. APT technology automatically adjusts the operating voltage of the power amplifier based on its pre-set output power and its own parameters, thereby improving efficiency and saving energy. The APT implementation circuit architecture includes a voltage regulation circuit that adjusts the voltage output from the electronic device's system power supply to power the load. However, when the mobile terminal is powered off or restarted, some switching devices in the existing voltage regulation circuit may conduct directly due to control logic malfunction, potentially causing a short circuit to ground in the mobile terminal's system power supply. This short circuit generates a large current, burning out some switching devices in the voltage regulation circuit and leading to circuit failure. Summary of the Invention
[0004] This application aims to provide a voltage regulation circuit and electronic device that solves the problem that some switching devices in the existing voltage regulation circuit may be directly turned on due to control logic disorder when the mobile terminal is turned off or restarted. This provides protection for the switching devices of the voltage regulation circuit and improves the reliability of the voltage regulation circuit.
[0005] To solve the above-mentioned technical problems, this application is implemented as follows:
[0006] In a first aspect, embodiments of this application provide a voltage regulation circuit, which includes:
[0007] First power source;
[0008] A boost module, wherein the input terminal of the boost module is connected to the first power supply;
[0009] A step-down module, wherein the input terminal of the step-down module is connected to the output terminal of the step-up module, and the output terminal of the step-down module is used to output voltage to the electrical load;
[0010] A timing control module, the output of which is connected to the boost module and the buck module respectively;
[0011] A protection circuit is connected to the first power supply and is used to protect the boost module when the timing control module is powered down.
[0012] Secondly, embodiments of this application provide an electronic device comprising:
[0013] The voltage regulation circuit as described in the first aspect.
[0014] In an embodiment of the present invention, a voltage regulation circuit is provided, which includes a first power supply, a boost module, a buck module, a timing control module, and a protection circuit. Specifically, by setting the protection circuit, the boost module is protected when the timing control module is powered down, so as to avoid damage to some switching devices of the boost module due to logic disorder caused by the power-down of the timing control module, thereby ensuring the normal operation of the voltage regulation circuit and improving the reliability of the voltage regulation circuit.
[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.
[0017] Figure 1 This is a circuit block diagram of a voltage regulation circuit provided in an embodiment of the present invention.
[0018] Figure 2 This is a schematic diagram of the structure of the first voltage regulation circuit provided in the embodiment of the present invention.
[0019] Figure 3 This is a schematic diagram of the structure of the second voltage regulation circuit provided in the embodiment of the present invention.
[0020] Figure 4 This is a schematic diagram of the third voltage regulation circuit provided in the embodiment of the present invention. Detailed Implementation
[0021] Embodiments of the present invention will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0022] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.
[0023] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0024] The control circuit provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.
[0025] This invention provides a voltage regulation circuit for use in electronic devices, such as mobile phones, tablets, laptops, and handheld computers.
[0026] Please see Figure 1 This invention discloses a circuit block diagram of a voltage regulation circuit, which includes a first power supply B1, a boost module U1, a buck module U2, a timing control module U3, and a protection circuit U4. The input terminal of the boost module U1 is connected to the first power supply B1; the input terminal of the buck module U2 is connected to the output terminal of the boost module U1, and the output terminal of the buck module U2 is used to output voltage to the electrical load EL; the output terminal of the timing control module U3 is connected to both the boost module U1 and the buck module U2; the protection circuit is connected to the first power supply, and the protection circuit U4 is used to protect the boost module U1 when the timing control module U3 is powered down.
[0027] In this embodiment, once the battery of the electronic device is installed, the first power supply B1 is in a powered-on state. Regardless of whether the electronic device is powered on or off, as long as the first power supply is not damaged, the first power supply B1 can output voltage. The output voltage of the first power supply B1 is VCC. The output voltage VCC of the first power supply B1 can supply power to the electrical load EL through the boost module U1 and the buck module U2. The output voltage VCC of the first power supply B1 can also supply power to the protection circuit U4.
[0028] In this embodiment, as Figure 2 , Figure 3 and Figure 4 As shown, the boost module U1 includes a switch group and a boost capacitor C1. The switch group is connected to the first power supply B1, the buck module U2 and the timing control module U3 respectively, and the boost capacitor C1 is connected to the switch group.
[0029] In this embodiment, the switch group includes a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, and a fourth NMOS transistor Q4. The gates of the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 are respectively connected to the output terminal of the timing control module U3. The drain of the first NMOS transistor Q1 is connected to the first power supply B1, and the source of the first NMOS transistor Q1 is connected to the drain of the second NMOS transistor Q2. The source of the second NMOS transistor Q2 is connected to the buck module U2. The drain of the third NMOS transistor Q3 is connected to the drain of the first NMOS transistor Q1, and the source of the third NMOS transistor Q3 is connected to the drain of the fourth NMOS transistor Q4. The source of the fourth NMOS transistor Q4 is connected to the ground terminal GND. The first terminal of the boost capacitor C1 is connected to the source of the first NMOS transistor Q1, and the second terminal of the boost capacitor C1 is connected to the source of the third NMOS transistor Q3.
[0030] In this embodiment, the boost module U1 is used to boost the output voltage VCC of the first power supply B1, and the voltage output by the boost module U1 supplies power to the buck module U2.
[0031] In this embodiment, the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 are field-effect transistor switches, and each of them can be selected as an enhancement-mode N-channel MOSFET. Utilizing the working principle of field-effect transistors, the timing control module U3 can control the on / off state of the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4, thereby controlling the output voltage of the boost module U1. The circuit structure is simple.
[0032] In this embodiment, the working principle of the boost module U1 is as follows: First, the timing control module U3 controls the first NMOS transistor Q1 and the fourth NMOS transistor Q4 to be turned on respectively, and the timing control module U3 controls the second NMOS transistor Q2 and the third NMOS transistor Q3 to be turned off respectively. When the first NMOS transistor Q1 and the fourth NMOS transistor Q4 are turned on respectively, and the second NMOS transistor Q2 and the third NMOS transistor Q3 are turned off respectively, the first power supply B1 charges the boost capacitor C1 through the first NMOS transistor Q1. At this time, the potential of the first terminal of the boost capacitor C1 is equal to the output voltage VCC of the first power supply B1, the potential of the second terminal of the boost capacitor C1 is zero, and the voltage across the boost capacitor C1 is equal to the output voltage VCC of the first power supply B1.
[0033] Then, the timing control module U3 controls the first NMOS transistor Q1 and the fourth NMOS transistor Q4 to turn off respectively, and controls the second NMOS transistor Q2 and the third NMOS transistor Q3 to turn on respectively. When the second NMOS transistor Q2 and the third NMOS transistor Q3 are turned on respectively, and the first NMOS transistor Q1 and the fourth NMOS transistor Q4 are turned off respectively, the first power supply B1 charges the boost capacitor C1 through the third NMOS transistor Q3. At this time, the potential of the second terminal of the boost capacitor C1 is equal to the output voltage VCC of the first power supply B1. Since the voltage across the boost capacitor C1 cannot change abruptly, the potential of the first terminal of the boost capacitor C1 rises to 2VCC, thereby making the output voltage of the boost module U1 2VCC, realizing the boost of the boost module U1.
[0034] In this embodiment, the output voltage of the boost module U1 is VCC to 2VCC.
[0035] For example, when the output voltage VCC of the first power supply B1 is 48V, the input voltage of the boost module U1 is 48V, and the output voltage of the boost module U1 is 48V to 96V.
[0036] In this embodiment, as Figure 2 , Figure 3 and Figure 4 As shown, the step-down module U2 includes the fifth NMOS transistor Q5, inductor L, and step-down capacitor C2.
[0037] In this embodiment, the gate of the fifth NMOS transistor Q5 is connected to the output terminal of the timing control module U3, the drain of the first NMOS transistor Q1 is connected to the source of the second NMOS transistor Q2, and the source of the fifth NMOS transistor Q5 is connected to the ground terminal GND; the first end of the inductor L is connected to the source of the second NMOS transistor Q2, and the second end of the inductor L is connected to one end of the step-down capacitor C2; the other end of the step-down capacitor C2 is connected to the ground terminal GND; the two ends of the step-down capacitor C2 are the output terminals of the step-down module U2.
[0038] In this embodiment, the step-down module U2 is used to step down the voltage output by the boost module U1, and the voltage output by the step-down module U2 supplies power to the electrical load EL.
[0039] In this embodiment, the fifth NMOS transistor Q5 is a field-effect transistor switch, and it can be selected as an enhancement-mode N-channel MOSFET. Utilizing the working principle of the field-effect transistor, the switching frequency or duty cycle of the second NMOS transistor Q2 and the fifth NMOS transistor Q5 can be controlled by the timing control module U3, thereby controlling the output voltage of the buck module U2. The circuit structure is simple.
[0040] In this embodiment, the working principle of the buck module U2 is as follows: the timing control module U3 controls the second NMOS transistor Q2 to turn on and the timing control module U3 controls the fifth NMOS transistor Q5 to turn off. Since the fifth NMOS transistor Q5 is turned off, the voltage output by the boost module U1 cannot be transmitted to the fifth NMOS transistor Q5. Therefore, the voltage output by the boost module U1 is transmitted to the inductor L. The inductor L converts electrical energy into magnetic energy and stores it. The voltage after energy storage in the inductor L charges the buck capacitor C2. At the same time, the voltage after energy storage in the inductor L supplies power to the electrical load EL. Since the current of the inductor L cannot change abruptly, the load voltage across the electrical load EL gradually increases.
[0041] When the load voltage reaches the preset load voltage, the timing control module U3 controls the second NMOS transistor Q2 to turn off and the timing control module U3 controls the fifth NMOS transistor Q5 to turn on. The boost module U1 no longer supplies power to the electrical load EL. The magnetic energy stored in the inductor L is converted into electrical energy and released. The inductor L acts as the power supply in the buck module U2 to supply power to the electrical load EL. The voltage output by the inductor L gradually decreases.
[0042] When the output voltage of inductor L is less than the preset load voltage, the timing control module U3 controls the second NMOS transistor Q2 to turn on again, and controls the fifth NMOS transistor Q5 to turn off. The boost module U1 supplies power to the electrical load EL again, and simultaneously charges the inductor L. This process repeats. By controlling the turn-on and turn-off of the second NMOS transistor Q2 and the fifth NMOS transistor Q5, the energy stored and released by the inductor L is controlled, thereby realizing the voltage reduction of the buck module U2.
[0043] In this embodiment, the preset load voltage is the voltage required for the electrical load EL to operate.
[0044] In this embodiment, the positive and negative terminals of inductor L change when the inductor L stores and releases energy; when inductor L stores energy, the first terminal of inductor L is the positive terminal and the second terminal of inductor L is the negative terminal; when inductor L releases energy, the first terminal of inductor L is the negative terminal and the second terminal of inductor L is the positive terminal.
[0045] In this embodiment, when the second NMOS transistor Q2 is turned off, the polarity of the inductor L is reversed. At this instant, the inductor L cannot supply power to the load EL. At this time, the buck capacitor C2 supplies power to the load EL.
[0046] In this embodiment, one end of the electrical load EL is connected to one end of the step-down capacitor C2, and the other end of the electrical load EL is connected to the ground terminal GND.
[0047] In this embodiment, the electrical load EL can be various electrical modules in an electronic device. Different electrical modules have different operating frequency bands and require different input voltages and input currents.
[0048] In this embodiment, the timing control module U3 is used to control the turn-on and turn-off of the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, the fourth NMOS transistor Q4, and the fifth NMOS transistor Q5, respectively. At the same time, the timing control module U3 is also used to control the order in which the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, the fourth NMOS transistor Q4, and the fifth NMOS transistor Q5 are turned on and turned off, respectively.
[0049] In this embodiment, without the protection circuit U4, the power supply voltage required by the timing control module U3 is much lower than that of the first power supply B1. Therefore, the first power supply B1 cannot be directly used to power the timing control module U3; an additional power supply is needed. When the electronic device is powered off or restarted, the additional power supply will power down, while the first power supply B1 will not. The first power supply B1 continues to power the boost module U1. The power-down of the additional power supply causes the timing control module U3 to power down. When the timing control module U3 powers down, it may cause damage to the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor in the timing control module U3. The control logic of transistor Q4 is disordered, causing the third NMOS transistor Q3 and the fourth NMOS transistor Q4 to conduct simultaneously. This results in a direct short circuit to ground of the first power supply B1, generating a large current. This large current will burn out the third NMOS transistor Q3 and the fourth NMOS transistor Q4, causing the voltage regulation circuit to fail. A protection circuit U4 is set up to protect the third NMOS transistor Q3 and the fourth NMOS transistor Q4 of the boost module U1 when the timing control module U3 is powered down. This prevents the third NMOS transistor Q3 and the fourth NMOS transistor Q4 from conducting due to the timing disorder caused by the timing control module U3 being powered down, thus ensuring the reliability of the voltage regulation circuit.
[0050] In this embodiment, the voltage regulation circuit uses a boost module U1 to boost the output voltage VCC of the first power supply B1 and a buck module U2 to buck the output voltage of the boost module U1. When the boost amount of the boost module U1 is greater than the buck amount of the buck module U2, the voltage regulation circuit is essentially a boost circuit; when the boost amount of the boost module U1 is less than the buck amount of the buck module U2, the voltage regulation circuit is essentially a buck circuit. This allows for dynamic adjustment of the output voltage of the buck module U2 according to the power demand of the electrical load EL, thus supplying power to the electrical load EL and saving energy.
[0051] For example, when the output voltage VCC of the first power supply B1 is 48V, the 48V output voltage of the first power supply B1 is boosted by the boost module U1, and the output voltage of the boost module U1 is 60V. Then, the 60V voltage is stepped down by the buck module U2, and the output voltage of the buck module U2 is 50V. The boost amount of the boost module U1 is 12V, and the buck amount of the buck module U2 is 10V. The boost amount of the boost module U1 is greater than the buck amount of the buck module U2. The output voltage of the buck module U2 is greater than the output voltage VCC of the first power supply B1. This voltage regulation circuit is essentially a boost circuit.
[0052] For example, when the output voltage VCC of the first power supply B1 is 48V, the 48V voltage is boosted by the boost module U1, and the output voltage of the boost module U1 is 60V. Then, the 60V voltage is stepped down by the buck module U2, and the output voltage of the buck module U2 is 24V. The boost of the boost module U1 is 12V, and the buck of the buck module U2 is 36V. The boost of the boost module U1 is less than the buck of the buck module U2. The output voltage of the buck module U2 is smaller than the output voltage VCC of the first power supply B1. This voltage regulation circuit is essentially a buck circuit.
[0053] In one embodiment, such as Figure 2 and Figure 3 As shown, the protection circuit U4 includes a voltage conversion circuit. The input terminal of the voltage conversion circuit is connected to the first power supply B1, and the output terminal of the voltage conversion circuit is connected to the power supply terminal of the timing control module U3.
[0054] In this embodiment, the voltage conversion circuit can step down the output voltage VCC of the first power supply B1 and use the output voltage of the voltage conversion circuit to power the timing control module U3.
[0055] In this embodiment, the voltage conversion circuit can be any type of step-down circuit with step-down function, such as an LDO module or a DC-DC conversion module.
[0056] In this embodiment, the output voltage of the voltage conversion circuit is much smaller than the output voltage VCC of the first power supply B1.
[0057] For example, the output voltage VCC of the first power supply B1 is 48V. The voltage conversion circuit reduces the output voltage of the first power supply B1 to 3.3V.
[0058] In one embodiment, such as Figure 2 As shown, the voltage conversion circuit includes an LDO module.
[0059] The input and enable terminals of the LDO module are connected to the first power supply B1, and the output terminal of the LDO module is connected to the power supply terminal of the timing control module U3.
[0060] In this embodiment, the LDO module is a low-dropout linear regulator module. The input and enable terminals of the LDO module are connected to the first power supply B1, and the output terminal of the LDO module is connected to the power supply terminal of the timing control module U3. The first power supply B1 supplies power to the timing control module U3 through the LDO module. Since the first power supply B1 is always powered on, the timing control module U3 is powered on regardless of whether the electronic device is powered on or off. This effectively avoids the timing control module U3 from being powered off or restarted due to the electronic device, thereby preventing the third NMOS transistor Q3 and the fourth NMOS transistor Q4 from being turned on simultaneously, thus improving the reliability of the voltage regulation circuit.
[0061] In one embodiment, such as Figure 3 As shown, the voltage conversion circuit includes a DC-DC conversion module.
[0062] The input terminal of the DC-DC converter module is connected to the first power supply B1, and the output terminal of the DC-DC converter module is connected to the power supply terminal of the timing control module U3.
[0063] In this embodiment, the DC-DC conversion module is a DC-DC step-down module. The input terminal of the DC-DC conversion module is connected to the first power supply B1, and the output terminal of the DC-DC conversion module is connected to the power supply terminal of the timing control module U3. The first power supply B1 supplies power to the timing control module U3 through the DC-DC conversion module. Since the first power supply B1 is always powered on, the timing control module U3 is powered on regardless of whether the electronic device is powered on or off. This effectively avoids the timing control module U3 being powered off due to the electronic device being powered off or restarted, thereby preventing the third NMOS transistor Q3 and the fourth NMOS transistor Q4 from being turned on simultaneously, thus improving the reliability of the voltage regulation circuit.
[0064] In one embodiment, such as Figure 4 As shown, it also includes a second power supply B2.
[0065] The second power supply B2 is connected to the power supply terminal of the timing control module U3.
[0066] The protection circuit U4 is connected between the first power supply B1 and the input terminal of the boost module U1, and the control terminal of the protection circuit U4 is connected to the second power supply B2.
[0067] The protection circuit U4 is used to disconnect the connection between the first power supply B1 and the input of the boost module U1 when the second power supply B2 is powered off.
[0068] In this embodiment, the timing control module U3 is powered by the second power supply B2. The output voltage of the second power supply B2 is much smaller than the output voltage of the first power supply B1. When the electronic device is powered on, the second power supply B2 is powered on; when the electronic device is powered off, the second power supply B2 is powered off.
[0069] In this embodiment, by setting a protection circuit U4 to disconnect the connection between the first power supply B1 and the input terminal of the boost module U1 when the second power supply B2 is powered off, the first power supply B1 stops supplying power to the boost module U1. During the power-off process of the second power supply B2, if the timing of the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are turned on simultaneously due to timing disorder of the timing control module U3, the boost module U1 will not be damaged because there is no input voltage. This improves the reliability of the voltage regulation circuit.
[0070] In one embodiment, such as Figure 4 As shown, the protection circuit U4 includes a voltage comparison circuit;
[0071] The voltage comparison circuit is connected between the first power supply B1 and the input terminal of the boost module U1, and the control terminal of the voltage comparison circuit is connected to the second power supply B2.
[0072] The voltage comparison circuit is used to disconnect the connection between the first power supply B1 and the input of the boost module U1 when the second power supply B2 is powered off.
[0073] In this embodiment, by setting a voltage comparison circuit to disconnect the connection between the first power supply B1 and the input terminal of the boost module U1 when the second power supply B2 is powered off, the first power supply B1 stops supplying power to the boost module U1. During the power-off process of the second power supply B2, if the timing of the timing control module U3 causes the third NMOS transistor Q3 and the fourth NMOS transistor Q4 to conduct simultaneously due to timing disorder, the boost module U1 will not be damaged because there is no input voltage. This improves the reliability of the voltage regulation circuit.
[0074] In one embodiment, such as Figure 4 As shown, the voltage comparison circuit includes a voltage regulation module, a switching element, and a voltage comparator U5.
[0075] One end of the voltage regulating module is connected to the first power supply B1.
[0076] A switching element is connected between the input terminal of the boost module U1 and the first power supply B1.
[0077] The first input terminal of voltage comparator U5 is connected to the second power supply B2.
[0078] The second input terminal of voltage comparator U5 is connected to the voltage regulation module.
[0079] The output of voltage comparator U5 is connected to the control terminal of the switching element.
[0080] The voltage comparator U5 is used to control the switching element to disconnect the connection between the first power supply B1 and the input of the boost module U1 when the second power supply B2 is powered off.
[0081] In this embodiment, the power supply terminal of voltage comparator U5 is connected to the first power supply B1, and the ground terminal of voltage comparator U5 is connected to the ground terminal GND.
[0082] In this embodiment, the input voltage of the first input terminal of the voltage comparator U5 is equal to the output voltage of the second power supply B2, the input voltage of the second input terminal of the voltage comparator U5 is less than the output voltage of the second power supply B2 after it is powered on, and the input voltage of the second input terminal of the voltage comparator U5 is greater than the output voltage of the second power supply B2 after it is powered off.
[0083] For example, if the output voltage of the second power supply B2 is 3.3V, then the input voltage of the first input terminal of the voltage comparator U5 is 3.3V, and the input voltage of the second input terminal of the voltage comparator U5 can be set to 2~3V.
[0084] In this embodiment, when the input voltage at the first input terminal of voltage comparator U5 is greater than the input voltage at the second input terminal of voltage comparator U5, it indicates that the second power supply B2 is in the power-on state, that is, the timing control module U3 is in the power-on state, the output terminal of voltage comparator U5 outputs a first level signal, and the output of voltage comparator U5 controls the sixth NMOS transistor Q6 to turn on, the first power supply B1 supplies power to the boost module U1, and the voltage regulation circuit works normally.
[0085] When the input voltage at the first input terminal of voltage comparator U5 is not greater than the input voltage at the second input terminal of voltage comparator U5, it indicates that the second power supply B2 starts to power down, that is, the timing control module U3 starts to power down. The output terminal of voltage comparator U5 outputs a second-level signal, which controls the sixth NMOS transistor Q6 to turn off. The first power supply B1 can no longer supply power to the boost module U1, and the voltage regulation circuit stops working. This effectively avoids the situation where the third NMOS transistor Q3 and the fourth NMOS transistor Q4 may both be turned on when the timing control module U3 is powered down, thus ensuring the reliability of the voltage regulation circuit.
[0086] In this embodiment, the first level signal and the second level signal are opposite in signal strength.
[0087] For example, if the first level signal is a high level signal, then the second level signal is a low level signal.
[0088] For example, if the first level signal is a low level signal, then the second level signal is a high level signal.
[0089] In one embodiment, such as Figure 4 As shown, the voltage regulation module includes a first resistor R1 and a second resistor R2.
[0090] The first end of the first resistor R1 is connected to the first power supply B1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the ground terminal GND.
[0091] The second input terminal of voltage comparator U5 is connected to the second terminal of the first resistor R1.
[0092] In this embodiment, the input voltage of the second input terminal of the voltage comparator U5 is adjusted by setting a voltage regulation module. Since the output voltage of the second power supply B2 is much smaller than the output voltage of the first power supply B1, the input voltage of the second input terminal of the voltage comparator U5 is less than the output voltage of the second power supply B2 after it is powered on. That is, the input voltage of the second input terminal of the voltage comparator U5 is much smaller than the output voltage of the first power supply B1. Considering the voltage division effect of the first resistor R1 and the second resistor R2, the resistance value of the first resistor R1 is greater than the resistance value of the second resistor R2.
[0093] In one embodiment, such as Figure 4 As shown, the switching element includes the sixth NMOS transistor Q6.
[0094] The output of voltage comparator U5 is connected to the gate of the sixth NMOS transistor Q6.
[0095] The drain of the sixth NMOS transistor Q6 is connected to the first power supply B1.
[0096] The source of the sixth NMOS transistor Q6 is connected to the input terminal of the boost module U1.
[0097] In this embodiment, the sixth NMOS transistor Q6 is a field-effect transistor switch, and the sixth NMOS transistor Q6 can be selected as an enhancement-mode N-channel MOS transistor.
[0098] This invention also provides an electronic device that includes any of the voltage regulation circuits provided in the circuit embodiments described above.
[0099] In this embodiment, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, etc.
[0100] In this embodiment, since the electronic device provided by the present invention includes any of the protection circuits provided in the above-described voltage regulation circuit embodiments, the electronic device provided by the present invention can achieve the same function as any of the voltage regulation circuits provided in the above-described voltage regulation circuit embodiments.
[0101] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0102] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims
1. A voltage regulation circuit, characterized in that, include: First power source; A boost module, wherein the input terminal of the boost module is connected to the first power supply; A step-down module, wherein the input terminal of the step-down module is connected to the output terminal of the step-up module, and the output terminal of the step-down module is used to output voltage to the electrical load; A timing control module, the output of which is connected to the boost module and the buck module respectively; A protection circuit is connected to the first power supply and is used to protect the boost module when the timing control module is powered down. The second power supply is connected to the power supply terminal of the timing control module. The protection circuit is connected between the first power supply and the input terminal of the boost module. The control terminal of the protection circuit is connected to the second power supply. The protection circuit is used to disconnect the connection between the first power supply and the input of the boost module when the second power supply is powered off.
2. The voltage regulation circuit according to claim 1, characterized in that, The protection circuit includes a voltage comparison circuit; The voltage comparison circuit is connected between the first power supply and the input terminal of the boost module, and the control terminal of the voltage comparison circuit is connected to the second power supply. The voltage comparison circuit is used to disconnect the connection between the first power supply and the input of the boost module when the second power supply is powered off.
3. The voltage regulation circuit according to claim 2, characterized in that, The voltage comparison circuit includes a voltage regulation module, a switching element, and a voltage comparator; One end of the voltage regulating module is connected to the first power supply; The switching element is connected between the input terminal of the boost module and the first power supply; The first input terminal of the voltage comparator is connected to the second power supply. The second input terminal of the voltage comparator is connected to the voltage regulation module; The output terminal of the voltage comparator is connected to the control terminal of the switching element; The voltage comparator is used to control the switching element to disconnect the connection between the first power supply and the input of the boost module when the second power supply is powered off.
4. The voltage regulation circuit according to claim 3, characterized in that, The voltage regulating module includes a first resistor and a second resistor; The first end of the first resistor is connected to the first power supply, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the ground terminal. The second input terminal of the voltage comparator is connected to the second terminal of the first resistor.
5. The voltage regulation circuit according to claim 4, characterized in that, The switching element includes a sixth NMOS transistor; The output terminal of the voltage comparator is connected to the gate of the sixth NMOS transistor; The drain of the sixth NMOS transistor is connected to the first power supply; The source of the sixth NMOS transistor is connected to the input terminal of the boost module.
6. An electronic device, characterized in that, include: The voltage regulation circuit as described in any one of claims 1-5.