A method for controlling capacitor voltage balance of submodules in modular multilevel converter

Abstract

A modular multi-level converter submodule capacitor voltage balance control method belongs to the field of converter control. The present invention includes setting a reference overall balance, a submodule capacitor voltage upper limit and a submodule capacitor voltage lower limit; comparing whether the overall balance of the current cycle is less than the reference overall balance, if so, adopting a first switching strategy, if not, adopting a second switching strategy; comparing the current submodule capacitor voltage with the submodule capacitor voltage upper limit and the submodule capacitor voltage lower limit respectively, and cutting off the submodule whose capacitor voltage is greater than the capacitor voltage upper limit and the capacitor voltage is less than the capacitor voltage lower limit. Under the premise of controlling the submodule capacitor voltage balance, the present invention can also ensure that the system has a lower switching frequency, reducing the loss of the power converter in the MMC system.

Description

Technical Field

[0001] The present invention relates to the field of converter control, and in particular to a method for controlling capacitor voltage balancing of submodules of a modular multi-level converter. Background Art

[0002] Today, power electronic converter technology has developed rapidly and has gradually become the core device for power conversion in power systems, mainly in terms of power supply, power transmission and power configuration. The modular multilevel converter topology was first proposed by German scholars A. Lesnicar and R. Marqugrdt in 2001. After development, it has shown extremely superior engineering application prospects. In the topological structure of the modular multilevel converter (MMC), the submodules are cascaded together to form a single-phase bridge arm, avoiding the problem of excessive power consumption after direct series connection. Therefore, this topology solves the problems of high switching frequency and large system loss in actual operation of two-level and three-level, and is widely used in DC transmission and distribution projects. MMC has been widely used in various DC transmission and distribution projects due to its characteristics of no commutation failure, independent adjustment of active and reactive power, easy modular configuration, low harmonic level, low switching frequency, and power supply to passive systems.

[0003] MMC relies on the submodule capacitors to achieve the transfer of AC and DC energy. The balance of the submodule capacitor voltage is a necessary prerequisite for the stable operation of the system. MMC obtains the desired sinusoidal output waveform by controlling the input or removal of the bridge arm submodule. Nearest Voltage Level Modulation (NLM) is a method of MMC modulation control that has been widely studied recently. A large number of submodules are usually required in MMC, so the use of NLM can obtain an output voltage with a very high number of levels and a low harmonic distortion rate, so it is widely used in MMC topology. The advantage of the traditional voltage balancing control method is that it is simple to implement, but the voltage balancing algorithm requires that the submodule capacitor voltage values ​​be strictly sorted at each action moment of the system to control the opening or closing of each module. This frequent switching action will inevitably increase the switching loss, so it is necessary to carry out corresponding research on the switching frequency of MMC. Summary of the invention

[0004] In view of the above-mentioned defects of the prior art, the present invention provides a modular multi-level converter sub-module capacitor voltage balancing control method, which can not only control the sub-module capacitor voltage balancing, but also ensure that the system has a lower switching frequency, thereby reducing the loss of the power converter in the MMC system.

[0005] The present invention provides a method for controlling capacitor voltage balancing of a modular multi-level converter sub-module, wherein the modular multi-level sub-module converter includes a plurality of sub-modules, and the control method includes:

[0006] S1. Define the overall balance of the reference , the upper limit u1 of the submodule capacitor voltage and the lower limit u2 of the submodule capacitor voltage;

[0007] S2. Compare the overall balance U of the current cycle max_c Is it less than the reference overall balance U? max_x If yes, adopt the first switching strategy, if no, adopt the second switching strategy;

[0008] S3, compare the current submodule capacitor voltage ui with the submodule capacitor voltage upper limit u1 and the submodule capacitor voltage lower limit u2 respectively, and remove the submodules whose capacitor voltage is greater than the capacitor voltage upper limit u1 and whose capacitor voltage is less than the capacitor voltage lower limit u2.

[0009] The first switching strategy includes:

[0010] Sort the submodules in ascending order according to voltage;

[0011] Calculate the number of sub-modules m that need to be invested;

[0012] When the bridge arm current Iarm<0, the last m sub-modules in the sorting sequence are put into use;

[0013] When the bridge arm current Iarm>0, the last m sub-modules in the sorting sequence are put into use.

[0014] The second switching strategy includes:

[0015] Sort the submodules in ascending order according to voltage;

[0016] Calculate the submodule change amount n=ba in the current cycle, where b is the number of submodules invested in the current cycle and a is the number of submodules invested in the previous cycle;

[0017] When n is less than 0 and the bridge arm current Iarm is less than 0, n submodules with the smallest voltage value are removed from the submodules that have been put into operation;

[0018] When n<0 and the bridge arm current Iarm>0, the n sub-modules with the largest voltage value are removed from the sub-modules that have been put into operation;

[0019] When n>0 and the bridge arm current Iarm<0, n sub-modules with the largest voltage value are added on the basis of the sub-modules already added;

[0020] When n>0 and the bridge arm current Iarm>0, n sub-modules with the smallest voltage value are put into use on the basis of the sub-modules that have been put into use;

[0021] When n=0, no action is taken.

[0022] The method for determining the number b of submodules invested in the current cycle includes:

[0023] ;

[0024] Where U ref is the actual reference value of the submodule capacitor voltage, U c is the average value of the capacitor voltage of the current submodule, and round is the rounding function.

[0025] The upper limit u1 of the submodule capacitor voltage is 1.1u s The lower limit u2 of the submodule capacitor voltage is 0.9u s .

[0026] Step S3 includes:

[0027] When the bridge arm current Iarm<0, determine whether the submodule in operation is less than the capacitor voltage lower limit u2. If so, remove the over-limit submodule and count it as d. Select d submodules with the highest voltage from the submodules that have not been put into operation and put them into operation. If not, do not act.

[0028] When the bridge arm current Iarm>0, determine whether the sub-module put into operation is greater than the capacitor voltage upper limit u1. If so, the sub-module that exceeds the limit is cut off and counted as o. Select o sub-modules with the lowest voltage from the sub-modules that have not been put into operation and put them into operation. If not, no action is taken.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. The present invention introduces a reference overall balance, compares the overall balance of the current cycle with the reference overall balance, and adopts different switching methods according to the comparison results. When the overall balance at a certain moment is less than the reference overall balance, the traditional switching method is adopted; when the overall balance at a certain moment is less than or greater than the reference overall balance, the improved control method is adopted. The combination of the two methods can reduce the transmission loss of the system to a lower level;

[0031] 2. The present invention sets the upper and lower limits of the capacitor voltage. After the switching operation is performed, it is determined whether the capacitor voltage at this time exceeds the limit. If it exceeds the upper and lower limits, the sub-module that exceeds the limit is removed to ensure a higher voltage balancing effect.

[0032] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a topological structure diagram of a main circuit of a modular multi-level converter in a specific embodiment of the present invention;

[0034] Figure 2 is a topological structure diagram of a power submodule in a specific embodiment of the present invention;

[0035] Figure 3 is a flow chart of an improved pressure balancing algorithm in a specific embodiment of the present invention;

[0036] Figure 4 is a comparison diagram of capacitor voltage waveforms of MMC using an improved algorithm and a traditional algorithm in a specific embodiment of the present invention, Figure 4 a is the capacitor voltage waveform of each submodule of the bridge arm using the traditional voltage balancing algorithm. Figure 4 b is the capacitor voltage waveform of each submodule using the improved voltage balancing algorithm;

[0037] Figure 5 is a comparison diagram of the switching frequencies of the MMC using the improved algorithm and the traditional algorithm in a specific embodiment of the present invention, Figure 5 a is the average switching frequency of the traditional algorithm, Figure 5 b is the average switching frequency of the improved algorithm. DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0039] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present invention in a schematic manner, and thus the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0040] While some exemplary embodiments of the present invention have been described for the purpose of illustration, it should be understood that the present invention may be implemented in other ways not specifically shown in the drawings.

[0041] In a specific embodiment, a method for controlling capacitor voltage balancing of a modular multi-level converter submodule is provided. The modular multi-level submodule converter includes a plurality of submodules, and the structure thereof is as follows: Figure 1 As shown, each bridge arm submodule adopts a half-bridge structure, and each phase bridge arm is composed of a commutation reactor and a half-bridge submodule. The power submodule topology is shown in Figure 2 As shown, each submodule includes two IGBTs, a storage capacitor and a freewheeling diode. By controlling the on and off of the submodules, a stable waveform can be output at the output end.

[0042] The MMC submodule is a single-phase half-bridge structure. The submodule SM has three main working states: a locked state in which both T1 and T2 are turned off and the submodule is in an abnormal state; an engaged state in which T1 is turned on and T2 is turned off; a cut-off state in which T1 is turned off and T2 is turned on; in the engaged state, SM is always connected to the main circuit for charging and discharging, and the voltage when the submodule is engaged is the reference voltage U c , the voltage is 0 in the cut-off state.

[0043] The modular multi-level converter submodule capacitor voltage balancing control method comprises:

[0044] S1. Set the reference overall balance U max_x , the upper limit u1 of the submodule capacitor voltage and the lower limit u2 of the submodule capacitor voltage; the reference overall balance is the maximum submodule voltage minus the minimum submodule voltage among all submodules divided by the submodule voltage reference value U c Multiply it by 100%, and it becomes:

[0045] ;

[0046] The overall balance degree reflects the balance degree of the submodule voltages. The smaller the value of the overall balance degree is, the better the balance degree of the submodules is, and the smaller the voltage difference between different submodules is.

[0047] The upper limit of the submodule capacitor voltage u1 is k1u s , the lower limit of the submodule capacitor voltage u2 is k2u s , where u s is the rated voltage, k1 and k2 are flexibly adjusted according to needs, and the range of k1 and k2 is set to [0.9, 1.5] according to historical data and expert experience. In this embodiment, the upper limit u1 of the submodule capacitor voltage is 1.1u s The lower limit u2 of the submodule capacitor voltage is 0.9u s .

[0048] S2. Compare the overall balance U of the current cycle max_c Is it less than the reference overall balance U? max_xThreshold, if yes, adopt the first switching strategy, if no, adopt the second switching strategy;

[0049] In a specific embodiment, by adopting the first switching strategy, it can be ensured that the m submodules with the largest input voltage are discharged when the bridge arm is discharged, and the m submodules with the smallest input voltage are charged when the bridge arm is in a charging state. The first switching strategy is used to balance the capacitor voltage in each round of switching, so that the overall imbalance is kept as small as possible. However, due to the frequent changes in the voltage sequence between the submodule capacitors caused by the charging and discharging of the capacitor, the switching state of the submodule is frequently changed, resulting in a large switching loss. Therefore, in order to ensure the stable operation of the system under the premise of the overall imbalance within a certain range, the second switching strategy is used to solve the problem of switching loss. The second switching strategy can memorize the switching state of the previous round when the submodule capacitor voltage imbalance is lower than the set imbalance threshold, and try to keep its switching state when it does not exceed the defined upper and lower limits, thereby reducing the switching frequency. When the imbalance exceeds the set threshold, the first switching strategy is used to reduce the imbalance, and the second switching strategy is continued after the imbalance is smaller than the set threshold.

[0050] In this embodiment, the first switching strategy includes:

[0051] S211, sorting the submodules in ascending order according to voltage magnitude;

[0052] In the present application, the sequence of each submodule according to the voltage size is obtained by sorting. In the subsequent switching strategy, the submodule to be put into or removed is determined according to the voltage size. The submodule serial number arranged according to the voltage size can be obtained by voltage sorting. When executing the switching program, the submodule that has been put into use is assigned a FLAG bit, and then the maximum or minimum required number of submodules is selected from the non-assigned FLAG bits, or the maximum or minimum submodule is selected from the submodules that have been assigned a FLAG bit for operation.

[0053] S212, calculating the number m of sub-modules that need to be invested;

[0054] S213, when the bridge arm current Iarm<0, the last m sub-modules in the sorting sequence are put into use;

[0055] When the bridge arm current Iarm>0, the last m sub-modules in the sorting sequence are put into use.

[0056] The second switching strategy includes:

[0057] S221, sorting the submodules in ascending order according to voltage magnitude;

[0058] S222, calculating the submodule change amount n=ba in the current cycle, where b is the number of submodules invested in the current cycle, and a is the number of submodules invested in the previous cycle, wherein the method for determining the number of submodules invested in the current cycle b includes:

[0059] ;

[0060] Where U ref is the actual reference value of the submodule capacitor voltage, U c is the actual value of the current submodule capacitor voltage, and round is the rounding function.

[0061] S223, judging whether additional submodules are needed in the current cycle according to the difference n between the number of submodules a invested in the previous cycle and the number of submodules b to be invested in the current cycle, when n>0, it indicates that ba submodules need to be invested in this control cycle, when n<0, it indicates that ab submodules need to be removed in this control cycle, and when n=0, it indicates that the number of invested modules does not need to be adjusted in this control cycle. The specific sorting and switching process includes:

[0062] When n is less than 0 and the bridge arm current Iarm is less than 0, n submodules with the smallest voltage value are removed from the submodules that have been put into operation;

[0063] When n<0 and the bridge arm current Iarm>0, the n sub-modules with the largest voltage value are removed from the sub-modules that have been put into operation;

[0064] When n>0 and the bridge arm current Iarm<0, n submodules with the largest capacitor voltage are selected from the submodules in bypass state based on the submodules that have been put into operation and put into operation;

[0065] When n>0 and the bridge arm current Iarm>0, n submodules with the smallest capacitor voltage are selected from the submodules in the bypass state based on the submodules that have been put into operation and put into operation;

[0066] When n=0, it means that this control cycle does not need to adjust the number of modules put into operation, and no action will be taken.

[0067] S3, the current submodule capacitor voltage u i The submodules whose capacitor voltage is greater than the upper limit u1 and whose capacitor voltage is less than the lower limit u2 are compared with the submodule capacitor voltage upper limit u1 and the submodule capacitor voltage lower limit u2 respectively, and the submodules whose capacitor voltage is greater than the upper limit u1 and whose capacitor voltage is less than the lower limit u2 are cut off.

[0068] After completing the above switching process, the capacitor voltage is detected again. At this time, the sub-module that exceeds the limit is cut off according to the preset upper and lower limit values ​​of the capacitor voltage. The specific process includes:

[0069] When the bridge arm current Iarm<0, determine whether the submodule in operation is less than the capacitor voltage lower limit u2. If so, remove the over-limit submodule and count it as d. Select d submodules with the highest voltage from the submodules that have not been put into operation and put them into operation. If not, do not act.

[0070] When the bridge arm current Iarm>0, determine whether the sub-module put into operation is greater than the capacitor voltage upper limit u1. If so, the sub-module that exceeds the limit is cut off and counted as o. Select o sub-modules with the lowest voltage from the sub-modules that have not been put into operation and put them into operation. If not, no action is taken.

[0071] The submodule capacitor voltage balancing control method is simulated and verified. Figure 4 As shown, Figure a shows the capacitor voltage values ​​of each submodule of the bridge arm using the traditional voltage balancing algorithm, and Figure b shows the capacitor voltage values ​​of each submodule using the improved voltage balancing algorithm. Figure 5 Figure a is the average switching frequency of the traditional algorithm, and Figure b is the average switching frequency of the improved algorithm. After adopting the voltage balancing algorithm, the voltage fluctuation rate and imbalance become larger, but the average switching frequency is significantly reduced. When the fluctuation rate and imbalance meet the operating conditions, the average switching frequency is reduced, that is, the switching loss is reduced, and the operating efficiency of the MMC is improved.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for controlling capacitor voltage balancing of a modular multi-level converter submodule, characterized in that: The modular multi-level sub-module converter includes a plurality of sub-modules, and the control method includes: S1. Define the overall balance of the reference , the upper limit of the submodule capacitor voltage u1 and the lower limit of the submodule capacitor voltage u2, where U cmax is the maximum submodule voltage among all submodules, U cmin is the minimum submodule voltage among all submodules, U c is the submodule voltage reference value; S2. Compare the overall balance U of the current cycle max_c Is it less than the reference overall balance U? max_x If yes, adopt the first switching strategy, if no, adopt the second switching strategy; The first switching strategy includes: Sort the submodules in ascending order according to voltage; Calculate the number of sub-modules m that need to be invested; When the bridge arm current Iarm<0, the last m sub-modules in the sorting sequence are put into use; When the bridge arm current Iarm>0, the last m submodules in the sorting sequence are put into use; The second switching strategy includes: Sort the submodules in ascending order according to voltage; Calculate the submodule change amount n=ba in the current cycle, where b is the number of submodules invested in the current cycle and a is the number of submodules invested in the previous cycle; When n is less than 0 and the bridge arm current Iarm is less than 0, n submodules with the smallest voltage value are removed from the submodules that have been put into operation; When n<0 and the bridge arm current Iarm>0, the n sub-modules with the largest voltage value are removed from the sub-modules that have been put into operation; When n>0 and the bridge arm current Iarm<0, n sub-modules with the largest voltage value are added on the basis of the sub-modules already added; When n>0 and the bridge arm current Iarm>0, n sub-modules with the smallest voltage value are put into use on the basis of the sub-modules that have been put into use; When n=0, no action; S3, compare the current submodule capacitor voltage ui with the submodule capacitor voltage upper limit u1 and the submodule capacitor voltage lower limit u2 respectively, and remove the submodules whose capacitor voltage is greater than the capacitor voltage upper limit u1 and whose capacitor voltage is less than the capacitor voltage lower limit u2.

2. A modular multi-level converter submodule capacitor voltage balancing control method according to claim 1, characterized in that: The method for determining the number b of submodules invested in the current cycle includes: ； Where U ref is the actual reference value of the submodule capacitor voltage, U c is the actual value of the current submodule capacitor voltage, and round is the rounding function.

3. A modular multi-level converter submodule capacitor voltage balancing control method according to claim 1, characterized in that: The upper limit u1 of the submodule capacitor voltage is 1.1u s The lower limit u2 of the submodule capacitor voltage is 0.9u s .

4. A modular multi-level converter submodule capacitor voltage balancing control method according to claim 1, characterized in that: Step S3 includes: When the bridge arm current Iarm<0, determine whether the submodule in operation is less than the capacitor voltage lower limit u2. If so, remove the over-limit submodule and count it as d. Select d submodules with the highest voltage from the submodules that have not been put into operation and put them into operation. If not, do not act. When the bridge arm current Iarm>0, determine whether the sub-module put into operation is greater than the capacitor voltage upper limit u1. If so, the sub-module that exceeds the limit is cut off and counted as o. Select o sub-modules with the lowest voltage from the sub-modules that have not been put into operation and put them into operation. If not, no action is taken.

Images