Fail-safe i / o interface circuit and system on chip

Abstract

The fault safety I / O interface circuit and the system on chip, the fault safety I / O interface circuit includes: enable signal end, control unit and output unit, wherein: the enable signal end is coupled with the output unit, is suitable for controlling the input node and the break and make of the output node of the output unit based on the input enable signal;The control unit is coupled with the power supply end and the output unit, is suitable for generating the control signal based on the power supply end voltage and the output node voltage of the output unit, and outputs the control signal to the output unit, so that the output node outputs the corresponding signal when the signal of the enable signal end changes;The output unit is coupled with the power supply end, the enable signal end and the control unit respectively, and is suitable for outputting the corresponding signal through the output node based on the enable signal and the control signal.The above scheme can improve the reliability of the fault safety I / O interface circuit output signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of integrated circuits, and in particular to a fail-safe I / O interface circuit and a system on chip. BACKGROUND

[0002] With the rapid development of integrated circuits (ICs), they are more widely used in the field of electronic products, and the requirement for their reliability is also higher and higher.

[0003] In a specific application scenario, for example, a system on chip (SOC), when the input end is powered off, and the device connected with the external connection point of the SOC circuit is working normally and at a high level, the current generated by the device will flow back to the internal SOC through the external connection point, causing the transistors in the internal SOC to overheat or even burn out. To avoid the above situation, a fail-safe I / O interface circuit can be used to prevent current backflow.

[0004] However, when the signal of the enable end of the fail-safe I / O interface circuit changes, the fail-safe I / O interface circuit is prone to output an error signal, affecting the normal operation of the system. SUMMARY

[0005] Therefore, embodiments of the present application provide a fail-safe I / O interface circuit and a system on chip, which can improve the reliability of the output signal of the fail-safe I / O interface circuit, and further improve the safety and service life of the system circuit.

[0006] First, the embodiments of the present application provide a fail-safe I / O interface circuit, which comprises an enable signal end, a control unit and an output unit, wherein:

[0007] The enable signal end is coupled with the output unit and is adapted to control the on-off of the input node and the output node of the output unit based on the input enable signal;

[0008] The control unit is coupled with the power supply end and the output unit, and is adapted to generate a control signal based on the voltage of the power supply end and the output node voltage of the output unit, and output the control signal to the output unit, so that the output node outputs a corresponding signal when the signal of the enable signal end changes;

[0009] The output unit is coupled with the power supply end, the enable signal end and the control unit, and is adapted to output the corresponding signal through the output node based on the enable signal and the control signal.

[0010] Correspondingly, the embodiment of the present application also provides a system on chip, which comprises the fail-safe I / O interface circuit in the foregoing embodiment, and the fail-safe I / O interface circuit comprises an enable signal terminal, a control unit and an output unit.

[0011] A processor is coupled with the power supply terminal, the enable signal terminal of the fail-safe I / O interface circuit and the input node of the output unit, and is adapted to input an enable signal to the fail-safe I / O interface circuit through the enable signal terminal and input a clock signal or a level signal to the input node of the output unit.

[0012] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0013] The fail-safe I / O interface circuit in the embodiment of the present application comprises an enable signal terminal, a control unit, an output unit and a pull-down protection unit. Since the control unit is coupled with the power supply terminal and the control unit, a control signal can be generated based on the voltage of the power supply terminal and the voltage of the output node of the output unit, and the control signal is output to the output unit. The output unit can output a corresponding signal instead of an incorrect signal when the signal of the enable signal terminal changes based on the enable signal of the enable signal terminal and the control signal. Therefore, the reliability of the output signal of the fail-safe I / O interface circuit can be improved, and the safety and service life of the system circuit are improved.

[0014] In an optional scheme, the control end of the control signal generation module is coupled with the power supply terminal, the first end is coupled with the output node of the output unit, and the second end is coupled with the first control end of the output unit. The control signal generation module can output a control signal which is not affected by the enable signal terminal based on the voltage of the power supply terminal and the voltage of the output node of the output unit, so that the fail-safe I / O interface circuit can still work normally in a fault state. In addition, the first control end of the well potential module is coupled with the power supply terminal, the first end is coupled with the output node of the output unit, the second control end is coupled with the output node of the output unit, the second end is coupled with the power supply terminal, and the third end is coupled with the first output end of the output unit and the third end of the control signal generation module, respectively. When the power supply terminal of the fail-safe I / O interface circuit is powered off, the well potential module and the output node of the output unit are turned on, so that the voltage of the well potential module is the same as the voltage of the output node. Current backflow can be avoided, and the reliability and service life of the fail-safe I / O interface circuit can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application or the prior art description. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0016] Figure 1 A circuit structure schematic diagram of a failsafe I / O interface circuit is shown.

[0017] Figure 2 A voltage variation waveform diagram of key nodes of the failsafe I / O interface circuit in the embodiment of the present application is shown. Figure 1

[0018] Figure 3 A structure schematic diagram of a failsafe I / O interface circuit in the embodiment of the present application is shown.

[0019] Figure 4 A specific structure schematic diagram of a failsafe I / O interface circuit in the embodiment of the present application is shown.

[0020] Figure 5 A voltage variation waveform diagram of key nodes of the failsafe I / O interface circuit in the third example of the embodiment of the present application is shown.

[0021] Figure 6 A structure schematic diagram of a system on chip in the embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] As described in the background, the current failsafe I / O interface circuit is easily affected by the enable end, when the signal of the enable end changes, it is easy to cause the failsafe I / O interface circuit to output an error signal, thereby affecting the normal work of the system.

[0023] In order to more clearly illustrate that the failsafe I / O interface circuit in the prior art is easily affected by the enable end, the following will be described in detail through the drawings and specific examples.

[0024] Referring to Figure 1 A structure schematic diagram of a failsafe I / O interface circuit is shown, the failsafe I / O interface circuit is powered by a power supply end VDD, wherein the failsafe I / O interface circuit comprises an enable signal end OEN, a control module 11, an output module 12 and a pull-down protection module PD, wherein:

[0025] ​The control module 11 can include a first inverter P11, an input node I, a NAND gate, a second inverter P12 and a third inverter P13 connected in sequence, a transmission gate TG, P-type transistors PM1 and PM2, and an output node PAD, wherein a first end of the NAND gate is coupled with an enable signal end OEN through the first inverter P11, a second end of the NAND gate is coupled with the input node I, an output of the third inverter P13 is coupled with an input end of the transmission gate TG; a second control end of the transmission gate TG is coupled with a power supply end VDD and a gate of the P-type transistor PM2 respectively, an output end of the transmission gate TG is coupled with a gate of the P-type transistor PM1; a source of the P-type transistor PM2 is coupled with the output end of the transmission gate TG and the gate of the P-type transistor PM1, a drain of the P-type transistor PM2 is coupled with the pull-down protection module PD; a source of the P-type transistor PM1 is coupled with the power supply end VDD, and a drain of the P-type transistor PM1 is coupled with the output node PAD.

[0026] The control module 12 can include P-type transistors PM3, PM4 and PM5 and N-type transistors NM1 and NM2, wherein a gate of the N-type transistor NM1 is directly coupled with the enable signal end OEN, a source of the N-type transistor NM1 is coupled with an output node PAD of the output module 11, a drain of the N-type transistor NM1 is coupled with a source of the N-type transistor NM2 and a first control end of a transmission gate TG in the output module 11, a substrate of the N-type transistor NM1 is coupled with a substrate of the N-type transistor NM2; the N-type transistor NM2 is coupled with the enable signal end OEN through a fourth inverter P14, and a drain of the N-type transistor NM2 is coupled with the ground; a gate of the P-type transistor PM3 is coupled with the power supply end VDD, a source of the P-type transistor PM3 is coupled with the output node PAD, and a drain of the P-type transistor PM3 is coupled with a gate of the P-type transistor PM4; a source of the P-type transistor PM4 is coupled with the power supply end VDD, a drain and a substrate of the P-type transistor PM4 are respectively coupled with a drain and a substrate of the P-type transistor PM5, and the drain and the substrate of the P-type transistor PM5 are coupled with a substrate of the P-type transistor PM1; a gate of the P-type transistor PM5 is coupled with the power supply end VDD, and a source of the P-type transistor PM5 is coupled with the output node PAD.

[0027] The pull-down protection module PD is coupled between the output node PAD of the output module 11 and the ground.

[0028] In a specific implementation, when a level of the enable signal end OEN is switched from 0 (corresponding to a low level) to 1 (corresponding to a high level), if a level of the output node PAD at this time is a high level 1, since a gate of the N-type transistor NM1 is coupled with the enable signal end OEN, a gate voltage of the N-type transistor NM1 is greater than a source voltage of the N-type transistor NM1, the N-type transistor NM1 is turned on, V P_PASS = V PAD -V thn , wherein V thnThis is the turn-on voltage of NMI.

[0029] The voltage V of the control signal P_PASS output by NM1 P_PASS The input is given to the gate of the PMOS transistor in the transmission gate TG. The PMOS transistor in the transmission gate TG is weakly turned on. Since the output potential of the transmission gate TG changes from low level 0 to high level 1, the gate voltage of the P-type transistor PM1 cannot quickly become 1, and the P-type transistor PM1 is weakly turned on. When the gate potential of the P-type transistor PM1 becomes high level 1, the resistor PD is enabled, which opens the path between the output node PAD and ground, pulling the potential of the output node PAD down to a low potential.

[0030] Because it takes time for the potential of PM1 to go from 0 to 1, the potential of the output node PAD cannot be pulled down to a low level quickly, causing the fault-safe I / O interface circuit to transmit incorrect signals and affecting the normal operation of the system.

[0031] Reference Figure 2 shown Figure 1 The voltage change waveforms of key nodes in the fault-safe I / O interface circuit are shown. The key nodes include: input node I, enable signal terminal OEN, resistor PD, and output node PAD.

[0032] Depend on Figure 2 It can be seen that when the enable signal terminal OEN is low level 0, the output node PAD changes with the input node I; at t = 50μs, the enable signal terminal OEN switches from low level 0 to high level 1, and the voltage of the input node PAD drops to 0V at t = 120μs.

[0033] However, during the time period t = 50μs to 120μs, the voltage of the output node PAD is not 0V, which will cause the fail-safe I / O interface circuit to transmit incorrect signals, affecting the normal operation of the system.

[0034] It should be noted that, by Figure 2 It can be seen that the level of the resistor PD is always high, but the pull-down capability of the resistor PD is weak. Therefore, when the enable signal terminal OEN is low level 0, the resistor PD does not work, and the potential of the output node PAD will not drop to low level 0.

[0035] To solve the above problems, the fault safety I / O interface circuit in the embodiment of the present application is adopted, the fault safety I / O interface includes an enable signal end, a control unit and an output unit, wherein, since the control unit is coupled with the power supply end and the control unit, the control signal can be generated based on the voltage of the power supply end and the voltage of the output node of the output unit, and the control signal is output to the output unit, the output unit can output the corresponding signal when the signal of the enable signal end changes based on the enable signal of the enable signal end and the control signal, and the false signal is not output, thus, the reliability of the output signal of the fault safety I / O interface circuit can be improved, and the safety and service life of the system circuit are improved.

[0036] To make the skilled in the art better understand and implement the embodiment of the present application, the implementation principle is introduced in detail below with reference to the drawings and in combination with the specific application circuit.

[0037] Referring to Figure 3 The structure schematic diagram of the fault safety I / O interface circuit in the embodiment of the present application is shown in the figure, the fault safety I / O interface circuit 30 includes an enable signal end 31, an output unit 32 and a control unit 33, wherein:

[0038] The enable signal end 31 is coupled with the output unit 32, and is adapted to control the on-off of the input node and the output node of the output unit 32 based on the input enable signal;

[0039] Specifically, when the level of the enable signal of the enable signal end 31 is low level 0, the path from the input node to the output node of the output unit 32 is turned on, when the level of the enable signal of the enable signal end 31 is high level 1, the path from the input node to the output node of the output unit 32 is turned off, thus, the on-off of the input node and the output node of the output unit 32 can be controlled by controlling the level of the input enable signal.

[0040] The output unit 32 is coupled with the power supply end VDD, the enable signal end 31 and the control unit 33 respectively, and is adapted to output the corresponding signal through the output node based on the enable signal and the control signal;

[0041] The control unit 33 is coupled with the power supply end VDD and the output unit 32, and is adapted to generate the control signal based on the voltage of the power supply end VDD and the voltage of the output node of the output unit 32, and output the control signal to the output unit 32, so that the output node outputs the corresponding signal when the signal of the enable signal end 31 changes;

[0042] In a specific implementation, when the level of the enable signal end 31 is high level 1, in order to make the voltage of the output node of the output unit 32 be 0V, a pull-down protection unit 34 can be coupled between the output unit 32 and the ground, and the pull-down protection unit 34 is adapted to pull down the voltage of the output node of the output unit 32 to zero volt when the level of the enable signal end 31 is high level 1.

[0043] With the above-mentioned fail-safe I / O interface circuit, the power supply end VDD supplies power to the fail-safe I / O interface circuit 30, the enable signal end 31 can receive an enable signal from the system on chip, and when the enable signal is 1 (corresponding to high level), the path between the input node and the output node of the output unit 32 is disconnected; when the enable signal is 0 (corresponding to low level), the path between the input node and the output node of the output unit 32 is turned on, and the output node of the output unit 32 is coupled with the control unit 33, the control unit 33 can generate a control signal according to the voltage of the output node and the voltage of the power supply end VDD coupled therewith, and output the control signal to the output unit 32, and the output unit based on the enable signal of the enable signal end 31 and the control signal can output a corresponding signal instead of an error signal when the signal of the enable signal end 31 changes, for example, the level of the enable signal end 31 is switched from low level to high level, therefore, the reliability of the output signal of the fail-safe I / O interface circuit can be improved, and the safety and service life of the system circuit can be improved.

[0044] In order for those skilled in the art to better understand and implement the embodiments of the present application, the implementation principle will be described in detail below with reference to the accompanying drawings and in combination with a specific application circuit.

[0045] In a specific implementation, the control unit can include a control signal generation module and a well potential module, wherein the control module has a control end coupled with the power supply end, a first end coupled with the output node of the output unit, and a second end coupled with the first control end of the output unit.

[0046] The well potential module has a first control end coupled with the power supply end, a first end coupled with the output node of the output unit, a second control end coupled with the output node of the output unit, a second end coupled with the power supply end, and a third end coupled with the first output end of the output unit and the third end of the control signal generation module, respectively.

[0047] By coupling the control end of the control signal generation module with the power supply end, coupling the first end with the output node of the output unit, coupling the second end with the first control end of the output unit, the control signal generation module can output the control signal which is not affected by the enable signal end based on the voltage of the power supply end and the voltage of the output node of the output unit, so that the fail-safe I / O interface circuit can still work normally in the fault state; and by coupling the first control end of the well potential module with the power supply end, coupling the first end with the output node of the output unit, coupling the second control end with the output node of the output unit, coupling the second end with the power supply end, and coupling the third end with the first output end of the output unit and the third end of the control signal generation module respectively, the path between the well potential module and the output node of the output unit can be turned on when the power supply end of the fail-safe I / O interface circuit is powered off, so that the voltage of the well potential module is the same as the voltage of the output node, current backflow can be avoided, and thus the reliability and service life of the fail-safe I / O interface circuit can be further improved

[0048] In a specific example of the present application, the control signal generation module comprises a first transistor and a second transistor, wherein: the gate of the first transistor is connected with the gate of the second transistor and serves as the control end of the control signal generation module, the source of the first transistor serves as the first end of the control signal generation module, the drain of the first transistor and the drain of the second transistor are connected and serve as the second end of the control signal generation module, and the substrate of the first transistor serves as the third end of the control signal generation module; and the substrate and the source of the second transistor are connected and grounded.

[0049] The well potential module comprises a third transistor and a fourth transistor, wherein: the gate of the third transistor serves as the first control end of the well potential module, the source of the third transistor serves as the first end of the well potential module, the drain and the substrate of the third transistor are connected with the drain and the substrate of the fourth transistor and serve as the third end of the well potential module; and the gate of the fourth transistor serves as the second control end of the well potential module, and the source of the fourth transistor serves as the second end of the well potential module.

[0050] It should be noted that, in the embodiment of the present application, the third transistor and the fourth transistor are both PMOS transistors, and the well potential module is an N-type well potential module.

[0051] In a specific implementation, the output unit can comprise a first logic circuit module, a first switch module, a fifth transistor, a sixth transistor and a first inverter, wherein: the first inverter is coupled between the enable signal end and the first logic circuit module.

[0052] The first input end of the first logic circuit module is coupled with the input node of the output unit, the second input end of the first logic circuit module is coupled with the enable signal end through the first inverter, and the output end of the first logic circuit module is coupled with the input end of the first switch module.

[0053] The first control end of the first switch module is used as the first control end of the control unit, the second control end of the first switch module is coupled with the control end of the fifth transistor and the power supply end, and the output end of the first switch module is coupled with the control end of the sixth transistor.

[0054] The first end of the fifth transistor is coupled with the power supply end, the second end of the fifth transistor is coupled with the output node of the output unit, and the third end of the fifth transistor is used as the first output end of the output unit.

[0055] The control end of the sixth transistor is coupled with the power supply end and the second control end of the first switch module, the first end of the sixth transistor is coupled between the output end of the first switch module and the control end of the fifth transistor, and the second end of the sixth transistor is coupled with the ground.

[0056] In the embodiment of the application, the first control end of the control unit is adapted to input the control signal, and the first output end of the control unit is adapted to turn on the output node when the power supply end is powered off, so that the potential of the first output end is equal to the potential of the output node.

[0057] In a specific example of the application, the first logic circuit module comprises a NAND gate, a second inverter and a third inverter connected in sequence, wherein the first input end of the NAND gate is used as the first input end of the first logic circuit module, the second input end of the NAND gate is used as the second input end of the first logic circuit module, the second inverter is located between the NAND gate and the third inverter, and the output end of the third inverter is used as the output end of the first logic circuit module.

[0058] The first switch module comprises a transmission gate, and the transmission gate comprises a P-type transistor and an N-type transistor which are connected in parallel, wherein the gate of the P-type transistor in the transmission gate is used as the first control end of the first switch module and is adapted to transmit a high-level signal, and the gate of the N-type transistor in the transmission gate is used as the second control end of the first switch module and is adapted to transmit a low-level signal.

[0059] The fifth transistor is a PMOS transistor, the gate of the fifth PMOS is coupled with the output end of the second switch module, the source of the fifth PMOS is coupled with the power supply end, the drain of the fifth PMOS is coupled with the output node, and the substrate of the fifth PMOS is used as the first output end of the output unit.

[0060] The sixth transistor is a PMOS transistor, a gate of the sixth PMOS transistor is coupled with the power supply end and a second control end of the first switch module, a source of the sixth PMOS transistor is coupled between an output end of the first switch module and a gate of the fifth transistor, and a drain of the sixth PMOS transistor is coupled with the pull-down protection unit.

[0061] In some embodiments of the application, the output unit can further include a second logic circuit module, a second switch module and a seventh transistor, wherein: a first input end of the second logic circuit module is coupled with the enable signal end, a second input end of the second logic circuit module is coupled with the input node, and an output end of the second logic circuit module is coupled with an input end of the second switch module; a first control end of the second switch module is coupled with the ground, a second control end of the second switch module is coupled with the power supply end, and an output end of the second switch module is coupled with a control end of the seventh transistor; a first end of the seventh transistor is coupled with a drain of the fifth transistor, and a second end of the seventh transistor is coupled with the ground.

[0062] In the embodiments of the application, the first logic circuit, the first switch module, the fifth transistor, the sixth transistor and the first inverter are adapted to transmit the input signal of the input node I of the output unit to the output node PAD of the output unit when the level of the input signal of the input node I of the output unit is high level 1; and the second logic circuit module, the second switch module and the seventh transistor are adapted to transmit the input signal of the input node I of the output unit to the output node PAD of the output unit when the level of the input signal of the input node I of the output unit is low level 0.

[0063] In specific implementations, when the level of the enable signal end of the fail-safe I / O interface circuit is high level, in order to make the voltage of the output node of the output unit be zero, a pull-down protection unit can be coupled between the output node of the output unit and the ground, thus, the fail-safe I / O interface circuit can further include a pull-down protection unit coupled between the output node of the output unit and the ground, and adapted to pull down the voltage of the output node of the output unit to zero volt when the level of the enable signal end of the fail-safe I / O interface circuit is high level.

[0064] Specifically, referring to Figure 4 FIG. 1 shows a circuit structure schematic diagram of a fail-safe I / O interface circuit in an embodiment of the application, the fail-safe I / O interface circuit 40 includes an enable signal end OEN, a control unit 41, an output unit 42 and a pull-down protection unit 43, wherein:

[0065] The control unit 41 is coupled with the power supply end VDD and the output unit 42 respectively, and can include a control signal generation module 411 and a well potential module 412.

[0066] The output unit 42 is coupled with the power supply end VDD, the enable signal end OEN and the control unit 41 respectively, and can include a first logic circuit module 421, a first switch module TG41, a fifth PMOS tube PM45 and a sixth PMOS tube PM46.

[0067] The pull-down protection unit 43 is coupled between the output node PAD of the output unit 42 and the ground.

[0068] In the embodiment of the present application, the control end of the control signal generation module 411 is coupled with the power supply end VDD, the first end is coupled with the output node PAD of the output unit 42, and the second end is coupled with the first control end of the output unit 42.

[0069] The first control end of the well potential module 412 is coupled with the power supply end VDD, the first end is coupled with the output node PAD of the output unit 42, the second control end is coupled with the output node PAD of the output unit 42, the second end is coupled with the power supply end VDD, and the third end is coupled with the first output end of the output unit 42 and the third end of the control signal generation module 411 respectively.

[0070] As a specific example, the control signal generation module 411 can specifically include a first PMOS transistor PM41 and a second NMOS transistor NM42, and the well potential module 412 can specifically include a third PMOS transistor PM43 and a fourth PMOS transistor PM44, wherein:

[0071] The gate of the first PMOS transistor PM41 is connected with the gate of the second NMOS transistor NM42 and is coupled with the power supply end VDD, the source of the first PMOS transistor PM41 is coupled with the power supply end VDD, the drain of the first PMOS transistor PM41 is connected with the drain of the second NMOS transistor NM42 and is coupled with the first control end of the first switch module TG41 of the output unit 42, the substrate of the first PMOS transistor PM41 is coupled with the drain of the third PMOS transistor PM43 and the fourth PMOS transistor PM44 respectively, and the substrate of the second NMOS transistor NM42 is connected with the source and grounded.

[0072] The third PMOS transistor PM43 is coupled with the power terminal VDD, the source of the third PMOS transistor PM43 is coupled with the output node PAD of the output unit 42, the drain and substrate of the third PMOS transistor PM43 are connected with the drain and substrate of the fourth PMOS transistor PM44, and are coupled with the first output terminal of the output unit 42, the gate of the fourth PMOS transistor PM44 is coupled with the output node PAD of the output unit 42, and the source of the fourth PMOS transistor PM44 is coupled with the power terminal VDD.

[0073] In the embodiment of the present application, the first input terminal of the first logic circuit module 421 is coupled with the input node I of the output unit 42, the second input terminal of the first logic circuit module 421 is coupled with the enable signal terminal OEN through the first inverter P1, and the output terminal of the first logic circuit module 421 is coupled with the input terminal of the first switch module TG41; the first control terminal of the first switch module TG41 is the first control terminal of the control unit 42, the second control terminal of the first switch module TG41 is coupled with the gate of the sixth PMOS transistor PM46 and the power terminal VDD, and the output terminal of the first switch module TG41 is coupled with the gate of the fifth PMOS transistor PM45; the source of the fifth PMOS transistor PM45 is coupled with the power terminal VDD, the drain of the fifth PMOS transistor PM45 is coupled with the output node PAD of the output unit 42 and the source of the seventh NMOS transistor NM47 respectively, and the substrate of the fifth PMOS transistor PM45 is the first output terminal of the output unit 42; the gate of the sixth PMOS transistor PM46 is coupled with the power terminal VDD and the second control terminal of the first switch module TG41, the source of the sixth PMOS transistor PM46 is coupled between the output terminal of the first switch module TG41 and the gate of the fifth PMOS transistor PM45, and the drain of the sixth PMOS transistor PM46 is coupled with the pull-down protection unit 43, wherein the first control terminal of the control unit 42 is adapted to input the control signal P_PASS, and the first output terminal of the control unit 42 is adapted to turn on the output node PAD when the power terminal VDD is powered off, so that the potential of the first output terminal is equal to the potential of the output node PAD.

[0074] As a specific example, the first logic circuit module 421 includes: a NAND gate, a second inverter P2 and a third inverter P3 connected in sequence, wherein a first input end of the NAND gate is a first input end of the first logic circuit module 421, and a second input end of the NAND gate is a second input end of the first logic circuit module 421; the second inverter P2 is located between the NAND gate and the third inverter P3; and an output end of the third inverter P3 is an output end of the first logic circuit module 421.

[0075] The first switch module TG41 can be a transmission gate, which includes a P-type transistor and an N-type transistor connected in parallel, wherein a gate of the P-type transistor in the transmission gate is a first control end of the first switch module TG41, and a gate of the N-type transistor in the transmission gate is a second control end of the first switch module TG41.

[0076] In a specific implementation, the output unit 42 can further include a second logic circuit module 422, a second switch module TG42 and a seventh NMOS tube NM47, wherein a first input end of the second logic circuit module 422 is coupled with the enable signal end OEN, a second input end of the second logic circuit module 422 is coupled with the input node I, and an output end of the second logic circuit module 422 is coupled with an input end of the fourth switch module TG42; a first control end of the second switch module TG42 is coupled with the ground, a second control end of the second switch module TG42 is coupled with the power supply end VDD, and an output end of the second switch module TG42 is coupled with a gate of the seventh NMOS tube NM47; a source of the seventh NMOS tube NM47 is coupled with a second end of the fifth PMOS tube PM45, and a drain of the seventh NMOS tube NM47 is coupled with the ground.

[0077] As a specific example, the second logic circuit module can include an XNOR gate, a fourth inverter P4 and a fifth inverter P5 connected in sequence, wherein a first input end of the XNOR gate is coupled with the enable signal end OEN, and a second input end of the XNOR gate is coupled with the input node I; the fourth inverter P4 is located between the XNOR gate and the fifth inverter P5, and an output end of the fifth inverter P5 is coupled with an input end of the second switch module TG42.

[0078] The second switch module TG42 can be a transmission gate, which includes a P-type transistor and an N-type transistor connected in parallel, wherein the gate of the P-type transistor is used as the first control end of the fourth switch module TG42 and is coupled with the ground, and the gate of the N-type transistor is used as the second control end of the fourth switch module TG42 and is coupled with the power supply end VDD.

[0079] In the embodiment of the application, the voltage of the power supply end VDD is the power supply voltage VDDIO when the fail-safe I / O interface circuit 40 is in the normal working mode, and is configured as 0V when the interface circuit is in the fail-safe mode.

[0080] First example: the voltage of the power supply end VDD is VDDIO when the fail-safe I / O interface circuit 40 is in the normal working mode.

[0081] Specifically, when the fail-safe I / O interface circuit 40 is in the normal working mode, the voltage of the power supply end VDD is VDDIO, and since the gate of the second NMOS tube NM42 is coupled with the power supply end VDD, the second NMOS tube NM42 is turned on, and the voltage V of the control signal P_PASS output by the second end of the control signal generation module 411 is 0V. P_PASS

[0082] The control signal P_PASS generated by the control generation module 41 is input to the first control end (gate of the PMOS tube) of the first switch module TG41, and the second control end (gate of the NMOS tube) of the first switch module TG41 is coupled with the power supply end VDD, so that the first control end of the first switch module TG41 has a low level, and the second control end has a high level, and the first switch module TG41 is completely turned on. At this time, the voltage level of the fifth PMOS tube PM45 is controlled by the signal PG output by the first switch module TG41, the power supply end VDD is directly added to the gate of the sixth PMOS tube PM46, and the sixth PMOS tube PM46 is turned off.

[0083] Since the source of the fourth PMOS tube PM44 is coupled with the power supply end, and the gate is coupled with the output node PAD of the output unit 42, the source voltage of the fourth PMOS tube PM44 is greater than the gate voltage, and the fourth PMOS tube PM44 makes the N_WELL of the output unit 42 have a high level 1.

[0084] Second example: the voltage of the power supply end VDD is 0V when the fail-safe I / O interface circuit 40 is in the fail-safe mode.

[0085] ​Specifically, when the fail-safe I / O interface circuit 40 is in the fail-safe mode, the voltage of the power supply end VDD is 0V, the output node PAD is coupled with the external circuit, and the potential of the output node PAD is high level 1. Since the first PMOS tube PM41 is coupled with the power supply end VDD, the output node PAD is coupled with the source of the first PMOS tube PM41, the voltage of the source of the first PMOS tube PM41 is greater than the voltage of the gate of the first PMOS tube PM41, the first PMOS tube PM41 is turned on, the voltage V P_PASS PAD .

[0086] The control signal P_PASS generated by the control generation module 41 is input to the first control end (gate of the PMOS tube) of the first switch module TG41, the second control end (gate of the NMOS tube) of the first switch module TG41 is coupled with the power supply end VDD, then the level of the first control end of the first switch module TG41 is high level, the level of the second control end of the first switch module TG41 is low level, the first switch module TG41 is completely turned off, the source of the fifth PMOS tube PM45 is coupled with the power supply end VDD, the fifth PMOS tube PM45 is turned off, the power supply end VDD is directly added to the gate of the sixth PMOS tube PM46, the voltage of the source of the sixth PMOS tube PM46 is greater than the voltage of the gate of the sixth PMOS tube PM46, the sixth PMOS tube PM46 is turned on, and the potential of the PG point is V PAD .

[0087] Since the gate of the third PMOS tube PM43 is coupled with the power supply end VDD, the output node PAD is coupled with the source of the third PMOS tube PM43, therefore, the voltage of the source of the third PMOS tube PM43 is greater than the voltage of the gate of the third PMOS tube PM43, the third PMOS tube PM43 is turned on, so that V N_WELL PAD , thereby blocking the external circuit from leaking electricity to the inside of the fail-safe I / O interface circuit 40 through the output node PAD.

[0088] Third example: when the fail-safe I / O interface circuit 40 is in the normal working mode, and the level of the enable signal end is switched from low level to high level (0 to 1), the voltage of the power supply end VDD is VDDIO.

[0089] ​​Specifically, when the fail-safe I / O interface circuit 40 is in normal operating mode and the level of the enable signal terminal switches from low level 0 to high level 1, the voltage of the power supply terminal VDD is VDDIO. Since the gate of the second NMOS transistor NM42 is coupled to it, the second NMOS transistor NM42 is turned on, and the voltage V of the control signal P_PASS output from the second terminal of the control signal generation module 411 is V. P_PASS =0V. The control signal P_PASS generated by the control generation module 41 is input to the first control terminal (gate of the PMOS transistor) of the first switch module TG41. The second control terminal (gate of the NMOS transistor) of the first switch module TG41 is coupled to the power supply terminal VDD. Then, the level of the first control terminal of the first switch module TG41 is low, and the level of its second control terminal is high. The first switch module TG41 is fully turned on. At this time, the voltage level of the fifth PMOS transistor PM45 is controlled by the signal PG output by the first switch module TG41. The power supply terminal VDD is directly applied to the gate of the sixth PMOS transistor PM46, and the sixth PMOS transistor PM46 is turned off.

[0090] As the level of the enable signal terminal OEN switches from 0 to 1, the level becomes low (0) after passing through the first inverter P1. Then, after passing through the input node I and the first logic circuit module 421, the level output to the first switch module TG41 becomes high (1). Since the first switch module TG41 is fully turned on and does not change the polarity of the signal, the output level of the first switch module TG41 is high (1), which is applied to the gate of the fifth PMOS transistor PM45, making the gate level of the fifth PMOS transistor PM45 high. The fifth PMOS transistor PM45 is turned off, and the pull-down protection unit 43 and the output node PAD of the output unit 42 form a conductive path. The output node PAD of the output unit 42 is coupled to ground, allowing the potential of the output node PAD to quickly drop to low (0).

[0091] Since the fourth PMOS transistor PM44 is coupled to the output node PAD and its source is coupled to the power supply terminal VDD, the gate voltage of the fourth PMOS transistor PM44 is less than its source voltage. When the fourth PMOS transistor PM44 is turned on, the N_WELL voltage of the output unit 42 is the power supply voltage VDDIO.

[0092] Reference Figure 5The voltage change waveform diagram of the key node of the fail-safe I / O interface circuit in the third example of the embodiment of the present invention is shown. The key node of the fail-safe I / O interface circuit includes: enable signal terminal OEN, input node I, pull-down protection unit PD and output node PAD.

[0093] Depend on Figure 5 It can be seen that when the enable signal terminal OEN is at a low level (0), the voltage of the output node PAD follows the voltage change of the input node I. That is, when the level of the input node I is low level (0), the level of the output node PAD is also low level (0). When t = 50μs, when the level of the enable signal terminal OEN switches from low level (0) to high level (1), the level of the input node I remains at its original level, while the level of the output node PAD no longer follows the level of the input node I, and at t = 52μs, its voltage level drops to zero volts.

[0094] It should be noted that, by Figure 5 It can be seen that the level of the pull-down protection unit PD is always high. However, the pull-down capability of the pull-down protection unit PD is weak. Therefore, when the enable signal terminal OEN is low level 0, the pull-down protection unit PD does not work, and the potential of the output node PAD will not drop to low level 0.

[0095] Depend on Figure 5 and Figure 2 As can be seen, by using the fail-safe I / O interface circuit in this embodiment of the invention, the time for the output node voltage of the output unit to drop to zero volts can be shortened when the level of the enable signal terminal switches from low to high. This avoids the transmission of erroneous signals when the level of the enable signal terminal of the fail-safe I / O interface circuit is high. Therefore, by using the fail-safe I / O interface circuit in this embodiment of the invention, the reliability of the output signal of the fail-safe I / O interface circuit can be improved, thereby improving the safety and service life of the system circuit.

[0096] This invention also provides a system-on-a-chip, such as... Figure 6 As shown, the system-on-chip 60 may include: a processor 61 and a fail-safe I / O interface circuit 62, wherein:

[0097] The processor 61 is coupled to the power supply terminal VDD, the enable signal terminal 621 of the fail-safe I / O interface circuit 62, and the input node of the output unit 622. It is adapted to input an enable signal ENB to the fail-safe I / O interface circuit 62 through the enable signal terminal 621, and to input a clock signal or a level signal to the input node I of the output unit 622.

[0098] The fail-safe I / O interface circuit 62 can include an enable signal terminal 621, an output unit 622 and a control unit 623, wherein each circuit unit of the fail-safe I / O interface circuit 62 can adopt the circuit structure shown in the foregoing embodiments, and can refer to the fail-safe I / O interface circuit shown in the foregoing embodiments for details, which will not be described herein again.

[0099] Specifically, the processor 61 in the system on chip 60 can input an enable signal ENB to the fail-safe I / O interface circuit 62 through the enable signal terminal 621, the output unit 622 of the fail-safe I / O interface circuit 62 can turn on or turn off the path between the input node I and the output node PAD of the output unit 622 according to the input enable signal ENB, and input the state information of the output node PAD to the control unit 623, the control unit 623 can output a corresponding control signal according to the voltage of the power supply terminal VDD and the voltage of the output node PAD, and output the control signal to the output unit 622, and the output unit 622 can output a corresponding signal according to the level of the input enable signal ENB and the control signal. For example, when the level of the input enable signal is high, the path between the input node I and the output node PAD is disconnected, the control unit outputs a control signal with a voltage value of 0V to the output unit 622, and the output unit 622 outputs a corresponding signal according to the control signal; when the level of the input enable signal is low, the path between the input node I and the output node PAD is turned on, and the system on chip 60 can input a clock signal or a level signal to the fail-safe I / O interface circuit 62 through the output node I of the output unit 622, and the fail-safe I / O interface circuit 62 can perform corresponding processing according to the input clock signal or level signal.

[0100] Although the embodiments of the present application are disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope defined in the claims.

Claims

1. A fail-safe I / O interface circuit, characterized in that, include: Enable signal terminal, control unit and output unit, wherein: The enable signal terminal is coupled to the output unit and is adapted to control the on / off state of the input node and the output node of the output unit based on the input enable signal. The control unit is coupled to the power supply terminal and the output unit, and is adapted to generate a control signal unaffected by the enable signal terminal based on the power supply terminal voltage and the output node voltage of the output unit, and output the control signal to the output unit, so that the output node outputs a corresponding signal when the signal at the enable signal terminal changes; The output unit is coupled to the power supply terminal, the enable signal terminal, and the control unit, respectively, and is adapted to output the corresponding signal through the output node based on the enable signal and the control signal.

2. The fail-safe I / O interface circuit according to claim 1, characterized in that, The output unit includes: a first control terminal, adapted to input the control signal; and a first output terminal, adapted to turn on the output node when the power supply terminal is powered off, such that the potential of the first output terminal is equal to the potential of the output node.

3. The fail-safe I / O interface circuit according to claim 2, characterized in that, The control unit includes: A control signal generation module, wherein its control terminal is coupled to the power supply terminal, its first terminal is coupled to the output node of the output unit, and its second terminal is coupled to the first control terminal of the output unit; The trap potential module has a first control terminal coupled to the power supply terminal, a first terminal coupled to the output node of the output unit, a second control terminal coupled to the output node of the output unit, a second terminal coupled to the power supply terminal, and a third terminal coupled to the first output terminal of the output unit and the third terminal of the control signal generation module, respectively.

4. The fail-safe I / O interface circuit according to claim 3, characterized in that, The control signal generation module includes a first transistor and a second transistor, wherein: The first transistor has its gate connected to the gate of the second transistor and serves as the control terminal of the control signal generation module. Its source serves as the first terminal of the control signal generation module, its drain is connected to the drain of the second transistor and serves as the second terminal of the control signal generation module, and its substrate serves as the third terminal of the control signal generation module. The second transistor has its substrate connected to its source and grounded.

5. The fail-safe I / O interface circuit according to claim 3, characterized in that, The well potential module includes a third transistor and a fourth transistor, wherein: The third transistor has its gate serving as the first control terminal of the well potential module, its source serving as the first terminal of the well potential module, and its drain and substrate connected to the drain and substrate of the fourth transistor, serving as the third terminal of the well potential module. The fourth transistor has its gate serving as the second control terminal of the well potential module, and its source serving as the second terminal of the well potential module.

6. The fail-safe I / O interface circuit according to claim 5, characterized in that, Both the third transistor and the fourth transistor are PMOS transistors, and the well potential module is an N-type well potential module.

7. The fail-safe I / O interface circuit according to claim 2, characterized in that, The output unit further includes: a first logic circuit module, a first switch module, a fifth transistor, a sixth transistor, and a first inverter, wherein: The first inverter is coupled between the enable signal terminal and the first logic circuit module; The first logic circuit module has a first input terminal coupled to the input node of the output unit, a second input terminal coupled to the enable signal terminal through the first inverter, and an output terminal coupled to the input terminal of the first switch module. The first switch module has a first control terminal that serves as the first control terminal of the control unit, a second control terminal that is coupled to the control terminal of the fifth transistor and the power supply terminal, and an output terminal that is coupled to the control terminal of the sixth transistor. The fifth transistor has a first terminal coupled to the power supply terminal, a second terminal coupled to the output node of the output unit, and a third terminal serving as the first output terminal of the output unit. The sixth transistor has its control terminal coupled to the power supply terminal and the second control terminal of the first switching module, its first terminal coupled between the output terminal of the first switching module and the control terminal of the fifth transistor, and its second terminal coupled to ground.

8. The fail-safe I / O interface circuit according to claim 7, characterized in that, The first logic circuit module includes a NAND gate, a second inverter, and a third inverter connected in sequence, wherein: The NAND gate has its first input terminal serving as the first input terminal of the first logic circuit module, and its second input terminal serving as the second input terminal of the first logic circuit module. The second inverter is located between the NAND gate and the third inverter; The output of the third inverter serves as the output of the first logic circuit module.

9. The fail-safe I / O interface circuit according to claim 7, characterized in that, The first switching module includes a transmission gate, which comprises a P-type transistor and an N-type transistor connected in parallel, wherein: The gate of the P-type transistor in the transmission gate serves as the first control terminal of the first switching module, and is suitable for transmitting high-level signals. The gate of the N-type transistor in the transmission gate serves as the second control terminal of the first switching module, and is suitable for transmitting low-level signals.

10. The fail-safe I / O interface circuit according to claim 7, characterized in that, The output unit further includes: a second logic circuit module, a second switching module, and a seventh transistor, wherein: The second logic circuit module has a first input terminal coupled to the enable signal terminal, a second input terminal coupled to the input node, and an output terminal coupled to the input terminal of the second switch module. The second switching module has a first control terminal coupled to ground, a second control terminal coupled to the power supply terminal, and an output terminal coupled to the control terminal of the seventh transistor. The seventh transistor has its first terminal coupled to the second terminal of the second switching module, and its second terminal coupled to the ground.

11. The fail-safe I / O interface circuit according to any one of claims 1 to 10, characterized in that, Also includes: A pull-down protection unit, coupled between the output node of the output unit and ground, is adapted to pull down the voltage of the output node of the output unit to zero volts when the level of the enable signal terminal is high.

12. A system-on-a-chip, characterized in that, include: The fail-safe I / O interface circuit according to any one of claims 1 to 11, the fail-safe I / O interface circuit includes an enable signal terminal, a control unit, and an output unit; The processor is coupled to a power supply terminal, an enable signal terminal of the fail-safe I / O interface circuit, and an input node of the output unit. It is adapted to input an enable signal to the fail-safe I / O interface circuit through the enable signal terminal, and to input a clock signal or a level signal to the input node of the output unit.

Images