A metastable state correction circuit and a successive approximation analog-to-digital conversion circuit

Abstract

The present application relates to the field of electronic technologies, and provides a metastability correction circuit for a successive approximation analog-to-digital conversion circuit, including: a first AND gate, a second AND gate, a first delay line, a second delay line, a flip-flop, and a metastability detection module; wherein, two input terminals of the first AND gate are respectively coupled to a longest time signal of comparison completion and a comparison completion signal, and an output terminal is respectively coupled to an input terminal of the first delay line and a first input terminal of the flip-flop; an input terminal of the second delay line is coupled to the longest time signal of comparison completion, an output terminal of the second delay line is coupled to a first input terminal of the second AND gate, a second input terminal of the second AND gate is coupled to the comparison completion signal, and an output terminal of the second AND gate is coupled to a first input terminal of the metastability detection module; an output terminal of the flip-flop is coupled to a second input terminal of the metastability detection module, and the metastability detection module outputs the longest time signal of comparison completion. The present application can detect the possible metastability in a comparator in a SAR ADC and perform correction.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and more particularly to a metastability correction circuit for a successive approximation analog-to-digital conversion circuit and a successive approximation analog-to-digital conversion circuit. Background Art

[0002] An ADC (Analog-to-Digital Convertor) is a circuit that converts an analog signal into a digital signal. The applications of ADCs are very extensive, including communication devices, test instruments, audio devices, etc. With the development of integrated circuit technology, SAR ADC (Successive-Approximation-Register ADC) has received increasing attention due to its advantages of low power consumption and less influence by the process. Figure 1 is a common system block diagram of SAR ADC Figure 1 Taking an 8-bit SAR ADC as an example.

[0003] In Figure 1 In the shown system block diagram, the part within the dashed box is a DAC (Digital-to-Analog Convertor), whose functions are to generate a signal for sampling and a successive approximation signal DAC_OUT for comparison during conversion. The specific waveform in its circuit is as shown in Figure 2 shown. The DAC_OUT signal generated by the DAC part in the circuit serves as one input signal of the comparator, is compared with another input signal VCM, and the switch of the DAC is changed according to the comparison result to generate the next signal to be compared.

[0004] As SAR ADCs develop towards high speed, asynchronous clocks have been more widely used. For example Figure 2 in, after a certain setup time t settle of the output of the DAC, a rising edge of CMPCLK is generated to notify the comparator to start comparison. After a comparison time t comp, a comparison result is generated, and a rising edge of CMPVALID indicates the completion of this comparison, and at the same time, the next DAC setup process starts.

[0005] From the above principle of asynchronous clocks, this type of ADC does not require an external master clock to synchronize each operation. Moreover, when the comparison speed of the comparator is fast, it can have a working speed faster than that of the synchronous master clock.

[0006] However, the comparison time of the comparator is related to the signal difference at the input terminal. When the input signal difference is large, the comparison time is short. However, when the input signal difference is small, the comparison time will be very long. Therefore, when the difference between DAC_OUT and VCM is very small, it may take a long time to generate a correct comparison result, as Figure 3 shown in

[0007] In Figure 3 , the difference Delta between DAC_OUT and VCM in the third beat is very small, so the comparison time tcomp for this time is particularly long. And if Delta is even smaller, it may even occur that this conversion cannot be completed normally. This phenomenon is called the metastability of the comparator in SAR ADC.

[0008] The metastability has a great impact on the normal operation of SAR ADC, making it possible for the ADC to fail to complete a normal comparison. Especially in low-voltage SAR ADCs, the impact of metastability is greater. Summary of the Invention

[0009] The purpose of this application is to provide a metastability correction circuit for a successive approximation analog-to-digital conversion circuit, which can detect the possible metastability of the comparator in SAR ADC and correct it.

[0010] This application discloses a metastability correction circuit for a successive approximation analog-to-digital conversion circuit, including: first and second AND gates, first and second delay lines, a flip-flop, and a metastability detection module; wherein,

[0011] Two input terminals of the first AND gate are respectively coupled to the longest time signal of comparison completion and the comparison completion signal, and the output terminal is respectively coupled to the input terminal of the first delay line and the first input terminal of the flip-flop;

[0012] The input terminal of the second delay line is coupled to the longest time signal of comparison completion, the output terminal of the second delay line is coupled to the first input terminal of the second AND gate, the second input terminal of the second AND gate is coupled to the comparison completion signal, and the output terminal of the second AND gate is coupled to the first input terminal of the metastability detection module;

[0013] The output terminal of the flip-flop is coupled to the second input terminal of the metastability detection module, and the metastability detection module outputs the longest time signal of comparison completion.

[0014] In a preferred example, the flip-flop outputs a comparison start signal to the comparator; when there is metastability in the comparator, the longest time signal of comparison completion output by the metastability detection module resets the comparison start signal, and the comparator outputs a specified level.

[0015] In a preferred example, after the comparator outputs a specified level, the signal of the longest time for comparison completion is reset.

[0016] In a preferred example, the specified level is a low level.

[0017] In a preferred example, the flip-flop includes a D flip-flop.

[0018] This application also discloses a successive approximation type analog-to-digital conversion circuit, including:

[0019] A digital-to-analog conversion circuit for outputting an analog signal;

[0020] An amplifier, the first input end of the amplifier is respectively coupled to a first reference signal and a second reference signal, and the second input end is coupled to its output end;

[0021] A comparator, the first input end of the comparator is coupled to the output end of the amplifier, and the second input end is coupled to the output end of the digital-to-analog conversion circuit;

[0022] A successive approximation logic, the successive approximation logic is connected to the output end of the comparator and outputs a digital signal for controlling the digital-to-analog conversion circuit;

[0023] The metastability correction circuit as described above, the metastability correction circuit outputs a comparison start signal to the comparator.

[0024] In a preferred example, the digital-to-analog conversion circuit includes:

[0025] A capacitive DAC structure, the capacitive DAC structure includes:

[0026] A capacitor array, the capacitor array has n-bit capacitors, one end of each capacitor is commonly connected as an output end, and the other end of each capacitor is connected to an input signal through a first switch and is connected to a first reference signal or a second reference signal through a second switch;

[0027] A resistive DAC structure, the resistive DAC structure includes 2 m resistors connected in series between the first reference signal and the second reference signal, the nodes between adjacent resistors and one end of the resistor connected to the second reference signal are respectively connected to one end of a third switch, and the other ends of each third switch are connected to the capacitive DAC structure.

[0028] Compared with the prior art, this application has at least the following beneficial effects:

[0029] First, the circuit structure is simple and the reliability is relatively high.

[0030] Second, the maximum comparison time can be adjusted. For different speeds, different maximum comparison times can be adjusted.

[0031] Third, the circuit has the function of automatic reset and the ability to continuously detect metastability multiple times.

[0032] A large number of technical features are recorded in this specification and are distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of this application are listed, the specification will be too lengthy. To avoid this problem, each technical feature disclosed in the above-mentioned invention content of this specification, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A + B + C are disclosed, and in another example, features A + B + D + E are disclosed. Features C and D are equivalent technical means that play the same role. Only one of them can be used technically and it is impossible to use both at the same time. Feature E can be combined with feature C technically. Then, the solution of A + B + C + D should not be regarded as having been recorded because it is technically infeasible, while the solution of A + B + C + E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shows a schematic diagram of a SAR ADC in the prior art.

[0034] Figure 2 Shows Figure 1 the waveform diagram of signal comparison.

[0035] Figure 3 Shows Figure 1 the waveform diagram of the comparator in metastable state.

[0036] Figure 4 Shows a schematic diagram of the metastability detection circuit in an example of this application.

[0037] Figure 5 Shows the timing diagram when there is no metastability in the comparator in an example of this application.

[0038] Figure 6 Shows the timing diagram when there is metastability in the comparator in an example of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] In the following description, many technical details are presented to enable a better understanding of the present application by the reader. However, those of ordinary skill in the art will understand that the technical solutions claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0040] To make the objectives, technical solutions, and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0041] The first embodiment of the present application provides a metastability correction circuit 400 for a successive approximation analog-to-digital conversion circuit, and its circuit structure is shown in Figure 4 and includes: a first AND gate 401, a second AND gate 402, a first delay line 403, a second delay line 404, a flip-flop 405, and a metastability detection module (delay_mstb) 406. The metastability correction circuit 400 can detect the possible metastability in the comparator of the successive approximation analog-to-digital conversion circuit (SAR ADC) and correct it.

[0042] In one embodiment, the structure of the successive approximation analog-to-digital conversion circuit is shown in Figure 1 and includes a digital-to-analog converter (DAC), an amplifier, a comparator, and successive approximation logic (SAR logic). The digital-to-analog conversion circuit is used to output an analog signal. The first input terminal of the amplifier is respectively coupled to the first reference signal VTOP and the second reference signal VBOT, and the second input terminal is coupled to its output terminal. The first input terminal of the comparator is coupled to the output terminal of the amplifier, and the second input terminal is coupled to the output terminal of the digital-to-analog conversion circuit. The successive approximation logic is connected to the output terminal of the comparator and outputs a digital signal XD0-XD7 for controlling the digital-to-analog conversion circuit. Among them, the metastability correction circuit outputs a comparison start signal CMPCLK to the comparator.

[0043] In one embodiment, the digital-to-analog conversion circuit includes: a capacitive DAC structure (C_DAC) and a resistive DAC structure (R_DAC). The resistive DAC structure includes 2 connected in series between the first reference signal VTOP and the second reference signal VBOT mA resistor, a node between adjacent resistors, and one end of the resistor connected to the second reference signal VBOT are each connected to one end of a third switch S0 to S7, and the other end of each third switch is connected to a capacitive DAC structure. The capacitive DAC structure includes: a capacitor array having n-bit capacitors, one end of each capacitor is commonly connected as an output end, and the other end of each capacitor is connected to an input signal through a first switch S and connected to the first reference signal VTOP or the second reference signal VBOT through a second switch S'. The capacitive DAC structure includes a dummy capacitor, one end of the dummy capacitor is connected to the output end through the first switch S, and the other end is connected to the second reference signal or the other ends of the third switches in the resistive DAC structure through the second switch S'.

[0044] Two input terminals of the first AND gate 401 are respectively coupled to the longest time signal CMPVALID_MAXTIME when the comparison is completed and the comparison completion signal CMPVALID, and the output terminal is respectively coupled to the input terminal of the first delay line 403 and the first input terminal of the flip-flop 405, and outputs CMPVALID_I to the first delay line 403 and the flip-flop 405. The input terminal of the second delay line 404 is coupled to the longest time signal CMPVALID_MAXTIME when the comparison is completed, the output terminal of the second delay line 404 is coupled to the first input terminal of the second AND gate 402, the second input terminal of the second AND gate 402 is coupled to the comparison completion signal CMPVALID, and the output terminal of the second AND gate 402 is coupled to the first input terminal of the metastability detection module 406.

[0045] The output terminal of the flip-flop 405 is coupled to the second input terminal of the metastability detection module 406, and the metastability detection module 406 outputs the longest time signal CMPVALID_MAXTIME when the comparison is completed. In one embodiment, the flip-flop may include a D flip-flop.

[0046] In one embodiment, the flip-flop 405 outputs a comparison start signal CMPCLK to the comparator. When there is metastability in the comparator, the longest time signal CMPVALID_MAXTIME output by the metastability detection module 406 resets the comparison start signal CMPCLK, and the comparator outputs a specified level. In one embodiment, the specified level is a low level. In one embodiment, after the comparator outputs the specified level, the longest time signal when the comparison is completed is reset.

[0047] In this embodiment, the possible metastability of the comparator in the SAR ADC can be detected and corrected.

[0048] Figure 5It is the timing diagram when there is no metastability in the comparator. When the comparator can normally compare and obtain a result, the comparison completion signal CMPVALID becomes high, resets the comparison start signal CMPCLK, and also resets the metastability detection module 406, while saving the comparison result of the comparator.

[0049] Figure 6 It is the timing diagram when there is metastability in the comparator. When a rising edge appears on the comparison start signal CMPCLK and the comparator starts to compare, if metastability occurs, that is, the maximum comparison time of the comparator is reached, then a rising edge will appear on the longest time signal CMPVALID_MAXTIME, indicating that metastability has occurred in the SAR ADC. The following operations will be performed at this time: reset the comparison start signal CMPCLK to 0, reset the comparator so that it no longer compares, assign the comparison result to a specified level (for example, 0) and save it. Then, after the delay of the second delay line 404, the metastability detection module 406 is automatically reset.

[0050] In this embodiment, a circuit for detecting and correcting metastability is added to the asynchronous SAR ADC, which can detect and correct the possible metastability in the comparator of the SAR ADC. The circuit structure is simple, but has high reliability and flexible functions.

[0051] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one" does not exclude the existence of another identical element in the process, method, article or device including the element. In the application documents of this patent, if it is mentioned that an action is performed according to a certain element, it means at least performing the action according to the element, including two cases: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple times, multiple types, etc. include 2, 2 times, 2 types, as well as more than 2, more than 2 times, more than 2 types.

[0052] The term "coupled to" and its derivatives may be used in this document. "Coupling" may mean that two or more elements are in direct physical or electrical contact. However, "coupling" may also mean that two or more elements are in contact with each other indirectly, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0053] This specification includes combinations of various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as being mutually exclusive or clearly understood by those skilled in the art to be mutually exclusive, these embodiments are not mutually exclusive. It should be noted that the word "or" is used in a non-exclusive sense in this specification unless the context clearly dictates otherwise or requires otherwise.

[0054] All documents mentioned in this specification are considered to be incorporated herein in their entirety so as to be available as a basis for modification if necessary. In addition, it should be understood that the above are only preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of one or more embodiments of this specification shall be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A metastability correction circuit for a successive approximation analog-to-digital conversion circuit, characterized in that, Comprising: A first AND gate, a second AND gate, a first delay line, a second delay line, a flip-flop, and a metastability detection module; wherein, Two input terminals of the first AND gate are respectively coupled to a longest comparison completion time signal and a comparison completion signal, and an output terminal is respectively coupled to an input terminal of the first delay line and a first input terminal of the flip-flop; An input terminal of the second delay line is coupled to the longest comparison completion time signal, an output terminal of the second delay line is coupled to a first input terminal of the second AND gate, a second input terminal of the second AND gate is coupled to the comparison completion signal, and an output terminal of the second AND gate is coupled to a first input terminal of the metastability detection module; An output terminal of the flip-flop is coupled to a second input terminal of the metastability detection module, and the metastability detection module outputs the longest comparison completion time signal.

2. The metastable state correction circuit according to claim 1, wherein The flip-flop outputs a comparison start signal to the comparator; when there is metastability in the successive approximation comparator, the longest comparison completion time signal output by the metastability detection module resets the comparison start signal, and the comparator outputs a specified level.

3. The metastable state correction circuit according to claim 2, wherein After the comparator outputs the specified level, the longest comparison completion time signal is reset.

4. The metastable state correction circuit according to claim 2, wherein The specified level is a low level.

5. The metastable state correction circuit according to claim 2, characterized in that The flip-flop includes a D flip-flop.

6. A successive approximation type analog-to-digital conversion circuit, characterized in that, Comprising: A digital-to-analog conversion circuit for outputting an analog signal; An amplifier, a first input terminal of the amplifier is respectively coupled to a first reference signal and a second reference signal, and a second input terminal is coupled to its output terminal; A comparator, a first input terminal of the comparator is coupled to the output terminal of the amplifier, and a second input terminal is coupled to the output terminal of the digital-to-analog conversion circuit; A successive approximation logic, the successive approximation logic is connected to the output terminal of the comparator and outputs a digital signal for controlling the digital-to-analog conversion circuit; The metastability correction circuit according to any one of claims 1-5, the metastability correction circuit outputs a comparison start signal to the comparator.

7. The successive approximation type analog-to-digital conversion circuit according to claim 6, wherein The digital-to-analog conversion circuit includes: A capacitive DAC structure, the capacitive DAC structure includes: A capacitor array, the capacitor array has n-bit capacitors, one end of each capacitor is commonly connected as an output terminal, and the other end of each capacitor is connected to an input signal through a first switch and connected to a first reference signal or a second reference signal through a second switch; Resistive DAC structure, the resistive DAC structure includes 2 resistors connected in series between the first reference signal and the second reference signal m The nodes between adjacent resistors and one end of the resistor connected to the second reference signal are each connected to one end of a third switch, and the other end of each third switch is connected to the capacitive DAC structure.

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