A mixed signal equalization receiver and method

Abstract

The application discloses a kind of mixed signal equalization receiver and method, wherein the mixed signal equalization receiver includes: baseline drift module, analog-digital conversion module, phase-locked loop module, forward feedback equalizer, decision feedback equalizer, decision module, adder A1, adder A2 and adder A3.The application combines digital signal processing with analog signal adjustment, improves the calculation precision while effectively reducing the chip area.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of equalization of received data in Ethernet communication, and particularly relates to a mixed signal equalization receiver and method. BACKGROUND

[0002] In Ethernet transmission, due to the non-ideal characteristics of twisted pair, there are channel effects such as attenuation and distortion in the transmission process, causing serious inter-symbol interference (ISI) and baseline drift, affecting the correctness of data recovery. Therefore, appropriate equalization technology must be used in the receiving circuit to compensate for the channel response, eliminate the influence of these non-ideal factors, and recover the disturbed signal to meet the 10 -10 bit error rate requirement.

[0003] The existing equalization technology either uses analog equalization, which is not high in precision, or uses digital equalization, which greatly increases the chip area, and most of them use linear equalization, which is not good for backward interference elimination. SUMMARY

[0004] The technical problem solved by the present application is to overcome the shortcomings of the prior art and provide a mixed signal equalization receiver and method, which combines digital signal processing with analog signal adjustment to improve the calculation precision while effectively reducing the chip area.

[0005] The present application is implemented by the following technical solutions: a mixed signal equalization receiving method, comprising: obtaining an offset correction signal by operating the received signal and the error signal on the channel; converting the offset correction signal into a digital signal according to the clock sampling; filtering the digital signal to obtain a first filtered signal; obtaining a difference signal by operating the first filtered signal and the second filtered signal; comparing the filtered signal with a preset expected signal to output an estimated original channel signal, and filtering the estimated original channel signal to obtain a second filtered signal; and obtaining an error signal by operating the estimated original channel signal and the difference signal.

[0006] The mixed signal equalization receiving method further comprises: adjusting the filter coefficients of the forward feedback equalizer and the decision feedback equalizer according to the error signal.

[0007] In the mixed signal equalization receiving method, the forward feedback equalizer and the decision feedback equalizer both use the same filter structure, which is composed of an input n-stage delay module, n multipliers and an adder.

[0008] In the mixed signal equalization receiving method, the output of the filter structure at time k is:

[0009] Y k = ω0X k+ ω1X k-1 +... + ω n X k-n ;

[0010] wherein Y k is the output of the filter structure at time k, ω0 is the filter coefficient of the filter structure at time k, ω1 is the filter coefficient of the filter structure at time k-1, ω n is the filter coefficient of the filter structure at time k-n; X k is the input of the filter structure at time k, X k-1 is the input of the filter structure at time k-1, X k-n is the input of the filter structure at time k-n.

[0011] In the above hybrid signal equalization receiving method, the decision module compares the filtered signal with the preset expected signal to output the estimated original channel signal; wherein the decision module is composed of a comparator, and the estimated original channel signal is obtained by comparing the filtered signal with the preset expected signal.

[0012] A hybrid signal equalization receiver comprises a baseline drift module, an analog-to-digital conversion module, a phase-locked loop module, a forward feedback equalizer, a decision feedback equalizer, a decision module, an adder A1, an adder A2 and an adder A3; wherein the adder A1 receives a received signal on a channel and an error signal from the baseline drift module, the adder A1 obtains an offset correction signal by performing operation according to the received signal on the channel and the error signal, and transmits the offset correction signal to the analog-to-digital conversion module; the analog-to-digital conversion module samples the offset correction signal according to a clock generated by the phase-locked loop module, and transmits the offset correction signal converted into a digital signal to the forward feedback equalizer; the forward feedback equalizer filters the digital signal to obtain a first filtered signal, and transmits the first filtered signal to the adder A2; the adder A2 receives the first filtered signal and a second filtered signal from the decision feedback equalizer, the adder A2 obtains a difference signal by performing operation according to the first filtered signal and the second filtered signal, and transmits the difference signal to the decision module and the adder A3 respectively; the decision module compares the filtered signal with a preset expected signal to output an estimated original channel signal, and transmits the estimated original channel signal to the adder A3 and the decision feedback equalizer respectively, the decision feedback equalizer receives the estimated original channel signal, filters the estimated original channel signal to obtain the second filtered signal; the adder A3 obtains an error signal by performing operation according to the estimated original channel signal and the difference signal, and transmits the error signal to the phase-locked loop module and the baseline drift module respectively.

[0013] The above-mentioned mixed signal equalization receiver further includes: an adaptive module; wherein the adder A3 transmits the error signal to the adaptive module; the adaptive module adjusts the filter coefficients of the forward feedback equalizer and the decision feedback equalizer according to the error signal.

[0014] In the above-mentioned mixed signal equalization receiver, the forward feedback equalizer and the decision feedback equalizer both adopt the same filter structure, which is composed of an input n-stage delay module, n multipliers and an adder.

[0015] In the above mixed signal equalization receiver, the output of the filter structure at time k is:

[0016] Y k =ω0X k +ω1X k-1 +...+ω n X k-n ;

[0017] Among them, Y k is the output of the filter structure at time k, ω0 is the filter coefficient of the filter structure at time k, ω1 is the filter coefficient of the filter structure at time k-1, ω n is the filter coefficient of the filter structure at time kn; X k is the input of the filter structure at time k, X k-1 is the input of the filter structure at time k-1, X k-n is the input of the filter structure at time kn.

[0018] In the above-mentioned mixed signal equalization receiver, the decision module is composed of a comparator, which obtains an estimated original channel signal by comparing the filtered signal with a preset expected signal.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] (1) The present invention combines digital signal processing with analog signal adjustment to improve calculation accuracy while effectively reducing chip area;

[0021] (2) The present invention effectively reduces the impact of forward interference and backward interference on the signal through an equalization method that combines a forward feedback equalizer with a decision feedback equalizer;

[0022] (3) The present invention accelerates the convergence speed of equalization through simultaneous adaptive adjustment of the forward feedback equalizer and the decision feedback equalizer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a better understanding of the preferred embodiments, and are not intended to be a limitation of the application. Moreover, in the drawings, like reference numerals denote same or similar components. In the drawings:

[0024] Figure 1 is a structural block diagram of a mixed signal equalization receiver provided by an embodiment of the application;

[0025] Figure 2 is a structural block diagram of a decision feedback equalizer provided by an embodiment of the application;

[0026] Figure 3 is a structural block diagram of a decision module provided by an embodiment of the application. DETAILED DESCRIPTION

[0027] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict, and the present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0028] Figure 1 is a structural block diagram of a mixed signal equalization receiver provided by an embodiment of the application. As shown in Figure 1 , the mixed signal equalization receiver includes a baseline wander module (BLW), an analog-to-digital conversion module (ADC), a phase-locked loop module (PLL), a feed-forward equalizer (FFE), a decision feedback equalizer (DFE), a decision module, an adaptive module, a summer A1, a summer A2, and a summer A3. Among them,

[0029] The adder A1 receives the received signal on the channel and the error signal from the baseline drift module, and the adder A1 obtains the offset correction signal by performing operation according to the received signal on the channel and the error signal, and transmits the offset correction signal to the analog-to-digital conversion module; the analog-to-digital conversion module samples the offset correction signal according to the clock generated by the phase-locked loop module, and transmits the offset correction signal converted into a digital signal to the forward feedback equalizer after the offset correction signal is converted into the digital signal; the forward feedback equalizer filters the digital signal to obtain a first filtered signal, and transmits the first filtered signal to the adder A2; the adder A2 receives the first filtered signal and a second filtered signal from the decision feedback equalizer, and the adder A2 obtains a difference signal by performing operation according to the first filtered signal and the second filtered signal, and transmits the difference signal to the decision module and the adder A3 respectively; the decision module compares the filtered signal with a preset expected signal to output an estimated original channel signal, and transmits the estimated original channel signal to the adder A3 and the decision feedback equalizer respectively, and the decision feedback equalizer receives the estimated original channel signal, filters the estimated original channel signal to obtain the second filtered signal; the adder A3 obtains the error signal by performing operation according to the estimated original channel signal and the difference signal, and transmits the error signal to the adaptive module, the phase-locked loop module and the baseline drift module respectively; the adaptive module is used for adjusting the filtering coefficients of the forward feedback equalizer and the decision feedback equalizer, and is also used for adjusting the frequency of the PLL and the offset of the BLW.

[0030] Specifically, the analog signal received on the channel is operated with the output of the baseline drift module (BLW), and the offset correction signal is output to the analog-to-digital conversion module (ADC) after the offset correction; the n-bit digital signal output by the ADC is transmitted to the forward feedback equalizer (FFE) of the digital module, the FFE is composed of multiple delay structures, each delay corresponds to a coefficient, and the data vector is convolved with the coefficient to output; the FFE output is transmitted to the adder A2, and the output of the decision feedback equalizer (DFE) is operated to be transmitted to the decision module, the decision module estimates the signal transmitted on the receiving channel after comparison operation, and then the error e is obtained by operating with the output of the adder A2; the output of the decision module is used as the input of the DFE, the DFE is composed of multiple delay structures, each delay corresponds to a coefficient, and the data vector is convolved with the coefficient to output, and the output result is transmitted to the adder A2 after being inverted; the error e is used as the input of the adaptive module to adjust the coefficients of each stage of the FFE and the DFE, and is also used as the input of the analog part clock recovery (PLL) and the BLW, and the BLW is adjusted each time to adjust the offset of the analog signal on the channel, and the PLL resamples the ADC.

[0031] The embodiment includes both analog and digital parts. The analog part includes baseline wander correction, ADC conversion and clock recovery; the recovered clock samples the ADC signal into the digital part, where it is processed by forward feedback equalization (FFE), filter (FIR) and decision feedback equalization (DFE) to output a signal, which is compared with an ideal signal in a decision module, and the difference is input into an adaptive module to adjust the DFE coefficients, the baseline wander of the analog signal and the phase of the clock recovery. The adjusted clock is used to sample the ADC again to enter the digital equalization until the clock is locked. The mixed signal can eliminate the signal attenuation and distortion caused by inter-symbol interference and noise.

[0032] The baseline wander module (BLW) includes charge and discharge units. According to the positive or negative of the error e input and output by the decision module, the error is converted into charge-up and charge-down signals as the input of the BLW to adjust the offset of the analog channel input, so that the analog differential signal of the channel is symmetric about zero.

[0033] The PLL output clock signal is used to sample the ADC, and the error e input and output by the decision module is used as the input of the PLL to adjust the clock signal after the digital part is equalized according to the sampled signal, and the process is repeated until the frequency of the PLL output clock signal is fixed.

[0034] The FFE and DFE modules adopt the same filter structure, which is composed of an input n-stage delay module, n multipliers and an adder; wherein n is a positive integer greater than or equal to 3. The given input is X, the n-stage delay input is X n-1 , the output of each stage is multiplied by the corresponding adaptive coefficient ω n , and the sum of all multiplied results is the output Y of the structure. Then the output at time k is:

[0035] Y k = ω0X k + ω1X k-1 +... + ω n X k-n ;

[0036] The structure is a standard filter structure, wherein the number of stages n is selected according to the convergence speed and filtering accuracy requirements, and the coefficients ω n are determined by adaptive algorithms.

[0037] The decision module is composed of a comparator. The analog input signal is estimated by comparing the input with the expected value, and the output of the decision module is the output of the entire mixed signal receiver, and the error obtained by subtracting the input of the decision module from the output is the input of the adaptive module. Specifically, as shown in Figure 3As shown. According to the encoding characteristics of different Ethernet rates, each expected value is trained to an expected range, the input signal Si is compared with the expectation to obtain the estimated value Yi, and the difference e between Yi and Si enters the equalization module to readjust the adaptive coefficient, Yi enters the decision feedback equalizer for eliminating backward interference.

[0038] This decision feedback structure combines the input of FFE with the output of the decision module, which can prevent the increase of error caused by the misjudgment of the decision maker and accelerate the convergence speed of the filter; meanwhile, the adaptive module can automatically adjust the coefficient ω n according to the length of the twisted pair.

[0039] BLW, ADC and PLL all belong to the analog part. The analog input on the receiving channel and the BLW module are connected to the adder A2 together, the BLW adjusts the deviation of the analog input, and the result is output to the ADC by A2. The ADC converts the corrected analog input into n-bit digital signal, which is then sampled by the clock output by the PLL module and output to the digital part for processing. The accuracy n of the ADC is determined according to the circuit characteristics.

[0040] FFE, DFE, adaptive module and decision module together constitute a complete adaptive decision feedback equalizer, as shown in Figure 2 The input signal Xi of the forward feedback equalizer (FFE) is the output of the analog-to-digital conversion module (ADC), one end is connected to the delay unit T10, and the other end is connected to the multiplier 10 and the multiplier 20, the other input of the multiplier 10 is the coefficient ω -n , and the multiplier 20 is used to calculate the coefficient ω -n ; the output of the delay unit T10 is connected to the next delay unit T11 and the multiplier 11 and the multiplier 21, the other input of the multiplier 11 is the coefficient ω -n-1 , and the multiplier 21 is used to calculate the coefficient ω -n-1; and so on. The output of the multiplier 4j (j = 0, 1,..., n) is added to the output of the FFE. The output of the FFE enters the adder A2, and the other input of the adder A2 is the output of the DFE. The output Si of the adder A2 is the input of the decision module, and the output Yi of the decision module is the input of the DFE. The Yi enters the delay unit T01, and the output of the T01 enters the next delay unit T02, and two multipliers 41 and 52. The other input of the multiplier 41 is the coefficient ω1, and the multiplier 52 is used to calculate the coefficient ω1. The output of the delay unit T02 enters the next delay unit and two multipliers 42 and 52. The other input of the multiplier 42 is the coefficient ω2, and the multiplier 52 is used to calculate the coefficient ω2. The process is repeated for n-1 times. The output of the delay unit T0n enters the next delay unit and two multipliers 4n and 5n. The other input of the multiplier 4n is the coefficient ωn, and the multiplier 5n is used to calculate the coefficient ωn. The output of the multiplier 4k (k = 1, 2,..., n) is added to the output of the DFE. The number of delay stages of the FFE and the DFE is determined by the characteristics of the communication system and the algorithm. The output of the DFE also enters the adder A2. n n The output of the multiplier 5k (k = 1, 2,..., n) is added to the output of the DFE. The number of delay stages of the FFE and the DFE is determined by the characteristics of the communication system and the algorithm. The output of the DFE also enters the adder A2.

[0041] The adder A2 adds the inputs of the FFE and the DFE to obtain Si, which is input to the decision module. The Si enters the expected comparator, and the expected value Yi is obtained after comparison with the expected range. The Yi and the input of the DFE are obtained.

[0042] At the same time, the Yi and the Si enter the adder A3, and the error e of the two is output by the adder A3, which is used for self-negotiation coefficient calculation.

[0043] The multiplier M3 is used for self-negotiation coefficient calculation, that is, the error e and the other input △ of the M3 are convolved, and △ is the calculation step. The output of the M3 is used as the other input of the multiplier 2j (j = 0, 1,..., n) in the FFE and the multiplier 5k (k = 1, 2,..., n) in the DFE. The output of the multiplier 2j (j = 0, 1,..., n) is used as the input of the Σ in the FFE, and the adaptive coefficient ωi (i = -n, -n+1,..., -1, 0) is obtained after operation. The output of the multiplier 5k (k = 1, 2,..., n) is used as the input of the Σ in the DFE, and the adaptive coefficient ωi (i = 1, 2,..., n) is obtained after operation. The value of △ is determined by the adaptive algorithm.

[0044] ​The embodiment also provides a mixed signal equalization receiving method, which comprises the following steps: an adder A1 receives a received signal on a channel and an error signal from a baseline wander module, and the adder A1 obtains an offset correction signal by performing calculation on the received signal on the channel and the error signal, and transmits the offset correction signal to an analog-to-digital conversion module; the analog-to-digital conversion module samples the offset correction signal according to a clock generated by a phase-locked loop module, and transmits the offset correction signal converted into a digital signal to a forward feedback equalizer after the offset correction signal is converted into the digital signal; the forward feedback equalizer filters the digital signal to obtain a first filtered signal, and transmits the first filtered signal to an adder A2; the adder A2 receives the first filtered signal and a second filtered signal from a decision feedback equalizer, and the adder A2 obtains a difference signal by performing calculation on the first filtered signal and the second filtered signal, and transmits the difference signal to a decision module and the adder A3 respectively; the decision module compares the filtered signal with a preset expected signal to output an estimated original channel signal, and transmits the estimated original channel signal to the adder A3 and the decision feedback equalizer respectively, and the decision feedback equalizer receives the estimated original channel signal, filters the estimated original channel signal to obtain the second filtered signal; and the adder A3 obtains the error signal by performing calculation on the estimated original channel signal and the difference signal, and transmits the error signal to the phase-locked loop module and the baseline wander module respectively.

[0045] Specifically, the BLW module is determined first, the module is converted into charge-up and charge-down signals according to the positive and negative of the error signal e, and the signals are input into the adder A1 to perform calculation with the input of the analog channel, so that the offset correction signal after calculation is symmetrical about zero, and when the error e is 0, the signal is 0;

[0046] The offset correction signal is input into the ADC module to be sampled into a digital signal output, and the sampling clock PLL is initially a fixed frequency clock, and since the clock edge may not be in the middle of the offset correction signal to cause the error e, the PLL adjusts the frequency until the clock edge is adjusted to the middle of the offset correction signal according to the error e, and when the error e is 0, the clock is fixed in frequency and does not move;

[0047] The filter order and the corresponding filter initial coefficient of the FFE filter are determined, the digital signal is input into the FFE module to obtain the first filtered signal as one input of the adder A2; the filter order and the corresponding filter initial coefficient of the DFE are determined, and the output of the DFE is another input of the adder A2;

[0048] The decision strategy of the decision module is determined. The input of the decision module is the output of the adder A2, and the output of the decision module is the input of the DFE. Meanwhile, the input and output of the decision module are input into the adder A3 to obtain the error e of the iterative loop adjustment after calculation.

[0049] The application combines digital signal processing with analog signal adjustment, improves the calculation precision, and effectively reduces the chip area; the application combines the equalization mode of the forward feedback equalizer and the decision feedback equalizer, effectively reduces the influence of the forward interference and the backward interference on the signal; the application simultaneously adjusts the forward feedback equalizer and the decision feedback equalizer, and accelerates the convergence speed of the equalization.

[0050] Although the application has been disclosed as above with the preferred embodiments, it is not intended to limit the application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the application by using the disclosed methods and technical contents without departing from the spirit and scope of the application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application without departing from the technical solutions of the application all belong to the protection scope of the technical solutions of the application.

Claims

1. A mixed signal equalization receiving method, characterized in that include: An offset correction signal is obtained by performing an operation based on a received signal on the channel and a first error signal; sampling the offset correction signal according to the clock, and converting the offset correction signal into a digital signal; Filtering the digital signal to obtain a first filtered signal; A difference signal is obtained by performing an operation on the first filtered signal and the second filtered signal; After comparing the first filtered signal with a preset expected signal, an estimated original channel signal is output, and the estimated original channel signal is filtered to obtain a second filtered signal; A second error signal is obtained by performing calculations based on the estimated original channel signal and the difference signal; The filter coefficients of the forward feedback equalizer and the decision feedback equalizer are adjusted according to the second error signal. The second error signal serves as the input of the analog part clock recovery and baseline drift module. Each time the baseline drift module is adjusted, the offset adjustment is performed on the analog signal on the channel, and the analog part clock recovery resamples the analog-to-digital conversion module.

2. The mixed signal equalization receiving method according to claim 1, wherein: The forward feedback equalizer and the decision feedback equalizer both adopt the same filter structure, which is composed of an input n-stage delay module, n multipliers and an adder.

3. The mixed signal equalization receiving method according to claim 2, wherein: The output of the filter structure at time k is: Y k =ω0X k +ω1X k-1 +...+oh n X k-n ; Among them, Y k is the output of the filter structure at time k, ω0 is the filter coefficient of the filter structure at time k, ω1 is the filter coefficient of the filter structure at time k-1, ω n is the filter coefficient of the filter structure at time kn; X k is the input of the filter structure at time k, X k-1 is the input of the filter structure at time k-1, X k-n is the input of the filter structure at time kn.

4. The mixed signal equalization receiving method according to claim 1, wherein: The decision module compares the filtered signal with a preset expected signal and outputs an estimated original channel signal; wherein the decision module is composed of a comparator, and obtains the estimated original channel signal by comparing the filtered signal with the preset expected signal.

5. A mixed signal equalization receiver, characterized in that include: Baseline drift module, analog-to-digital conversion module, phase-locked loop module, forward feedback equalizer, decision feedback equalizer, decision module, adder A1, adder A2 and adder A3; wherein, The adder A1 receives a received signal on the channel and a first error signal from the baseline drift module, performs an operation based on the received signal on the channel and the first error signal to obtain an offset correction signal, and transmits the offset correction signal to the analog-to-digital conversion module; The analog-to-digital conversion module samples the offset correction signal according to the clock generated by the phase-locked loop module, converts the offset correction signal into a digital signal, and transmits it to the forward feedback equalizer; The forward feedback equalizer filters the digital signal to obtain a first filtered signal, and transmits the first filtered signal to the adder A2; The adder A2 receives the first filtered signal and the second filtered signal from the decision feedback equalizer, and performs an operation on the first filtered signal and the second filtered signal to obtain a difference signal, and transmits the difference signal to the decision module and the adder A3 respectively; The decision module compares the first filtered signal with a preset expected signal and outputs an estimated original channel signal, and transmits the estimated original channel signal to the adder A3 and the decision feedback equalizer respectively. The decision feedback equalizer receives the estimated original channel signal and filters the estimated original channel signal to obtain a second filtered signal. The adder A3 obtains a second error signal after performing calculation based on the estimated original channel signal and the difference signal, and transmits the second error signal to the phase-locked loop module and the baseline drift module respectively; Also includes: an adaptive module; wherein, The adder A3 transmits the second error signal to the adaptive module; The adaptive module adjusts the filter coefficients of the forward feedback equalizer and the decision feedback equalizer according to the second error signal; The second error signal is used as the input of the analog part clock recovery and baseline drift module. The baseline drift module adjusts the offset of the analog signal on the channel each time, and the analog part clock recovery resamples the analog-to-digital conversion module.

6. The hybrid signal equalization receiver according to claim 5, wherein: The forward feedback equalizer and the decision feedback equalizer both adopt the same filter structure, which is composed of an input n-stage delay module, n multipliers and an adder.

7. The hybrid signal equalization receiver according to claim 6, wherein: The output of the filter structure at time k is: Y k =ω0X k +ω1X k-1 +...+oh n X k-n ; Among them, Y k is the output of the filter structure at time k, ω0 is the filter coefficient of the filter structure at time k, ω1 is the filter coefficient of the filter structure at time k-1, ω n is the filter coefficient of the filter structure at time kn; X k is the input of the filter structure at time k, X k-1 is the input of the filter structure at time k-1, X k-n is the input of the filter structure at time kn.

8. The hybrid signal equalization receiver according to claim 5, wherein: The decision module is composed of a comparator, and estimates the original channel signal by comparing the filtered signal with a preset expected signal.

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