Dynamic reconfigurable signal processing platform based on ZYNQ architecture

Abstract

The invention discloses a dynamic reconfigurable signal processing platform based on a ZYNQ architecture, and belongs to the technical field of digital signal processing, and the dynamic reconfigurable signal processing platform comprises a channel preprocessing unit, a high-speed AD sampling unit, a ZYNQ-PL logic unit and a ZYNQ-PS algorithm processing unit. A radio frequency signal is fed in from an antenna end and then enters the channel preprocessing unit, a balun circuit and a filter bank are adopted to carry out preselection filtering, amplification and conditioning on the radio frequency signal, and the signal is extracted and sent to the high-speed AD sampling unit; the high-speed AD acquisition unit converts a received analog signal into a digital signal and transmits the digital signal to the ZYNQ-PL logic unit, and the ZYNQ-PL logic unit is connected with the ZYNQ-PS algorithm processing unit through an AXI bus; wherein the ZYNQ-PL logic unit is composed of a static region and three dynamic regions, and is mainly used for realizing a logic part of a functional waveform and completing reconstruction and loading of the functional waveform; and the ZYNQ-PS algorithm processing unit completes algorithm processing, realizes modulation and demodulation of a functional waveform and realizes a functional algorithm.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital signal processing, and particularly relates to a dynamic reconfigurable signal processing platform based on a ZYNQ architecture. BACKGROUND

[0002] The integrated radio frequency system is an important component of the aircraft avionics system, adopts an integrated and modular design idea, integrally designs voice communication, radio navigation, monitoring and other functions, completes a specific flight task, and is an important system for ensuring aircraft safety and performing aircraft take-off and landing tasks.

[0003] The signal processing platform is the information processing center of the integrated radio frequency system, and bears a large amount of real-time response and processing of flight data and instructions, and the technical level and processing capacity of the platform are crucial to aircraft safety and task execution efficiency. The traditional signal processing platform adopts a multi-channel FPGA+DSP design architecture, different functional threads run on each independent channel, the functional cross-channel reconfiguration process is complex, and the function needs to be deconstructed on the original channel before being executed on the new channel, which will cause a certain time interruption of the function, generally about 2-5 seconds, which will have a great influence on important task implementation and execution.

[0004] The traditional platform functional cross-channel reconfiguration is complex, cannot meet the system dynamic, real-time and uninterrupted reconfiguration requirements, and is relatively large in volume, weight and power consumption, and cannot meet the requirements of high integration, task real-time performance and reliability of the integrated radio frequency system. SUMMARY

[0005] The application aims to overcome the problems of the prior art, and discloses a dynamic reconfigurable signal processing platform based on a ZYNQ architecture, which utilizes the partial reconfigurable characteristics of the ZYNQ-PL part to time-division multiplex the limited logic resources, improves the reliability and robustness of the integrated radio frequency system task, reduces the power consumption and volume of the system, and meets the demand of modern aircraft task rapid response.

[0006] The application aims to achieve the following technical solutions: A dynamic reconfigurable signal processing platform based on a ZYNQ architecture, comprising a channel preprocessing unit, a high-speed AD sampling unit, a ZYNQ-PL logic unit and a ZYNQ-PS algorithm processing unit. Wherein, after the radio frequency signal is fed from an antenna end, the channel preprocessing unit is entered, a balun circuit and a filter bank are adopted to preselect, amplify and condition the radio frequency signal, and the signal is extracted and sent to the high-speed AD sampling unit. The high-speed AD acquisition unit converts the analog signal into a digital signal and transmits the digital signal to the ZYNQ-PL logic unit through a JESD204B bus, and the ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit are connected through an AXI bus. The ZYNQ-PL logic unit is composed of a static area and three dynamic areas, and mainly implements the logic part of the function waveform, including AD data framing, digital data exchange, and external radio component control, to complete the reconstruction and loading of the function waveform; the ZYNQ-PS algorithm processing unit completes algorithm processing, and implements modulation, demodulation, and function algorithm implementation of the function waveform.

[0007] According to a preferred embodiment, the ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit are implemented by a ZYNQ chip, which is divided into a ZYNQ-PL logic unit part and a ZYNQ-PS algorithm processing part.

[0008] According to a preferred embodiment, the ZYNQ-PL logic unit part is arranged with a dynamic area 1, a dynamic area 2, and a static area, The static area is a fixed basic resource, including a bottom interface, a clock configuration, and a system reset resource. The static area program remains unchanged during function reconstruction, and different function programs are dynamically loaded and reconstructed on the dynamic area 1 and the dynamic area 2.

[0009] According to a preferred embodiment, the ZYNQ-PS algorithm processing unit part includes an ARM1 and an ARM2, The ZYNQ-PS algorithm processing unit utilizes the multi-task processing performance of the ARM53 dual-core processor to implement C control and measurement functions and ATC functions on the ARM1, and to implement L control and measurement functions and Ka satellite communication functions on the ARM2. Different function programs are dynamically loaded in the dynamic area of the ZYNQ-PL logic unit part according to the requirements of different task stages of the aircraft, If the dynamic area 1 is reconstructed, the default C control and measurement is reconstructed to ATC, and the L control and measurement function of the dynamic area 2 is not affected during the reconstruction. If the dynamic area 2 is reconstructed, the default L control and measurement is reconstructed to Ka satellite communication.

[0010] According to a preferred embodiment, the function reconstruction process of the ZYNQ chip includes: After power-on, the initialization operation is first completed, and the board-level management program resets the hardware parts such as the ZYNQ unit, the phase-locked loop unit, and the storage unit, Then the ZYNQ-PS algorithm processing unit waits to receive a reconstruction instruction, and if no reconstruction instruction is received, the ZYNQ-PS algorithm processing unit continues to wait. After receiving the reconstruction instruction, the ZYNQ-PS algorithm processing unit program is started to be reconstructed. First, the Golden program of the Flash sector is run. After the Golden program is started, the function program to be reconstructed is booted and loaded. Then, it is determined whether the ZYNQ-PL logic unit loading completion flag is 1. If the flag is not 1, the function program is reloaded. If the flag is 1, the next step of loading the ZYNQ-PS program is started. The ZYNQ-PS algorithm processing unit executes the internal BootLoader program, and the function program stored in the external FLASH is booted and loaded to the PS end. Then, it is determined whether the PS program loading completion flag is 1. If the flag is not 1, the function program is reloaded. If the flag is 1, it indicates that the loading is completed, and the program jumps to the PS program entry to start the program running. The program jumps to the function waveform entry address to start executing the newly loaded waveform program. The signal processing channel completes the function waveform reconstruction.

[0011] According to a preferred embodiment, the high-speed AD sampling unit adopts a time interleaving algorithm to complete platform sampling through the stacking of a number of moving knives; and an adaptive clock mismatch calibration algorithm is adopted to calibrate errors of the multi-channel AD sampling data.

[0012] According to a preferred embodiment, the error calibration process of the multi-channel AD sampling data by using the adaptive clock mismatch calibration algorithm includes: X(t) is an analog input signal to be sampled, which is sampled by two ADC channels ADC1 and ADC2, and a digital signal is output after AD sampling , wherein the digital signal is the reference input of the LMS algorithm module, and the output of the LMS algorithm module after calculation is the clock error of the two channels, and the corresponding error and the digital signal are sent to the reconstruction filter H together to calculate the calibrated digital signal , and then the digital multiplexer MUX is used for time division multiplexing to output the final AD sampling signal X(K) after calibration and synthesis.

[0013] According to a preferred embodiment, the LMS algorithm module adopts the following improved LMS algorithm to calculate the clock error , including: First step: calculating the channel sampling clock: first, initializing the target function clock error , calculating the sampling clock according to the formula , wherein is the current clock error, j is the iteration number of the algorithm; Second step: calculate the objective function and the gradient, define the objective function, the objective function V is defined as:

[0014] wherein, is the signal processed by the reconstruction filter H, is the reference signal; Calculate the gradient, calculate the gradient value of the objective function:

[0015] Third step: update the clock error, adaptively adjust the learning rate, dynamically adjust the learning rate according to the modulus of the gradient:

[0016] wherein, is a preset threshold; Calculate the updated clock error:

[0017] Through the above three steps, the current is calculated by iterative calculation, which is used to calibrate the clock error of the digital signal processed by the reconstruction filter H.

[0018] According to a preferred embodiment, the frequency response of the reconstruction filter H is:

[0019] wherein is the angular frequency, is the clock error, is the sampling period.

[0020] According to a preferred embodiment, the balun circuit uses JBL2012-2-06 / 28 wideband balun chip, and the frequency range is from 5MHz to 6000MHz; The ADC chip in the high-speed AD sampling unit uses B9361NY, and the sampled signal is sent to the ZYNQ-PL logic unit through JESD204B, The data processing part is composed of ZYNQ-PL logic unit and ZYNQ-PS algorithm processing unit, and uses FMQL architecture processor JFMQL100T900-N as the control chip.

[0021] The foregoing main scheme of the application and each further selected scheme thereof can be freely combined to form multiple schemes, all of which are the schemes that can be adopted and claimed by the application. Those skilled in the art can understand that there are multiple combinations according to the prior art and common knowledge after understanding the schemes of the application, all of which are the technical schemes claimed by the application, and are not listed here.

[0022] The beneficial effects of the application are as follows: The advantages of the dynamic reconfigurable signal processing platform based on the ZYNQ architecture of the application are as follows: 1) resource saving: the functional waveforms can be dynamically reconfigured in real time in the dynamic area, multiple functional waveforms are reconfigured in time sharing on the same chip, and it is suitable for resource limited scenarios; 2) real-time and response speed is improved: the reconfiguration time is usually in microseconds or milliseconds, which meets the demand of the integrated radio frequency system for fast switching of tasks, and when a function is reconfigured, other functions can continue to work normally without being affected; 3) dynamic upgrade and power consumption reduction: the FPGA part of logic can be updated or switched without shutdown, supporting online upgrade of the system. Power consumption optimization, according to the task demand, the required functional modules can be activated, the idle logic is closed, and the invalid power consumption is reduced.

[0023] The dynamic reconfigurable signal processing platform based on the ZYNQ architecture improves the reliability and robustness of the integrated radio frequency system task, reduces the power consumption and volume of the system, and meets the demand of modern aircraft for fast response. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a structural schematic diagram of the dynamic reconfigurable signal processing platform of the application; Figure 2 is an AD sampling algorithm block diagram of the application; Figure 3 is a hardware architecture schematic diagram of the signal processing platform of the application; Figure 4 is a signal processing platform software initialization flowchart of the application; Figure 5 is an SCA software architecture of the application; Figure 6 is a dynamic area function distribution schematic diagram of the ZYNQ chip of the application; Figure 7 is a functional reconfiguration strategy flowchart of the application. DETAILED DESCRIPTION

[0025] Following make the specific concrete example explain the implementation of the present application, the person skilled in the art can easily understand the other advantages and efficacy of the present application from the disclosure of the present application. The present application can also be implemented or applied by another different specific implementation, and the details in the specification can be variously modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0026] Need to be explained, in order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme in the embodiments of the present application is described clearly and completely, obviously, the described embodiments are a part of the embodiments of the present application, rather than all the embodiments.

[0027] Reference Figure 1 As shown in the application, a dynamic reconfigurable signal processing platform based on ZYNQ architecture is disclosed, which comprises a channel preprocessing unit, a high-speed AD sampling unit, a ZYNQ-PL logic unit and a ZYNQ-PS algorithm processing unit.

[0028] Wherein, the radio frequency signal (frequency range 30Mhz ~ 6Ghz) is fed into the channel preprocessing unit from the antenna end, adopts the balun circuit and the filter set, carries out preselected filtering, amplification and conditioning to the radio frequency signal, extracts the signal and sends it into the high-speed AD sampling unit.

[0029] The high-speed AD acquisition unit can realize the sampling frequency of 6Gbps at most, the sampling accuracy is 12 bits, converts the analog signal into digital signal, and transmits it to the ZYNQ-PL logic unit through the JESD204B bus, utilizes the characteristics of JESD204B bus delay fixing, phase consistency, ensures the phase consistency and data synchronization of three AD signals to the rear end.

[0030] The information processing part mainly contains ZYNQ-PL logic unit and ZYNQ-PS algorithm processing unit. Among them, the ZYNQ-PL logic unit is composed of a static area and three dynamic areas, mainly realizes the logic part of the function waveform, including AD data group framing, digital, data exchange and external radio frequency component control, completes the reconstruction and loading of the function waveform; ZYNQ-PS algorithm processing unit completes the algorithm processing, realizes the modulation, demodulation of the function waveform, and realizes the function algorithm.

[0031] Preferably, reference Figure 2 As shown in the application, the high-speed AD sampling unit adopts time interleaving algorithm, completes the platform sampling through the number of dynamic knife stacking; and adopts adaptive clock mismatch calibration algorithm, carries out error calibration to the multi-channel AD sampling data.

[0032] Further, an adaptive clock mismatch calibration algorithm is adopted to perform error calibration on the multi-channel AD sampling data, including: X(t) is an analog input signal to be sampled, which is sampled by two ADC channels ADC1 and ADC2, and the AD sampling output digital signal is , wherein the digital signal is the reference input of the LMS algorithm module, and the output after calculation by the LMS algorithm module is The clock error is calculated with respect to , and the corresponding error and the digital signal are sent into the reconstruction filter H to calculate the calibrated digital signal , which is then time-division multiplexed by the digital multiplexer MUX to output the final AD sampling signal X(K) after calibration and synthesis.

[0033] Preferably, the LMS algorithm module adopts the following improved LMS algorithm to calculate the clock error , including: Step 1: Calculate the channel sampling clock. First, initialize the target function clock error , calculate the sampling clock according to the formula , wherein is the current clock error, and j is the iteration number of the algorithm; Step 2: Calculate the target function and gradient. Define the target function, and the target function V is defined as:

[0034] , wherein is the signal processed by the reconstruction filter H, is the reference signal; Calculate the gradient value of the target function:

[0035] Step 3: Update the clock error. Adaptively adjust the learning rate according to the modulus of the gradient to dynamically adjust the learning rate:

[0036] , wherein is a preset threshold; Calculate the updated clock error:

[0037] Through the above three steps, the current is calculated by iterative calculation, which is used to calibrate the clock error of the digital signal of the later-stage reconstruction filter H.

[0038] Preferably, the frequency response of the reconstruction filter H is: where is the angular frequency, is the clock error, is the sampling period.

[0039] Referring to Figure 3 shown, a signal processing platform hardware design is disclosed. After the radio frequency signal is processed by the balun circuit, it enters the ADC sampling circuit for AD conversion. The converted digital signal is transmitted to the FPGA minimum system through the JESD204B bus. The FPGA minimum system is externally connected with a 4Gbit DDR3 memory and a 1Gbit BPI FLASH unit to realize FPGA program loading and data storage. The FPGA minimum system interacts with the DSP minimum system through the EMIF bus. The DSP minimum system is externally connected with a DDR3 memory and a NOR FLASH memory to realize function algorithm processing and data caching. The management unit circuit realizes board card health state management, voltage monitoring, temperature monitoring, and power consumption management. The memory management circuit realizes board card memory resource control and distribution management. The management unit circuit interacts with the DSP minimum system through the SPI bus. The power management circuit realizes the conversion of the first power supply (voltage +12VDC) to the second power supply (voltage +5V / 3.3V / 2.5V / 1.8V / 1.0V / 0.75VDC), controls the power-on sequence of each second power supply, and realizes the frequency division and frequency multiplication of the input clock to the frequency required by the system.

[0040] Since the AD input frequency range is required to be wide (30MHz-6GHz), a super low insertion loss balun circuit is selected in the hardware design to pre-process, match and filter the input single-ended radio frequency signal. The JBL2012-2-06 / 28 wideband balun chip of Shenzhen Zhenhuafu Company is selected, and the frequency range from 5MHz to 6000MHz meets the design requirements.

[0041] The pre-processed radio frequency signal is sent to an ADC sampling circuit for AD conversion. The ADC chip is designed using B9361NYB from Beijing Microelectronics Technology Institute. B9361NYB is a high-performance, high-integration wideband programmable radio frequency converter for comprehensive radio frequency systems, with a working frequency of 70 MHz-6 GHz, supporting a channel bandwidth of less than 200 kHz to 56 MHz, and integrating a 12-bit DAC and an ADC wideband radio frequency 2x2 transceiver, which can realize zero intermediate frequency sampling of radio frequency signals. The sampled signal is sent to the ZYNQ-PL logic unit through JESD204B, the high-speed serial bus output parameter of which matches the rate of the receiving channel, and the sampling data synchronization design of three AD devices is provided through SYSREF and SYNCB input management control.

[0042] The data processing part is composed of ZYNQ-PL logic unit and ZYNQ-PS algorithm processing unit, and uses JFMQL100T900-N of FMQL architecture of Fudan Micro Company as the core control chip. The internal structure of JFMQL100T900-N chip is divided into programmable logic ZYNQ-PL and processor ZYNQ-PS two parts. The ZYNQ-PL part is a programmable logic processing unit, which provides 350K logic resources, 19.2Mb block RAM, 900 DSP processor resources, and 16 pairs of GTX high-speed interfaces. The PL and PS communicate through AXI bus, and according to the standard AXI protocol, the data bit width supports 32bit or 64bit, and the main port capacity is: 8 read, 8 write. ZYNQ-PS contains four-core high-performance ARM53 processor, each processor has a high-performance, low-power core, single-core computing power reaches 1.9DMIPS / MHz, independently has 32K L1 level Cache and 256K L2 level Cache, and the PS part can be externally connected with DDR3, SPI-FLASH and other memories to complete the solidification and loading of programs.

[0043] The ZYNQ-PL part mainly completes AD data framing, digital preprocessing and radio frequency front-end control functions, and completes JESD204B interface adaptation and data buffering with B9361NYB; the ZYNQ-PS processor end completes the processing of functional waveform algorithms, including control function, navigation function method, approach guide and other algorithm processing functions.

[0044] The power supply circuit completes the conversion of the primary power 28VDC to the secondary power supply, and uses an isolation DC-DC (DPX30-28T5-6V5-12FM of Beijing Xinle Energy Technology Co., Ltd.) to complete the functions of voltage conversion, surge suppression, overvoltage / overcurrent protection, etc. The phase-locked loop circuit completes the conversion and distribution of the board-level clock, uses the GM4526CN of Chengdu Zhenxin Technology, converts and distributes the 100MHz clock as the input signal, outputs the sampling clock and the synchronous sampling clock of B9361NYB to provide the clock source for the JESD204B special chip, and simultaneously outputs 156.25MHz, 100MHz, 66MHz and 33MHz to provide the clock source for the ZYNQ processor of the signal processing platform.

[0045] The management unit circuit selects the JFM7K325T8-AS chip of Fudan Micro Company, communicates with the DSP through the SPI interface, and completes the functions of the health state management of the board card, the multi-version program switching control and the like.

[0046] The software initialization process of the signal processing platform is as shown in Figure 4 After the module is powered on, the initialization of the underlying hardware is first completed, the management unit program is run after the initialization is completed, the management unit program controls each group of power supplies to start according to the preset power-on sequence, in order to ensure the normal operation of the platform, the FPGA minimum system circuit is first started, and then the DSP minimum system circuit and the AD circuit are started after the FPGA startup is completed, the initial default AD sampling rate and the DSP working mode configuration are completed. After the module startup is completed, the management unit controls the FPGA and the DSP to load the default version, after the program loading is successful, the management unit controls the initialization of the clock phase-locked loop chip, outputs the required sampling rate clock, the initialization of the AD chip, configures the default sampling rate and precision, the FPGA register and DSP register initialization, including the initialization operation of the external interface, the DDR controller, the GTH interface, the SRIO interface and the JESE204B interface. After all the chips are initialized, the power-on BIT self-check is automatically executed, the self-check result is reported, and thus the module initialization startup is completed.

[0047] The signal processing platform uses the SCA software architecture, constructs the micro-standard software system through the hierarchical method, realizes the decoupling of software and hardware through the open architecture of SCA, realizes the abstraction and encapsulation of domain knowledge through the domain model and framework technology, provides a large number of reusable software components, provides the matching tool software, establishes the system model and uses the model-driven method to accelerate the development, configuration and deployment of the software platform, constitutes the standardized platform container environment of waveform operation, promotes the portability and reusability of the waveform components, and the software architecture is as shown in Figure 5 .

[0048] The SCA software architecture is composed of the following parts: a) hardware platform: composed of 3 ZYNQ computing nodes, storage nodes, system management nodes and IO control nodes, and data exchange between nodes is realized through high-speed interconnection buses (such as RIO / PCIE / AS5643 / Ethernet) and the like; b) platform basic software: providing a basic running environment for software, including an embedded operating system and hardware drivers, realizing hardware access and online updating and the like; c) SCA general technology software: the core software of the SCA architecture, realizing decoupling of upper-layer software and lower-layer hardware through MHAL communication middleware and MOCB communication middleware, realizing waveform construction and deconstruction on the platform through core control software, and realizing network topology establishment, logical relationship management and the like through network configuration software; d) platform management software: realizing framework running of health management, resource scheduling, reconstruction management and the like through business framework software, and providing running basis for AD configuration, clock configuration, platform control management services, platform BIT management and the like; e) waveform application software: providing a running carrier for multiple waveform application software, providing a control interface of a radio frequency front end, a functional algorithm running platform, and realizing functions of various sensors of the integrated radio frequency system.

[0049] The application subzone dynamic loading technology is a technology of realizing time-sharing loading of different functions of a single chip by re-dividing on-chip resources of a ZYNQ chip, and differentiating several small areas for layout and wiring of specific programs. The logic in the reconstruction area is dynamically reconfigured locally to meet the needs of multi-function and large-scale applications. Figure 6 As shown in the figure, the ZYNQ chip is divided into a logic unit ZYNQ-PL part and a processor ZYNQ-PS part, the ZYNQ-PL part is arranged with a dynamic area 1, a dynamic area 2 and a static area, wherein the static area is a fixed basic resource, including bottom interface, clock configuration, system reset and the like, the program in the static area remains unchanged during function reconstruction, and different function programs are dynamically loaded and reconstructed on the dynamic area 1 and the dynamic area 2, the ZYNQ-PS part fully utilizes the multi-task processing performance of the ARM53 dual-core processor, and runs the function C control (default function) and the ATC function on ARM1, and runs the L control (default function) and the Ka satellite communication function on ARM2, according to the needs of the function program in different task stages of the aircraft, the logic resource corresponding to the different function programs is dynamically loaded in the dynamic area of the ZYNQ-PL part, if the dynamic area 1 is reconfigured from the default function C control to the ATC function, the L control function of the dynamic area 2 is not affected during the reconstruction, and vice versa, the advantage of this is that the control function related to the safety of the aircraft is not affected during the dynamic area reconstruction, and the stability and reliability of the integrated radio frequency system are increased.

[0050] The dynamic loading of the partition allows the reconfiguration of the ZYNQ-PL specified area by using a new program, and allows the current function to continue to run in the remaining space of the device, so that the reconfiguration of the function of the dynamic area 1 does not affect the normal running of the function of the dynamic area 2, ensures the continuity of the key function of the system, and further expands the inherent flexibility of the ZYNQ-PL.

[0051] The dynamic reconfiguration refers to that the resources are time-division multiplexed by different function waveforms under the system control scheduling when the aircraft performs different flight tasks. The reconfiguration design is divided into two types: task reconfiguration and fault reconfiguration. The task reconfiguration refers to that different flight stages, such as take-off, cruising and approach landing, the system has different requirements for general signal processing function waveforms, and different functions are reconfigured; the fault reconfiguration refers to that when a high-priority function fails, the system reconfigures the high-priority function waveform by using the existing resources, so as to ensure the execution of the key task in flight.

[0052] The dynamic reconfiguration flow is shown in FIG. 7. After power-on, the initialization operation is first completed, the board-level management program is run to reset the hardware parts such as the ZYNQ unit, the phase-locked loop unit and the storage unit, then the ZYNQ-PS algorithm processing unit waits whether the reconfiguration instruction is received, if not, it continues to wait, after receiving the reconfiguration instruction, the reconfiguration of the ZYNQ-PL program is started, the Golden program of the Flash sector is first run, the Golden program is started to boot and load the reconfigured function program, then it is judged whether the ZYNQ-PL loading completion flag is 1, if not, the function program is reloaded, if it is 1, the next step of loading the ZYNQ-PS program is started. The ZYNQ-PS executes the internal BootLoader program, boots the function program stored in the external FLASH to the PS end for loading, then it is judged whether the PS program loading completion flag is 1, if the flag is not 1, the function program is reloaded, if the flag is 1, it indicates that the loading is completed, the program jumps to the PS program entry to start the program running, and jumps to the function waveform entry address to start executing the newly loaded waveform program, and the signal processing channel completes the function waveform reconfiguration.

[0053] In view of the real-time and uninterrupted requirement of the important function reconfiguration of the integrated radio frequency system, the application provides a dynamic reconfigurable signal processing platform based on a ZYNQ platform. By using the reconfigurable technology of the ZYNQ-PL part, time-division multiplexing is performed in the limited on-chip resources, the reconfiguration and real-time refreshing of multiple function waveforms at the chip level are realized, the unification of the resource sharing and the flexibility of the function reconfiguration of the integrated radio frequency system is realized. The platform can be applied to the fields of aerospace, ship, weapon and the like.

[0054] The above only describes preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A dynamic reconfigurable signal processing platform based on ZYNQ architecture, characterized in that, The dynamic reconfigurable signal processing platform comprises a channel preprocessing unit, a high-speed AD sampling unit, a ZYNQ-PL logic unit and a ZYNQ-PS algorithm processing unit. Wherein, after the radio frequency signal is fed from the antenna end, it enters the channel preprocessing unit, adopts a balun circuit and a filter set to preselect, amplify and condition the radio frequency signal, and extracts the signal to the high-speed AD sampling unit. The high-speed AD sampling unit converts the accepted analog signal into a digital signal and transmits the digital signal to the ZYNQ-PL logic unit through a JESD204B bus, and the ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit are connected through an AXI bus. The ZYNQ-PL logic unit is composed of a static area and three dynamic areas, realizes the logic part of the functional waveform, includes AD data framing, digital data exchange and external radio component control, and completes the reconstruction and loading of the functional waveform; the ZYNQ-PS algorithm processing unit completes algorithm processing and realizes the modulation, demodulation and functional algorithm of the functional waveform.

2. The dynamically reconfigurable signal processing platform based on ZYNQ architecture as claimed in claim 1, wherein, The ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit are realized by a ZYNQ chip, which is divided into a ZYNQ-PL logic unit part and a ZYNQ-PS algorithm processing part.

3. The dynamically reconfigurable signal processing platform based on ZYNQ architecture as claimed in claim 2, wherein, The ZYNQ-PL logic unit part is arranged with a dynamic area 1, a dynamic area 2 and a static area, The static area is a fixed basic resource, including a bottom interface, a clock configuration, a system reset resource, the static area program remains unchanged during the functional reconstruction, and different functional programs are dynamically loaded and reconstructed on the dynamic area 1 and the dynamic area 2.

4. The dynamically reconfigurable signal processing platform based on ZYNQ architecture as claimed in claim 3, wherein, The ZYNQ-PS algorithm processing unit part includes an ARM1 and an ARM2, The ZYNQ-PS algorithm processing unit utilizes the multi-task processing performance of the ARM53 dual-core processor, realizes the C control function and the ATC function on the ARM1, realizes the L control function and the Ka satellite communication function on the ARM2, and dynamically loads the logic resource corresponding to the different functional programs in the dynamic area of the ZYNQ-PL logic unit part according to the requirement of the functional program in different task stages of the aircraft, If the dynamic area 1 is reconstructed, it is reconstructed from the default C control to the ATC, and the L control function of the dynamic area 2 is not affected during the reconstruction, and if the dynamic area 2 is reconstructed, it is reconstructed from the default L control to the Ka satellite communication.

5. The dynamically reconfigurable signal processing platform based on ZYNQ architecture as claimed in claim 4, wherein, The functional reconstruction process of the ZYNQ chip comprises: After power-on, the initialization operation is first completed, the board-level management program is run to reset the hardware parts such as the ZYNQ unit, the phase-locked loop unit and the storage unit, Then the ZYNQ-PS algorithm processing unit waits to receive the reconstruction instruction, if no instruction is received, it continues to wait, after receiving the reconstruction instruction, the ZYNQ-PS algorithm processing unit program is started to be reconstructed, the Golden program of the Flash sector is first run, the Golden program is started to load the reconstructed functional program, then it is judged whether the ZYNQ-PL logic unit loading completion flag is 1, if it is not 1, the functional program is reloaded, if it is 1, the next step of loading the ZYNQ-PS program is started. The ZYNQ-PS algorithm processing unit executes an internal BootLoader program, guides a function program stored in an external FLASH memory to be loaded to a PS end, and then judges whether a PS program loading completion identifier is 1. If the identifier is not 1, the function program is reloaded. If the identifier is 1, it is indicated that the loading is completed, the program jumps to a PS program entrance to start program running, and jumps to a function waveform entrance address to start execution of a newly loaded waveform program. A signal processing channel completes function waveform reconstruction.

6. The dynamically reconfigurable signal processing platform based on ZYNQ architecture as claimed in claim 1 wherein, The high-speed AD sampling unit adopts a time interleaving algorithm to complete platform sampling through stacking of a number of moving knives, and adopts an adaptive clock mismatch calibration algorithm to calibrate errors of multi-channel AD sampling data.

7. The dynamically reconfigurable signal processing platform based on ZYNQ architecture as claimed in claim 6, wherein, The adaptive clock mismatch calibration algorithm includes the following steps: X(t) is the analog input signal to be sampled, which is sampled by two ADC channels ADC1 and ADC2 respectively, and the digital signal is outputted after AD sampling , wherein the digital signal is the reference input of the LMS algorithm module, and the output after calculation by the LMS algorithm module is , wherein the clock error is the clock error , and the corresponding error and the digital signal are sent into the reconstruction filter H together to calculate the calibrated digital signal , and then time division multiplexing is performed by the digital multiplexer MUX to output the final AD sampling signal X(K) after calibration and synthesis.

8. The dynamically reconfigurable signal processing platform based on ZYNQ architecture as claimed in claim 7, wherein, The LMS algorithm module adopts the following improved LMS algorithm to correct the clock error The calculation includes: First step: Calculate the channel sampling clock: First, initialize the objective function clock error , according to the formula Calculate the sampling clock , where is the current clock error, and j is the number of algorithm iterations; Second step: calculating a target function and a gradient, defining the target function, and defining the target function V as: wherein, is a signal processed by a reconfigurable filter H, is a reference signal; Calculating the gradient, calculating the gradient value of the target function: Third step: updating the clock error, adaptively adjusting the learning rate, and dynamically adjusting the learning rate according to the modulus of the gradient: wherein, is a preset threshold value; Calculating the updated clock error: Through the above three steps, the current , for the latter stage reconstruction filter H calibration digital signal clock error.

9. The dynamically reconfigurable signal processing platform based on ZYNQ architecture as claimed in claim 7, wherein, The frequency response of the reconstructed filter H is: wherein is the angular frequency, is the clock error, is the sampling period.

10. The dynamically reconfigurable signal processing platform based on ZYNQ architecture as claimed in claim 1, wherein, The balun circuit adopts a JBL2012-2-06 / 28 wideband balun chip, and the frequency range is from 5 MHz to 6000 MHz; In the high-speed AD sampling unit, the ADC chip adopts B9361NY, and the sampled signal is sent to the ZYNQ-PL logic unit through JESD204B, The data processing part is composed of the ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit, and adopts a FMQL architecture processor JFMQL100T900-N as a control chip.

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