Semiconductor device and method for manufacturing semiconductor device

Abstract

The semiconductor device of the present invention comprises: a substrate; a plurality of electrodes arranged on the substrate; an insulator provided with one or more openings for exposing at least one of the plurality of electrodes on the substrate and covering at least a portion of the plurality of electrodes; and a semiconductor chip arranged between the coating portion and one or more exposed portions exposed from the one or more openings on the substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] For example, as a semiconductor device, a field-effect transistor and a sensor using the field-effect transistor are disclosed in Patent Document 1. In the field-effect transistor described in Patent Document 1, particles composed of a non-metallic material are used as growth nuclei, and a single-layer carbon nanotube thin film is grown by chemical vapor deposition to form the channel of the field-effect transistor.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2016 / 021693 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] In recent years, there has been a demand for improved performance of semiconductor devices.

[0008] An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the performance of the device.

[0009] Means used to solve problems

[0010] A semiconductor device according to one embodiment of the present invention includes:

[0011] substrate;

[0012] a plurality of electrodes disposed on the substrate;

[0013] an insulator having one or more openings for exposing at least one of the plurality of electrodes on the substrate and covering at least a portion of the plurality of electrodes; and

[0014] A semiconductor chip is disposed between the insulator and one or more exposed portions exposed from the one or more openings on the substrate.

[0015] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes:

[0016] a step of preparing a substrate provided with a plurality of electrodes;

[0017] forming an insulator having one or more openings for exposing at least one of the plurality of electrodes on the substrate and covering at least a portion of the plurality of electrodes; and

[0018] A step of forming a semiconductor chip on the insulator and the one or more exposed portions on the substrate exposed from the one or more openings.

[0019] Effects of the Invention

[0020] According to the present invention, a semiconductor device and a method for manufacturing the semiconductor device that can improve performance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic perspective view showing an example of the main structure of the semiconductor device according to the first embodiment of the present invention.

[0022] Figure 2 This is a schematic plan view showing an example of the main structure of the semiconductor device according to the first embodiment of the present invention.

[0023] Figure 3 Cut along line AA Figure 2 A schematic cross-sectional view of a semiconductor device is provided.

[0024] Figure 4 This is a schematic perspective view of an example of a sensor according to Embodiment 1 of the present invention.

[0025] Figure 5 yes Figure 4 Schematic cross-sectional view of the sensor.

[0026] Figure 6 This is a flowchart of an example of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0027] Figure 7A This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0028] Figure 7B This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0029] Figure 7C This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0030] Figure 7D This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0031] Figure 7E This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0032] Figure 8 This is a schematic plan view showing an example of a substrate on which a plurality of electrodes are arranged.

[0033] Figure 9 It will Figure 8 A schematic enlarged view of a portion of the substrate.

[0034] Figure 10 This is a schematic plan view showing an example of a substrate on which an insulator is arranged.

[0035] Figure 11 It will Figure 10 An enlarged schematic diagram of the exposed portion of the substrate.

[0036] Figure 12 This is a diagram for explaining an example of a process for forming a semiconductor wafer.

[0037] Figure 13A This is a diagram for explaining another example of the process of forming a semiconductor wafer.

[0038] Figure 13B This is a diagram for explaining another example of the process of forming a semiconductor wafer.

[0039] Figure 13C This is a diagram for explaining another example of the process of forming a semiconductor wafer.

[0040] Figure 14 This is a schematic perspective view of a semiconductor device according to a modified example of the first embodiment of the present invention.

[0041] Figure 15A This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0042] Figure 15B This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0043] Figure 15C This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0044] Figure 15D This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0045] Figure 15E This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0046] Figure 15F This is a schematic diagram showing an example of the process of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0047] Figure 16AThis is a schematic diagram showing an example of the steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0048] Figure 16B This is a schematic diagram showing an example of the steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0049] Figure 16C This is a schematic diagram showing an example of the steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0050] Figure 16D This is a schematic diagram showing an example of the steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0051] Figure 16E This is a schematic diagram showing an example of the steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0052] Figure 16F This is a schematic diagram showing an example of the steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0053] Figure 16G This is a schematic diagram showing an example of the steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0054] Figure 17 This is a schematic diagram showing an example of the main structure of a semiconductor device according to a fourth embodiment of the present invention.

[0055] Figure 18 This is a schematic plan view showing an example of the main structure of a semiconductor device according to a fourth embodiment of the present invention.

[0056] Figure 19 This is a schematic enlarged view showing a portion of the exposed portion.

[0057] Figure 20 This is a flowchart of an example of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

[0058] Figure 21A This is a schematic diagram showing an example of the process of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

[0059] Figure 21B This is a schematic diagram showing an example of the process of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

[0060] Figure 21C This is a schematic diagram showing an example of the process of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

[0061] Figure 21DThis is a schematic diagram showing an example of the process of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

[0062] Figure 22 This is a schematic plan view showing an example of the main structure of a semiconductor device according to a modified example of the fourth embodiment of the present invention.

[0063] Figure 23 This is a schematic diagram showing an example of the main structure of a semiconductor device according to a fifth embodiment of the present invention.

[0064] Figure 24 This is a schematic plan view showing an example of a main structure of a semiconductor device according to a fifth embodiment of the present invention.

[0065] Figure 25 This is a schematic enlarged view showing a portion of the exposed portion.

[0066] Figure 26 This is a flowchart of an example of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[0067] Figure 27A This is a schematic diagram showing an example of operations in a process of forming a semiconductor wafer.

[0068] Figure 27B This is a schematic diagram showing an example of operations in a process of forming a semiconductor wafer.

[0069] Figure 27C This is a schematic diagram showing an example of operations in a process of forming a semiconductor wafer. DETAILED DESCRIPTION

[0070] (Process of completing the present invention)

[0071] In the manufacturing method of semiconductor devices such as field-effect transistors, multiple semiconductor chips are wired with electrodes on a substrate, and then an insulator is applied. The insulator is then removed by photolithography or the like to form a semiconductor channel.

[0072] There is also a method for forming a semiconductor channel using a resist. In this method, a resist film is formed at a location where the semiconductor channel is to be formed on a substrate, and then an insulator is applied. After the insulator is applied, the resist film is removed to form the semiconductor channel.

[0073] However, the above manufacturing method is difficult to improve the performance of semiconductor devices. When removing the insulator on the semiconductor wafer using photolithography or other methods, some of the insulator may remain on the surface of the semiconductor wafer. Furthermore, when using a resist, some of the resist may also remain on the surface of the semiconductor wafer. This can cause the surface of the semiconductor wafer to become contaminated by the insulator and resist, deteriorating the electrical properties of the semiconductor wafer.

[0074] When using semiconductor devices as biosensors for virus detection, multiple receptors that capture target molecules are placed on the semiconductor wafer. However, receptors cannot be placed on areas of the semiconductor wafer where insulators or resist remain. Consequently, target molecules cannot be captured in areas of the semiconductor wafer where receptors are not present. This makes it difficult to improve virus detection accuracy.

[0075] The present inventors have discovered a method for manufacturing a semiconductor device by coating a plurality of electrodes on a substrate with an insulator and then transferring a semiconductor wafer from the insulator, thereby completing the following invention.

[0076] A semiconductor device according to one embodiment of the present invention includes:

[0077] substrate;

[0078] a plurality of electrodes disposed on the substrate;

[0079] an insulator having one or more openings for exposing at least one of the plurality of electrodes on the substrate and covering at least a portion of the plurality of electrodes; and

[0080] A semiconductor chip is disposed between the insulator and one or more exposed portions exposed from the one or more openings on the substrate.

[0081] According to such a configuration, the performance of the device can be improved.

[0082] In the semiconductor device, the plurality of electrodes may include a first electrode and a second electrode disposed spaced apart from the first electrode.

[0083] At least one of a portion of the first electrode and a portion of the second electrode is located at the one or more exposed portions,

[0084] The semiconductor chip is connected to the first electrode and the second electrode.

[0085] According to such a structure, the performance of the device can be further improved.

[0086] A region of the first electrode including an end portion facing the second electrode and a region of the second electrode including an end portion facing the first electrode may be located in the exposed portion.

[0087] According to such a structure, the performance of the device can be further improved.

[0088] In the semiconductor device, the insulator may include a connecting insulating portion arranged across the first electrode and the second electrode.

[0089] The plurality of openings include a first opening that exposes a portion of the first electrode on the substrate, and a second opening that exposes a portion of the second electrode on the substrate.

[0090] The plurality of exposed portions include a first exposed portion exposed from the first opening on the substrate, and a second exposed portion exposed from the second opening.

[0091] The semiconductor piece is continuously arranged on the connecting insulating portion, the first exposed portion, and the second exposed portion.

[0092] According to such a structure, the performance of the device can be further improved.

[0093] In the plurality of exposed portions, gaps may be formed between a side wall of the insulator having the plurality of openings, the semiconductor chip, and the substrate.

[0094] With such a structure, stress applied to the semiconductor wafer can be alleviated, and device performance can be further improved.

[0095] The semiconductor wafer may also have:

[0096] A first semiconductor chip is disposed on the insulator; and

[0097] The second semiconductor chip is separated from the first semiconductor chip and is disposed on the exposed portion.

[0098] With such a structure, it is possible to cut off the electrical short circuit of the semiconductor chip.

[0099] In the semiconductor device, an end portion of the second semiconductor wafer may be bent in a thickness direction of the second semiconductor wafer.

[0100] According to such a structure, the second semiconductor wafer can be easily confirmed.

[0101] In the semiconductor device, the semiconductor sheet may be formed of any one of graphene, carbon nanotubes, organic semiconductors, MXENES, and transition metal dichalcogenide layered materials.

[0102] According to such a structure, the performance of the device can be further improved.

[0103] The semiconductor device may further include a plurality of receptors, which are arranged on the semiconductor chip and are used to capture target molecules.

[0104] With such a structure, target molecules can be captured.

[0105] The semiconductor device may further include a calculation unit that receives an electrical signal output from the semiconductor chip and calculates the amount of the target molecule based on the electrical signal.

[0106] With such a structure, the amount of the target molecule can be calculated.

[0107] In the semiconductor device, the semiconductor chip may be in close contact with the insulator and the one or more exposed portions by van der Waals forces.

[0108] According to such a structure, the semiconductor chip can be easily fixed.

[0109] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes:

[0110] a step of preparing a substrate provided with a plurality of electrodes;

[0111] forming an insulator having one or more openings for exposing at least one of the plurality of electrodes on the substrate and covering at least a portion of the plurality of electrodes; and

[0112] A step of forming a semiconductor chip on the insulator and the one or more exposed portions on the substrate exposed from the one or more openings.

[0113] With such a structure, a semiconductor device with improved device performance can be manufactured.

[0114] In the manufacturing method, the plurality of electrodes may include a first electrode and a second electrode disposed at a distance from the first electrode.

[0115] At least one of a portion of the first electrode and a portion of the second electrode is located at the one or more exposed portions,

[0116] The semiconductor sheet electrically connects the first electrode and the second electrode.

[0117] With such a structure, a semiconductor device with further improved device performance can be manufactured.

[0118] In the manufacturing method, a region of the first electrode including an end portion facing the second electrode and a region of the second electrode including an end portion facing the first electrode may be located in the exposed portion.

[0119] With such a structure, a semiconductor device with further improved device performance can be manufactured.

[0120] In the manufacturing method, the step of forming the insulator may include:

[0121] forming a connecting insulating portion arranged to straddle the first electrode and the second electrode; and

[0122] A first opening for exposing a portion of the first electrode on the substrate and a second opening for exposing a portion of the second electrode on the substrate are formed in the insulator.

[0123] The step of forming the semiconductor piece includes forming a semiconductor piece in which the first exposed portion where a part of the first electrode is exposed from the first opening and the second exposed portion where a part of the second electrode is exposed from the second opening are continuous with the connecting insulating portion.

[0124] With such a structure, a semiconductor device with further improved device performance can be manufactured.

[0125] In the manufacturing method, the step of forming the insulator may include forming an opening in the insulator to expose a portion of the first electrode and a portion of the second electrode on the substrate,

[0126] The step of forming the semiconductor piece includes separating the semiconductor piece into a first semiconductor piece arranged on the insulator and a second semiconductor piece arranged on an exposed portion of the substrate exposed from the opening.

[0127] With such a structure, it is possible to cut off the electrical short circuit of the semiconductor chip, and to manufacture a semiconductor device with further improved performance.

[0128] In the manufacturing method, in the separation, the semiconductor wafer may be cut along a step formed by the insulator and the substrate in the opening.

[0129] With such a structure, the semiconductor wafers can be easily separated.

[0130] Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings. In each drawing, each element is exaggerated for ease of description.

[0131] (Implementation Method 1)

[0132] [Overall structure]

[0133] Figure 1 This is a schematic perspective view showing an example of the main structure of a semiconductor device 1A according to the first embodiment of the present invention. Figure 2 This is a schematic plan view showing an example of the main structure of a semiconductor device 1A according to the first embodiment of the present invention. Figure 3 Cut along line AA Figure 2A schematic cross-sectional view of a semiconductor device 1A. Figure 2 and Figure 3 In the figure, the electrolyte 20 and the third electrode 21 are omitted. The X, Y, and Z directions in the figure represent the longitudinal, lateral, and height directions of the semiconductor device 1A, respectively.

[0134] like Figure 1-3 As shown, the semiconductor device 1A includes a substrate 11 , a plurality of electrodes 12 , an insulator 13 , and a semiconductor chip 14 .

[0135] In Embodiment 1, a semiconductor device 1A is described using a field-effect transistor as an example. In semiconductor device 1A, multiple electrodes 12 include a first electrode 12a and a second electrode 12b disposed on a substrate 11. First electrode 12a is a drain electrode, and second electrode 12b is a source electrode. A drain-source voltage Vds is applied between first electrode 12a and second electrode 12b. A semiconductor wafer 14 is disposed in an electrolyte 20. A third electrode 21 is disposed in the electrolyte 20. Third electrode 21 is a gate electrode to which a gate voltage Vg is applied.

[0136] Hereinafter, the detailed structure of the semiconductor device 1A will be described.

[0137] <Substrate>

[0138] The substrate 11 is formed of an insulating material. For example, the substrate 11 is formed of an insulating material such as SiO 2 . The substrate 11 has a plate shape. A wiring pattern including a plurality of electrodes 12 is formed on the substrate 11 .

[0139] Multiple electrodes

[0140] Multiple electrodes 12 are arranged on substrate 11. Multiple electrodes 12 are arranged at intervals. Specifically, multiple electrodes 12 include first electrodes 12a arranged on substrate 11 and second electrodes 12b arranged at intervals from first electrodes 12a. Furthermore, first electrodes 12a and second electrodes 12b are arranged opposite each other on substrate 11.

[0141] The plurality of electrodes 12 have a plate shape and are formed of a conductive material. For example, the plurality of electrodes 12 are formed of a conductive material such as Cu, Ti, Ni, Cr, Au, or Pt.

[0142] <Insulator>

[0143] The insulator 13 covers at least a portion of the plurality of electrodes 12 on the substrate 11. The insulator 13 is formed of an insulating material such as, for example, ceramics such as SiO2, Si3N4, Al2O3, or HfO2; resin materials such as epoxy resin, polyimide resin, silicone resin, fluorine-based resin, or photoresist; or two-dimensional insulating materials such as boron nitride. In the first embodiment, since the pattern is formed by photolithography, the material forming the insulator 13 is preferably a photosensitive material.

[0144] The insulator 13 is provided to cover a portion of the first electrode 12a and a portion of the second electrode 12b, while exposing a portion of the substrate 11, a portion of the first electrode 12a, and a portion of the second electrode 12b. The insulator 13 is provided with an opening 16 that exposes at least one of the plurality of electrodes 12 on the substrate 11.

[0145] like Figure 2 As shown, when the semiconductor device 1A is viewed from the height direction (Z direction), the opening 16 is provided in a rectangular shape.

[0146] The opening 16 exposes a portion of the substrate 11. Thus, an exposed portion 17, which is a portion of the substrate 11 exposed from the opening 16, is formed.

[0147] In the first embodiment, the region 15 a including the end portion facing the second electrode 12 b in the first electrode 12 a and the region 15 b including the end portion facing the first electrode 12 a in the second electrode 12 b are located in the exposed portion 17 .

[0148] Semiconductor wafers

[0149] Semiconductor sheet 14 is a sheet formed of a semiconductor. Made of a conductive material, semiconductor sheet 14 converts the attachment of molecules into an electrical signal (e.g., a current signal) and outputs it. When molecules attach, the electrical properties of semiconductor sheet 14 (e.g., current-voltage characteristics) change. For example, semiconductor sheet 14 can be formed from any of graphene, carbon nanotubes, organic semiconductors, MXENES, and transition metal dichalcogenide layered materials. In Embodiment 1, semiconductor sheet 14 is formed from graphene. Graphene has a higher carrier mobility than other semiconductor materials. As a result, the amount of current modulated by the same attached molecules can be increased compared to other semiconductor materials.

[0150] The thickness of the semiconductor wafer 14 is, for example, not less than 0.3 nm and not more than 300 nm.

[0151] Semiconductor chip 14 is disposed between insulator 13 and exposed portion 17 exposed from opening 16 on substrate 11. Specifically, semiconductor chip 14 is disposed on the upper surface of insulator 13. The upper surface of insulator 13 is the surface opposite to the surface in contact with substrate 11 and multiple electrodes 12 in the height direction (Z direction) of semiconductor device 1A. Semiconductor chip 14 also covers region 15a of first electrode 12a located in exposed portion 17, including the end portion facing second electrode 12b, and region 15b of second electrode 12b, including the end portion facing first electrode 12a.

[0152] In the first embodiment, semiconductor sheet 14 is continuously disposed on insulator 13 and exposed portion 17. Specifically, semiconductor sheet 14 is continuously disposed on the top surface of insulator 13, the sidewalls 13a of the insulator, and exposed portion 17. Here, "continuously disposed" means that semiconductor sheet 14 is disposed in a continuous state. In other words, a single semiconductor sheet 14 covers insulator 13 and exposed portion 17.

[0153] The semiconductor chip 14 is in close contact with the insulator 13 and the exposed portion 17 by van der Waals force.

[0154] The semiconductor chip 14 is connected to a portion of the first electrode 12a and the second electrode 12b in the exposed portion 17. That is, the semiconductor chip 14 is electrically connected to the first electrode 12a and the second electrode 12b. In this way, the semiconductor chip 14 can function as a semiconductor channel.

[0155] Alternatively, a PMMA (Polymethyl methacrylate) protective film may be provided on the surface of the semiconductor wafer 14 .

[0156] Next, use Figure 4 and Figure 5 An example in which the semiconductor device 1A is used as a sensor will be described. Figure 4 This is a schematic perspective view of an example of the sensor 2 according to the first embodiment of the present invention. Figure 5 yes Figure 4 A schematic cross-sectional view of the sensor 2. It should be noted that, Figure 4 and Figure 5 The sensor 2 shown is a biosensor for detecting target molecules 50 such as viruses.

[0157] like Figure 4 and Figure 5 As shown, the sensor 2 includes a plurality of receptors 31 and a computing unit 32. The remaining structure of the sensor 2 is the same as that of the semiconductor device 1A.

[0158] Multiple receptors

[0159] The plurality of receptors 31 are disposed on the semiconductor chip 14 to capture the target molecules 50. The plurality of receptors 31 are disposed on the semiconductor chip 14 disposed between the insulator 13 and the exposed portion 17. The plurality of receptors 31 are disposed in the electrolyte 20.

[0160] The plurality of receptors 31 capture target molecules 50 such as viruses that are detection targets. The plurality of receptors 31 capture target molecules 50 that are present in the electrolyte 20 .

[0161] <Calculation unit>

[0162] The calculation unit 32 receives the electrical signal output from the semiconductor chip 14 and calculates the amount of the target molecule 50 based on the electrical signal. The calculation unit 32 detects the target molecule 50 quantitatively based on the electrical signal.

[0163] The calculation unit 32 is connected to the first electrode 12a, the second electrode 12b, and the third electrode 21. Here, the first electrode 12a is a drain electrode, and the second electrode 12b is a source electrode. The calculation unit 32 controls the drain-source voltage Vds applied between the first electrode 12a and the second electrode 12b, and the gate voltage Vg applied to the third electrode 21.

[0164] When the target molecule 50 is captured by the receptor 31, the electrical properties (e.g., current-voltage properties) of the semiconductor chip 14 change according to the surface charge of the target molecule 50. Due to the change in the electrical properties of the semiconductor chip 14, the electrical signal (e.g., current signal) output from the semiconductor chip 14 also changes.

[0165] The calculation unit 32 receives the electrical signal output from the semiconductor chip 14 and calculates the amount of the target molecule 50 based on the electrical signal. It is known that the amount of the target molecule 50 is correlated with the amount of change in the electrical signal. The calculation unit 32 calculates the amount of the target molecule 50 based on the amount of change in the electrical signal. This allows the presence of the target molecule 50 to be determined and / or its concentration to be calculated.

[0166] The computing unit 32 can be implemented by semiconductor elements, etc. For example, the computing unit 32 can be composed of a microcomputer, a CPU, an MPU, a GPU, a DSP, an FPGA, an ASIC, a discrete semiconductor, or an LSI. The functions of the computing unit 32 can be implemented solely by hardware or by a combination of hardware and software. The computing unit 32 performs predetermined functions by reading data and programs stored in a storage unit (not shown) within the computing unit 32 and performing various calculations. The storage unit can be implemented by a hard disk drive (HDD), an SSD, RAM, DRAM, a ferroelectric memory, a flash memory, a magnetic disk, or a combination thereof.

[0167] [Manufacturing method]

[0168] An example of a method for manufacturing the semiconductor device 1A will be described. Figure 6This is a flowchart of an example of a method for manufacturing the semiconductor device 1A according to the first embodiment of the present invention. Figures 7A to 7E This is a schematic diagram showing an example of the steps of the method for manufacturing the semiconductor device 1A according to the first embodiment of the present invention. Note that the steps described below are executed by a manufacturing apparatus.

[0169] like Figure 6 As shown, in step ST1, a substrate 11 having a plurality of electrodes 12 is prepared. Figure 7A As shown, in step ST1, a substrate 11 provided with a first electrode 12a and a second electrode 12b is prepared. For example, step ST1 is performed by a metal film forming apparatus represented by a sputtering apparatus or an EB (Electron Beam) vapor deposition apparatus included in a manufacturing apparatus.

[0170] Figure 8 It is a schematic plan view showing an example of a substrate 11 on which a plurality of electrodes 12 are arranged. Figure 9 It will Figure 8 A schematic enlarged view of a portion of the substrate 11 is enlarged. Figure 9 It will Figure 8 The enlarged summary diagram of the Z1 part of Figure 8 and Figure 9 As shown, a wiring pattern having a plurality of electrodes 12 is provided on a substrate 11. For example, the wiring pattern can be formed on the substrate 11 by photolithography.

[0171] Among the multiple electrodes 12, the first electrode 12a and the second electrode 12b are arranged with a predetermined interval L1. For example, the predetermined interval L1 is 50 nm to 5 mm. Thus, when viewing the substrate 11 from the height direction (Z direction), the substrate 11 is sandwiched between the first electrode 12a and the second electrode 12b.

[0172] In the first embodiment, the electrode pattern including the first electrode 12a and the second electrode 12b arranged with a predetermined interval L1 is set as one group. Figure 8 The wiring pattern on the illustrated substrate 11 has a plurality of groups.

[0173] Return to Figure 6In step ST2, an insulator 13 is formed on the substrate 11. Specifically, in step ST2, an insulator 13 having openings 16 that partially expose the plurality of electrodes 12 is formed on the substrate 11. The insulator 13 exposes a portion of the plurality of electrodes 12 from the openings 16 and covers a portion of the plurality of electrodes 12. In the first embodiment, the insulator 13 covers a portion of the first electrode 12a and a portion of the second electrode 12b, exposing a portion of the substrate 11, a portion of the first electrode 12a, and a portion of the second electrode 12b. For example, step ST2 is performed using an insulating film forming apparatus such as a spin coater, various vapor deposition apparatuses, or a CVD apparatus included in a manufacturing apparatus, and a photolithography apparatus.

[0174] like Figure 7B As shown, the insulating coating material 41 is formed into a film on the substrate 11 provided with a plurality of electrodes 12. For example, the insulating coating material 41 is applied to the substrate 11 and cured. Figure 7C As shown, a portion of the insulating coating material 41 is removed by photolithography. Thus, the insulator 13 provided with the opening 16 is formed on the substrate 11.

[0175] Figure 10 It is a schematic plan view showing an example of the substrate 11 on which the insulator 13 is arranged. Figure 11 It will Figure 10 FIG. 1 is a schematic enlarged view of an enlarged portion 17 of the substrate 11. FIG. Figure 11 It will Figure 10 The enlarged summary diagram of the Z2 part of Figure 10 and Figure 11 As shown, when substrate 11 is viewed from the height direction (Z direction), a portion of first electrode 12a and a portion of second electrode 12b are located in exposed portion 17 exposed from opening 16 on substrate 11. In Embodiment 1, region 15a of first electrode 12a including the end portion facing second electrode 12b and region 15b of second electrode 12b including the end portion facing first electrode 12a are located in exposed portion 17.

[0176] Return to Figure 6 In step ST3, semiconductor sheet 14 is formed on insulator 13 and exposed portion 17. Step ST3 is performed, for example, by a semiconductor sheet forming device included in the manufacturing apparatus.

[0177] For example, in step ST3 , the semiconductor chip 14 is transferred to the insulator 13 and the exposed portion 17 exposed from the opening 16 on the substrate 11 .

[0178] Figure 12 This is a diagram for explaining an example of a process for forming the semiconductor wafer 14 . Figure 12 FIG. 2 shows a process for forming the semiconductor wafer 14 by transfer. Figure 12 As shown, a semiconductor sheet 14 formed on a base material 3 such as copper foil is moved onto a substrate 11 covered with an insulator 13 .

[0179] The transfer of semiconductor sheet 14 will be described in detail. First, copper foil is prepared. Semiconductor sheet 14 is formed on the surface of the copper foil using a CVD device. PMMA is coated on the surface of semiconductor sheet 14 as a graphene-retaining film. The copper foil with semiconductor sheet 14 and PMMA is floated on the surface of an etchant that dissolves copper. This dissolves the copper foil, leaving semiconductor sheet 14 with PMMA coated on its surface floating on the etchant. Semiconductor sheet 14 floating on the etchant is scooped up and placed on substrate 11 formed with insulator 13. The PMMA is then cleaned with a cleaning solution.

[0180] like Figure 7D As shown, when semiconductor chip 14 is transferred to the upper surface of insulator 13, semiconductor chip 14 deforms due to its own weight in opening 16 and is positioned in exposed portion 17. In exposed portion 17, semiconductor chip 14 is positioned over a portion of first electrode 12a and a portion of second electrode 12b located in exposed portion 17, electrically connecting first electrode 12a and second electrode 12b. After semiconductor chip 14 is transferred, it is dried.

[0181] Then, if Figure 7E As shown, a portion of the semiconductor chip 14 disposed on the insulator 13 is removed by etching to perform patterning.

[0182] In this manner, the semiconductor device 1A is manufactured by executing steps ST1 to ST3 . Note that the method for manufacturing the sensor 2 includes, in addition to steps ST1 to ST3 , a step of arranging a plurality of receptors 31 on the surface of the semiconductor wafer 14 .

[0183] In the first embodiment, the semiconductor sheet 14 is formed by transfer in step ST3 , but the present invention is not limited thereto. For example, the semiconductor sheet 14 may be formed by lamination, growth, or coating.

[0184] Figures 13A to 13C This is a diagram for explaining another example of the process of forming the semiconductor wafer 14 . Figure 13A An example of a process for forming the semiconductor sheet 14 by pasting is shown. Figure 13A As shown, when the semiconductor chip 14 is a single body and stable, the semiconductor chip 14 can be pressed against the substrate 11 covered by the insulator 13 . Figure 13B An example of a process for forming a growing semiconductor wafer 14 is shown. Figure 13B As shown, a semiconductor wafer 14 may be placed on a substrate 11 covered with an insulator 13 and grown using the reaction gas 4 . Figure 13C An example of the process of forming the semiconductor sheet 14 by coating is shown. Figure 13C As shown, the semiconductor wafer 14 may be placed on the substrate 11 covered with the insulator 13 and the liquid 5 may be applied. The semiconductor wafer 14 may be formed by drying the liquid 5 after application.

[0185] In this way, step ST3 can form the semiconductor wafer 14 by methods such as transfer, pasting, growth or coating.

[0186] [Effect]

[0187] According to the semiconductor device 1A and the method for manufacturing the semiconductor device 1A according to the first embodiment, the following effects can be achieved.

[0188] Semiconductor device 1A includes a substrate 11, multiple electrodes 12, an insulator 13, and a semiconductor chip 14. Multiple electrodes 12 are arranged on substrate 11. Insulator 13 is provided with openings 16 that expose portions of multiple electrodes 12 on substrate 11. Insulator 13 exposes portions of multiple electrodes 12 through openings 16 and covers portions of multiple electrodes 12. Semiconductor chip 14 is arranged between insulator 13 and exposed portion 17 on substrate 11 that is exposed through openings 16.

[0189] This structure improves the performance of semiconductor device 1A. In semiconductor device 1A, contamination of the surface of semiconductor wafer 14 is suppressed, thereby suppressing degradation of the electrical characteristics of semiconductor wafer 14. Furthermore, multiple receptors 31 and the like can be precisely arranged on the surface of semiconductor wafer 14.

[0190] When semiconductor device 1A is used as sensor 2, sensor 2 includes multiple receptors 31 disposed on semiconductor chip 14 and capturing target molecules 50. This structure allows the capture of target molecules 50, such as viruses. Furthermore, semiconductor chip 14 is disposed not only on exposed portion 17 but also on insulator 13. Therefore, multiple receptors 31 can be disposed on semiconductor chip 14 disposed on insulator 13. This increases the detection area for target molecules 50, facilitating the capture of target molecules 50.

[0191] The sensor 2 includes a calculation unit 32 that receives an electrical signal output from the semiconductor chip 14 and calculates the amount of the target molecule 50 based on the electrical signal. This configuration can calculate the amount of the target molecule 50, determine the presence of the target molecule 50, and / or calculate the concentration.

[0192] Semiconductor chip 14 is in close contact with insulator 13 and exposed portion 17 by van der Waals force. This structure allows semiconductor chip 14 to be easily fixed to insulator 13 and exposed portion 17. Furthermore, since adhesives are not required, costs can be reduced.

[0193] The method for manufacturing the semiconductor device 1A includes step ST1 of preparing a substrate 11, step ST2 of forming an insulator 13, and step ST3 of forming a semiconductor chip 14. Step ST1 prepares the substrate 11 on which the plurality of electrodes 12 are arranged. Step ST2 forms the insulator 13, which has openings 16 that expose portions of the plurality of electrodes 12 on the substrate 11 and covers the portions of the plurality of electrodes 12. Step ST3 forms the semiconductor chip 14 between the insulator 13 and the exposed portion 17 that is exposed from the openings 16 on the substrate 11.

[0194] According to such a structure, the semiconductor device 1A with improved performance can be manufactured. According to the manufacturing method, the semiconductor wafer 14 is formed after the insulator 13 is formed, so that the surface of the semiconductor wafer 14 can be prevented from being contaminated.

[0195] It should be noted that, in the first embodiment, the semiconductor device 1A is described as an example of a field-effect transistor including an electrolyte 20, but the present invention is not limited thereto. The semiconductor device 1A may be a device including a semiconductor wafer 14. For example, other devices include a cyclic voltammetry device and a semiconductor heterojunction device.

[0196] In the first embodiment, the semiconductor device 1A is described as the sensor 2 serving as a biosensor for detecting viruses, but the present invention is not limited thereto. For example, the semiconductor device 1A may be used as a sensor such as a chemical sensor for detecting ions.

[0197] In the first embodiment, the example in which the plurality of electrodes 12 are covered by the insulator 13 having the openings 16 for exposing the plurality of electrodes 12 on the substrate 11 is described, but the present invention is not limited thereto. For example, the insulator 13 may cover at least a portion of the plurality of electrodes 12 .

[0198] In the first embodiment, an example in which the opening 16 exposes the plurality of electrodes 12 is described, but the present invention is not limited thereto. For example, the opening 16 may expose at least one of the plurality of electrodes 12 on the substrate 11 .

[0199] In Embodiment 1, an example was described in which region 15a of first electrode 12a including the end portion facing second electrode 12b and region 15b of second electrode 12b including the end portion facing first electrode 12a are located in exposed portion 17. However, the present invention is not limited thereto. At least one of a portion of first electrode 12a and a portion of second electrode 12b may be located in exposed portion 17.

[0200] In the first embodiment, an example is described in which one opening 16 is provided in the insulator 13 for one electrode pattern group including the first electrode 12a and the second electrode 12b, but the present invention is not limited thereto. For example, one or more openings 16 may be provided in the insulator 13 for one electrode pattern group.

[0201] In Embodiment 1, an example is described in which one opening 16 is formed for exposing the first electrode 12a and the second electrode 12b in one electrode pattern group including the first electrode 12a and the second electrode 12b, but the present invention is not limited thereto. For example, one or more openings 16 may be formed in one electrode pattern group.

[0202] In the first embodiment, the example in which the opening 16 is formed into a rectangular shape when the semiconductor device 1A is viewed from the height direction (Z direction) is described, but the invention is not limited thereto. For example, the opening 16 may be circular, elliptical, or polygonal.

[0203] In the first embodiment, as an example of a method for manufacturing the semiconductor device 1A, a method is used. Figure 6 The steps ST1 to ST3 are described in detail, but are not limited thereto. For example, Figure 6 The steps ST1 to ST3 shown can be combined or divided. Figure 6 The flowchart shown may include additional steps, such as a step of pre-treating the substrate 11 before forming the semiconductor wafer 14 , a step of drying the semiconductor wafer 14 , a step of etching the semiconductor wafer 14 , and the like.

[0204] In embodiment 1, use Figures 7A to 7E The illustrated process example describes step ST2 of forming the insulator 13, but the present invention is not limited thereto. For example, in step ST2, the insulator 13 may be formed using a resist.

[0205] In the first embodiment, an example in which the opening 16 is formed by photolithography in step ST2 has been described, but the present invention is not limited thereto and the opening 16 may be formed by a method other than photolithography.

[0206] Figure 14 This is a schematic perspective view of a semiconductor device 1B according to a modified example of the first embodiment of the present invention. Figure 14 The semiconductor device 1B shown is a device for detecting viruses by cyclic voltammetry. Figure 14As shown, semiconductor device 1B includes a working electrode 12c, a counter electrode 12d, and a reference electrode 12f as the plurality of electrodes 12. In semiconductor device 1B, working electrode 12c, counter electrode 12d, and reference electrode 12f are provided on substrate 11. Counter electrode 12d and reference electrode 12f are covered by an insulator 13 having an opening 16. Opening 16 exposes portions of working electrode 12c, counter electrode 12d, and reference electrode 12f. Semiconductor chip 14 is formed on the surface of working electrode 12c. Thus, semiconductor chip 14 may also be provided as one of the plurality of electrodes 12.

[0207] (Implementation Method 2)

[0208] A method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described.

[0209] In Embodiment 2, the differences from Embodiment 1 will be mainly described. In Embodiment 2, the same or equivalent components as those in Embodiment 1 are denoted by the same reference numerals and described. In addition, in Embodiment 2, descriptions that overlap with those in Embodiment 1 are omitted.

[0210] The second embodiment differs from the first embodiment in that a resist is used in step ST2 of forming an insulator.

[0211] use Figures 15A to 15F A method for manufacturing the semiconductor device 1A according to the second embodiment will be described. Figures 15A to 15F This is a schematic diagram showing an example of the process of the method for manufacturing the semiconductor device 1A according to the second embodiment of the present invention. Figure 6 The flowchart shown is the same.

[0212] In step ST1, as Figure 15A As shown, a substrate 11 provided with a plurality of electrodes 12 is prepared.

[0213] In step ST2, an insulator 13 having openings 16 is formed on a substrate 11 provided with a plurality of electrodes 12. Figure 15B As shown, a resist is applied on the substrate 11 and dried, thereby forming a resist film 42 .

[0214] like Figure 15CAs shown, a portion of the resist film 42 is removed by photolithography. Specifically, by photolithography, the resist film 42 corresponding to the position where the opening 16 is provided is left on the substrate 11, and the resist film 42 corresponding to the portion where the insulator 13 is formed is removed. For example, the resist film 42 covering the first electrode 12a and the second electrode 12b is left on the substrate 11, and the resist film 42 covering the first electrode 12a and the second electrode 12b is removed.

[0215] like Figure 15D As shown, the insulating coating material 43 is formed into a film on the substrate 11. Thus, the first electrode 12a and the second electrode 12b on the substrate 11 are covered with the insulating coating material 43.

[0216] like Figure 15E As shown, the resist film 42 is removed by lift-off. Openings 16 are formed in the portion where the resist film 42 has been removed. Thus, an insulator 13 having openings 16 is formed. Parts of the plurality of electrodes 12 are located in exposed portions 17 exposed from openings 16 on the substrate 11. In the second embodiment, a region 15a of the first electrode 12a including an end portion facing the second electrode 12b and a region 15b of the second electrode 12b including an end portion facing the first electrode 12a are located in the exposed portions 17.

[0217] In step ST3, as Figure 15F As shown, a semiconductor sheet 14 is formed on the insulator 13 and the exposed portion 17. For example, the semiconductor sheet 14 can be formed by transfer, bonding, growth, or coating.

[0218] In this way, in step ST2 , the insulator 13 provided with the opening 16 can be formed using the resist film 42 .

[0219] [Effect]

[0220] According to the method for manufacturing the semiconductor device 1A of the second embodiment, the following effects can be achieved.

[0221] In the method for manufacturing semiconductor device 1A according to the second embodiment, step ST2 of forming insulator 13 involves forming insulator 13 having opening 16 on substrate 11 using resist film 42. Specifically, resist film 42 is disposed at the location where opening 16 is to be provided, and insulating coating material 43 is formed on resist film 42. Thereafter, resist film 42 is removed. This facilitates formation of insulator 13 having opening 16.

[0222] Furthermore, in the manufacturing method of the second embodiment, there is no need to remove a portion of the insulating coating material by photolithography as in the first embodiment. Therefore, the range of choices for insulating materials used to form the insulating coating material 43 of the insulator 13 is wider than in the first embodiment. For example, an insulating coating material 43 having superior insulation and / or water resistance to the insulating coating material 41 of the first embodiment can be used.

[0223] In addition, in Embodiment 2, an example in which a part of the resist film 42 is removed by photolithography is described, but the present invention is not limited to this. The resist film 42 may be removed by a method other than photolithography.

[0224] (Implementation Method 3)

[0225] A method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described.

[0226] In Embodiment 3, the differences from Embodiment 1 will be mainly described. In Embodiment 3, the same or equivalent components as those in Embodiment 1 are denoted by the same reference numerals and described. In Embodiment 3, overlapping descriptions with those in Embodiment 1 will be omitted.

[0227] The third embodiment differs from the first embodiment in that a resist is used in step ST2 of forming an insulator and an opening is formed by etching.

[0228] use Figures 16A to 16G A method for manufacturing the semiconductor device 1A according to the third embodiment will be described. Figures 16A to 16G This is a schematic diagram showing an example of the process of the method for manufacturing the semiconductor device 1A according to the third embodiment of the present invention. Figure 6 The flowchart shown is the same.

[0229] In step ST1, as Figure 16A As shown, a substrate 11 provided with a plurality of electrodes 12 is prepared.

[0230] In step ST2, an insulator 13 is formed on the substrate 11 provided with a plurality of electrodes 12. Figure 16B As shown, the insulating coating material 44 is formed into a film on the substrate 11 .

[0231] like Figure 16C As shown, a resist film 45 is formed on the insulating coating material 44 .

[0232] like Figure 16DAs shown, a portion of the resist film 45 is removed by photolithography. Specifically, by photolithography, the resist film 45 on the insulating coating material 44 corresponding to the portion where the coating portion 15 is formed remains, and the resist film 45 corresponding to the portion where the opening 16 is provided is removed. For example, the resist film 42 on the insulating coating material 44 covering the first electrode 12a and the second electrode 12b remains, and the resist film 45 on the insulating coating material 44 spanning the first electrode 12a and the second electrode 12b is removed.

[0233] like Figure 16E As shown, the insulating coating material 44 is removed by etching from the portion where the resist film 45 has been removed. This forms an opening 16. A portion of the plurality of electrodes 12 is located in an exposed portion 17 exposed on the substrate 11 through the opening 16. In the third embodiment, a region 15a of the first electrode 12a including the end portion facing the second electrode 12b and a region 15b of the second electrode 12b including the end portion facing the first electrode 12a are located in the exposed portion 17.

[0234] like Figure 16F As shown, the resist film 45 is removed. Thus, the insulator 13 provided with the opening 16 is formed.

[0235] In step ST3, as Figure 16G As shown, a semiconductor sheet 14 is formed on the insulator 13 and the exposed portion 17. For example, the semiconductor sheet 14 can be formed by transfer, bonding, growth, or coating.

[0236] In this way, in step ST2 , the insulator 13 provided with the opening 16 is formed by forming the resist film 45 on the insulating coating material 44 and removing a portion of the insulating coating material 44 by etching.

[0237] [Effect]

[0238] According to the method for manufacturing the semiconductor device 1A of the third embodiment, the following effects can be achieved.

[0239] In the method for manufacturing semiconductor device 1A according to the third embodiment, step ST2 of forming insulator 13 forms insulator 13 having opening 16 using resist film 45. Specifically, resist film 45 is formed on insulating coating material 44, and the portion of resist film 45 corresponding to the portion where opening 16 is to be provided is removed. Then, the portion of insulating coating material 44 where resist film 45 has been removed is removed by etching. This facilitates formation of insulator 13 having opening 16.

[0240] Furthermore, in the manufacturing method of Embodiment 3, since openings 16 are formed by etching, the range of materials available for insulating coating material 44 is wider than that of Embodiment 1. For example, insulating coating material 44 having superior insulation and / or water resistance to insulating coating material 41 of Embodiment 1 can be used.

[0241] (Implementation Method 4)

[0242] A semiconductor device and a method for manufacturing the semiconductor device according to a fourth embodiment of the present invention will be described.

[0243] In Embodiment 4, the differences from Embodiment 1 will be mainly described. In Embodiment 4, the same or equivalent components as those in Embodiment 1 are denoted by the same reference numerals and described. In addition, in Embodiment 4, descriptions that overlap with those in Embodiment 1 are omitted.

[0244] In embodiment 4, the difference from embodiment 1 lies in that the insulator has a connecting insulating portion spanning the first electrode and the second electrode, a first opening for exposing the first electrode and a second opening for exposing the second electrode are provided in the insulator, and the semiconductor chip is continuously arranged in the connecting insulating portion, the first exposed portion exposed from the first opening, and the second exposed portion exposed from the second opening.

[0245] use Figure 17 and Figure 18 A semiconductor device 1C according to a fourth embodiment will be described. Figure 17 This is a schematic diagram showing an example of a main structure of a semiconductor device 1C according to a fourth embodiment of the present invention. Figure 18 This is a schematic plan view showing an example of the main structure of a semiconductor device 1C according to a fourth embodiment of the present invention.

[0246] like Figure 17 and Figure 18 As shown, the insulator 13 includes a connecting insulating portion 13b arranged on the substrate 11, spanning the first electrode 12a and the second electrode 12b. Specifically, the connecting insulating portion 13b is arranged over a portion of the substrate 11, a portion of the first electrode 12a, and a portion of the second electrode 12b. In the fourth embodiment, the connecting insulating portion 13b is arranged across a region 15a of the first electrode 12a including the end facing the second electrode 12b, and a region 15b of the second electrode 12b including the end facing the first electrode 12a.

[0247] Insulator 13 is provided with a plurality of openings 16. Openings 16 include a first opening 16a and a second opening 16b. Connecting insulating portion 13b is a portion of insulator 13 that separates first opening 16a from second opening 16b. The two side walls of connecting insulating portion 13b define first opening 16a and second opening 16b, respectively.

[0248] In embodiment 4, Figure 18 As shown, the first opening 16a and the second opening 16b are formed in a rectangular shape when the semiconductor device 1C is viewed from the height direction (Z direction). The first opening 16a exposes a portion of the substrate 11 and a portion of the first electrode 12a. The second opening 16b exposes a portion of the substrate 11 and a portion of the second electrode 12b.

[0249] The substrate 11 has a plurality of exposed portions 17 exposed through the plurality of openings 16a and 16b. The first exposed portion 17a is a portion exposed from the first opening 16a on the substrate 11. The second exposed portion 17b is a portion exposed from the second opening 16b on the substrate 11.

[0250] In Embodiment 4, a portion of the first electrode 12a is located in the first exposed portion 17a, and a portion of the second electrode 12b is located in the second exposed portion 17b.

[0251] Semiconductor sheet 14a is continuously arranged across insulating connecting portion 13b, first exposed portion 17a, and second exposed portion 17b. "Continuously arranged" here means that semiconductor sheet 14a is arranged in a continuous state. In other words, a single semiconductor sheet 14a covers insulating connecting portion 13b, first exposed portion 17a, and second exposed portion 17b. Semiconductor sheet 14a electrically connects first electrode 12a located on first exposed portion 17a with second electrode 12b located on second exposed portion 17b.

[0252] Figure 19 This is a schematic enlarged view showing a portion of the exposed portion 17 . Figure 19 1 is an enlarged view of the vicinity of the portion where the substrate 11 located at the second exposed portion 17b is connected to the insulator 13. Figure 19 As shown, a gap 18 is formed between the sidewall 13a of the insulator 13 having the second opening 16b, the semiconductor chip 14a, and the substrate 11. The "sidewall 13a of the insulator 13 having the second opening 16b" refers to the sidewall 13a of the insulator 13 that defines the second opening 16b.

[0253] Specifically, the semiconductor chip 14 a has an arc-shaped curved portion 14 aa at a corner portion connecting the side wall 13 a of the insulator 13 defining the second opening 16 b and the surface of the substrate 11 .

[0254] At second opening 16b, semiconductor chip 14a extends from the upper surface of insulator 13 along sidewall 13a. Semiconductor chip 14a, extending along sidewall 13a of insulator 13, extends toward substrate 11. At the corner connecting sidewall 13a of insulator 13 and the surface of substrate 11, semiconductor chip 14a curves away from sidewall 13a through curved portion 14aa. Thereafter, semiconductor chip 14a extends along the surface of substrate 11.

[0255] It should be noted that Figure 19 The illustrated example uses second exposed portion 17b as an example, but the present invention is not limited thereto. The same structure can also be employed in first exposed portion 17a. In other words, gap 18 can also be formed between sidewall 13a of insulator 13 having first opening 16a, semiconductor chip 14a, and substrate 11.

[0256] Alternatively, the sidewall 13a of the insulator 13 may also serve as the sidewall of the connecting insulating portion 13b. In the fourth embodiment, the sidewall of the connecting insulating portion 13b defines the first opening 16a and the second opening 16b. Therefore, a gap 18 may be formed between the sidewall of the connecting insulating portion 13b with the first opening 16a, the semiconductor chip 14a, and the substrate 11. Alternatively, a gap 18 may be formed between the sidewall of the connecting insulating portion 13b with the second opening 16b, the semiconductor chip 14a, and the substrate 11.

[0257] [Manufacturing method]

[0258] An example of a method for manufacturing the semiconductor device 1C will be described. Figure 20 This is a flowchart of an example of a method for manufacturing a semiconductor device 1C according to a fourth embodiment of the present invention. Figures 21A to 21D This is a schematic diagram showing an example of the process of the method for manufacturing the semiconductor device 1C according to the fourth embodiment of the present invention. It should be noted that the steps described below are performed by the manufacturing apparatus. It should be noted that step ST11 is the same as that of the first embodiment. Figure 6 The step ST1 shown is the same, so the detailed description is omitted.

[0259] like Figure 20 and Figure 21A As shown, in step ST11, a substrate 11 is prepared on which a plurality of electrodes 12 are arranged. For example, step ST11 is performed by a metal film forming apparatus represented by a sputtering apparatus or an EB (Electron Beam) vapor deposition apparatus included in a manufacturing apparatus.

[0260] In step ST12, an insulator 13 having a plurality of openings 16 is formed on the substrate 11. Specifically, in step ST12, the insulator 13 is formed on the substrate 11 with a first opening 16a that exposes a portion of the first electrode 12a, and a second opening 16b that exposes a portion of the second electrode 12b. The insulator 13 exposes a portion of the first electrode 12a and a portion of the second electrode 12b through the first opening 16a and the second opening 16b, respectively, while covering a portion of the first electrode 12a and a portion of the second electrode 12b. Step ST12 is performed, for example, using an insulating film forming apparatus such as a spin coater, various vapor deposition apparatuses, or a CVD apparatus, as part of a manufacturing apparatus, and a photolithography apparatus.

[0261] Step ST12 includes step ST12A of forming the coupling insulating portion 13 b and step ST12B of forming the first opening 16 a and the second opening 16 b .

[0262] In step ST12A of forming the connecting insulating portion 13 b , the connecting insulating portion 13 b arranged to straddle the first electrode 12 a and the second electrode 12 b is formed.

[0263] In step ST12B of forming the first opening 16a and the second opening 16b , the first opening 16a for exposing a portion of the first electrode 12a on the substrate 11 and the second opening 16b for exposing a portion of the second electrode 12b on the substrate 11 are formed in the insulator 13 .

[0264] It should be noted that steps ST12A and ST12B can be combined or their order can be reversed. The connecting insulating portion 13b, first opening 16a, and second opening 16b can be formed using the same method as step ST2 for forming the insulator 13 in embodiments 1 to 3. For example, an insulating coating material can be formed on the substrate 11 and then photolithography can be used to form the connecting insulating portion 13b, first opening 16a, and second opening 16b.

[0265] like Figure 21B As shown, the insulating coating material 46 is formed into a film on the substrate 11 provided with the plurality of electrodes 12. For example, the insulating coating material 46 is applied onto the substrate 11 and cured.

[0266] like Figure 21CAs shown, the insulating coating material 46 extending across the first electrode 12a and the second electrode 12b remains on the substrate 11, and the insulating coating material 46 disposed on the first electrode 12a and the second electrode 12b is removed by photolithography. This forms the insulator 13 including the connecting insulating portion 13b extending across the first electrode 12a and the second electrode 12b. Furthermore, the portion removed by photolithography forms the first opening 16a, which exposes a portion of the first electrode 12a, and the second opening 16b, which exposes a portion of the second electrode 12b, on the substrate 11.

[0267] A first exposed portion 17a and a second exposed portion 17b are formed at positions where the first opening 16a and the second opening 16b are provided on the substrate 11. The first exposed portion 17a is the portion of the substrate 11 exposed from the first opening 16a. The second exposed portion 17b is the portion of the substrate 11 exposed from the second opening 16b.

[0268] In step ST13, as Figure 21D As shown, semiconductor piece 14a is formed on insulator 13 and multiple exposed portions 17. Specifically, step ST13 includes step ST13A of forming semiconductor piece 14a continuously connected to insulating portion 13b, first exposed portion 17a, and second exposed portion 17b.

[0269] In step ST13A, semiconductor chip 14a is placed on the upper surface of insulator 13, including connecting insulating portion 13b. Semiconductor chip 14a deforms under its own weight within first opening 16a and second opening 16b, allowing it to be placed on first exposed portion 17a and second exposed portion 17b. Semiconductor chip 14a is placed on first electrode 12a located on first exposed portion 17a. Semiconductor chip 14a is placed on second electrode 12b located on second exposed portion 17b. Step ST13 can be performed, for example, using a semiconductor chip forming device included in a manufacturing apparatus.

[0270] The semiconductor piece 14a is continuously arranged from the first electrode 12a located at the first exposed portion 17a to the second electrode 12b located at the second exposed portion 17b with the connecting insulating portion 13b interposed therebetween.

[0271] In this way, the semiconductor device 1C is manufactured by executing steps ST11 to ST13 .

[0272] [Effect]

[0273] According to the semiconductor device 1C and the method for manufacturing the semiconductor device 1C according to the fourth embodiment, the following effects can be achieved.

[0274] In the semiconductor device 1C, the insulator 13 includes a connecting insulating portion 13b extending across the first electrode 12a and the second electrode 12b. The plurality of openings 16 include a first opening 16a that exposes a portion of the first electrode 12a on the substrate 11, and a second opening 16b that exposes a portion of the second electrode 12b on the substrate 11. The plurality of exposed portions 17 include a first exposed portion 17a that is exposed from the first opening 16a on the substrate 11, and a second exposed portion 17b that is exposed from the second opening 16b on the substrate 11. The semiconductor chip 14a is continuously arranged on the connecting insulating portion 13b, the first exposed portion 17a, and the second exposed portion 17b.

[0275] This structure can further improve device performance. The semiconductor sheet 14a is continuously arranged on the connecting insulating portion 13b, the first exposed portion 17a, and the second exposed portion 17b, thereby improving adhesion. This makes the semiconductor sheet 14a less likely to peel off, thereby improving durability.

[0276] In the semiconductor device 1C of the third embodiment, the base layer of the semiconductor wafer 14a can be arbitrarily selected, as compared to the first embodiment. It is known that substrate 11, typically made of SiO2, acts as a carrier scattering source for graphene, significantly degrading its electrical properties. In the semiconductor device 1C, the base layer can be an organic resin layer or a two-dimensional insulating layer, which is unlikely to interfere with graphene. Therefore, the electrical properties of graphene can be fully utilized.

[0277] In the plurality of exposed portions 17, gaps 18 are formed between the sidewall 13a of the insulator 13 having the plurality of openings 16, the semiconductor chip 14a, and the substrate 11. Specifically, in the first exposed portion 17a, gaps 18 are formed between the sidewall 13a of the insulator 13 having the first opening 16a, the semiconductor chip 14a, and the substrate 11. Gap 18 is also formed between the sidewall 13a of the insulator 13 having the second opening 16b, the semiconductor chip 14a, and the substrate 11.

[0278] With such a structure, stress applied to the semiconductor chip 14 a can be alleviated.

[0279] It should be noted that in Embodiment 4, an example is described in which the first opening 16a exposes a portion of the substrate 11 and a portion of the first electrode 12a, and the second opening 16b exposes a portion of the substrate 11 and a portion of the second electrode 12b, but the present invention is not limited to this. The first opening 16a only needs to expose the first electrode 12a. The second opening 16b only needs to expose the second electrode 12b. The first opening 16a and the second opening 16b do not need to expose the substrate 11.

[0280] Figure 221 is a schematic top view showing an example of the main structure of a semiconductor device 1D according to a modification of the fourth embodiment of the present invention. Figure 22 As shown, in the semiconductor device 1D, the insulator 13 is provided with a first opening 16 c and a second opening 16 d .

[0281] The first opening 16c exposes the first electrode 12a without exposing the substrate 11. The second opening 16d exposes the second electrode 12b without exposing the substrate 11.

[0282] Specifically, when the semiconductor device 1D is viewed from the height (Z direction), the first opening 16c is formed so as to project onto the upper surface of the first electrode 12a. When the semiconductor device 1D is viewed from the height (Z direction), the first opening 16c is formed within a range that does not extend beyond the upper surface of the first electrode 12a. That is, the dimensions of the first opening 16c in the X and Y directions are smaller than the dimensions of the upper surface of the first electrode 12a in the X and Y directions. When the semiconductor device 1D is viewed from the height (Z direction), the second opening 16d is formed so as to project onto the upper surface of the second electrode 12b. When the semiconductor device 1D is viewed from the height (Z direction), the second opening 16d is formed within a range that does not extend beyond the upper surface of the second electrode 12b. That is, the dimensions of the second opening 16d in the X and Y directions are smaller than the dimensions of the upper surface of the second electrode 12b in the X and Y directions.

[0283] In semiconductor device 1D, a portion of first electrode 12a is located in first exposed portion 17c exposed from first opening 16c. A portion of second electrode 12b is located in second exposed portion 17d exposed from second opening 16d. Substrate 11 is not located in first exposed portion 17c or second exposed portion 17d.

[0284] Semiconductor chip 14b is continuously arranged between connecting insulating portion 13b, first exposed portion 17c, and second exposed portion 17d. In first exposed portion 17c, semiconductor chip 14b is positioned on first electrode 12a. In second exposed portion 17d, semiconductor chip 14b is positioned on second electrode 12b. This allows for electrical connection between first electrode 12a and second electrode 12b via semiconductor chip 14b without placing semiconductor chip 14b on substrate 11.

[0285] This structure can suppress degradation of the electrical characteristics of the semiconductor chip 14b caused by the substrate 11. Furthermore, the substrate 11 can be formed of any material. In the semiconductor device 1D, the substrate 11 can be formed of, for example, resin materials such as PMMA, polyimide, styrene, PET, and silicone, as well as two-dimensional insulating materials such as boron nitride.

[0286] (Implementation method 5)

[0287] A semiconductor device and a method for manufacturing the semiconductor device according to a fifth embodiment of the present invention will be described.

[0288] In Embodiment 5, the differences from Embodiment 1 will be mainly described. In Embodiment 5, the same or equivalent components as those in Embodiment 1 are denoted by the same reference numerals and described. In addition, in Embodiment 5, descriptions overlapping with those in Embodiment 1 are omitted.

[0289] The fifth embodiment is different from the first embodiment in that the semiconductor chip is separated into a first semiconductor chip arranged on the insulator and a second semiconductor chip arranged on the exposed portion.

[0290] use Figure 23 and Figure 24 A semiconductor device 1E according to the fifth embodiment will be described. Figure 23 This is a schematic diagram showing an example of the main structure of a semiconductor device 1D according to a fifth embodiment of the present invention. Figure 24 This is a schematic plan view showing an example of the main structure of a semiconductor device 1D according to a fifth embodiment of the present invention.

[0291] like Figure 23 and Figure 24 As shown, the semiconductor chip 14 has a first semiconductor chip 14c and a second semiconductor chip 14d.

[0292] The first semiconductor chip 14 c is disposed on the insulator 13 . Specifically, the first semiconductor chip 14 c is disposed on the upper surface of the insulator 13 .

[0293] The second semiconductor chip 14d is separated from the first semiconductor chip 14c and is arranged in the exposed portion 17. The second semiconductor chip 14d is arranged between the first electrode 12a and the second electrode 12b located in the exposed portion 17, electrically connecting the first electrode 12a and the second electrode 12b. In the fifth embodiment, the second semiconductor chip 14d is arranged between a region 15a of the first electrode 12a including the end facing the second electrode 12b and a region 15b of the second electrode 12b including the end facing the first electrode 12a.

[0294] Figure 25 This is a schematic enlarged view of a part of the exposed portion 17. Figure 25 As shown, the end portion 14da of the second semiconductor chip 14d is bent in the thickness direction (Z direction) of the second semiconductor chip 14d. The end portion 14da of the second semiconductor chip 14d is bent in a direction away from the substrate 11. For example, when the semiconductor device 1E is viewed from the height direction (Z direction), the end portion 14da of the second semiconductor chip 14d is bent so as to overlap with the second semiconductor chip 14d.

[0295] In the semiconductor device 1E, when the semiconductor device 1E is viewed from the height direction (Z direction), the end portion 14 da of the second semiconductor chip 14 d can be easily confirmed. This makes it easy to confirm that the second semiconductor chip 14 d is disposed on the substrate 11 .

[0296] [Manufacturing method]

[0297] An example of a method for manufacturing the semiconductor device 1E will be described. Figure 26 This is a flowchart of an example of a method for manufacturing a semiconductor device 1E according to the fifth embodiment of the present invention. Figures 27A to 27C This is a schematic diagram showing an example of the operation in the process of forming a semiconductor wafer by transfer. It should be noted that the steps described below are performed by the manufacturing device. It should be noted that steps ST21 and ST22 are the same as those in the first embodiment. Figure 6 Steps ST1 and ST2 shown are the same, so detailed description is omitted.

[0298] like Figure 20 As shown, in step ST21, a substrate 11 is prepared on which a plurality of electrodes 12 are arranged. For example, step ST21 is performed by a metal film forming apparatus represented by a sputtering apparatus or an EB (Electron Beam) vapor deposition apparatus included in a manufacturing apparatus.

[0299] In step ST22, the insulator 13 having the coating portion 15 provided with the opening 16 is formed on the substrate 11. Step ST22 is performed, for example, by an insulating film forming apparatus represented by a spin coater, various vapor deposition apparatuses, a CVD apparatus, and a photolithography apparatus included in the manufacturing apparatus.

[0300] Step ST22 includes step ST22A of forming openings 16 that partially expose the plurality of electrodes 12. In step ST22A, openings 16 are formed to partially expose first electrode 12a and second electrode 12b. A portion of first electrode 12a and a portion of second electrode 12b are located in exposed portion 17 on substrate 11 exposed by opening 16. In Embodiment 5, region 15a of first electrode 12a including the end facing second electrode 12b and region 15b of second electrode 12b including the end facing first electrode 12a are located in exposed portion 17.

[0301] In step ST23, semiconductor chip 14 is formed on insulator 13 and exposed portion 17. Specifically, in step ST23, first semiconductor chip 14c is formed on insulator 13, and second semiconductor chip 14d is formed on exposed portion 17 exposed from opening 16 on substrate 11. Step ST23 is performed, for example, by a semiconductor chip forming device included in a manufacturing apparatus.

[0302] Step ST23 includes step ST23A of separating the semiconductor wafer 14 into the first semiconductor wafer 14 c and the second semiconductor wafer 14 d .

[0303] In step ST23A, the semiconductor piece 14 is separated into a first semiconductor piece 14 c arranged on the insulator 13 and a second semiconductor piece 14 d arranged on the exposed portion 17 exposed from the opening 16 on the substrate 11 .

[0304] For example, Figures 27A to 27C As shown, in step ST23A, the semiconductor piece 14 is cut in the opening 16 by the step 19 formed by the insulator 13 and the substrate 11. Thus, the semiconductor piece 14 is separated into the first semiconductor piece 14c and the second semiconductor piece 14d.

[0305] like Figure 27A As shown, step 19 is formed by insulator 13 and substrate 11. The size of step 19 is determined by distance L2 from substrate 11 to the top surface of insulator 13. By adjusting the size of step 19 (distance L2), semiconductor wafer 14 can be cut using its own weight. For example, the size of step 19 (distance L2) is preferably not less than 100 nm and not more than 1 mm.

[0306] like Figure 27B As shown, when semiconductor chip 14 is transferred from insulator 13, semiconductor chip 14 deforms under its own weight in opening 16. Specifically, semiconductor chip 14 deforms in opening 16 toward a portion of first electrode 12a and a portion of second electrode 12b as exposed portion 17.

[0307] In order for semiconductor chip 14 to adhere closely to the side surfaces, regions 15a, 15b, and exposed portion 17 of insulator 13, semiconductor chip 14 must deform and stretch. If the size of step 19 (distance L2) is sufficiently small, the rigidity of semiconductor chip 14 is low, and its ductility is sufficiently high, semiconductor chip 14 can stretch without breaking and adhere closely to the side surfaces, regions 15a, 15b, and exposed portion 17 of insulator 13. If the size of step 19 (distance L2) is large, the rigidity and ductility of semiconductor chip 14 are low, semiconductor chip 14 deforms under its own weight, preventing it from fully stretching and causing it to break. In this case, fracture occurs at the end of insulator 13, where the greatest stress is applied.

[0308] When the rigidity of the semiconductor chip 14 is high, neither deformation nor cutting occurs, and the chip is placed between the insulators 13 on the upper part of the exposed portion 17. However, in this state, the first electrode 12a, the second electrode 12b and the semiconductor chip are not electrically connected, and therefore, the chip does not operate as a semiconductor device.

[0309] like Figure 27CAs shown, the semiconductor chip 14 is cut at the step 19 , so that the first semiconductor chip 14 c is arranged on the insulator 13 and the second semiconductor chip 14 d is arranged on the exposed portion 17 .

[0310] In this way, the semiconductor device 1E is manufactured by executing steps ST21 to ST23.

[0311] [Effect]

[0312] According to the semiconductor device 1E and the method for manufacturing the semiconductor device 1E of the fifth embodiment, the following effects can be achieved.

[0313] In the semiconductor device 1E, the exposed portion 17 includes a portion of the first electrode 12a and a portion of the second electrode 12b. The semiconductor chip 14 includes a first semiconductor chip 14c disposed on the insulator 13 and a second semiconductor chip 14d separated from the first semiconductor chip 14c and disposed on the exposed portion 17.

[0314] This structure prevents electrical short circuits in the semiconductor wafer 14. Furthermore, because the first semiconductor wafer 14c and the second semiconductor wafer 14d are physically separated, even if a physical load is applied to the first semiconductor wafer 14c, the second semiconductor wafer 14d is not affected. Consequently, degradation in the performance of the semiconductor device 1E due to separation of the semiconductor wafer 14 under external physical load can be suppressed.

[0315] The end portion 14da of the second semiconductor sheet 14d is curved in the thickness direction (Z direction) of the second semiconductor sheet 14d. This structure makes it easy to identify the area where the second semiconductor sheet 14d is located. Furthermore, it is possible to suppress the adsorption of target molecules 50 to the end portion 14da of the second semiconductor sheet 14d.

[0316] In the method for manufacturing the semiconductor device 1E, step ST22 of forming the insulator 13 includes step ST22A of forming openings 16 in the insulator 13 to expose a portion of the first electrode 12a and a portion of the second electrode 12b on the substrate 11. Step ST23 of forming the semiconductor wafer 14 includes step ST23A of separating the semiconductor wafer 14 into a first semiconductor wafer 14c disposed on the insulator 13 and a second semiconductor wafer 14d disposed on an exposed portion 17 exposed from the openings 16 on the substrate 11.

[0317] In the separation step ST23A, the semiconductor piece 14 is cut in the opening 16 via the step 19 formed by the insulator 13 and the substrate 11 .

[0318] With such a structure, the semiconductor chip 14 can be easily separated into the first semiconductor chip 14 c and the second semiconductor chip 14 d .

[0319] Furthermore, in the manufacturing method of the fifth embodiment, the etching process of the semiconductor wafer 14 in the forming step of the manufacturing method of the first embodiment can be omitted.

[0320] It should be noted that, in the fifth embodiment, the semiconductor sheet 14 is formed by transfer in step ST23 , but the present invention is not limited thereto. For example, the semiconductor sheet 14 may be formed by lamination, growth, or coating in step ST23 .

[0321] While the present invention has been fully described in connection with the preferred embodiments with reference to the accompanying drawings, various modifications and variations will be apparent to those skilled in the art. Such modifications and variations are to be understood as being within the scope of the present invention as defined by the appended claims, provided they do not depart from the scope of the present invention.

[0322] Industrial applicability

[0323] The semiconductor device of the present invention is useful in chemical sensors that detect ions or biosensors that detect viruses or the like.

[0324] Description of Reference Numerals

[0325] 1A, 1B, 1C, 1D, 1E semiconductor equipment;

[0326] 2 sensors;

[0327] 3. Base material;

[0328] 4. Reaction gas;

[0329] 5 liquid;

[0330] 11 substrate;

[0331] 12 electrodes;

[0332] 12a first electrode;

[0333] 12b second electrode;

[0334] 12c active electrode;

[0335] 12d counter electrode;

[0336] 12f reference electrode;

[0337] 13 insulators;

[0338] 13a sidewall;

[0339] 13b connecting the insulating part;

[0340] 14, 14a, 14b semiconductor wafer;

[0341] 14c a first semiconductor wafer;

[0342] 14d a second semiconductor wafer;

[0343] 14da end;

[0344] Areas 15a and 15b;

[0345] 16, 16a, 16b, 16c, 16d openings;

[0346] 17, 17a, 17b, 17c, 17d exposed portion;

[0347] 18 gap;

[0348] 19 order difference;

[0349] 20 electrolyte;

[0350] 21 third electrode;

[0351] 31 receptors;

[0352] 32 operation unit;

[0353] 41, 43, 44, 46 Insulation coating materials;

[0354] 42, 45 resist film;

[0355] 50 target molecules.

Claims

1. A semiconductor device comprising: substrate; a plurality of electrodes disposed on the substrate; an insulator having one or more openings for exposing at least one of the plurality of electrodes on the substrate and covering at least a portion of each of the plurality of electrodes; as well as a semiconductor chip disposed between the insulator and one or more exposed portions exposed from the one or more openings on the substrate; The plurality of electrodes are also exposed from the one or more openings, When viewed in the Z direction, which is a height direction of the substrate, the area of the insulator is larger than the area of the plurality of electrodes exposed from the insulator.

2. The semiconductor device according to claim 1, wherein The plurality of electrodes include a first electrode and a second electrode disposed at a distance from the first electrode. At least one of a portion of the first electrode and a portion of the second electrode is located at the one or more exposed portions, The semiconductor chip is connected to the first electrode and the second electrode.

3. The semiconductor device according to claim 2, wherein A region of the first electrode including an end portion facing the second electrode and a region of the second electrode including an end portion facing the first electrode are located in the exposed portion.

4. The semiconductor device according to claim 2, wherein The insulator has a connecting insulating portion arranged across the first electrode and the second electrode, The plurality of openings include a first opening that exposes a portion of the first electrode on the substrate and a second opening that exposes a portion of the second electrode on the substrate. The plurality of exposed portions include a first exposed portion exposed from the first opening on the substrate and a second exposed portion exposed from the second opening on the substrate, The semiconductor piece is continuously arranged on the connecting insulating portion, the first exposed portion, and the second exposed portion.

5. The semiconductor device according to claim 4, wherein A gap is formed between the sidewall of the insulator provided with the plurality of openings, the semiconductor chip, and the substrate. The semiconductor device according to claim 3 , wherein: The semiconductor wafer has: A first semiconductor chip is disposed on the insulator; and The second semiconductor chip is separated from the first semiconductor chip and is disposed on the exposed portion.

7. The semiconductor device according to claim 6, wherein An end portion of the second semiconductor piece is bent in a thickness direction of the second semiconductor piece.

8. The semiconductor device according to any one of claims 1 to 7, wherein The semiconductor sheet is formed of any one of graphene, carbon nanotubes, organic semiconductors, MXENES and transition metal dichalcogenide layered materials.

9. The semiconductor device according to any one of claims 1 to 7, wherein The semiconductor device further includes a plurality of receptors, which are arranged on the semiconductor chip and are used to capture target molecules.

10. The semiconductor device according to claim 9, wherein The semiconductor device further includes a calculation unit that receives an electrical signal output from the semiconductor chip and calculates the amount of the target molecule based on the electrical signal.

11. The semiconductor device according to any one of claims 1 to 7, wherein The semiconductor chip is closely attached to the insulator and the one or more exposed portions by van der Waals forces.

12. A method for manufacturing a semiconductor device, used for the semiconductor device according to claim 1, the method comprising: a step of preparing a substrate provided with a plurality of electrodes; forming an insulator having one or more openings for exposing at least one of the plurality of electrodes on the substrate and covering at least a portion of each of the plurality of electrodes; as well as A step of forming a semiconductor chip on the insulator and the one or more exposed portions on the substrate exposed from the one or more openings.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The plurality of electrodes include a first electrode and a second electrode disposed at a distance from the first electrode. At least one of a portion of the first electrode and a portion of the second electrode is located at the one or more exposed portions, The semiconductor sheet electrically connects the first electrode and the second electrode.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: A region of the first electrode including an end portion facing the second electrode and a region of the second electrode including an end portion facing the first electrode are located in the exposed portion.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: The steps of forming the insulator include: forming a connecting insulating portion arranged across the first electrode and the second electrode; as well as A first opening for exposing a portion of the first electrode on the substrate and a second opening for exposing a portion of the second electrode on the substrate are formed in the insulator. The step of forming the semiconductor sheet includes forming a semiconductor sheet in which the connecting insulating portion, a first exposed portion in which a portion of the first electrode is exposed from the first opening, and a second exposed portion in which a portion of the second electrode is exposed from the second opening are continuous.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: The step of forming the insulator includes forming an opening in the insulator so as to expose a portion of the first electrode and a portion of the second electrode on the substrate, The step of forming the semiconductor piece includes separating the semiconductor piece into a first semiconductor piece arranged on the insulator and a second semiconductor piece arranged on an exposed portion of the substrate exposed from the opening.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: In the separation, the semiconductor piece is cut in the opening along a step formed by the insulator and the substrate.

Images