Electronic device having a differential transmission line equipped with a capacitor supported by a base and corresponding manufacturing method

Abstract

An electronic device and a method for manufacturing the electronic device, the electronic device comprising a board (200) provided with a pair (201) of differential transmission lines (202A, 202A', 202B, 202B'), each line in the pair having an opening extending between two line terminals, the device also comprising a capacitor module (CM), the capacitor module (CM) comprising: a base (203); two 3D capacitors (204A, 204B) supported by the base, each 3D capacitor comprising two capacitor terminals, the two capacitor terminals being respectively connected to the two line terminals of one line in the pair of transmission lines.

Description

Technical Field

[0001] The present invention relates to the field of integration, and more particularly, to electronic devices in which differential signals are used. Background Art

[0002] Many current electronic devices use pairs of conductors or wires to transmit complementary signals in a technique known to those skilled in the art as differential signaling. Each conductor in these pairs of conductors transmits a signal that is complementary to the signal received on the other conductor.

[0003] Such a pair of conductors or lines is often referred to as a differential pair, or a differential transmission line pair, or a differential transmission conductor pair.

[0004] In many devices, there is a need to provide DC isolation between active circuits that are connected together and that may use different DC supply voltages.

[0005] Typically, a discrete capacitor is connected in series between the two sections of the conductors in the differential pair, one for each differential channel. Multilayer ceramic capacitors (MLCC) capacitors are commonly used in current circuits.

[0006] Due to the need for smaller devices, smaller MLCC capacitors are now used. However, MLCC capacitors have several disadvantages that will be Figure 1A and Figure 1B more clearly presented in the view.

[0007] Figure 1A 1 is a schematic perspective view of an example of an arrangement according to the prior art. The arrangement comprises a board 100 which may be a PCB. On this PCB 100 several differential line pairs 101 have been printed. Each pair 101 comprises two lines 102 extending on the surface of the board 100. Each line 102 is provided with a capacitor 103 connected in series in the middle of the line 102.

[0008] It has been observed that while MLCC capacitors can be manufactured in small sizes, the solder pads 104 used to connect these capacitors to the lines 102 limit the number of capacitors that can be connected adjacently in an area of ​​a board such as board 100. In addition, various rules associated with the manufacturing processes to be used when using MLCC capacitors (e.g., keep-out zones, etc.) limit the number of capacitors that can be connected adjacently.

[0009] This is due to design rules that generally require compliance with critical distances between adjacent solder pads, such as solder pad 104 .

[0010] Furthermore, on circuits with several differential pairs, it is often required that the lines all have the same characteristic impedance, and this often results in an arrangement where the capacitors are preferably aligned and there are gaps with a constant gap width between the pairs.

[0011] In a differential pair, the wires are also preferably of the same length. This results in the use of a larger surface area, as shown in the figure, where the capacitors are distributed in a direction substantially orthogonal to the general direction of the current that can circulate in the wires. In addition, for a given pair of wires, the gap cannot have a constant gap width due to the constraints of the manufacturing process used.

[0012] Due to the thickness of capacitors 103, it has been observed that parasitic capacitors may appear between capacitors 103 arranged as shown. This phenomenon is known as parasitic coupling and has an impact on the characteristic impedance of the differential pair.

[0013] Figure 1B yes Figure 1A Top view of the device.

[0014] It would therefore be desirable to have a device that shows limited parasitic coupling between capacitors, limited surface area occupation and still provides good DC blocking.

[0015] According to the prior art, documents US 8373967, US 10470296 and US 10475786 disclose known arrangements of capacitors on differential line pairs.

[0016] The present invention has been made in view of the above-mentioned problems. Summary of the invention

[0017] The present invention provides an electronic device comprising a board provided with a pair of differential transmission lines, each line of the pair having an opening extending between two line terminals, and a capacitor module comprising:

[0018] base;

[0019] Two 3D capacitors are supported by the base, each 3D capacitor including two capacitor terminals connected to two line terminals of one of the pair of transmission lines, respectively.

[0020] The inventors of the present invention have observed that by using 3D capacitors, the size of the overall device can be reduced while maintaining good capacitance values.

[0021] The two 3D capacitors are arranged using a base, here a single base, that will support them, and the two 3D capacitors can be arranged closer to each other, and more particularly closer to each other than two discrete 3D capacitors. The use of a single base for the two 3D capacitors will also facilitate, for example, handling and connecting the two capacitors in a single step. In fact, fewer assembly steps are required, such as pick-and-place steps and positioning steps.

[0022] For example, a 3D capacitor includes a functional electrode presenting a concave-convex shape (for example, it includes a surface presenting a concave-convex shape, or it is formed on a concave-convex shape such as a hole, a hole, a groove or a column). A 3D capacitor can also be defined as: including functional electrodes extending in three directions orthogonal to each other (for example, two directions parallel to the base and one direction orthogonal to the base). In the present invention, a functional electrode is an electrode facing another electrode of the capacitor and participating in the capacitance of the device. The capacitor terminal may be included in the functional electrode, partially included in the functional electrode, or may be connected to the functional electrode. A functional electrode extending in three directions is a functional electrode having an outer surface extending in these three directions.

[0023] It should be noted that being supported by the base means that the two 3D capacitors may be formed in or on the base.

[0024] According to a specific embodiment, the 3D capacitor includes electrodes arranged to form a 3D structure having a size less than 200 microns between two parallel portions.

[0025] For example, the two parallel parts can be parallel walls of a groove, two opposite walls of a column or hole, two diametrically opposite walls of a hole. These examples are examples of vertically parallel parts of functional electrodes of a 3D capacitor, and these examples can be separated by a distance of less than 10 microns.

[0026] Furthermore, the two parallel portions may be the top portion and the bottom portion of the groove / hole / cavity / pillar. These examples are examples of horizontal parallel portions, and these examples may be separated by a distance of less than 200 microns.

[0027] This embodiment is obtained by using micromachining techniques such as those used in the semiconductor industry.

[0028] According to an embodiment, the two 3D capacitors are formed using at least one common manufacturing step.

[0029] The common manufacturing step may be a material deposition step, an etching step, a photolithography step or any manufacturing step that allows for the parallel manufacturing of two features belonging to two 3D capacitors, respectively.

[0030] With common fabrication steps, it will be appreciated that a single step may allow the same features to be formed in both 3D capacitors.

[0031] According to a specific embodiment, the capacitor module has a symmetry plane separating the two 3D capacitors.

[0032] The inventors of the present invention have observed that comprising a capacitor module with a plane of symmetry ensures that the differential characteristic impedance of the device is well controlled: for a signal travelling through both capacitors, there is no difference in the distance travelled between the two capacitors.

[0033] According to a specific embodiment, the wires of the differential transmission line pair extend in a straight direction near the capacitor module.

[0034] Since a base supporting two 3D capacitors is used, the following straight line can be used: Figure 1A and Figure 1B The turns, enlargements and tapers required for welding that are visible on the prior art devices of the present invention are shown in FIG. For example, a wire extending in a straight direction may have two edges that remain parallel in the vicinity.

[0035] Those skilled in the art understand what is meant by being near a capacitor module. As an example, being near means being within a distance of less than a few millimeters, such as less than 500 micrometers, or less than 1 millimeter, or less than 5 millimeters, or less than 10 millimeters.

[0036] According to a particular embodiment, the base comprises an insulating region separating the two 3D capacitors.

[0037] The material included in the insulating region may be selected so as to have insulating and / or dielectric properties to better control the differential characteristic impedance within the capacitor module. For example, silicon may be used, in particular undoped or low-doped silicon (close to intrinsic).

[0038] According to a specific embodiment, the base includes a semiconductor material, and each 3D capacitor includes: at least one electrode, which includes a semiconductor material structure formed in the shape of a groove, a hole or a pillar; a dielectric layer arranged on the semiconductor material structure in a conformal manner; and another electrode arranged on the dielectric layer in a conformal manner.

[0039] As an example, this embodiment may implement a structure as disclosed in document WO2007125510 for each capacitor.

[0040] In this embodiment, the walls of the trenches, holes or pillars may be doped to form the electrodes of each capacitor, and undoped or lowly doped silicon may be used to isolate the two 3D capacitors.

[0041] According to a specific embodiment, the base includes a material having a porous region in which pores extend along a first direction (from a face of a layer including the material, the first direction being, for example, orthogonal to the face) for each 3D capacitor, each 3D capacitor including: an electrode arranged in a conformal manner at least inside the pores of the porous region of the capacitor; a dielectric layer arranged in a conformal manner on the electrode at least inside the pores of the porous region of the capacitor; and another electrode arranged in a conformal manner on the dielectric layer at least inside the pores of the porous region.

[0042] This embodiment can be implemented using the method disclosed in document WO 2015 / 063420 to produce two 3D capacitors. In this document, holes are made in porous anodized aluminum.

[0043] According to a particular embodiment, the base further comprises a semiconductor region arranged below the region comprising the material having the porous region.

[0044] For example, the semiconductor region may include silicon.The present invention is not limited to the use of a semiconductor substrate, and the 3D capacitor of the present embodiment may be formed on various substrates such as a glass substrate or formed over an integrated circuit.

[0045] According to a particular embodiment, the plate comprises a face supporting a pair of transmission lines, the capacitor modules being connected on said face of the plate.

[0046] It should be noted that the invention is not limited to capacitor modules being connected on the face of a board, but also relates to arrangements in which the capacitor modules are, for example, embedded in a board.

[0047] In this embodiment, a pair of transmission lines can be printed on this face of the board, and the capacitor modules are then placed close to the lines, which limits the distance the signal has to travel from the lines to the capacitors and back.

[0048] According to a particular embodiment, the two 3D capacitors are supported by the side of the base facing the face of the plate.

[0049] This particular embodiment enables the two 3D capacitors to be as close to the line pair as possible. Therefore, the presence of the 3D capacitors hardly affects the propagation of the signal in the line, and the differential characteristic impedance is well controlled. Also, by supported, it is meant that the two 3D capacitors can be on this side of the base; or in the case where they are made in the base, the two 3D capacitors can appear on this side of the base.

[0050] According to a specific embodiment, the two capacitor terminals are respectively connected to two line terminals of one line of a pair of transmission lines using conductive bumps.

[0051] The use of conductive bumps enables the use of a technique known to those skilled in the art as flip chip. This technique helps to reduce the surface area occupied on the board relative to standard solder pads.

[0052] Alternatively, wires may be used to connect the capacitor terminals.

[0053] According to a specific embodiment, the surface of the board supports multiple pairs of differential transmission lines, and wherein the capacitor module includes, for each pair of differential transmission lines, two 3D capacitors of the 3D capacitor arranged on the base, the 3D capacitor having two capacitor terminals, which are respectively connected to two terminals of a line from one of the multiple pairs.

[0054] In this particular embodiment, all differential transmission line pairs may be parallel and straight at least in the vicinity of the capacitor module (ie, within a distance that is substantially the width of the capacitor module).

[0055] Furthermore, preferably all of the 3D capacitors are oriented in the same direction and aligned in a direction substantially orthogonal to the general direction of a pair of differential transmission lines.

[0056] The present invention also provides a communication module comprising the electronic device as defined above.

[0057] The communication module may be, for example, an optical communication module or any communication module requiring the use of differential transmission lines.

[0058] The present invention also provides a method for manufacturing an electronic device, comprising:

[0059] - obtaining a board equipped with a pair of differential transmission lines, each line of the pair having an opening extending between two line terminals,

[0060] - obtaining a capacitor module comprising a base and two 3D capacitors supported by the base, each 3D capacitor comprising two capacitor terminals,

[0061] -Connect the two capacitor terminals of each capacitor to the two line terminals respectively.

[0062] The method may be adapted to manufacture any of the different embodiments of the device as defined above.

[0063] According to a particular embodiment, the electrodes of the 3D capacitor are formed using a manufacturing process selected to obtain a 3D structure having dimensions smaller than 200 micrometers between two parallel portions.

[0064] According to a particular embodiment, the method comprises at least one common manufacturing step for forming two 3D capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Further features and advantages of the present invention will become apparent from the following description of specific embodiments of the invention given by way of illustration only and not by way of limitation with reference to the accompanying drawings, in which:

[0066] - Already described Figure 1A and Figure 1B is an example of an apparatus according to the prior art,

[0067] - Figure 2A and Figure 2B is a schematic representation of an electronic device according to an example,

[0068] - Figure 3 is an example of a capacitor module in which trenches are used,

[0069] - Figure 4 is an example of a capacitor module in which a porous region is used,

[0070] - Figure 5A and Figure 5B is an example where there are multiple differential transmission line pairs. DETAILED DESCRIPTION

[0071] An embodiment of an electronic device in which a capacitor embedded in a capacitor module is mounted on a differential line pair arranged on a board will now be described.

[0072] The electronic device according to the embodiments may be used in any communication module (eg, an optical communication module) that requires the use of differential lines.

[0073] Figure 2A is a perspective view of a device comprising a base 200, which is a PCB, typically comprising epoxy or ceramic.

[0074] On this base 200, a differential transmission line pair 201 has been printed (other alternatives are possible where the lines are etched or patterned). The line pair comprises four line segments shown on the visible part of the device. These segments comprise a segment 202A and a segment 202A' of a first line and a segment 202B and a segment 202B' of a second line. The two segments 202A and 202A' of the first line are separated by an opening which will be described below. Figure 2B The two segments 202B and 202B' of the second line are separated by an opening which will be described below. Figure 2B Visible above.

[0075] In order to block the DC component of the signal transmitted through the differential pair 201, the capacitor module CM is used.

[0076] The capacitor module CM includes a first capacitor 204A and a second capacitor 204B.

[0077] As can be seen in the figure, the capacitors 204A and 204B are arranged as close as possible to the face of the board 200 that supports the differential transmission line pair 201. This makes it possible to keep the differential impedance as close as possible to that of the lines.

[0078] The capacitor 204A and the capacitor 204B are 3D capacitors, and examples of 3D capacitors will be given below.

[0079] In this figure, line terminals 205A (at the end of segment 202A), line terminals 205A' (at the end of segment 202A'), line terminals 205B (at the end of segment 202B), and line terminals 205B' (at the end of segment 202B') are also visible. These line terminals are separated by the openings mentioned above, and capacitors 204A and 204B have capacitor terminals connected to these line terminals in a manner that will be referred to in detail. Figure 2B To describe it more accurately.

[0080] Figure 2B is along Figure 2A The figure shows how capacitor 204 is arranged close to board 200 when capacitor 204A is arranged on the side of the base facing the face of the board supporting differential line pairs 201 .

[0081] In this figure, an opening OP is visible between the line terminal 205A and the line terminal 205A'.

[0082] The figure also shows that the capacitor module CM includes capacitor terminals 206A and 206A'. Figure 2A Also shown are conductive bumps 207A and 207A' that form electrical contacts between capacitor terminal 206A and line terminal 205A and between capacitor terminal 206A' and line terminal 205A', respectively. The capacitor module CM is assembled with the line terminals using a flip chip method.

[0083] In the example shown, there is one conductive bump per capacitor electrode: for the capacitor module CM, there are four bumps. This facilitates the arrangement of the capacitor module CM and prevents any tilting when the device is arranged. Thus, a good differential characteristic impedance is obtained and the propagation of the signal is hardly affected.

[0084] Furthermore, preferably, the conductive bump has substantially the same shape as the line terminal and the capacitor terminal, which ensures good control of the differential characteristic impedance.

[0085] It should be noted that Figure 2A and Figure 2B The capacitor module presents a symmetry plane between the two capacitors passing through the capacitor module CM.

[0086] Figure 3 Two 3D capacitors are shown formed in a capacitor module CM', which can be used as Figure 2A and Figure 2B The capacitor module CM in the embodiment.

[0087] The capacitor module CM′ comprises a base 303 which is a semiconductor substrate comprising silicon, gallium arsenide or even gallium nitride.

[0088] Two trenches TRA and TRB are formed in the base 303. The walls of these two trenches may be doped (represented in the figure by doped regions DRA and DRB) so as to be conductive and act as capacitor electrodes and more precisely functional capacitor electrodes.

[0089] To form the first 3D capacitor 304A, the trench TRA is filled with a dielectric layer 310 , a first conductive layer 311 , a second dielectric layer 312 , and a second conductive layer 313 .

[0090] The second 3D capacitor 304 is formed by filling the trench TRB with the dielectric layer 320 , the first conductive layer 321 , the second dielectric layer 322 , and the second conductive layer 323 .

[0091] A person skilled in the art will appreciate that the structure obtained is a MIMIM structure: a metal-insulator-metal-insulator-metal structure, which allows two capacitors to be connected in parallel to obtain a single capacitor with increased capacitance. It should be noted that all capacitor modules described herein can be formed using MIM or MIMIM structures. Furthermore, in the examples shown, for simplicity, the interconnections between the electrodes of the capacitors are not fully shown.

[0092] It should be noted that forming the two 3D capacitors 304A and 304B may be accomplished using common fabrication steps.

[0093] For example, the formation of two trenches TRA and TRB can be completed simultaneously in a single step, the deposition of dielectric layers 310 and 320 can be completed simultaneously in a single step, the deposition of conductive layers 311 and 321 can be completed simultaneously in a single step, the deposition of dielectric layers 312 and 322 can be completed simultaneously in a single step, and the deposition of dielectric layers 313 and 323 can be completed simultaneously in a single step.

[0094] It should be noted that the use of a common step ensures that the resulting features have very similar characteristics in terms of size and material, which will then translate into good control of the differential characteristic impedance: the device is well balanced.

[0095] To access the electrodes of the capacitor, terminals 307A, 307A', 307B and 307B' are formed to obtain connections with layers 313, 311, 323 and 321. Although not shown, doped regions DRA and DRB will be connected to layers 313 and 323 respectively to form parallel capacitors.

[0096] In the example shown, trenches TRA and TRB may have a depth of less than 200 microns and a width of less than 10 microns.

[0097] However, the invention is not limited to grooves and also encompasses the use of holes, posts, etc.

[0098] It should be noted that in the example shown, the two 3D capacitors are formed in the same silicon substrate, which has very low conductivity and can be considered insulating by those skilled in the art: the relative dielectric constant of silicon has a value of 11.68 which is acceptable for setting the characteristic impedance.

[0099] Figure 4 Another example of two 3D capacitors formed in a capacitor module CM" is shown, which can be used as Figure 2A and Figure 2B The capacitor module CM in the embodiment.

[0100] The capacitor module CM″ includes a base 403, which may include a semiconductor material. For example, the base may include active components formed in silicon and may be a complete integrated circuit or a silicon substrate without any components.

[0101] There are two porous regions PRA and PRB formed in the aluminum oxide layer ALA above the base 403. The two porous regions are porous anodic aluminum oxide (AAO) or any other material with pores extending from the face.

[0102] To form the first 3D capacitor 404A, the porous region is filled with a first conductive layer 410 , a dielectric layer 411 , and a second conductive layer 412 .

[0103] To form the second 3D capacitor 404B, the porous region is filled with the first conductive layer 420 , the dielectric layer 421 , and the second conductive layer 422 .

[0104] A person skilled in the art will understand that the structure obtained is a MIM structure: a metal-insulator-metal structure. However, a MIMIM structure may also be used in the porous region.

[0105] It should be noted that forming the two 3D capacitors 404A and 404B may be accomplished using common fabrication steps.

[0106] For example, forming two porous regions PRA and PRB may be simultaneously completed in a single step, depositing conductive layers 410 and 420 may be simultaneously completed in a single step, depositing dielectric layers 411 and 421 may be simultaneously completed in a single step, and depositing conductive layers 412 and 422 may be simultaneously completed in a single step.

[0107] To access the electrodes of the capacitor, terminals 407A, 407A', 407B, and 407B' are formed to obtain connections to layers 412, 410, 422, and 420, respectively.

[0108] In the example shown, the porous region may have a depth of a few micrometers to tens of micrometers.

[0109] It should be noted that in the example shown, the two 3D capacitors are insulated from each other by the aluminum oxide of the aluminum oxide layer ALA.

[0110] Figure 5A The invention includes supporting a plurality of differential transmission line pairs 501 (with reference to Figure 2A and Figure 2B 201 ), each line pair includes a line segment 502 .

[0111] In the portion of the device visible on the diagram, the line segments are all straight, with no shoulders introducing a length difference between two line pairs.

[0112] The electronic device further comprises a capacitor module CM'', the capacitor module CM''' comprising two capacitors 504, the capacitors 504 being used to connect each pair of Figure 2A and Figure 2B Capacitors 204A and 204B are connected to the line in substantially the same manner.

[0113] Figure 5B yes Figure 5A A perspective view of the device.

[0114] Although the invention has been described above with reference to certain specific embodiments, it should be understood that the invention is not limited to the particularities of the specific embodiments. Numerous variations, modifications and developments may be made to the above-described embodiments within the scope of the appended claims.

Claims

1. An electronic device comprising a board (200), the board (200) comprising a face supporting a pair (201) of differential transmission lines (202A, 202A', 202B, 202B'), each line of the pair having an opening (OP) extending between two line terminals (205A, 205A', 205B, 205B'), the device further comprising a capacitor module (CM), the capacitor module (CM) comprising: base (203), Two 3D capacitors (204A, 204B) supported by a side of the base facing the surface of the board supporting the pair of differential transmission lines, each 3D capacitor comprising two capacitor terminals (206A, 206A'), the two capacitor terminals being respectively connected to the two line terminals of one of the pair of transmission lines so as to be as close as possible to the surface of the board supporting the pair of differential transmission lines, wherein the 3D capacitor comprises a functional electrode presenting a concave and convex shape.

2. The device according to claim 1, wherein: The 3D capacitor includes electrodes arranged to form a 3D structure having a size less than 200 microns between two parallel portions.

3. The device according to claim 1 or 2, wherein: The two 3D capacitors are formed using at least one common manufacturing step.

4. The device according to claim 1 or 2, wherein: The capacitor module has a symmetry plane separating the two 3D capacitors.

5. The device according to claim 1 or 2, wherein: The lines of the pair of differential transmission lines extend in a straight direction near the capacitor module.

6. The device according to claim 1 or 2, wherein: The base includes an insulating region separating the two 3D capacitors.

7. The device according to claim 1 or 2, wherein: The base includes a semiconductor material, and each 3D capacitor includes: at least one electrode, the electrode including a semiconductor material structure formed in the shape of a groove, a hole or a pillar; a dielectric layer arranged on the semiconductor material structure in a conformal manner; and another electrode arranged on the dielectric layer in a conformal manner.

8. The device according to claim 1 or 2, wherein: The base includes a material having a porous region with pores extending along a first direction for each 3D capacitor, each 3D capacitor including: an electrode arranged in a conformal manner at least inside the pores of the porous region of the capacitor; a dielectric layer arranged in a conformal manner on the electrode at least inside the pores of the porous region of the capacitor; and another electrode arranged in a conformal manner on the dielectric layer at least inside the pores of the porous region.

9. The device according to claim 8, wherein: The base further comprises a semiconductor region arranged below the region comprising the material having the porous region.

10. The device according to claim 1 or 2, wherein: The two capacitor terminals are respectively connected to the two line terminals of one line of the pair of transmission lines using conductive bumps.

11. The device according to claim 1 or 2, wherein: The face of the board supports a plurality of pairs of the differential transmission lines, and wherein the capacitor module comprises, for each pair of differential transmission lines, two of the 3D capacitors arranged on the base, the 3D capacitor having two capacitor terminals, the two capacitor terminals being respectively connected to two terminals of one line of one of the plurality of pairs.

12. A communication module comprising the electronic device according to any one of claims 1 to 11.

13. A method for manufacturing an electronic device, the method comprising: - obtaining a board (200) comprising a face supporting a pair (201) of differential transmission lines (202A, 202A', 202B, 202B'), each line of the pair having an opening (OP) extending between two line terminals (205A, 205A', 205B, 205B'), - obtaining a capacitor module comprising a base (203) and two 3D capacitors (204A, 204B) supported by a side of the base facing the face of the board supporting the pair of differential transmission lines, each 3D capacitor comprising two capacitor terminals (206A, 206A'), wherein the 3D capacitors comprise functional electrodes presenting concave and convex shapes, - connecting the two capacitor terminals of each capacitor to the two line terminals, respectively, as close as possible to the face of the board supporting the pair of differential transmission lines.

14. The method according to claim 13, wherein: The electrodes of the 3D capacitor are formed using a manufacturing process selected to obtain a 3D structure with dimensions less than 200 microns between the two parallel parts.

15. The method according to claim 13 or 14, comprising at least one common manufacturing step for forming the two 3D capacitors.

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