Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes: a base substrate; a semiconductor material layer on the base substrate; and a plurality of voltage supply lines, which are located on a side of the semiconductor material layer away from the base substrate. In a corresponding sub-pixel, the semiconductor material layer includes an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion, and the third node portion is connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the corresponding sub-pixel. At least 30% of the orthographic projection of the third node portion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line of each row and a drain terminal connected to a data line of each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] In one aspect, the present disclosure provides an array substrate, comprising: a base substrate; a semiconductor material layer on the base substrate; and a plurality of voltage supply lines, which are located on a side of the semiconductor material layer away from the base substrate; wherein, in a corresponding sub-pixel, the semiconductor material layer includes an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion, and the third node portion is connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the corresponding sub-pixel; and at least 30% of the orthographic projection of the third node portion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

[0004] Optionally, the third node portion continuously includes a first part and a second part; the first part is connected to the active layer of the fifth transistor, the active layer of the driving transistor and the second part; the second part connects the first part to the active layer of the third transistor; and the orthographic projection of the first part on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

[0005] Optionally, the array substrate also includes: a gate insulating layer, which is located on a side of the semiconductor material layer away from the base substrate; and a plurality of gate lines, which are located on a side of the gate insulating layer away from the base substrate; wherein the orthographic projection of the active layer of the third transistor on the base substrate overlaps with the orthographic projection of the corresponding gate line on the base substrate; and the orthographic projection of the active layer of the fifth transistor on the base substrate overlaps with the orthographic projection of the corresponding light-emitting control signal line on the base substrate.

[0006] Optionally, in the corresponding sub-pixel, the corresponding voltage supply line continuously includes a first wide portion, a narrow portion and a second wide portion; wherein the orthographic projection of the first wide portion on the base substrate at least partially overlaps with the orthographic projection of the second portion on the base substrate; the orthographic projection of the narrow portion on the base substrate does not overlap with the orthographic projection of the semiconductor material layer on the base substrate; the orthographic projection of the second wide portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the fifth transistor on the base substrate and the orthographic projection of the corresponding light-emitting control signal line on the base substrate; and the average line width of the narrow portion is smaller than the average line width of the first wide portion, and smaller than the average line width of the second wide portion.

[0007] Optionally, the array substrate also includes: an insulating layer, which is located on a side of the semiconductor material layer away from the base substrate; a second capacitor electrode of the storage capacitor, which is located on a side of the insulating layer away from the base substrate; and an interlayer dielectric layer, which is located on a side of the second capacitor electrode away from the base substrate; wherein the first wide portion is connected to the second capacitor electrode of the storage capacitor via a ninth through hole extending through the interlayer dielectric layer.

[0008] Optionally, in the corresponding sub-pixel, the corresponding voltage supply line also includes a first segment connected to the first wide portion; and the orthographic projection of the first segment on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the base substrate and the orthographic projection of the corresponding gate line on the base substrate.

[0009] Optionally, in an adjacent sub-pixel immediately adjacent to the corresponding sub-pixel, the semiconductor material layer includes an active layer of a second transistor, an active layer of a fourth transistor, an active layer of a driving transistor, and a second node portion, the second node portion being connected to the active layer of the second transistor, the active layer of the fourth transistor, and the active layer of the driving transistor in the adjacent sub-pixel; and an orthographic projection of the second node portion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

[0010] Optionally, the narrow portion of the corresponding voltage supply line in the corresponding sub-pixel is located at least between the second node portion and the third node portion; and the orthographic projection of the narrow portion on the base substrate does not overlap with the orthographic projection of the second node portion on the base substrate, and does not overlap with the orthographic projection of the third node portion on the base substrate.

[0011] Optionally, the array substrate further comprises a plurality of gate lines located on a side of the semiconductor material layer away from the base substrate; wherein, in the corresponding sub-pixel, the corresponding gate line comprises a main body portion extending along an extension direction of the corresponding gate line and a gate protrusion protruding away from the main body portion; an orthographic projection of the gate protrusion on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor on the base substrate; and at least 90% of the orthographic projection of the gate protrusion on the base substrate does not overlap with an orthographic projection of a corresponding voltage supply line on the base substrate.

[0012] Optionally, the array substrate also includes a plurality of reset control signal lines located on a side of the semiconductor material layer away from the base substrate; wherein, in the corresponding sub-pixels, the corresponding voltage supply line continuously includes a third segment, a fourth segment and a fifth segment, and the fourth segment connects the third segment and the fifth segment; the orthographic projection of the fourth segment on the base substrate at least partially overlaps with the orthographic projection of the corresponding reset control signal line on the base substrate; and the average line width of the fourth segment is smaller than the average line width of the third segment and smaller than the average line width of the fifth segment.

[0013] On the other hand, the present disclosure provides an array substrate, comprising: a base substrate; a semiconductor material layer on the base substrate; a plurality of gate lines located on a side of the semiconductor material layer away from the base substrate; and a plurality of voltage supply lines located on a side of the plurality of gate lines away from the base substrate; wherein, in a corresponding sub-pixel, the corresponding gate line comprises a main body portion extending along an extension direction of the corresponding gate line and a gate protrusion protruding away from the main body portion; wherein, in the corresponding sub-pixel, the semiconductor material layer comprises an active layer of a third transistor; an orthographic projection of the gate protrusion on the base substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor on the base substrate; and at least 90% of the orthographic projection of the gate protrusion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

[0014] Optionally, the orthographic projection of the gate protrusion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

[0015] Optionally, the array substrate further comprises: a plurality of reset control signal lines, which are located on a side of the semiconductor material layer away from the base substrate; an anti-interference block, which is located on a side of the plurality of reset control signal lines away from the base substrate; and an interlayer dielectric layer, which is located on a side of the anti-interference block away from the base substrate; wherein, in the corresponding sub-pixel, the corresponding voltage supply line continuously comprises a first segment, a second segment, a third segment and a fourth segment; wherein the orthographic projection of the first segment on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the base substrate, and at least partially overlaps with the orthographic projection of the corresponding gate line on the base substrate; the orthographic projection of the fourth segment on the base substrate at least partially overlaps with the orthographic projection of the corresponding reset control signal line on the base substrate; the second segment connects the first segment to the third segment; the third segment connects the second segment to the fourth segment; and the third segment is connected to the anti-interference block via a third through hole extending through the interlayer dielectric layer.

[0016] Optionally, the average line width of the third segment is greater than the average line width of the second segment.

[0017] On the other hand, the present disclosure provides an array substrate, comprising: a base substrate; a plurality of reset control signal lines on the base substrate; and a plurality of voltage supply lines, which are located on a side of the plurality of reset control signal lines away from the base substrate; wherein, in a corresponding sub-pixel, the corresponding voltage supply line continuously includes a third segment, a fourth segment and a fifth segment, and the fourth segment connects the third segment and the fifth segment; the orthographic projection of the fourth segment on the base substrate at least partially overlaps with the orthographic projection of the corresponding reset control signal line on the base substrate; and the average line width of the fourth segment is smaller than the average line width of the third segment and smaller than the average line width of the fifth segment.

[0018] Optionally, the array substrate further comprises a plurality of reset signal lines located on a side of the plurality of reset control signal lines away from the base substrate; wherein the orthographic projection of the fifth segment on the base substrate at least partially overlaps with the orthographic projection of the corresponding reset signal line on the base substrate.

[0019] Optionally, the array substrate also includes: an anti-interference block, which is located on the side of the multiple reset control signal lines away from the base substrate; and an interlayer dielectric layer, which is located on the side of the anti-interference block away from the base substrate; wherein the third segment is connected to the anti-interference block via a third through hole extending through the interlayer dielectric layer.

[0020] Optionally, the array substrate also includes a semiconductor material layer on the base substrate; wherein, in a sub-pixel of the previous level and adjacent to the corresponding sub-pixel, the semiconductor material layer includes an active layer of a sixth transistor; and an orthographic projection of the corresponding reset control signal line on the base substrate at least partially overlaps with an orthographic projection of the active layer of the sixth transistor on the base substrate; and at least 80% of the orthographic projection of the active layer of the sixth transistor in the sub-pixel of the previous level on the base substrate does not overlap with the orthographic projection of the fourth segment on the base substrate.

[0021] In another aspect, the present disclosure provides a display device, including an array substrate described herein or manufactured by the method described herein and an integrated circuit connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0023] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0024] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0025] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0026] Figure 3A is a diagram showing the structure of multiple sub-pixels of an array substrate in some embodiments of the present disclosure.

[0027] Figure 3B It is shown Figure 3A A diagram showing the structure of semiconductor material layers in multiple sub-pixels of an array substrate.

[0028] Figure 3C It is shown Figure 3A A diagram showing the structure of the first conductive layer in multiple sub-pixels of an array substrate.

[0029] Figure 3D It is shown Figure 3A A diagram showing the structure of the second conductive layer in multiple sub-pixels of an array substrate.

[0030] Figure 3E It is shown Figure 3A A diagram showing the structure of the first signal line layer in multiple sub-pixels of an array substrate.

[0031] Figure 3FIt is shown Figure 3A A diagram showing the structure of the second signal line layer in multiple sub-pixels of an array substrate.

[0032] Figure 4A is along Figure 3A Cross-sectional view along line A-A'.

[0033] Figure 4B is along Figure 3A Cross-sectional view along line BB'.

[0034] Figure 4C is along Figure 3A Cross-sectional view along line CC'.

[0035] Figure 4D is along Figure 3A Cross-sectional view along line D-D'.

[0036] Figure 4E is along Figure 3A Cross-sectional view along line E-E'.

[0037] Figure 4F is along Figure 3A Cross-sectional view along line F-F'.

[0038] Figure 4G is along Figure 3A Cross-sectional view along line G-G'.

[0039] Figure 5A is a diagram showing a semiconductor material layer, a first conductive layer, and a first signal line layer in an array substrate according to some embodiments of the present disclosure.

[0040] Figure 5B yes Figure 5A A magnified view of the area around the third node in .

[0041] Figure 5C It is shown Figure 5B Diagram of the partial structure of the semiconductor material layer in the corresponding sub-pixel.

[0042] Figure 5D It is shown Figure 5B FIG. 5 is a diagram of a partial structure of a corresponding voltage supply line.

[0043] Figure 5E It is shown Figure 5B Diagram of the partial structure of semiconductor material layers in adjacent sub-pixels.

[0044] Fig. 6A yes Figure 3A A magnified view of the area around the anti-interference block.

[0045] Figure 6B It is shown Fig. 6A Figure 2. Partial structure of the corresponding grid line in FIG.

[0046] Figure 6C It is shown Fig. 6A FIG. 5 is a diagram of a partial structure of a corresponding voltage supply line.

[0047] Fig.6D It is shown Fig. 6A Diagram of the partial structure of the semiconductor material layer in the corresponding sub-pixel. DETAILED DESCRIPTION

[0048] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0049] The present disclosure provides, in particular, an array substrate and a display device, which substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes: a base substrate; a semiconductor material layer on the base substrate; and a plurality of voltage supply lines, which are located on the side of the semiconductor material layer away from the base substrate. Optionally, in the corresponding sub-pixel, the semiconductor material layer includes an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion, and the third node portion is connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the corresponding sub-pixel. Optionally, at least 30% of the positive projection of the third node portion on the base substrate does not overlap with the positive projection of the corresponding voltage supply line on the base substrate.

[0050] Various suitable pixel driving circuits can be used in the present array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the present array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0051] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1, the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by each pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of sensing signal lines SL, a plurality of voltage supply lines (e.g., a high voltage supply line Vdd) and each second voltage supply line (e.g., a low voltage supply line Vss), each of which is electrically connected to each pixel driving circuit PDC. The light emission of each sub-pixel sp is driven by each pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to each pixel driving circuit PDC connected to the anode of the light-emitting element through the high voltage supply line Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element through the low voltage supply line Vss. The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light. The array substrate according to the present disclosure includes a plurality of sensing signal lines SL, which are respectively connected to the sensing sub-circuits in the plurality of pixel driving circuits.

[0052] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to each reset control signal line rstN of a current stage, a source connected to each reset signal line VintN of a current stage of a plurality of reset signal lines, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding one of a plurality of gate lines GL, a source connected to a corresponding one of a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; a third transistor T3 having a gate connected to the corresponding gate line, a source connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the driving transistor The pixel driving circuit further comprises a switching transistor Tw, which has a gate connected to a corresponding light emitting control signal line SW, a source connected to the drain of the driving transistor Td and the drain of the third transistor T3, and a drain connected to the anode of the light emitting element LE; and a sixth transistor T6, which has a gate connected to a reset control signal line rst(N+1) of the next stage, a source connected to a reset signal line Vint(N+1) of the next stage, and a drain connected to the drain of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source of the fourth transistor T4. The pixel driving circuit also includes a switching transistor Tw, which has a gate connected to the switching control signal line SW, a source connected to each data line, and a drain connected to the source of the second transistor T2.

[0053] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2B In some embodiments, the third transistor T3 is a "dual gate" transistor and the first transistor T1 is a "dual gate" transistor. Optionally, in the "dual gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual gate" third transistor, the active layer of the third transistor T3 crosses the corresponding gate line of the plurality of gate lines GL twice (alternatively, the corresponding gate line crosses the active layer of the third transistor T3 twice).

[0054] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1 and the source of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2 and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the drain of the third transistor T3 and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light emitting element LE.

[0055] Figure 3A is a diagram showing the structure of each sub-pixel of an array substrate in some embodiments of the present disclosure. Figure 3A In some embodiments, the array substrate includes a plurality of sub-pixels (e.g., red sub-pixels, green sub-pixels, and blue sub-pixels). In some embodiments, the array substrate includes a plurality of gate lines GL extending along the first direction DR1, a plurality of data lines DL extending along the second direction DR2, and a plurality of voltage supply lines Vdd extending along the second direction DR2. Optionally, the array substrate further includes a plurality of reset control signal lines extending along the first direction DR1 (including the reset control signal line rstN of the current stage and the reset control signal line rst(N+1) of the next stage); a plurality of reset signal lines extending along the first direction DR1 (including the reset signal line VintN of the current stage and the reset signal line Vinit(N+1) of the next stage); and a plurality of light emitting control signal lines em extending along the first direction DR1. Figure 3A 2 depicts the corresponding positions of multiple transistors in the pixel driving circuit. The pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0056] Figure 3B It is shown Figure 3A A diagram showing the structure of the semiconductor material layer in each sub-pixel of the array substrate. Figure 3C It is shown Figure 3A A diagram showing the structure of the first conductive layer in each sub-pixel of the array substrate. Figure 3D It is shown Figure 3A A diagram showing the structure of the second conductive layer in each sub-pixel of the array substrate. Figure 3E It is shown Figure 3A A diagram showing the structure of the first signal line layer in each sub-pixel of the array substrate. Figure 3F It is shown Figure 3A A diagram showing the structure of the second signal line layer in multiple sub-pixels of an array substrate. Figure 4A is along Figure 3A Cross-sectional view along line A-A'. Figure 4B is along Figure 3A Cross-sectional view of line BB' in Fig. FIG. 3A to FIG. 3F as well as FIG. 4A to FIG. 4B In some embodiments, the array substrate includes a base substrate BS, a semiconductor material layer SML on the base substrate BS, a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS, a first conductive layer located on a side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on a side of the first conductive layer away from the gate insulating layer GI, a second conductive layer located on a side of the insulating layer IN away from the first conductive layer, an interlayer dielectric layer ILD located on a side of the second conductive layer away from the insulating layer IN, a first signal line layer located on a side of the interlayer dielectric layer ILD away from the second conductive layer, a first planarization layer PLN1 located on a side of the signal line layer away from the interlayer dielectric layer ILD, a second signal line layer located on a side of the first planarization layer ILD away from the first signal line layer, and a second planarization layer PLN2 located on a side of the second signal line layer away from the first planarization layer PLN1.

[0057] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3B In some embodiments, in each sub-pixel sp, the semiconductor material layer has an integral structure. Figure 3BIn the figure, each sub-pixel sp is marked with a mark indicating the area corresponding to multiple transistors in each pixel driving circuit, which include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td. Each sub-pixel sp is also marked with a mark indicating the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The sixth transistor T6 includes an active layer ACT6, a source S6, and a drain D6. The driving transistor Td includes an active layer ACTd, a source Sd, and a drain Dd. In one example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), source (S1, S2, S3, S4, S5, S6, and Sd), and drain (D1, D2, D3, D4, D5, D6, and Dd) of the transistor (T1, T2, T3, T4, T5, T6, and Td) in each sub-pixel are part of the overall structure in each sub-pixel sp. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), source (S1, S2, S3, S4, S5, S6, and Sd), and drain (D1, D2, D3, D4, D5, D6, and Dd) of the transistor (T1, T2, T3, T4, T5, T6, and Td) are in the same layer.

[0058] As used herein, an active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, the orthographic projection of at least a portion of the semiconductor material layer on the base substrate overlaps with the orthographic projection of the gate on the base substrate. As used herein, a source electrode refers to a component of a transistor connected to one side of the active layer, and a drain electrode refers to a component of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, the orthographic projection of the first portion of the semiconductor material layer on the base substrate overlaps with the orthographic projection of the first gate on the base substrate, and the orthographic projection of the second portion of the semiconductor material layer on the base substrate overlaps with the orthographic projection of the second gate on the base substrate. In the case of a dual-gate transistor, a source electrode refers to a component of a transistor connected to the first portion on a side away from the third portion, and a drain electrode refers to a component of a transistor connected to the second portion on a side away from the third portion.

[0059] Reference Figure 2A , Figure 2B , Figure 3A , Figure 3C , Figure 4A as well as Figure 4B In some embodiments, the first conductive layer includes a plurality of gate lines GL, a plurality of reset control signal lines (including the respective reset control signal lines rstN of the current stage and the reset control signal line rst(N+1) of the next stage), a plurality of light emitting control signal lines em, and a first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, the plurality of gate lines GL, the plurality of reset control signal lines, the plurality of light emitting control signal lines em, and the first capacitor electrode Ce1 are in the same layer.

[0060] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the plurality of gate lines GL and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process performed in the same material layer, the plurality of gate lines GL and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the steps of forming the plurality of gate lines GL and the steps of forming the first capacitor electrode Ce1, the plurality of gate lines GL and the first capacitor electrode Ce1 may be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0061] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3DIn some embodiments, the second conductive layer includes a plurality of reset signal lines (including each reset signal line VintN of the current stage and the reset signal line Vinit(N+1) of the next stage), an anti-interference block IPB and a second capacitor electrode Ce2 of the storage capacitor Cst. The anti-interference block IPB can effectively reduce crosstalk, especially the vertical crosstalk between the N1 nodes of adjacent data lines. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of reset signal lines, the second capacitor electrode Ce2 and the anti-interference block IPB are located in the same layer.

[0062] Reference Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3E In some embodiments, the first signal line layer includes a plurality of voltage supply lines Vdd, a node connection line Cln, a first initialization connection line Cli1, a second initialization connection line Cli2, and an anode contact pad ACP. The node connection line Cln connects the first capacitor electrode Ce1 and the source of the third transistor T3 in the corresponding sub-pixel sp together. The first initialization connection line Cli1 connects the corresponding reset signal line (e.g., the reset signal line VintN of the current stage) among the plurality of reset signal lines and the source S1 of the first transistor T1 in the corresponding sub-pixel sp together. The second initialization connection line Cli2 connects the corresponding reset signal line (e.g., the reset signal line Vinit(n+1) of the next stage) among the plurality of reset signal lines and the source S6 of the sixth transistor T6 in the corresponding sub-pixel sp together. The anode contact pad ACP connects the source S5 of the fifth transistor T5 in the corresponding sub-pixel sp to the anode in the corresponding sub-pixel sp. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the signal line layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of voltage supply lines Vdd, node connection lines Cln, first initialization connection lines Cli1, second initialization connection lines Cli2 and anode contact pads ACP are located on the same layer.

[0063] Reference Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3F In some embodiments, the second signal line layer includes a plurality of data lines DL. Optionally, the second signal line layer further includes an anode contact pad ACP in each of the plurality of sub-pixels sp. The anode contact pad ACP is electrically connected to a source of a fifth transistor T5 in each of the plurality of sub-pixels sp through a relay electrode in each of the plurality of sub-pixels sp. Figure 2A , Figure 3A , Figure 3F , Figure 3E and Figure 4B In some embodiments, each of the multiple data lines DL is connected to the connecting part CP through a through hole v4-1 extending through the first planarization layer PLN-1, and the connecting part CP is connected to the source S2 of the second transistor through a through hole v4-2 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0064] Reference Figure 2A , Figure 3A , Figure 3D , Figure 3E and Figure 4A In some embodiments, except for the hole area H in which a portion of the second capacitor electrode Ce2 does not exist, the orthographic projection of the second capacitor electrode Ce2 on the base substrate BS completely covers the orthographic projection of the first capacitor electrode Ce1 on the base substrate BS, leaving a margin. In some embodiments, the first signal line layer includes a node connection line Cln, which is located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located on the same layer as the plurality of voltage supply lines Vdd. Optionally, the array substrate further includes a first through hole v1 located in the hole area H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first through hole v1. In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the base substrate BS. Optionally, the array substrate further includes a first through hole v1 and a second through hole v2. The first through hole v1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second through hole v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first through hole v1 and is connected to the semiconductor material layer SML through the second through hole v2. Optionally, the node connection line Cln is connected to the source S3 of the third transistor, as shown in FIG. Figure 4A shown.

[0065] refer to Figure 2A , Figure 3A , Figure 3E and Figure 4B , in some embodiments, the anti-interference block IPB is in the same layer as the second capacitor electrode Ce2. Each of the multiple voltage supply lines Vdd is connected to the anti-interference block IPB through a third through hole v3. Optionally, the third through hole v3 extends through the interlayer dielectric layer ILD. Optionally, the positive projection of the anti-interference block IPB on the base substrate BS partially overlaps with the positive projection of the corresponding voltage supply line in the multiple voltage supply lines Vdd on the base substrate BS. Optionally, the positive projection of the anti-interference block IPB on the base substrate BS overlaps at least partially with the positive projection of the active layer ACT3 of the third transistor T3 on the base substrate BS. Optionally, the positive projection of the anti-interference block IPB on the base substrate BS overlaps at least partially with the positive projection of the drain D1 of the first transistor T1 on the base substrate BS. In addition, each of the multiple voltage supply lines Vdd is connected to the second capacitor electrode Ce2 through a ninth through hole v9. Optionally, the ninth through hole v9 extends through the interlayer dielectric layer ILD. Alternatively, an orthographic projection of the second capacitor electrode Ce2 on the base substrate BS partially overlaps with an orthographic projection of a corresponding voltage supply line among the plurality of voltage supply lines Vdd on the base substrate BS.

[0066] refer to Figure 2A , Figure 3A , Figure 3E and Figure 4B In some embodiments, each of the plurality of data lines DL is connected to the connection portion CP via a through hole v4-1 extending through the first planarization layer PLN-1, and the connection portion CP is connected to the source S2 of the second transistor via a through hole v4-2 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0067] Figure 4C is along Figure 3A Cross-sectional view of line C-C' in FIG. Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3E and Figure 4CIn some embodiments, the first initialization connection line Cli1 connects a corresponding reset signal line among a plurality of reset signal lines (e.g., the reset signal line VintN of the current stage) to the source S1 of the first transistor T1 in the corresponding sub-pixel sp. The corresponding reset signal line among the plurality of reset signal lines (e.g., the reset signal line VintN of the current stage) is configured to provide a reset signal to the source S1 of the first transistor T1 in the corresponding sub-pixel through the first initialization connection line Cli1. Optionally, the first initialization connection line Cli1 is connected to the reset signal line VintN of the current stage through a fifth through hole v5 extending through the interlayer dielectric layer ILD. Optionally, the first initialization connection line Cli1 is connected to the source S1 of the first transistor T1 in the corresponding sub-pixel through a sixth through hole v6 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0068] Figure 4D is along Figure 3A Cross-sectional view of line D-D' in FIG. Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3E and Figure 4D In some embodiments, the second initialization connection line Cli2 connects a corresponding reset signal line among the plurality of reset signal lines (e.g., the reset signal line Vinit(N+1) of the next stage) to the source S6 of the sixth transistor T6 in the corresponding sub-pixel sp. A corresponding reset signal line among the plurality of reset signal lines (e.g., the reset signal line Vinit(N+1) of the next stage) is configured to provide a reset signal to the source S6 of the sixth transistor T6 in the corresponding sub-pixel through the second initialization connection line Cli2. Optionally, the second initialization connection line Cli2 is connected to the reset signal line Vinit(N+1) of the next stage through a seventh through hole v7 extending through the interlayer dielectric layer ILD. Optionally, the second initialization connection line Cli2 is connected to the source S6 of the sixth transistor T6 in the corresponding sub-pixel through an eighth through hole v8 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0069] Figure 5A is a diagram showing a semiconductor material layer, a first conductive layer, and a first signal line layer in an array substrate according to some embodiments of the present disclosure. Figure 5B yes Figure 5A A magnified view of the area around the third node in . Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5BIn some embodiments, the array substrate includes a base substrate BS; a semiconductor material layer SML on the base substrate; and a plurality of voltage supply lines Vdd located on a side of the semiconductor material layer SML away from the base substrate BS. Optionally, in each sub-pixel sp, the semiconductor material layer SML includes an active layer ACT3 of a third transistor T3, an active layer ACT5 of a fifth transistor T5, an active layer ACTd of a driving transistor Td, and a third node portion NP3 connected to the active layer ACT3 of the third transistor T3, the active layer ACT5 of the fifth transistor T5, and the active layer ACTd of the driving transistor Td in each sub-pixel sp. Reference Figure 2A , Figure 2B , Figure 3A , Figure 5A and Figure 5B , the third node portion NP3 is a portion of the semiconductor material layer having the third node N3.

[0070] In one example, the boundary of the third node portion NP3 is defined by the corresponding boundary of the adjacent active layer. In another example, the boundary of the adjacent active layer is defined by the positive projection of the corresponding gate on the semiconductor material layer SML. For example, the boundary of the active layer ACT3 of the third transistor T3 is defined by the positive projection of the corresponding gate line on the semiconductor material layer SML; the boundary of the active layer ACT5 of the fifth transistor T5 is defined by the positive projection of the corresponding light emitting control signal line on the semiconductor material layer SML; the boundary of the active layer ACTd of the driving transistor Td is defined by the positive projection of the first capacitor electrode Ce1 (used as the gate of the driving transistor Td) on the semiconductor material layer SML. Therefore, in some embodiments, the boundary of the third node portion NP3 is defined by the adjacent boundary of the active layer ACT3 of the third transistor T3, the adjacent boundary of the active layer ACT5 of the fifth transistor T5, and the adjacent boundary of the active layer ACTd of the driving transistor Td.

[0071] The inventors of the present disclosure have found that the parasitic capacitance between the corresponding voltage supply line and the third node N3 may unnecessarily increase the minimum charging time for charging the driving transistor T3 (e.g., by charging the N1 node). The inventors of the present disclosure have found that, surprisingly and unexpectedly, minimizing the parasitic capacitance between the corresponding voltage supply line and the third node N3 can reduce the minimum charging time for charging the driving transistor T3, achieve faster response and enhance image display quality.

[0072] Therefore, each voltage signal line in the present disclosure has a non-uniform line width. For example, the line width of a portion of the corresponding voltage signal line around the third node N3 is smaller than the line width of a portion immediately adjacent to the portion around the third node N3. The complex structure of the corresponding voltage signal line in the present disclosure reduces the overlap between the corresponding voltage signal line and the third node portion NP3, thereby reducing the parasitic capacitance between the corresponding voltage supply line and the third node N3.

[0073] In some embodiments, at least 30% (e.g., at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) of the orthographic projection of the third node portion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate. Optionally, at least 50% of the orthographic projection of the third node portion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

[0074] Figure 4E is along Figure 3A Cross-sectional view along line E-E'. Figure 4F is along Figure 3A Cross-sectional view of line F-F' in FIG. Figure 4E and Figure 5A , along the row direction (e.g., perpendicular to the extension direction of the corresponding voltage supply line), the orthogonal projection of at least a portion of the corresponding voltage supply line on the base substrate BS does not overlap with the orthogonal projection of at least a portion of the semiconductor material layer SML on the base substrate BS, and the orthogonal projection of at least a portion of the corresponding voltage supply line is between the source Sd of the driving transistor Td in the adjacent sub-pixel ASp immediately adjacent to the corresponding sub-pixel RSp and the drain Dd of the driving transistor Td in the corresponding sub-pixel RSp. Along the column direction (e.g., parallel to the extension direction of the corresponding voltage supply line), the orthogonal projection of the corresponding voltage supply line on the base substrate BS does not overlap with the orthogonal projection of the semiconductor material layer SML on the base substrate BS at least partially. In one example, along the column direction, the orthogonal projection of the corresponding voltage supply line on the base substrate BS does not overlap with the orthogonal projection of the drain Dd of the driving transistor Td in the corresponding sub-pixel RSp on the base substrate BS at least partially; and does not overlap with the orthogonal projection of the source S5 of the fifth transistor T5 in the corresponding sub-pixel RSp on the base substrate BS at least partially.

[0075] Figure 5C It is shown Figure 5B Figure 1 shows a partial structure of a semiconductor material layer in a corresponding sub-pixel in FIG. Figure 3A , Figure 5A , Figure 5B and Figure 5CIn some embodiments, the third node portion NP3 continuously includes a first portion P1 and a second portion P2. The first portion P1 is connected to the active layer ACT5 of the fifth transistor T5, the active layer ACTd of the driving transistor Td, and the second portion P2. The second portion P2 connects the first portion P1 to the active layer ACT3 of the third transistor T3. Figure 3A , Figure 5A , Figure 5B , Figure 5C and Figure 4F In some embodiments, the orthographic projection of the first portion P1 does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate BS, wherein the orthographic projection of the second portion P2 at least partially overlaps with the orthographic projection of the corresponding voltage supply line on the base substrate BS. The orthographic projection of the active layer ACT3 of the third transistor T3 on the base substrate BS overlaps with the orthographic projection of the corresponding gate line among the plurality of gate lines GL on the base substrate BS. The orthographic projection of the active layer ACT5 of the fifth transistor T5 on the base substrate BS overlaps with the orthographic projection of the corresponding light emitting control signal line among the plurality of light emitting control signal lines em on the base substrate BS.

[0076] Optionally, the first portion P1 includes at least a portion of the drain Dd of the driving transistor Td in the corresponding sub-pixel RSp. Optionally, the first portion P1 includes at least a portion of the source S5 of the fifth transistor T5 in the corresponding sub-pixel RSp. Optionally, the second portion P2 includes at least a portion of the drain D3 of the third transistor T3 in the corresponding sub-pixel RSp.

[0077] Figure 5D It is shown Figure 5B FIG. 10 is a diagram of a partial structure of a corresponding voltage supply line. Figure 3A , Figure 5A , Figure 5B and Figure 5D In the corresponding sub-pixel RSp, in some embodiments, the corresponding voltage supply line among the plurality of voltage supply lines Vdd continuously includes a first wide portion WP1, a narrow portion NP, and a second wide portion WP2. The narrow portion NP connects the first wide portion WP1 and the second wide portion WP2 together.

[0078] refer to Figure 3A , Figure 5A , Figure 5B , Figure 5D , Figure 4E and Figure 4FIn some embodiments, the orthographic projection of the first wide portion WP1 on the base substrate BS at least partially overlaps with the orthographic projection of the second portion P2 on the base substrate BS. Optionally, the orthographic projection of the first wide portion WP1 on the base substrate BS covers the orthographic projection of the second portion P2 on the base substrate BS. In some embodiments, the orthographic projection of the narrow portion NP on the base substrate BS does not overlap with the orthographic projection of the semiconductor material layer SML on the base substrate BS. In some embodiments, the orthographic projection of the second wide portion WP2 on the base substrate BS at least partially overlaps with the orthographic projection of the active layer ACT5 of the fifth transistor T5 on the base substrate BS and the orthographic projection of the corresponding light emitting control signal line among the plurality of light emitting control signal lines em on the base substrate BS.

[0079] In some embodiments, the first wide portion WP1 has an average line width wp1, the narrow portion NP has an average line width wn, and the second wide portion WP2 has an average line width wp2. Optionally, the average line width wn is smaller than the average line width wp1, and smaller than the average line width wp2.

[0080] refer to Figure 3A , Figure 5A , Figure 5B , Figure 5D and Figure 4B In some embodiments, the first wide portion WP1 is a portion of the corresponding voltage supply line connected to the second capacitor electrode Ce2 of the storage capacitor through a ninth via v9 extending through the interlayer dielectric layer ILD.

[0081] refer to Figure 3A , Figure 5A , Figure 5B , Figure 5D , Figure 4E and Figure 4F , in some embodiments, in the corresponding sub-pixel RSp, in some embodiments, the corresponding voltage supply line of the plurality of voltage supply lines Vdd continuously includes a first segment F1, a first wide portion WP1, a narrow portion NP, and a second wide portion WP2. The narrow portion NP connects the first wide portion WP1 and the second wide portion WP2 together. The first wide portion WP1 connects the first segment F1 and the narrow portion NP together. The orthographic projection of the first segment F1 on the base substrate BS overlaps at least partially with the orthographic projection of the active layer ACT3 of the third transistor T3 in the corresponding sub-pixel RSp on the base substrate BS and the orthographic projection of the corresponding gate line of the plurality of gate lines GL on the base substrate BS. The orthographic projection of the boundary between the first segment F1 and the first wide portion WP1 on the base substrate BS overlaps with the orthographic projection of the boundary between the active layer ACT3 of the third transistor T3 and the second portion P2 on the base substrate BS.

[0082] Figure 5AThe corresponding subpixel RSp and the adjacent subpixel ASp immediately adjacent to the corresponding subpixel RSp are shown. In one example, the corresponding subpixel RSp and the adjacent subpixel ASp are two immediately adjacent subpixels along the row direction (eg, parallel to the extension direction of each gate line). Figure 5E It is shown Figure 5B FIG. 1 is a diagram of a partial structure of a semiconductor material layer in adjacent sub-pixels. Figure 3A , Figure 5A , Figure 5B , Figure 5D , Figure 5E and Figure 4E , in the adjacent sub-pixel ASp immediately adjacent to the corresponding sub-pixel RSp, the semiconductor material layer SML includes an active layer ACT2 of the second transistor T2, an active layer ACT4 of the fourth transistor T4, an active layer ACTd of the driving transistor Td, and a second node portion NP2. The second node portion NP2 is connected to the active layer ACT2 of the second transistor T2, the active layer ACT4 of the fourth transistor T4, and the active layer ACTd of the driving transistor Td in the adjacent sub-pixel ASp. Figure 2A , Figure 2B , Figure 3A , Figure 5A , Figure 5B and Figure 5E , the second node portion NP2 is a portion of the semiconductor material layer having the second node N2. In some embodiments, at least 80% (e.g., at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the second node portion NP2 on the base substrate BS does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate BS. Figure 4E In one example, an orthographic projection of the second node portion NP2 on the base substrate BS does not overlap with an orthographic projection of the corresponding voltage supply line on the base substrate BS.

[0083] refer to Figure 3A , FIG. 5A to FIG. 5E , Figure 4E and Figure 4F , the narrow portion NP of the corresponding voltage supply line in the corresponding sub-pixel RSp is at least between the second node portion NP2 and the third node portion NP3, more specifically, between the second node portion NP2 and the first portion P1. The orthographic projection of the narrow portion NP on the base substrate BS does not overlap with the orthographic projection of the second node portion NP2 on the base substrate BS, and does not overlap with the orthographic projection of the third node portion NP3 on the base substrate BS.

[0084] The inventors of the present disclosure have found that the overlap between the multiple voltage supply lines Vdd and the multiple gate lines GL increases the load of the multiple gate lines GL. Reducing the overlap area between the multiple voltage supply lines Vdd and the multiple gate lines GL can effectively reduce the load of the multiple gate lines GL, achieve faster response, and improve image display quality.

[0085] Therefore, each voltage signal line in the present disclosure has a non-uniform line width. Fig. 6A yes Figure 3A A magnified view of the area around the anti-interference block. Figure 6B It is shown Fig. 6A Figure 1. The partial structure of the corresponding grid line in FIG. Figure 3A , Fig. 6A and Figure 6B In the corresponding sub-pixel, in some embodiments, the corresponding gate line among the plurality of gate lines GL includes a main body portion MP extending along the extension direction of the corresponding gate line, and a gate protrusion GP protruding away from the main body portion MP, for example, protruding toward the anti-interference block IPB. Optionally, the gate protrusion GP protrudes away from the main body portion MP along the column direction (for example, a direction perpendicular to the extension direction of the corresponding gate line).

[0086] In some embodiments, as described above, the third transistor T3 is a dual-gate transistor. In some embodiments, the gate protrusion GP is one of the dual gates in the third transistor T3. Figure 4A , the orthographic projection of the gate protrusion GP on the base substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the base substrate BS. In order to reduce the load of the plurality of gate lines GL, at least 90% (e.g., at least 95%, at least 98%, at least 99% or 100%) of the orthographic projection of the gate protrusion GP on the base substrate BS does not overlap with the orthographic projection of the corresponding voltage supply line among the plurality of voltage supply lines Vdd on the base substrate BS. Figure 3A , Fig. 6A , Figure 6B and Figure 4A Optionally, an orthographic projection of the gate protrusion GP on the base substrate BS does not overlap with an orthographic projection of a corresponding voltage supply line on the base substrate BS.

[0087] Figure 6C It is shown Fig. 6A FIG. 10 is a diagram of a partial structure of a corresponding voltage supply line. Figure 3A , Fig. 6A , Figure 6B and Figure 6CIn some embodiments, in a corresponding sub-pixel, a corresponding voltage supply line among the plurality of voltage supply lines Vdd continuously includes a first segment F1, a second segment F2, a third segment F3, and a fourth segment F4. The second segment F2 connects the first segment F1 to the third segment F3. The third segment F3 connects the second segment F2 to the fourth segment F4. Figure 3A , Fig. 6A , Figure 6B , Figure 6C and Figure 4B , the third segment F3 is a segment of the corresponding voltage supply line connected to the anti-interference block IPB through a third via v3 extending through the interlayer dielectric layer ILD.

[0088] Reference Figure 4F In some embodiments, the orthographic projection of the first segment F1 on the base substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the base substrate BS, and at least partially overlaps with the orthographic projection of the corresponding gate line among the plurality of gate lines GL on the base substrate BS. The orthographic projection of the fourth segment F4 on the base substrate BS at least partially overlaps with the orthographic projection of the corresponding reset control signal line (e.g., the corresponding reset control signal line rstN of the current stage) on the base substrate BS.

[0089] Reference Figure 6C , the average line width of the second segment F2 is wf2. The average line width of the third segment F3 is wf3. Optionally, the average line width wf3 is greater than the average line width wf2.

[0090] Fig.6D It is shown Fig. 6A Figure 1 shows a partial structure of a semiconductor material layer in a corresponding sub-pixel in FIG. Figure 3A , Fig. 6A , Figure 6B , Figure 6C and Fig.6D In some embodiments, the active layer ACT3 of the third transistor T3 includes a first overlapping portion Po1, a second overlapping portion Po2, and an intermediate portion Pi connecting the first overlapping portion Po1 and the second overlapping portion Po2. Figure 4F , the orthographic projection of the first overlapping portion Po1 on the base substrate BS is covered by the orthographic projection of the corresponding gate line GL among the plurality of gate lines GL on the base substrate BS. Figure 4A , the orthographic projection of the second overlapping portion Po2 on the base substrate BS is covered by the orthographic projection of the gate protrusion GP on the base substrate BS. Figure 4F , an orthographic projection of the middle portion Pi on the base substrate BS at least partially overlaps with an orthographic projection of a corresponding gate line among the plurality of gate lines GL on the base substrate BS.

[0091] Reference Figure 3A , Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Figure 4F In some embodiments, the orthographic projection of the first overlapping portion Po1 on the base substrate BS at least partially overlaps with the orthographic projection of the main portion MP on the base substrate BS. Figure 3A , Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Figure 4A In some embodiments, the orthographic projection of the second overlapping portion Po2 on the base substrate BS at least partially overlaps with the orthographic projection of the gate protrusion GP on the base substrate BS. Figure 3A , Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Figure 4A as well as Figure 4F In some embodiments, the orthographic projection of the middle portion Pi on the base substrate BS does not overlap with the orthographic projection of the corresponding gate line on the base substrate BS. Optionally, the orthographic projection of the corresponding voltage supply line among the plurality of voltage supply lines on the base substrate BS at least partially overlaps with the orthographic projection of the middle portion Pi on the base substrate BS, and at least partially overlaps with the orthographic projection of the first overlapping portion Po1 on the base substrate BS.

[0092] The inventor of the present disclosure has found that the overlap between multiple voltage supply lines Vdd and multiple reset control signal lines increases the load of the multiple reset control signal lines. Reducing the overlap area between multiple voltage supply lines Vdd and multiple reset control signal lines can effectively reduce the load of the multiple reset control signal lines, achieve faster response, and improve image display quality.

[0093] Therefore, the corresponding voltage signal line in the present disclosure has a non-uniform line width. For example, the line width of the portion of the corresponding voltage signal line that intersects the corresponding reset control signal line is smaller than the line width of the portion that is immediately adjacent to the portion that intersects the corresponding reset control signal line. The complex structure of the corresponding voltage signal line in the present disclosure reduces the overlap between the corresponding voltage signal line and the corresponding reset control signal line, thereby reducing the parasitic capacitance between the corresponding voltage supply line and the corresponding reset control signal line.

[0094] refer to Figure 3A , Fig. 6A , Figure 6B , Figure 6C and Fig.6DIn some embodiments, in the corresponding sub-pixel, the corresponding voltage supply line continuously includes a third segment F3, a fourth segment F4, and a fifth segment F5. The fourth segment F4 connects the third segment F3 and the fifth segment F5. In some embodiments, the fourth segment F4 crosses the corresponding reset control signal line (e.g., the corresponding reset control signal line rstN of the current stage or the corresponding reset control signal line rst(N+1) of the next stage). The orthographic projection of the fourth segment F4 on the base substrate BS at least partially overlaps with the orthographic projection of the corresponding reset control signal line on the base substrate BS.

[0095] refer to Figure 6C In some embodiments, the third segment F3 has an average line width wf3; the fourth segment F4 has an average line width wf4; and the fifth segment F5 has an average line width wf5. Optionally, the average line width wf4 is smaller than the average line width wf3, and smaller than the average line width wf5.

[0096] Reference Figure 3A , Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Figure 4F In some embodiments, the orthographic projection of the fifth segment F5 on the base substrate BS at least partially overlaps with the orthographic projection of the corresponding reset signal line (eg, the corresponding reset signal line VintN of the current stage or the corresponding reset signal line Vint(N+1) of the next stage) on the base substrate BS. Figure 3A , Fig. 6A , Figure 6B , Figure 6C and Figure 4B , the third segment F3 is a segment of the corresponding voltage supply line connected to the anti-interference block IPB through a third via v3 extending through the interlayer dielectric layer ILD.

[0097] Figure 4G is along Figure 3A Cross-sectional view of line G-G' in Fig. Figure 3A , Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Figure 4G, in the sub-pixel PSASp of the previous stage and immediately adjacent to the corresponding sub-pixel RSp, the semiconductor material layer includes the active layer ACT6 of the sixth transistor T6. The orthographic projection of the corresponding reset control signal line (for example, the corresponding reset control signal line rstN at the current stage) on the base substrate BS at least partially overlaps with the orthographic projection of the active layer ACT6 of the sixth transistor T6 on the base substrate BS. In some embodiments, at least 80% (for example, at least 85%, at least 90%, at least 95%, at least 99% or 100%) of the orthographic projection of the active layer ACT6 of the sixth transistor T6 in the sub-pixel PSASp of the previous stage on the base substrate BS does not overlap with the orthographic projection of the fourth segment F4 on the base substrate BS. Refer to Figure 4G , the orthographic projection of the active layer ACT6 of the sixth transistor T6 in the sub-pixel PSASp of the previous stage on the base substrate BS does not overlap with the orthographic projection of the fourth segment F4 on the base substrate BS.

[0098] In another aspect, the present disclosure provides a display panel, comprising an array substrate described herein or manufactured by a method described herein and an opposing substrate facing the array substrate. Optionally, the display panel is an organic light emitting diode display panel. Optionally, the display panel is a micro light emitting diode display panel.

[0099] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a liquid crystal display device.

[0100] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a semiconductor material layer on a base substrate; and forming a plurality of voltage supply lines on a side of the semiconductor material layer away from the base substrate. Optionally, in a corresponding sub-pixel, the semiconductor material layer is formed to include an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion. The third node portion is formed to be connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the corresponding sub-pixel. Optionally, at least 30% of the positive projection of the third node portion on the base substrate does not overlap with the positive projection of the corresponding voltage supply line on the base substrate.

[0101] In some embodiments, a method for manufacturing an array substrate includes forming a semiconductor material layer on a base substrate; forming a plurality of gate lines on a side of the semiconductor material layer away from the base substrate; and forming a plurality of voltage supply lines on a side of the plurality of gate lines away from the base substrate. Optionally, in a corresponding sub-pixel, the corresponding gate line is formed to include a main body portion extending along an extension direction of the corresponding gate line and a gate protrusion protruding away from the main body portion. Optionally, in a corresponding sub-pixel, the semiconductor material layer is formed to include an active layer of a third transistor. Optionally, the orthographic projection of the gate protrusion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the base substrate. Optionally, at least 90% of the orthographic projection of the gate protrusion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

[0102] In some embodiments, a method for manufacturing an array substrate includes forming a plurality of reset control signal lines on a base substrate; and forming a plurality of voltage supply lines on a side of the plurality of reset control signal lines away from the base substrate. Optionally, in a corresponding sub-pixel, the corresponding voltage supply line is formed to include a third segment, a fourth segment, and a fifth segment arranged in series. Optionally, the fourth segment is formed to connect the third segment and the fifth segment. Optionally, the orthographic projection of the fourth segment on the base substrate overlaps at least partially with the orthographic projection of the corresponding reset control signal line on the base substrate. Optionally, the average line width of the fourth segment is less than the average line width of the third segment and less than the average line width of the fifth segment.

[0103] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising: base substrate; a layer of semiconductor material on the base substrate; as well as a plurality of voltage supply lines located on a side of the semiconductor material layer away from the base substrate; wherein, in a corresponding sub-pixel, the semiconductor material layer includes an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion, and the third node portion is connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the corresponding sub-pixel; and at least 30% of the orthographic projection of the third node portion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate; The third node portion continuously includes the first portion and the second portion; The first portion is connected to the active layer of the fifth transistor, the active layer of the driving transistor, and the second portion; The second portion connects the first portion to an active layer of the third transistor; and an orthographic projection of the first portion on the base substrate and a orthographic projection of the corresponding voltage supply line on the base substrate that do not overlap; In the corresponding sub-pixel, the corresponding voltage supply line continuously includes a first wide portion, a narrow portion, and a second wide portion; wherein an orthographic projection of the first wide portion on the base substrate at least partially overlaps with an orthographic projection of the second portion on the base substrate; The orthographic projection of the narrow portion on the base substrate does not overlap with the orthographic projection of the semiconductor material layer on the base substrate; The orthographic projection of the second wide portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the fifth transistor on the base substrate and the orthographic projection of the corresponding light emitting control signal line on the base substrate; and An average line width of the narrow portion is smaller than an average line width of the first wide portion, and smaller than an average line width of the second wide portion.

2. The array substrate according to claim 1, further comprising: a gate insulating layer, which is located on a side of the semiconductor material layer away from the base substrate; as well as A plurality of gate lines, which are located on a side of the gate insulating layer away from the base substrate; wherein the orthographic projection of the active layer of the third transistor on the base substrate overlaps with the orthographic projection of the corresponding gate line on the base substrate; as well as An orthographic projection of an active layer of the fifth transistor on the base substrate overlaps with an orthographic projection of a corresponding light emitting control signal line on the base substrate.

3. The array substrate according to claim 1 or 2, further comprising: an insulating layer, which is located on a side of the semiconductor material layer away from the base substrate; a second capacitor electrode of a storage capacitor, which is located on a side of the insulating layer away from the base substrate; as well as an interlayer dielectric layer located on a side of the second capacitor electrode away from the base substrate; Wherein, the first wide portion is connected to the second capacitor electrode of the storage capacitor through a ninth through hole extending through the interlayer dielectric layer.

4. The array substrate according to any one of claims 1 to 3, wherein: In the corresponding sub-pixel, the corresponding voltage supply line further includes a first segment connected to the first wide portion; as well as An orthographic projection of the first segment on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor on the base substrate and an orthographic projection of a corresponding gate line on the base substrate.

5. The array substrate according to any one of claims 1 to 4, wherein: In an adjacent sub-pixel immediately adjacent to the corresponding sub-pixel, the semiconductor material layer includes an active layer of a second transistor, an active layer of a fourth transistor, an active layer of a driving transistor, and a second node portion, the second node portion being connected to the active layer of the second transistor, the active layer of the fourth transistor, and the active layer of the driving transistor in the adjacent sub-pixel; as well as An orthographic projection of the second node portion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

6. The array substrate according to claim 5, wherein: The narrow portion of the corresponding voltage supply line in the corresponding sub-pixel is located at least between the second node portion and the third node portion; as well as An orthographic projection of the narrow portion on the base substrate does not overlap with an orthographic projection of the second node portion on the base substrate, and does not overlap with an orthographic projection of the third node portion on the base substrate.

7. The array substrate according to any one of claims 1 to 6, further comprising a plurality of gate lines located on a side of the semiconductor material layer away from the base substrate; in, In the corresponding sub-pixel, the corresponding gate line includes a main body portion extending along an extending direction of the corresponding gate line and a gate protrusion protruding away from the main body portion; An orthographic projection of the gate protrusion on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor on the base substrate; as well as At least 90% of the orthographic projection of the gate protrusion on the base substrate does not overlap with an orthographic projection of a corresponding voltage supply line on the base substrate.

8. The array substrate according to any one of claims 1 to 7, further comprising a plurality of reset control signal lines located on a side of the semiconductor material layer away from the base substrate; in, In the corresponding sub-pixel, the corresponding voltage supply line continuously includes a third segment, a fourth segment, and a fifth segment, and the fourth segment connects the third segment and the fifth segment; The orthographic projection of the fourth segment on the base substrate at least partially overlaps with the orthographic projection of the corresponding reset control signal line on the base substrate; as well as The average line width of the fourth segment is smaller than the average line width of the third segment and smaller than the average line width of the fifth segment.

9. An array substrate, comprising: base substrate; a layer of semiconductor material on the base substrate; A plurality of gate lines, which are located on a side of the semiconductor material layer away from the base substrate; as well as a plurality of voltage supply lines, which are located on a side of the plurality of gate lines away from the base substrate; Wherein, in the corresponding sub-pixel, the corresponding gate line includes a main body portion extending along an extending direction of the corresponding gate line and a gate protrusion protruding away from the main body portion; Wherein, in the corresponding sub-pixel, the semiconductor material layer includes an active layer of a third transistor; An orthographic projection of the gate protrusion on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor on the base substrate; and At least 90% of the orthographic projection of the gate protrusion on the base substrate does not overlap with an orthographic projection of a corresponding voltage supply line on the base substrate.

10. The array substrate according to claim 9, wherein: The orthographic projection of the gate protrusion on the base substrate does not overlap with the orthographic projection of the corresponding voltage supply line on the base substrate.

11. The array substrate according to claim 9 or 10, further comprising: A plurality of reset control signal lines, which are located on a side of the semiconductor material layer away from the base substrate; an anti-interference block, which is located at a side of the plurality of reset control signal lines away from the base substrate; as well as an interlayer dielectric layer, which is located on a side of the anti-interference block away from the base substrate; wherein, in the corresponding sub-pixel, the corresponding voltage supply line continuously includes a first segment, a second segment, a third segment and a fourth segment; wherein the orthographic projection of the first segment on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the base substrate, and at least partially overlaps with the orthographic projection of the corresponding gate line on the base substrate; The orthographic projection of the fourth segment on the base substrate at least partially overlaps with the orthographic projection of the corresponding reset control signal line on the base substrate; The second segment connects the first segment to the third segment; The third segment connects the second segment to the fourth segment; and The third segment is connected to the anti-tamper block through a third via extending through the interlayer dielectric layer.

12. The array substrate according to claim 11, wherein: The average line width of the third segment is greater than the average line width of the second segment.

13. An array substrate, comprising: base substrate; a plurality of reset control signal lines on the base substrate; as well as a plurality of voltage supply lines located on a side of the plurality of reset control signal lines away from the base substrate; wherein, in the corresponding sub-pixel, the corresponding voltage supply line continuously includes a third segment, a fourth segment and a fifth segment, and the fourth segment connects the third segment and the fifth segment; The orthographic projection of the fourth segment on the base substrate at least partially overlaps with the orthographic projection of the corresponding reset control signal line on the base substrate; as well as The average line width of the fourth segment is smaller than the average line width of the third segment and smaller than the average line width of the fifth segment.

14. The array substrate according to claim 13, further comprising a plurality of reset signal lines located on a side of the plurality of reset control signal lines away from the base substrate; in, An orthographic projection of the fifth segment on the base substrate at least partially overlaps with an orthographic projection of a corresponding reset signal line on the base substrate.

15. The array substrate according to claim 13 or 14, further comprising: an anti-interference block, which is located at a side of the plurality of reset control signal lines away from the base substrate; as well as an interlayer dielectric layer, which is located on a side of the anti-interference block away from the base substrate; The third segment is connected to the anti-interference block via a third through hole extending through the interlayer dielectric layer.

16. The array substrate according to any one of claims 13 to 15, further comprising a semiconductor material layer on the base substrate; in, In a sub-pixel of a previous stage and immediately adjacent to the corresponding sub-pixel, the semiconductor material layer includes an active layer of a sixth transistor; as well as The orthographic projection of the corresponding reset control signal line on the base substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the base substrate; as well as At least 80% of an orthographic projection of an active layer of the sixth transistor in the sub-pixel of the previous stage on the base substrate does not overlap with an orthographic projection of the fourth segment on the base substrate. 17 . A display device comprising the array substrate according to claim 1 and an integrated circuit connected to the array substrate.

Images