eFuse Testing Method

Abstract

The present invention discloses a test method for an eFuse, comprising: step one, providing a device to be tested consisting of a test structure of an eFuse, including an eFuse and a programming transistor connected in series. Step two, measuring the initial value of the resistance of the eFuse and the second output impedance when the programming transistor is turned on, and adding them to form the actual resistance of the device to be tested. Step three, providing a pulse generator with a built-in resistor, and calculating the pulse voltage setting value of the pulse generator according to the built-in resistor, the actual resistance of the device to be tested and the target voltage of the device to be tested. Step four, rewriting the state, including: turning on the programming transistor. The pulse generator outputs a first pulse signal to the device to be tested according to the pulse voltage setting value to rewrite the state of the eFuse, and the peak voltage value of the first pulse signal is equal to the pulse voltage setting value. Step five, measuring the post-resistance value of the eFuse. The present invention can prevent the situation of insufficient or excessive fusing when the state of the eFuse is rewritten during the test process, thereby improving the measurement accuracy.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit manufacturing method, in particular to an eFuse testing method. Background Art

[0002] Electrically programmable silicided polysilicon fuses, also known as eFuse, have become popular one-time programmable memories due to their ease of use and suitability for integration with logic CMOS. eFuse can be used to deal with certain defects in the chip. Adding these fuses to the chip does not increase the cost, and the speed of each circuit can be controlled, thereby managing the performance and power consumption of the circuit. In addition, eFuse design can also be used to implement Electronic Chip ID (ECID), greatly improving the intelligence of the chip.

[0003] eFuse is formed by P-type silicided polysilicon resistors on shallow trench isolation. The square cathode and anode are connected by a thin resistance wire. One end of the resistance wire is connected to a MOS transistor, and the cathode and anode are connected by test pads. The function of the MOS transistor is mainly to control the fusing operation process of the fuse. Only when the MOS transistor is turned on can the fuse have a large enough current to change the state of the fuse. At the same time, the MOS transistor can limit the excessive current.

[0004] like Figure 1 As shown, it is a structural diagram of the existing eFuse test structure; the device under test (dut) 201 is composed of the test structure of eFuse 101, and the test structure of eFuse 101 includes eFuse 101 and programming transistor 102 connected in series. Figure 1 In the figure, the eFuse 101 is also represented by fuse, and the programming transistor 102 is also represented by Programming Transistor.

[0005] Typically, the test structure of the eFuse 101 further includes a cathode and an anode 103 formed by a metal pad, and the eFuse 101 and the programming transistor 102 are connected in series between the cathode and the anode 103 . Figure 2 In the photo, the anode is individually indicated by the mark 103a and is also indicated by Anode, the cathode is individually indicated by the mark 104a and is also indicated by Cathode. The eFuse is indicated by the mark 101a and is also indicated by Link. Figure 2 Also shown are metal contacts 105 formed on the metal pad surfaces of the anode 103a and the cathode 104a.

[0006] The test structure of the eFuse 101 includes the eFuse 101 and the programming transistor 102 .

[0007] The programming transistor 102 is an NMOS.

[0008] The eFuse 101 is composed of a P-type silicided polysilicon resistor.

[0009] The eFuse 101 is formed on the shallow trench isolation.

[0010] The eFuse 101 is in a filament-like structure, and the cathode and the anode 103 are both in a block-like structure.

[0011] For eFuse testing, the measurement process is also a process of rewriting the eFuse and changing its fuse state. This process is one-time, irreversible, and non-repeatable. Therefore, the measurement accuracy of eFuse is even more important. Keysight 4082F automatic measuring instrument, Keysight B1500 measuring instrument, Guangli T4100S measuring instrument and other models can realize the writing and measurement of eFuse.

[0012] In the existing measuring equipment, there are two options for setting the resistance (Rdut) of the device under test 201: 50 ohms and 1M ohms. The impedance value Rdut of the actual device of eFuse 101 is related to various factors such as design, process, size, etc. The two resistance options of 50 ohms and 1M ohms are prone to the situation where the voltage division on the eFuse 101 is too large or too small, resulting in over-burning or insufficient fusing. Summary of the invention

[0013] The technical problem to be solved by the present invention is to provide an eFuse testing method, which can prevent insufficient or excessive fusing when the eFuse state is rewritten during the test process, thereby improving the measurement accuracy.

[0014] In order to solve the above technical problems, the eFuse testing method provided by the present invention comprises the following steps:

[0015] Step 1: Provide a device under test, wherein the device under test is composed of an eFuse test structure, and the eFuse test structure includes an eFuse and a programming transistor, namely a control transistor, which are connected in series.

[0016] Step 2: measuring the initial resistance value of the eFuse and the second output impedance when the programming transistor is turned on; and forming the actual resistance of the device under test by adding the initial resistance value and the second output impedance.

[0017] Step three: provide a pulse generator, wherein the pulse generator and the device under test have a built-in resistor connected in series, and a pulse voltage setting value of the pulse generator is calculated based on the built-in resistor, the actual resistance of the device under test and the target voltage of the device under test.

[0018] Step 4: rewriting the state of the eFuse of the device under test, including:

[0019] The programming transistor is turned on.

[0020] The pulse generator outputs a first pulse signal to the device under test according to the pulse voltage setting value to rewrite the state of the eFuse, and the peak voltage value of the first pulse signal is equal to the pulse voltage setting value, so that the actual voltage applied to the device under test by the first pulse signal is consistent with the target voltage of the device under test, so as to improve the accuracy of the state rewriting.

[0021] Step 5: Measure the resistance value after the eFuse, and determine whether the state change in step 4 is complete based on the resistance value after the eFuse.

[0022] A further improvement is that the test structure of the eFuse further includes a cathode and an anode formed by a metal pad, and the eFuse and the programming transistor are connected in series between the cathode and the anode.

[0023] A further improvement is that the programming transistor is NMOS or PMOS.

[0024] A further improvement is that the eFuse is composed of a P-type silicided polysilicon resistor.

[0025] A further improvement is that the eFuse is formed on a shallow trench isolation.

[0026] A further improvement is that the eFuse has a filament structure, and the cathode and the anode both have a block structure.

[0027] A further improvement is that the self-contained resistance is 50 ohms.

[0028] A further improvement is that the pulse generator has two built-in impedance options, the resistance values ​​of the two impedance options are 50 ohms and 1 M ohms respectively, for selecting the resistance of the device under test.

[0029] The pulse generator sets a second pulse voltage setting value according to the selected resistance value of the impedance option and the target voltage of the device under test.

[0030] A further improvement is that in step three, the pulse generator calculates the pulse voltage setting value based on the resistance value of one of the impedance options and the corresponding second pulse voltage setting value, the built-in resistance and the actual resistance of the device under test.

[0031] A further improvement is that the formula for calculating the pulse voltage setting value is:

[0032]

[0033] Wherein, Vset' represents the second pulse voltage setting value, Vset represents the pulse voltage setting value, Rdut represents the actual resistance of the device under test, and Rdut' represents the resistance value of one of the impedance options.

[0034] A further improvement is that Vset' is equal to Vf, where Vf represents a voltage value that the user wishes to set, ie, a voltage value expected by the user.

[0035] A further improvement is that the eFuse test structure includes an eFuse and a programming transistor.

[0036] During the testing process of the present invention, before the state of the eFuse is rewritten, in addition to measuring the initial resistance value of the eFuse, the second output impedance when the programming transistor is turned on is also measured, and the initial resistance value and the second output impedance are superimposed to form an accurate actual resistance of the device under test, and then the pulse voltage setting value is calculated according to the actual resistance of the device under test, and then the first pulse signal is formed according to the pulse voltage setting value to achieve the state rewriting of the eFuse. In this way, when the process structure of the eFuse and the programming transistor changes so that the initial resistance value and the second output impedance change, the first pulse signal will also change accordingly, and finally the voltage actually applied to the device under test is consistent with the target voltage of the device under test, thereby preventing insufficient fusing when the actual voltage is less than the target voltage of the device under test and excessive fusing when the actual voltage is greater than the target voltage of the device under test, which can improve the state rewriting accuracy and finally improve the measurement accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0038] Figure 1 It is a structural diagram of the existing eFuse test structure;

[0039] Figure 2 yes Figure 1 Corresponding photos;

[0040] Figure 3 It is a connection diagram of a pulse generator and a device to be tested in an existing eFuse test method;

[0041] Figure 4 is a flow chart of a method for testing eFuse according to an embodiment of the present invention;

[0042] Figure 5 is a comparison curve of the resistance value of the eFuse obtained by the eFuse testing method of the embodiment of the present invention and the existing method;

[0043] Fig. 6A yes Figure 5 A photograph of the device under test corresponding to the middle curve 302;

[0044] Figure 6B yes Figure 5 A photograph of the device under test corresponding to the middle curve 303;

[0045] Figure 6C yes Figure 5 The photograph of the device under test corresponding to the middle curve 304 is shown. DETAILED DESCRIPTION

[0046] Since the present invention is obtained on the basis of analyzing the existing technical problems, before introducing the embodiments of the present invention in detail, the existing eFuse testing method is first introduced in detail:

[0047] The test module for programming eFuse is the pulse generator unit 202 (PGU), and the hardware structure and circuit are as follows: Figure 3 As shown:

[0048] from Figure 3 As can be seen in FIG. 1 , the pulse generator 202 has an inevitable built-in resistor 205, so there is a 50-ohm resistor, i.e., the built-in resistor 205, connected in series with the device under test. The built-in resistor 205 of 50 ohms has a voltage-dividing effect on the pulse signal output by the pulse generator 202, and the actual voltage Vdut of the device under test is:

[0049]

[0050] In order to ensure that the voltage actually applied to the device under test 201 does not change due to the voltage division of the 50 ohm built-in resistor 205, the actual voltage value output from the pulse generator 202 needs to be calculated using formula (1). In the process of calculating the actual output value required by the pulse generator 202, the impedance Rdut of the eFuse 101 must be correctly considered based on the actual circuit situation. If the impedance input value of the eFuse 101 does not match the actual value, assuming that the impedance input value is Rdut', which is not equal to Rdut, the pulse voltage value calculated by the machine from Rdut' is Vset':

[0051]

[0052] From Equation (1) and Equation (2), the relationship between Vset and Vset’ can be obtained:

[0053]

[0054] Considering the size of the device under test 201 in the circuit, the variation range of Rdut is 50 ohm to 1 Mohm. When Rdut > Rdut’, Vset’ > Vset, that is, the pulse voltage applied to eFuse101 is relatively large, and overburn may occur. When Rdut < Rdut’, Vset’ < Vset, that is, the pulse voltage applied to eFuse is relatively small, and it may not be able to be blown. If considering the most extreme case, when Rdut = 50 ohm and Rdut’ = 1 Mohm, Vset’ = 1 / 2 * Vset; when Rdut = 1 Mohm and Rdut’ = 50 ohm, Vset’ = 2 * Vset.

[0055] It can be seen from the above that the existing test method for eFuse101 is to select the resistance of the device under test 201 between 50 ohms and 1 M ohms. This is only a very rough estimated value, which often differs greatly from the actual resistance of the device under test 201, thus easily resulting in overburn or insufficient fusing.

[0056] As Figure 4 shown, it is the flowchart of the test method for eFuse101 in an embodiment of the present invention; for the test structure of the device under test 201 composed of eFuse101 in an embodiment of the present invention, please also refer to Figure 1 shown, and for the connection diagram of the pulse generator 202 and the device under test 201, please also refer to Figure 3 shown. The test method for eFuse101 in an embodiment of the present invention includes the following steps:

[0057] Step 1: As Figure 1 shown, provide the device under test 201, where the device under test 201 is composed of the test structure of eFuse101, and the test structure of eFuse101 includes an eFuse101 and a programming transistor 102 connected in series.

[0058] Figure 1 In , eFuse101 is also represented by fuse, and the programming transistor 102 is also represented by ProgrammingTransistor.

[0059] In the embodiment of the present invention, the test structure of the eFuse 101 further includes a cathode and an anode 103 formed by a metal pad, and the eFuse 101 and the programming transistor 102 are connected in series between the cathode and the anode 103 . Figure 2 In the photo, the anode is individually indicated by the mark 103a and is also indicated by Anode, the cathode is individually indicated by the mark 104a and is also indicated by Cathode. The eFuse is indicated by the mark 101a and is also indicated by Link. Figure 2 Also shown are metal contacts 105 formed on the metal pad surfaces of the anode 103a and the cathode 104a.

[0060] The test structure of the eFuse 101 includes the eFuse 101 and the programming transistor 102 .

[0061] The programming transistor 102 is an NMOS. In other embodiments, it can also be: or the programming transistor 102 is a PMOS.

[0062] The eFuse 101 is composed of a P-type silicided polysilicon resistor.

[0063] The eFuse 101 is formed on the shallow trench isolation.

[0064] The eFuse 101 is in a filament-like structure, and the cathode and the anode 103 are both in a block-like structure.

[0065] Step 2: Measure the initial resistance value of the eFuse 101 and the second output impedance when the programming transistor 102 is turned on; and form the actual resistance of the device under test by adding the initial resistance value and the second output impedance.

[0066] Step 3: Figure 3 As shown, a pulse generator 202 is provided, and the pulse generator 202 has a built-in resistor 205 connected in series with the device under test 201. The pulse voltage setting value of the pulse generator 202 is calculated according to the built-in resistor 205, the actual resistance of the device under test and the target voltage of the device under test 201.

[0067] Figure 3 In the embodiment, the pulse generator 202 further includes a pulse source 203 and a voltmeter 204. The self-contained resistor 205 is also represented by Input Impedance of SPGU, and the pulse source 203 is represented by Pulse Source. The subsequent first pulse signal 206 is output by the pulse source 203. Figure 3 The first pulse signal 206 corresponding to the mark 206 is an enlarged view of the pulse in the pulse source 203 .

[0068] The built-in resistor 205 is 50 ohms.

[0069] The pulse generator 202 has two built-in impedance options, and the resistance values ​​of the two impedance options are 50 ohms and 1 M ohms respectively, which are used to select the resistance of the device under test 201 .

[0070] The pulse generator 202 sets a second pulse voltage setting value according to the resistance value of the selected impedance option and the target voltage of the device under test 201 .

[0071] In the embodiment of the present invention, the pulse generator 202 calculates the pulse voltage setting value according to the resistance value of one of the impedance options and the corresponding second pulse voltage setting value, the built-in resistor 205 and the actual resistance of the device under test.

[0072] The formula for calculating the pulse voltage setting value is:

[0073]

[0074] Wherein, Vset' represents the second pulse voltage setting value, Vset represents the pulse voltage setting value, Rdut represents the actual resistance of the device under test, and Rdut' represents the resistance value of one of the impedance options.

[0075] Vset' is equal to Vf, and Vf represents the voltage value that the user wants to set, that is, the user's expected voltage value.

[0076] In formula (3), since Vset', Rdut' and Rdut are all known values, Vset can be calculated by formula (3).

[0077] Step 4: rewriting the state of the eFuse 101 of the device under test 201, including:

[0078] The programming transistor 102 is turned on.

[0079] The pulse generator 202 outputs a first pulse signal 206 to the device under test 201 according to the pulse voltage setting value to rewrite the state of the eFuse 101. The peak voltage value of the first pulse signal 206 is equal to the pulse voltage setting value, so that the actual voltage added to the device under test 201 by the first pulse signal 206 is consistent with the target voltage of the device under test 201, so as to improve the accuracy of the state rewriting.

[0080] Figure 3In FIG. 2 , it is shown that the peak voltage of the first pulse signal 206 is Vset, and the divided voltage on the device under test 201 is the target voltage of the device under test 201, namely Vdut.

[0081] Step 5: Measure the resistance value after the eFuse 101, and determine whether the state change in step 4 is complete based on the resistance value after the eFuse 101.

[0082] In the test process of the embodiment of the present invention, before the state of eFuse101 is rewritten, in addition to measuring the initial resistance value of eFuse101, the second output impedance of the programming transistor 102 when it is turned on is also measured, and the initial resistance value and the second output impedance are superimposed to form an accurate actual resistance of the device under test, and then the pulse voltage setting value is calculated according to the actual resistance of the device under test, and then the first pulse signal 206 is formed according to the pulse voltage setting value to achieve the state rewriting of eFuse101. In this way, when the process structure of eFuse101 and the programming transistor 102 changes so that the initial resistance value and the second output impedance change, the first pulse signal 206 will also change accordingly, and finally the voltage actually applied to the device under test 201 is consistent with the target voltage of the device under test 201, thereby preventing insufficient fusing when the actual voltage is less than the target voltage of the device under test 201 and excessive fusing when the actual voltage is greater than the target voltage of the device under test 201, thereby improving the state rewriting accuracy and finally improving the measurement accuracy.

[0083] like Figure 5 As shown, it is a comparison curve of the resistance value after the eFuse is tested by the eFuse test method of the embodiment of the present invention and the existing method; the horizontal axis represents the resistance value of the device under test 201, including three values, namely 1M ohm, the actual resistance of the device under test and 50 ohms; the vertical axis is the resistance value after the eFuse. Figure 5 The initial resistance value curve of the eFuse, namely curve 301, is also given.

[0084] Among them, curve 302 represents the curve of the post-resistance value of the eFuse when the resistance of the device under test 201 is 1M ohm; curve 303 represents the curve of the post-resistance value of the eFuse when the resistance of the device under test 201 is the actual resistance of the device under test; curve 304 represents the curve of the post-resistance value of the eFuse when the resistance of the device under test 201 is 50 ohms.

[0085] It can be seen that the resistance post value of curve 302 is relatively small and the resistance post value of curve 304 is relatively large, and the resistance post value of curve 303 is relatively accurate.

[0086] In the curve 302, 1M ohm is greater than the actual resistance of the actual device under test, so after the first pulse signal 206 is generated according to 1M ohm, the actual voltage division obtained on the eFuse 101 will become smaller, resulting in insufficient fusing, which will reduce the resistance value. Fig. 6A As shown, the mark 401 corresponds to the unblown eFuse 101, and the mark 402 corresponds to Figure 2 The metal contacts 105 in.

[0087] In curve 303, 50 ohms is less than the actual resistance of the actual device under test, so after the first pulse signal 206 is generated according to 50 ohms, the actual voltage division obtained on the eFuse 101 will increase, resulting in an over-fusing phenomenon, which will increase the resistance value. Figure 6C As shown, label 402 corresponds to Figure 2 The metal contact 105 in the figure, mark 402a indicates that the metal contact on the cathode migrates to the anode side.

[0088] As shown in the curve 301 , the initial resistance values ​​(R_pre) of the three data groups are all around 100 ohms, but the post resistance values ​​(R_post) after the control transistor 102 is turned on to blow the eFuse 101 are different:

[0089] The R_post corresponding to the data group A of the curve 302 is between 1000 ohms and 10000 ohms. Usually, a value greater than 5000 ohms is used as the standard for the resistance wire, ie, the eFuse 101 to be blown. Therefore, part of the fuse is not completely blown.

[0090] The R_post of the data group B corresponding to the curve 303 is between 10000 ohms and 100000 ohms, and all the fuses are blown.

[0091] The R_post of the data group C corresponding to the curve 304 is 1e+8 ohms, all the fuses are blown, and the resistance value after blowing is relatively large.

[0092] Scanning electron microscope (SEM) analysis was performed on the fuse status of the resistor under three conditions: the fuse in data group A still had some residue, and the fuse was not completely blown, corresponding to a low R_post resistance value; the fuse in data group B was basically blown, corresponding to a normal R_post value; the fuse in data group C was blown, and the electrons in the cathode including the circular contacts were pushed toward the anode, that is, overburning occurred, corresponding to a relatively large R_post resistance value.

[0093] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for testing an eFuse, characterized in that: The steps include: Step 1: providing a device under test, wherein the device under test is composed of an eFuse test structure, and the eFuse test structure includes an eFuse and a programming transistor connected in series; Step 2: measuring the initial resistance value of the eFuse and the second output impedance when the programming transistor is turned on; The actual resistance of the device under test is formed by adding the initial resistance value and the second output impedance; Step 3, providing a pulse generator, wherein the pulse generator and the device under test are connected in series with a built-in resistor, and calculating a pulse voltage setting value of the pulse generator according to the built-in resistor, the actual resistance of the device under test and the target voltage of the device under test; Step 4: rewriting the state of the eFuse of the device under test, including: Turning on the programming transistor; The pulse generator outputs a first pulse signal to the device under test according to the pulse voltage setting value to rewrite the state of the eFuse, and the peak voltage value of the first pulse signal is equal to the pulse voltage setting value, so that the actual voltage applied to the device under test by the first pulse signal is consistent with the target voltage of the device under test, so as to improve the accuracy of the state rewriting; Step 5: Measure the resistance value after the eFuse, and determine whether the state change in step 4 is complete based on the resistance value after the eFuse.

2. The eFuse testing method according to claim 1, wherein: The eFuse test structure further includes a cathode and an anode formed by a metal pad, and the eFuse and the programming transistor are connected in series between the cathode and the anode.

3. The eFuse testing method according to claim 2, wherein: The programming transistor is NMOS or PMOS.

4. The eFuse testing method according to claim 2, wherein: The eFuse is composed of a P-type silicided polysilicon resistor.

5. The eFuse testing method according to claim 4, wherein: The eFuse is formed on the shallow trench isolation.

6. The eFuse testing method according to claim 4, wherein: The eFuse has a filament structure, and the cathode and the anode both have a block structure.

7. The eFuse testing method according to claim 1, wherein: The built-in resistor is 50 ohms.

8. The eFuse testing method according to claim 7, wherein: The pulse generator has two built-in impedance options, the resistance values ​​of the two impedance options are 50 ohms and 1M ohms respectively, which are used to select the resistance of the device under test; The pulse generator sets a second pulse voltage setting value according to the selected resistance value of the impedance option and the target voltage of the device under test.

9. The eFuse testing method according to claim 8, wherein: In step three, the pulse generator calculates the pulse voltage setting value according to the resistance value of one of the impedance options and the corresponding second pulse voltage setting value, the built-in resistance and the actual resistance of the device under test.

10. The eFuse testing method according to claim 9, wherein: The formula for calculating the pulse voltage setting value is: Wherein, Vset' represents the second pulse voltage setting value, Vset represents the pulse voltage setting value, Rdut represents the actual resistance of the device under test, and Rdut' represents the resistance value of one of the impedance options.

11. The eFuse testing method according to claim 10, wherein: Vset' is equal to Vf, where Vf represents the voltage value expected by the user.

12. The eFuse testing method according to claim 1, wherein: The eFuse test structure includes the eFuse and the programming transistor.

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