A method for automatically maintaining data cache data consistency by hardware

Abstract

The method for automatically maintaining the consistency of DataCache by hardware includes the following steps: S1, software configures the processing unit to write the destination address A into the memory; S2, when the processing unit writes the address into the destination address A, the hardware device invalidates the storage area of the destination address A in the DataCache; S3, if the CPU accesses the destination address A again, the destination address A in the DataCache is not hit, and the CPU reads the data from the memory. The method has the advantages that the corresponding data in the DataCache is automatically invalidated by hardware, potential important links are avoided, the requirement of the program on the experience of engineers is reduced, the robustness of the program is improved, and the error is avoided.

Description

Technical Field

[0001] This invention relates to the field of CPU data caching, and more particularly to a method for automatically maintaining the consistency of DataCache data in hardware. Background Technology

[0002] Currently, embedded microcontrollers or chips have many processing units or coprocessors to assist the CPU in handling or performing data calculations, freeing up CPU time to handle more tasks and improving application performance. Because CPU access to main memory or secondary storage is inefficient, some CPUs have data caching capabilities to improve data access efficiency. The working principle of a cache is as follows: if the CPU needs to read L data starting from address A, it will access the cache. If the required data is in the cache, it's considered a cache hit; otherwise, it's a cache miss. In the case of a miss, the cache will proactively read an entire cache line from memory address A, creating a backup identical to the data in memory, and then provide it to the CPU. The next time the CPU accesses data at address A+1, this data already exists in the cache, resulting in a direct cache hit. When the CPU needs to modify data in main memory, it is actually modifying the data in the cache. This predictive data caching method effectively hides the time spent by the CPU directly accessing other storage devices, thereby improving CPU processing efficiency. When software requests the cache to write updated data back to memory, or when the cache, based on its own control, writes data back to its memory addresses, the data is truly updated for the program. However, this backup-based caching mechanism, along with the simultaneous presence of processing units or coprocessors, introduces a new problem: cache data consistency. Theoretically, if only the CPU reads and writes data, the data between the cache and memory will remain consistent within the CPU-DataCache-Memory closed loop. However, due to the existence of processing units, coprocessors, and other units outside the CPU that can update data, data can be modified outside the CPU-DataCache-Memory closed loop. If some data happens to have a backup in the DataCache, and a unit outside the loop happens to modify the original data in memory without the DataCache being aware of this and not handling it, failing to maintain data consistency between the cache and memory, when the CPU needs to use this outdated, incorrect data from the DataCache for calculation, it will directly hit the cache, leading to a calculation error. Summary of the Invention

[0003] The purpose of this invention is to maintain data consistency in the DataCache by autonomously executing data invalidation operations in the DataCache through hardware. This invention employs the following technical solution:

[0004] A method for automatically maintaining the consistency of DataCache data using hardware includes the following steps:

[0005] Step S1: The software configuration processing unit writes destination address A into the memory;

[0006] Step S2: When the processing unit writes the address to the destination address A, the storage area of ​​the destination address A in the DataCache is invalidated by the hardware device;

[0007] Step S3: If the CPU accesses destination address A again and misses the destination address A in the DataCache, the CPU reads the data from the memory.

[0008] Specifically, in step S2, the hardware includes a buffer and an arbiter. The DataCache and the buffer are connected through the IDF interface, the buffer and the arbiter are connected through the IBA interface, and the arbiter is connected to multiple processing units through the IAU interface.

[0009] The arbitrator's role is to select one request from multiple processing units and send it to the buffer receiver via the IBA interface. The arbitrator has multiple ports with different IDs, and processing units connect to different ports via the IAU interface. The smaller the port ID, the higher the priority of requests processed by the arbitrator on that port. When multiple requests occur simultaneously, the arbitrator sends them to the buffer receiver in descending order of priority according to this fixed priority principle. If it is necessary to adjust the priority of a processing unit's request processing, it can be changed to connect to an arbitrator port with a smaller ID via the IAU.

[0010] The advantage of using an arbitrator is that it allows for the handling of concurrent requests. Without an arbitrator, either a single-device system, where only one processing unit can send requests, or a preemptive bus system must be designed.

[0011] The buffer's function is to receive and cache requests from the arbitrator via the IBA interface. Cached requests are then sent to the DataCache for processing via the IDF interface. The buffer's storage units are implemented using a FIFO with a depth of 2. When the FIFO is not full, if there is a valid request, it should be received and cached within the same cycle. When the FIFO is not empty, it indicates that there is a cached request; the first cached request is sent to the DataCache for processing, waiting for the DataCache's `done_ack` flag to be set, and then the already processed request is removed. When the FIFO is full, it should wait for the DataCache to process the request.

[0012] Specifically, multiple IAU interfaces send requests to the arbitrator, and the arbitrator's arbitration principle is either a fixed priority principle or a circular priority principle.

[0013] Specifically, the processing unit includes one or more of DMA, coprocessor, and accelerator.

[0014] Specifically, the cache receives and caches requests from the arbitrator. The cached requests are then sent to the DataCache for processing. The cache contains storage units, including FIFO (First-In, First-Out) storage units. The storage depth of the FIFO storage units is set according to the number of requests. The advantages of using FIFO storage units in the buffer are: it hides the time it takes for the DataCache to process requests, allowing requests from processing units to be responded to quickly, improving the efficiency of request response; and the first-in, first-out characteristic of the FIFO storage units ensures that the first-arriving requests are processed first. If FIFO storage units are not used (where the FIFO storage depth is greater than or equal to 1), requests issued by processing units must wait for the DataCache to complete processing, which would reduce the efficiency of the processing units.

[0015] Specifically, in step S2, invalidating the storage area at destination address A in the DataCache using hardware means includes the following steps:

[0016] Step S21: When n processing units simultaneously request DataCache invalidation, the n processing units, including processing unit 1, processing unit 2, processing unit 3, ..., processing unit n, simultaneously send requests to the arbitrator through the IAU interface. The arbitrator responds to the requests of the n processing units and transmits them to the arbitrator simultaneously. The arbitrator responds to and transmits the requests of the n processing units to the cache in sequence according to the arbitration priority.

[0017] Step S22: The cache sends the request to DataCache via the IDF interface. DataCache begins processing the request, and at the same time, the arbitrator sends the request of the next priority processing unit to the cache. The cache then determines whether the storage units in the cache are full.

[0018] If the storage unit is not full, the cache caches the request of the next priority processing unit and responds, and at the same time feeds the response back to the arbitrator. The arbitrator then feeds the response back to the next priority processing unit. The request response of the next priority processing unit is completed, and the process proceeds to step S26.

[0019] If the storage unit is full, proceed to step S23;

[0020] Step S23: After DataCache completes the request of the previous priority processing unit and sends the feedback to the cache, proceed to step S24;

[0021] Step S24: After the cache removes the request from the previous priority processing unit, it caches the response to the request from the next priority processing unit and feeds back the response to the request from the next priority processing unit to the arbitrator. The arbitrator then feeds back the response to the next priority processing unit, and the request response from the next priority processing unit is completed.

[0022] Step S25: Proceed to step S23 again until DataCache completes all processing unit requests;

[0023] Step S26: Proceed back to step S22 until DataCache completes all processing unit requests.

[0024] The advantages of this method are: by automatically invalidating the corresponding data in the DataCache through hardware, it avoids potential human oversights in critical steps, reduces the program's reliance on engineer experience, improves program robustness, and prevents such errors from occurring. Attached Figure Description

[0025] Figure 1 This is a flowchart of a hardware-automatic method for maintaining the consistency of DataCache data.

[0026] Figure 2 This is a timing diagram of the handshake process using IAU interface signals, request and ack signals;

[0027] Figure 3 This is a timing diagram of the handshake process using the IBA interface signals, request and notfull_ack signals.

[0028] Figure 4 The handshake is performed through the IDF interface signals notempty_request and notfull_ack. Detailed Implementation

[0029] according to Figures 1 to 4 The workflow in this method is as follows:

[0030] A method for automatically maintaining the consistency of DataCache data using hardware includes the following steps:

[0031] Step S1: The software configures three processing units to write destination address A into the memory. These processing units are the first processing unit, the second processing unit, and the third processing unit.

[0032] Step S2: When the three processing units write the address to the destination address A, the storage area of ​​the destination address A in the DataCache is invalidated by the hardware device, which includes the following steps:

[0033] 1. When the system is reset, the FIFO in the buffer is empty and can buffer requests at any time.

[0034] 2. The first cycle at the beginning of a certain cycle:

[0035] 2.1 When both the first processing unit and the second processing unit need to request a DataCache invalidation, they should send the request to the arbitrator through the IAU interface.

[0036] 2.2 When the arbitrator receives requests from two ports simultaneously, it prioritizes responding to request 1 from port 0 (the first processing unit), and then processes request 2 from port 1 (the second processing unit). The arbitrator first sends the request from the first processing unit to the buffer.

[0037] 2.3 At this time, since the FIFO is empty, the buffer directly buffers the request and responds. The arbitrator in the same cycle transmits the buffer's response back to the first processing unit, and the request response of the first processing unit is completed.

[0038] 3. Second cycle:

[0039] 3.1 The buffer sends request 1, the first processing unit in the buffer, to the DataCache. The DataCache begins processing request 1.

[0040] 3.2 The arbitrator first sends the request from the second processing unit to the buffer.

[0041] 3.3 The FIFO in the buffer has a buffer depth of 2, so the FIFO in the buffer is still not full and can be buffered directly. The arbitrator in the same cycle sends the buffer's response back to the second processing unit, and the second processing unit's request response is completed.

[0042] 4. The third cycle:

[0043] 4.1 DataCache is still processing request 1.

[0044] 4.2 The third processing unit sends request 3. The arbitrator forwards request 3 to the buffer. Since the buffer's FIFO is full, it cannot cache request 3 and waits for DataCache to process it.

[0045] 5. The 4th cycle:

[0046] 5.1 DataCache completes the processing of request 1 and returns the buffer via done_ack.

[0047] 5.2 The buffer ejects request 1, sends request 2 to DataCache, buffers request 3, and sends feedback to the arbitrator via notfull_ack.

[0048] 5.3 The same-period arbitrator feeds back to the processing unit, and the request response of the third processing unit is completed.

[0049] 6. In the 5th and 6th cycles, DataCache processes requests in the second processing unit.

[0050] 7. The 7th cycle

[0051] 7.1 DataCache completes the processing of request 2 and returns the buffer via done_ack.

[0052] 7.2 The buffer ejects request 2 and sends request 3 to the DataCache.

[0053] 8. In the 8th and 9th cycles, the DataCache processes requests in the third processing unit.

[0054] 9. In the 10th cycle, DataCache completes the processing of request 3.

[0055] Step S3: If the CPU accesses destination address A again and misses the destination address A in the DataCache, the CPU reads the data from the memory.

[0056] In step S2, the hardware includes a buffer and an arbiter. The DataCache and the buffer are connected via the IDF interface, the buffer and the arbiter are connected via the IBA interface, and the arbiter and the processing unit are connected via the IAU interface.

[0057] The IAU interface signals are shown in Table 1 below. A handshake is performed using the request and ack signals. When both the request and ack signals are high, it indicates that a request and response have been completed. The timing diagram is as follows. Figure 2As shown in Table 2, the IBA interface signals are specifically designed for handshaking via the request and notfull_ack signals. When both the request and notfull_ack signals are high, it indicates that a request and response cycle is complete. The timing diagram is shown below. Figure 3 As shown in Table 3, the IDF interface signals are used for handshaking via the notempty_request and notfull_ack signals. When both notempty_request and notfull_ack signals are high, it indicates that a request and response have been completed. The timing diagram is shown below. Figure 4 As shown.

[0058] The arbitrator's role is to select one request from multiple processing units and send it to the buffer via IBA. The arbitrator has multiple ports with different IDs, and processing units connect to different ports via IAU interfaces. The smaller the port ID, the higher the priority of the arbitrator in processing requests on that port. When multiple requests occur simultaneously, the arbitrator sends them to the buffer in descending order of priority according to this fixed priority principle. If it is necessary to adjust the priority of a processing unit's request processing, it can be changed to an arbitrator port with a smaller ID connected via IAU. The advantage of using an arbitrator is that it allows for the handling of concurrent requests. Without an arbitrator, either a single-device system (e.g., only one processing unit can send requests) or a preemptive bus system must be designed. The advantage of using a fixed-priority arbitration strategy is that this simple arbitration strategy is easy to design and highly efficient for such uncomplicated concurrent requests.

[0059] The cache's function is to receive and cache requests from the arbitrator via IBA. Cached requests are then sent to DataCache for processing via IDF. The cache's storage units are implemented using FIFO with an FIO depth of 2. When the FIFO is not full, if there is a valid request, it should be received and cached within the same cycle. When the FIFO is not empty, it indicates that there is a cached request; the first cached request is sent to DataCache for processing, waiting for DataCache's `done_ack` flag to be set, and then the already processed request is removed. When the FIFO is full, it should wait for DataCache to process the request.

[0060] The advantage of using FIFO in a cache is that it hides the time it takes for the DataCache to process requests, allowing requests from processing units to be responded to quickly, thus improving the efficiency of request response. At the same time, the first-in-first-out characteristic of FIFO ensures that the first-arriving request is processed first. Without FIFO (FIFO depth >= 1), requests issued by processing units must wait for the DataCache to complete processing, reducing the efficiency of the processing units.

[0061] In summary, the advantages of this method are: by automatically invalidating the corresponding data in the DataCache through hardware, it avoids potential human oversights in critical steps, reduces the program's reliance on engineer experience, improves program robustness, and prevents such errors from occurring.

[0062] Table 1 shows the specific IAU interface signals as follows:

[0063]

[0064] Table 2 shows the specific IBA interface signals as follows:

[0065]

[0066] Table 3 shows the specific IDF interface signals as follows:

[0067]

[0068]

[0069] It is understood that the above detailed description of the present invention is for illustrative purposes only and is not intended to limit the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention to achieve the same technical effects; as long as the usage requirements are met, they are all within the protection scope of the present invention.

Claims

1. A method for automatically maintaining the consistency of DataCache data using hardware, characterized in that, Includes the following steps: Step S1: The software configures multiple processing units to write destination address A into the memory; Step S2: The multiple processing units operate, and when the multiple processing units write the address to the destination address A, the storage area of ​​the destination address A in the DataCache is invalidated by the hardware device; Step S3: If the CPU accesses the destination address A again and fails to find the destination address A in the DataCache, the CPU reads the data from the memory; In step S2, the hardware device includes a cache and an arbitrator. The DataCache and the cache are connected via an IDF interface, the cache and the arbitrator are connected via an IBA interface, and the arbitrator is connected to the plurality of processing units via IAU interfaces. In step S2, invalidating the storage area of ​​destination address A in DataCache using a hardware device includes the following steps: Step S21: When the multiple processing units simultaneously request DataCache invalidation, they simultaneously send requests to the arbitrator through the IAU interface. The arbitrator responds to the requests of the multiple processing units and transmits them to the cache according to a fixed priority. Step S22: The cache sends the request to DataCache via the IDF interface. DataCache begins processing the request. Simultaneously, the arbitrator sends the request for the next priority processing unit to the cache. The cache then determines whether its storage units are full. If the storage unit is not full, the cache caches the request of the next priority processing unit and responds, and at the same time feeds the response back to the arbitrator, which then feeds it back to the next priority processing unit. The request response of the next priority processing unit is completed, and the process proceeds to step S26. If the storage unit is full, proceed to step S23; Step S23: After DataCache completes the request of the previous priority processing unit and sends it back to the cache, proceed to step S24; Step S24: After the cache removes the request from the previous priority processing unit, it caches the response to the request from the next priority processing unit and feeds back the response to the request from the next priority processing unit to the arbitrator. The arbitrator then feeds back the response to the next priority processing unit, and the request response from the next priority processing unit is completed. Step S25: Proceed to step S23 again until DataCache completes all processing unit requests; Step S26: Proceed back to step S22 until DataCache completes all processing unit requests.

2. The method for automatically maintaining the consistency of DataCache data according to claim 1, characterized in that, When the multiple processing units send requests to the arbitrator through multiple IAU interfaces, the arbitration principle of the arbitrator is either a fixed priority principle or a cyclic priority principle.

3. The method for automatically maintaining the consistency of DataCache data according to claim 1, characterized in that, The processing unit includes one or more of DMA, coprocessor, and accelerator.

4. The method for automatically maintaining the consistency of DataCache data according to claim 1, characterized in that, The cache is used to receive and cache requests from the arbitrator, and send the cached requests to DataCache for processing. The cache has a storage unit, which is a FIFO. The storage depth of the FIFO is set according to the number of requests.

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