A shield-gate trench MOSFET structure and a manufacturing method thereof

Abstract

The present invention provides a shielded-gate trench MOSFET structure and a manufacturing method thereof. The shielded-gate trench MOSFET structure includes a semiconductor layer, a first trench, a dielectric layer, a shielded-gate layer, a second trench, a third trench, a gate dielectric layer, a gate conductive layer, a shielded-gate contact hole, and a gate contact hole. Among them, the first trench is located in the semiconductor layer and includes a first end region, a gate lead-out region, and a second end region; the dielectric layer and the shielded-gate layer are located in the first trench, the second trench is located in the gate lead-out region and opens upward; the third trench is located above the dielectric layer between the first end region and the second end region and communicates with the second trench; the gate dielectric layer and the gate conductive layer are located in the second trench and the third trench; the bottom parts of the shielded-gate contact hole and the gate contact hole respectively extend into the shielded-gate layer and the gate conductive layer. By forming the second trench communicating with the third trench in the gate lead-out region, the present invention enables there to be sufficient space in the gate conductive layer to form the gate contact hole.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a shielded gate trench MOSFET structure and a preparation method thereof. Background Art

[0002] In power MOSFET devices, due to the advantages of lower on-resistance, faster switching speed, etc. of shielded gate trench MOSFETs compared to traditional trench MOSFETs, they have received increasing attention. As Figure 1 shown, it is a schematic cross-sectional structure diagram of the trench part of a shielded gate trench MOSFET structure, including a semiconductor layer 01, a trench 011, a dielectric layer 012, a shielded gate layer 013, a gate conductive layer 014, a gate dielectric layer 015, an interlayer dielectric layer 016, and a source contact hole 017.

[0003] With the development of shielded gate trench MOSFET technology, in order to reduce the internal resistance of the device, the cell unit size of the device is continuously reduced, and there is not enough space on the shielded gate layer and the gate conductive layer to form contact holes, and an area needs to be set aside on the layout to connect out the contact holes. Since the polysilicon thickness is usually above 1 μm, there will be a large height difference on the wafer surface, increasing the process complexity. Currently, the lithography of the shielded gate layer can be omitted to eliminate the height difference between the shielded gate layer and the epitaxial layer, but there is still no way to omit the gate light mask and the height difference between the gate and the epitaxial layer.

[0004] Therefore, there is an urgent need to find a preparation method for a shielded gate trench MOSFET structure that does not require the formation of a gate light mask. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a shielded gate trench MOSFET structure and a preparation method thereof, which are used to solve the problems of the contact holes that need to be connected out through the gate light mask and the height difference of the semiconductor layer in the prior art.

[0006] To achieve the above purpose and other related purposes, the present invention provides a preparation method for a shielded gate trench MOSFET structure, including the following steps:

[0007] Provide a semiconductor layer, and form a plurality of first trenches arranged at intervals along the X direction in the semiconductor layer, and the openings of the first trenches face upward and extend along the Y direction, and the X direction is perpendicular to the Y direction;

[0008] Form a dielectric material layer and a conductive material layer in the first trenches in sequence, and the dielectric material layer is located on the inner wall and bottom surface of the first trenches and wraps the side wall and bottom surface of the conductive material layer;

[0009] A first end region, a gate lead-out region, and a second end region are defined in sequence along the Y direction in the first trench. A second trench is formed in a preset region of the gate lead-out region. The second trench opens from the top of the conductive material layer and extends downward. The conductive material layer in the first trench outside the second trench constitutes a shielding gate layer;

[0010] Etch the dielectric material layer between the first end region and the second end region to obtain a third trench located on both sides of the shielding gate layer and both sides of the second trench along the X direction. The third trench communicates with the second trench in the X direction, and the dielectric material layer in the first trench outside the third trench constitutes a dielectric layer;

[0011] A gate dielectric layer and a gate conductive layer are sequentially formed in the third trench and the second trench. The gate dielectric layer is located on the inner walls and bottom surfaces of the second trench and the third trench, and the gate dielectric layer wraps the side walls and bottom surface of the gate conductive layer;

[0012] Form a shielding gate contact hole extending to the shielding gate layer at the bottom, and form a gate contact hole extending to the gate conductive layer at the bottom in the second trench

[0013] Optionally, the upper surface of the gate conductive layer is flush with the upper surface of the semiconductor layer.

[0014] Optionally, the shielding gate contact holes are distributed in the shielding gate layer in the first end region and the second end region.

[0015] Optionally, the upper surface of the dielectric layer in the first end region is flush with the upper surface of the semiconductor layer, and the upper surface of the dielectric layer in the second end region is flush with the upper surface of the semiconductor layer.

[0016] Optionally, the length of the third trench in the Y direction is the same as the length of the gate lead-out region.

[0017] Optionally, the depth of the second trench is less than the depth of the third trench.

[0018] Optionally, after forming the gate conductive layer and before forming the gate contact hole and the shielding gate contact hole, further include the steps of forming a second-conductivity-type body region and a first-conductivity-type source region, and the body region is located on the upper surface layer of the semiconductor layer between two adjacent first trenches, and the source region is located on the upper surface layer of the body region.

[0019] Optionally, after forming the body region and the source region and before forming the gate contact hole and the shielding gate contact hole, further include the step of forming an interlayer dielectric layer on the upper surface of the semiconductor layer.

[0020] Optionally, after forming the gate contact hole and the shield gate contact hole, the method further includes steps of forming a source electrode, a gate electrode, a drain electrode, and a passivation layer.

[0021] The present invention further provides a shield gate trench MOSFET structure, including:

[0022] A semiconductor layer;

[0023] A plurality of first trenches located in the semiconductor layer, spaced apart along the X direction, and having openings facing upward and extending along the Y direction, where the X direction is perpendicular to the Y direction. The first trenches include a first end region, a gate lead-out region, and a second end region sequentially arranged along the Y direction;

[0024] A dielectric layer located on the inner walls and bottom surface of the first trenches;

[0025] A shield gate layer filling the first trenches, and the side walls and bottom surface of the shield gate layer are wrapped by the dielectric layer;

[0026] A second trench located in a preset region of the gate lead-out region, and having an opening facing upward. The bottom surface and the side wall in the Y direction of the second trench are both the shield gate layer;

[0027] A third trench located above the dielectric layer between the first end region and the second end region, and along the X direction, the third trench is located on both sides of the shield gate layer and on both sides of the second trench. The third trench communicates with the second trench in the X direction;

[0028] A gate dielectric layer and a gate conductive layer. The gate dielectric layer is located on the inner walls and bottom surface of the second trench and the third trench, and the gate conductive layer is located in the second trench and the third trench and is wrapped by the gate dielectric layer;

[0029] A shield gate contact hole and a gate contact hole. The bottom of the shield gate contact hole extends into the shield gate layer, and the gate contact hole is located in the second trench and the bottom extends into the gate conductive layer.

[0030] As described above, the shielded gate trench MOSFET structure and its manufacturing method of the present invention form the second trench in the gate lead-out region to provide a sufficiently large space for forming the contact hole, and form the third trench along both sides in the X direction of the shielded gate layer and the second trench in the gate lead-out region 112, and the third trench communicates with the second trench in the X direction, so that the gate conductive layer filled in the second trench and the third trench is a continuous whole, and then the gate contact hole can be formed in the second trench, avoiding the situation that due to the too small device size, there is not enough space in the gate conductive layer on both sides of the shielded gate layer in the X direction to form the gate contact hole, eliminating the risk of setting aside an area for leading out the gate contact hole in the device layout and the risk of the bridging process for leading out the gate conductive layer, and at the same time avoiding the problem of complex process caused by the height difference between the upper surface of the formed gate conductive layer and the upper surface of the semiconductor layer, simplifying the process steps of forming the gate contact hole. In addition, no gate conductive layer is formed in the first end region and the second end region to prevent the shielded gate contact hole formed in the limited space of the first end region and the second end region from extending into the gate conductive layer, thereby affecting the yield of the device, and having high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic cross-sectional structure diagram of the trench part of the shielded gate trench MOSFET shown in a left-right structure.

[0032] Figure 2 Process flow chart of the manufacturing method of the shielded gate trench MOSFET structure of the present invention.

[0033] Figure 3 Schematic cross-sectional structure diagram after forming the first trench in the manufacturing method of the shielded gate trench MOSFET structure of the present invention.

[0034] Figure 4 Regional distribution diagram of the first end region, gate lead-out region and second end region divided by the first trench in the manufacturing method of the shielded gate trench MOSFET structure of the present invention.

[0035] Figure 5 Schematic cross-sectional structure diagram after forming the dielectric material layer in the manufacturing method of the shielded gate trench MOSFET structure of the present invention.

[0036] Figure 6 Schematic cross-sectional structure diagram after removing the conductive material layer on the upper surface of the semiconductor layer in the manufacturing method of the shielded gate trench MOSFET structure of the present invention.

[0037] Figure 7Schematic cross-sectional structure diagram after the formation of the second trench in the manufacturing method of the shield-gate trench MOSFET structure of the present invention.

[0038] Figure 8 Schematic cross-sectional structure diagram after the formation of the third trench in the manufacturing method of the shield-gate trench MOSFET structure of the present invention.

[0039] Figure 9 Schematic cross-sectional structure diagram at the second trench after the formation of the third trench in the manufacturing method of the shield-gate trench MOSFET structure of the present invention.

[0040] Figure 10 Schematic cross-sectional structure diagram at the third trench after the formation of the gate conductive layer in the manufacturing method of the shield-gate trench MOSFET structure of the present invention.

[0041] Figure 11 Schematic cross-sectional structure diagram at the second trench after the formation of the gate conductive layer in the manufacturing method of the shield-gate trench MOSFET structure of the present invention.

[0042] Figure 12 Planar layout diagram after the formation of the gate contact hole and the shield-gate contact hole in the manufacturing method of the shield-gate trench MOSFET structure of the present invention.

[0043] Explanation of the reference numerals in the attached drawings

[0044] 01 Semiconductor layer

[0045] 011 Trench

[0046] 012 Dielectric layer

[0047] 013 Shield-gate layer

[0048] 014 Gate conductive layer

[0049] 015 Gate dielectric layer

[0050] 016 Interlayer dielectric layer

[0051] 017 Source contact hole

[0052] 1 Semiconductor layer

[0053] 11 First trench

[0054] 111 First end region

[0055] 112 Gate lead-out region

[0056] 113 Second end region

[0057] 12 Dielectric material layer

[0058] 121 dielectric layer

[0059] 13 conductive material layer

[0060] 131 shielding gate layer

[0061] 14 second trench

[0062] 141 gate dielectric layer

[0063] 142 gate conductive layer

[0064] 15 third trench

[0065] 2 mask layer

[0066] 3 shielding gate contact hole

[0067] 31 gate contact hole Detailed implementation manners

[0068] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0069] Please refer to Figures 2 to 12 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0070] Embodiment 1

[0071] This embodiment provides a preparation method for a shielding gate trench MOSFET structure. As Figure 2 shown, it is the process flow diagram of the preparation method for the shielding gate trench MOSFET structure, including the following steps:

[0072] S1: Provide a semiconductor layer, and form a plurality of first trenches arranged at intervals in the X direction in the semiconductor layer, and the openings of the first trenches face upward and extend in the Y direction, and the X direction is perpendicular to the Y direction;

[0073] S2: Form a dielectric material layer on the upper surface of the semiconductor layer, and form a conductive material layer on the upper surface of the dielectric material layer. Sequentially form a dielectric material layer and a conductive material layer in the first trench. The dielectric material layer covers the inner wall and bottom surface of the first trench and wraps the side wall and bottom surface of the conductive material layer.

[0074] S3: Define a first end region, a gate lead-out region, and a second end region arranged in sequence along the Y direction in the first trench. Form a second trench in a preset region of the gate lead-out region. The second trench opens from the top of the conductive material layer and extends downward. The conductive material layer in the first trench outside the second trench constitutes a shielding gate layer.

[0075] S4: Etch the dielectric material layer between the first end region and the second end region to obtain third trenches located on both sides of the shielding gate layer and on both sides of the second trench along the X direction. The third trenches communicate with the second trench in the X direction, and the dielectric material layer in the first trench outside the third trenches constitutes a dielectric layer.

[0076] S5: Sequentially form a gate dielectric layer and a gate conductive layer in the third trench and the second trench. The gate dielectric layer is located on the inner wall and bottom surface of the second trench and the third trench, and the gate dielectric layer wraps the side wall and bottom surface of the gate conductive layer.

[0077] S6: Form a shielding gate contact hole with the bottom extending to the shielding gate layer, and form a gate contact hole with the bottom extending into the gate conductive layer in the second trench.

[0078] Please refer to Figures 3 to 6 , perform step S1 and step S2: Provide a semiconductor layer 1, and form a plurality of first trenches 11 arranged at intervals along the X direction in the semiconductor layer 1. The openings of the first trenches 11 face upward and extend along the Y direction. The X direction and the Y direction are perpendicular to each other. Sequentially form a dielectric material layer 12 and a conductive material layer 13 in the first trench 11. The dielectric material layer 12 is located on the inner wall and bottom surface of the first trench 11 and wraps the side wall and bottom surface of the conductive material layer 13.

[0079] Specifically, the semiconductor layer 1 includes at least one doping layer of the first conduction type, and the doping concentration range in the semiconductor layer 1 can be selected according to actual conditions and will not be limited here.

[0080] Specifically, the material of the semiconductor layer 1 includes silicon, silicon germanium, silicon carbide, or other suitable semiconductor materials.

[0081] As an example, before forming the first trench 11, a step of forming a mask layer 2 covering the upper surface of the semiconductor layer 1 is further included.

[0082] Specifically, the thickness of the formed mask layer 2 can be selected according to actual circumstances and will not be limited here.

[0083] Specifically, the method of forming the mask layer 2 includes physical vapor deposition, chemical vapor deposition, or other suitable methods.

[0084] Specifically, forming the first trench 11 further includes the following steps: forming a first photoresist layer on the upper surface of the mask layer 2 and patterning the first photoresist layer; forming the first trench 11 based on the patterned first photoresist layer.

[0085] Specifically, as Figure 3 and Figure 4 shown, respectively, are the cross-sectional structure schematic diagram after forming the first trench 11 and the regional distribution diagram of the first end region 111, gate lead-out region 112, and second end region 113 divided by the first trench 11 (see subsequent step S3). The method of forming the first trench 11 includes dry etching, wet etching, or other suitable methods.

[0086] Specifically, the opening size and trench depth of the formed first trench 11 can be selected according to actual circumstances and will not be limited here.

[0087] Specifically, after forming the first trench 11 and before forming the dielectric material layer 12, a step of removing the mask layer 2 on the upper surface of the semiconductor layer 1 is further included.

[0088] Specifically, the method of forming the dielectric material layer 12 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the formed dielectric material layer 12 also covers the upper surface of the semiconductor layer 1.

[0089] Specifically, under the condition of ensuring device performance, the thickness of the dielectric material layer 12 can be selected according to actual circumstances and will not be limited here.

[0090] Specifically, as Figure 5 shown, is the cross-sectional structure schematic diagram after forming the dielectric material layer 12. The method of forming the conductive material layer 13 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0091] Specifically, as Figure 6As shown, it is a schematic cross-sectional structure diagram after removing the conductive material layer 13 on the upper surface of the semiconductor layer 1. The formed conductive material layer 13 also covers the upper surface of the dielectric material layer 12, and after forming the conductive material layer 13, it further includes the step of removing the conductive material layer 13 on the upper surface of the dielectric material layer 12.

[0092] Specifically, the method for removing the conductive material layer 13 on the upper surface of the dielectric material layer 12 includes chemical mechanical polishing, dry etching, wet etching or other suitable methods.

[0093] Please refer to Figures 7 to 9 again, and perform step S3 and step S4: Define a first end region 111, a gate lead-out region 112 and a second end region 113 arranged in sequence along the Y direction in the first trench 11. Form a second trench 14 in a preset region of the gate lead-out region 112. The second trench 14 opens from the top of the conductive material layer 13 and extends downward. The conductive material layer 13 within the first trench 11 and outside the second trench 14 constitutes a shielding gate layer 131; etch the dielectric material layer 12 between the first end region 111 and the second end region 113 to obtain a third trench 15 located on both sides of the shielding gate layer 131 and both sides of the second trench 14 along the X direction. The third trench 15 communicates with the second trench 14 in the X direction, and the dielectric material layer 12 within the first trench 11 and outside the third trench 15 constitutes a dielectric layer 121.

[0094] Specifically, when ensuring that there is enough space in the first end region 111 and the second end region 113 to form shielding gate contact holes (see subsequent Figure 11 ), the length of the first end region 111 in the Y direction can be selected according to actual conditions and will not be limited here; the length of the second end region 113 in the Y direction can be selected according to actual conditions and will not be limited here.

[0095] Specifically, the depth of the second trench 14 is less than the depth of the first trench 11. The second trench 14 is located at any position on the upper surface layer of the conductive material layer 13 along the Y direction of the gate lead-out region 112, and during the formation of the second trench 14, the dielectric material layer 12 is not damaged. In this embodiment, the second trench 14 is located at the middle position along the Y direction of the gate lead-out region 112.

[0096] Specifically, as Figure 7As shown, it is a schematic cross-sectional structure diagram after forming the second trench 14. The formation of the second trench 14 includes the following steps: forming a second photoresist layer on the upper surface of the dielectric material layer 12, and patterning the second photoresist layer based on a shield gate mask; etching the conductive material layer 13 in the first trench 11 based on the patterned second photoresist layer to obtain the second trench 14, and simultaneously obtaining the shield gate layer 131.

[0097] Specifically, the method for forming the second trench 14 includes dry etching, wet etching, or other suitable methods.

[0098] As an example, the upper surface of the dielectric layer 121 in the first end region 111 is flush with the upper surface of the semiconductor layer 1, and the upper surface of the dielectric layer 121 in the second end region 113 is flush with the upper surface of the semiconductor layer 1.

[0099] As an example, the length of the third trench 15 in the Y direction is the same as the length of the gate lead-out region 112.

[0100] Specifically, as Figure 8 shown, it is a schematic cross-sectional structure diagram after forming the third trench 15. The formation of the third trench 15 includes the following steps: forming a third photoresist layer on the upper surface of the semiconductor layer 1, and patterning the third photoresist layer; forming the third trench 15 based on the patterned third photoresist layer.

[0101] Specifically, after patterning the third photoresist layer, the third photoresist layer covers the first end region 111 and the second end region 113 and exposes the upper surface of the dielectric material layer 12 in the gate lead-out region 112.

[0102] Specifically, before forming the third trench 15, it further includes the step of removing the dielectric material layer 12 on the upper surface of the semiconductor layer 1. The method for removing the dielectric material layer 12 on the upper surface of the semiconductor layer 1 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0103] Specifically, the method for etching the dielectric material layer 12 in the first trench 11 between the first end region 111 and the second end region 113 includes dry etching, wet etching, or other suitable methods.

[0104] As an example, as Figure 9 shown, it is a schematic cross-sectional structure diagram at the second trench 14 after forming the third trench 15. The depth of the second trench 14 is less than the depth of the third trench 15.

[0105] Specifically, the depth of the second trench 14 may also be the same as the depth of the third trench 15.

[0106] Please refer to Figures 10 to 12 , and perform the step S5 and the step S6: sequentially form a gate dielectric layer 141 and a gate conductive layer 142 in the third trench 15 and the second trench 14, and the gate dielectric layer 141 is located on the inner walls and bottom surface of the second trench 14 and the third trench 15, and the gate dielectric layer 141 wraps the side walls and bottom surface of the gate conductive layer 142; form a shielding gate contact hole 3 extending to the shielding gate layer 131 at the bottom, and form a gate contact hole 31 extending to the gate conductive layer 142 at the bottom in the second trench 14.

[0107] Specifically, the method for forming the gate dielectric layer 141 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0108] Specifically, as Figure 10 shown, it is a schematic cross-sectional structure diagram at the third trench 15 after forming the gate conductive layer 142. The steps for forming the gate conductive layer 142 include: forming a layer of gate conductive material layer on the upper surface of the gate dielectric layer 141, and the gate conductive material layer fills the third trench 15 and the second trench 14; removing the gate conductive material layer above the semiconductor layer 1 to obtain the gate conductive layer 142.

[0109] Specifically, as Figure 11 shown, it is a schematic cross-sectional structure diagram at the second trench 14 after forming the gate conductive layer 142. Since the second trench 14 communicates with the third trench 15 along the X direction, the gate conductive material layer filling the third trench 15 and the second trench 14 is a continuous whole, that is, the gate conductive layer 142 is a continuous whole.

[0110] Specifically, the method for forming the gate conductive material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0111] Specifically, the material of the gate conductive layer 142 includes polysilicon or other suitable conductive materials. In this embodiment, polysilicon is used as the material of the gate conductive layer 142.

[0112] As an example, the upper surface of the gate conductive layer 142 is flush with the upper surface of the semiconductor layer 1.

[0113] As an example, after forming the gate conductive layer 142 and before forming the gate contact hole 31 and the shield gate contact hole 3, it further includes steps of forming a body region of a second conductivity type (not shown) and a source region of a first conductivity type (not shown), and the body region is located on the upper surface layer of the semiconductor layer 1 between two adjacent first trenches 11, and the source region is located on the upper surface layer of the body region.

[0114] Specifically, the first conductivity type includes one of N-type or P-type, the second conductivity type includes one of N-type or P-type, and the conductivity types of the first conductivity type and the second conductivity type are opposite.

[0115] Specifically, the method of forming the body region includes ion implantation or other suitable methods; the method of forming the source region includes ion implantation or other suitable methods.

[0116] As an example, after forming the body region and the source region and before forming the gate contact hole 31 and the shield gate contact hole 3, it further includes a step of forming an interlayer dielectric layer (not shown) on the upper surface of the semiconductor layer 1.

[0117] Specifically, the method of forming the interlayer dielectric layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0118] Specifically, the material of the interlayer dielectric layer includes silicon oxide, silicon nitride or other suitable materials. In this embodiment, silicon oxide is used as the material of the interlayer dielectric layer.

[0119] Specifically, under the condition of ensuring device safety, the thickness of the interlayer dielectric layer can be selected according to actual situations and will not be limited here.

[0120] Specifically, as Figure 12 shown, it is a plan layout diagram after forming the gate contact hole 31 and the shield gate contact hole 3. The method of forming the shield gate contact hole 3 includes dry etching, wet etching or other suitable methods; the method of forming the gate contact hole 31 includes dry etching, wet etching or other suitable methods.

[0121] Specifically, under the condition of ensuring that it does not exceed the shield gate layer 131 in the first end region 111 and the second end region 113 in the X direction and the Y direction, the size of the shield gate contact hole 3 can be selected according to actual situations and will not be limited here.

[0122] Specifically, since the second trench 14 is located in the gate lead-out region 112, it can ensure that there is a sufficiently large space in the second trench 14, and then there is sufficient space in the gate conductive layer 142 filling the second trench 14 for forming the gate contact hole 31, avoiding the problem that due to the too small size of the gate conductive layer 142 on both sides of the shielding gate layer 131 along the X direction and there is not enough space to form the gate contact hole 31, resulting in the need to set aside an area for leading out the gate contact hole 31 in the layout. Subsequently, the photomask for setting aside the area for forming the gate contact hole in the layout is omitted, and the risk of bridging the gate is also avoided, simplifying the process complexity and saving the manufacturing cost.

[0123] Specifically, on the premise of ensuring that the length of the gate contact hole 31 in the Y direction is less than the length of the second trench 14, the size of the second trench 14 can be selected according to the actual situation and will not be limited here.

[0124] Specifically, on the premise that the bottom of the gate contact hole 31 is located in the gate conductive layer 142 in the second trench 14 and the device performance is stable, the depth of the gate contact hole 31 extending into the gate conductive layer 142 can be selected according to the actual situation and will not be limited here.

[0125] Specifically, the gate conductive layer 142 is not formed in the first end region 111 and the second end region 113 to prevent the shielding gate contact hole 3 formed may extend into the gate conductive layer 142 due to the limited space of the shielding gate layer 131 in the first end region 111 and the second end region 113, affecting the yield of the device.

[0126] As an example, after forming the gate contact hole 31 and the shielding gate contact hole 3, it further includes the steps of forming a source electrode, a gate electrode, a drain electrode and a passivation layer.

[0127] Specifically, after forming the gate contact hole 31, it further includes the step of forming a source contact hole, and the source electrode fills the source contact hole, the gate electrode fills the gate contact hole, and the drain electrode is located on the lower surface of the semiconductor layer.

[0128] Specifically, after forming the shielding gate contact hole 3, it further includes the step of forming an electrode filling the shielding gate contact hole 3 to electrically connect the shielding gate layer 131 with an external circuit, balance the charges in the drift region of the device, improve the electric field distribution in the device, and reduce the internal resistance of the device.

[0129] Specifically, the methods for forming the source electrode, the gate electrode, the drain electrode and the passivation layer are common process methods and will not be elaborated here.

[0130] The manufacturing method of the shielded-gate trench MOSFET structure in this embodiment forms the second trench 14 in the gate lead-out region 112 between the first end region 111 and the second end region 113 of the first trench 11, and forms the third trench 15 on both sides of the shielded-gate layer 131 and the second trench 14 in the gate lead-out region 112 along the X direction. The third trench 15 communicates with the second trench 14 in the X direction, so that the gate conductive layer 142 filled in the second trench 14 and the third trench 15 is a continuous whole. Since the space in the gate lead-out region 112 is much larger than the space required for the gate contact hole 31, it can ensure that there is enough space in the second trench 14 located in the gate lead-out region 112. Subsequently, the gate contact hole 31 can be formed in the second trench 14, avoiding the situation that due to the too small device size, there is not enough space in the gate conductive layer 142 on both sides of the shielded-gate layer 131 in the X direction to form the gate contact hole 31, eliminating the risk of delineating the region for leading out the gate contact hole 31 in the device layout and the risk of the bridging process for leading out the gate conductive layer 142. At the same time, it solves the problem that there is a height difference between the upper surface of the formed gate conductive layer 142 and the upper surface of the semiconductor layer 1, reducing the process complexity and simplifying the process steps for forming the gate contact hole 31. In addition, the gate conductive layer 142 is not formed in the first end region 111 and the second end region 113 of the first trench 11 to prevent the shielded-gate contact hole 3 formed in the shielded-gate layer 131 in the first end region 111 and the second end region 113 from extending to the gate conductive layer 142, which affects the yield of the device.

[0131] Embodiment 2

[0132] This embodiment provides a shielded-gate trench MOSFET structure, as Figure 10 and Figure 11As shown, they are respectively a schematic cross-sectional structure diagram of the structures in the first trench and the second trench of the shield-gate trench MOSFET structure, and a schematic cross-sectional structure diagram of the structures in the first trench, the second trench and the third trench of the shield-gate trench MOSFET structure, including a semiconductor layer 1, a first trench 11, a dielectric layer 121, a shield-gate layer 131, a second trench 14, a third trench 15, a gate dielectric layer 141, a gate conductive layer 142, a shield-gate contact hole 3 and a gate contact hole 31. Among them, the first trench 11 is located in the semiconductor layer 1 and is arranged at intervals in the X direction, and the opening of the first trench 11 faces upward and extends in the Y direction. The X direction and the Y direction are perpendicular to each other. The first trench 11 includes a first end region 111, a gate lead-out region 112 and a second end region 113 arranged in sequence along the Y direction; the dielectric layer 121 is located on the inner wall and the bottom surface of the first trench 11; the shield-gate layer 131 fills the first trench 11, and the side wall and the bottom surface of the shield-gate layer 131 are wrapped by the dielectric layer 121; the second trench 14 is located in a preset area of the gate lead-out region 112, and the opening of the second trench 14 faces upward. The bottom surface and the side wall in the Y direction of the second trench 14 are both the shield-gate layer 131; the third trench 15 is located above the dielectric layer 121 between the first end region 111 and the second end region 113, and the third trench 15 is located on both sides of the shield-gate layer 131 and on both sides of the second trench 14 in the X direction. The third trench 15 communicates with the second trench 14 in the X direction; the gate dielectric layer 141 is located on the inner wall and the bottom surface of the second trench 14 and the third trench 15, and the gate conductive layer 142 is located in the second trench 14 and the third trench 15 and is wrapped by the gate dielectric layer 141; the bottom of the shield-gate contact hole 3 extends into the shield-gate layer 131, and the gate contact hole 31 is located in the second trench 14 and the bottom extends into the gate conductive layer 142.

[0133] Specifically, the thickness of the semiconductor layer 1 can be selected according to the actual situation and will not be limited here.

[0134] Specifically, the opening size and trench depth of the first trench 11 can be selected according to the actual situation and will not be limited here.

[0135] Specifically, the number of the formed first trenches 11 can be set according to the actual situation and will not be limited here.

[0136] Specifically, on the premise of ensuring that there is enough area in the second trench 14 to set the gate contact hole 31, the opening size of the second trench 14 in the Y direction can be set according to the actual situation and will not be limited here.

[0137] Specifically, the depth of the second trench 14 may be the same as the depth of the third trench 15 or less than the depth of the third trench 15.

[0138] Specifically, the thickness of the gate dielectric layer 141 can be set according to actual conditions and will not be limited here.

[0139] Specifically, as Figure 12 shown, it is a planar layout diagram of the shielded gate trench MOSFET structure. By providing the second trench 14 in the gate lead-out region 112 and the second trench 14 communicating with the third trench 15 in the X direction, sufficient space is provided for forming the gate contact hole 31 in the gate conductive layer 42, eliminating the need to set a dedicated gate contact hole lead-out region in the device layout, simplifying the process, and saving costs.

[0140] Specifically, the gate conductive layer 142 is not provided in the first end region 111 and the second end region 113 to prevent insufficient space for forming the shielded gate contact hole 3 in the first end region 111 and the second end region 113, or to prevent the shielded gate contact hole 3 from extending into the gate conductive layer 142 due to the position offset of the contact hole, which affects the yield of the contact hole.

[0141] Specifically, the shielded gate trench MOSFET structure further includes a second conductivity type body region, a first conductivity type source region, a source contact hole, a source, a gate, a drain, and a passivation layer.

[0142] The shielded gate trench MOSFET structure of this embodiment provides sufficient space for setting the gate contact hole 31 by providing the second trench communicating with the third trench in the X direction in the gate lead-out region 112 of the first trench 11, eliminating the need to set a gate contact hole lead-out region in the layout, simplifying the process complexity, and saving the manufacturing cost.

[0143] In summary, for the shielded-gate trench MOSFET structure and its manufacturing method of the present invention, a first end region, a gate lead-out region, and a second end region are defined in the first trench, and a second trench with a sufficiently large space is formed in the gate lead-out region. In the X direction, the second trench communicates with third trenches located on both sides of the shielded-gate layer and the second trench, so that the gate contact hole can be formed in the second trench with sufficient space, avoiding the problem that there is not enough space in the gate conductive layers on both sides of the shielded-gate layer in the X direction due to the too small device size, eliminating the problem that it is easy to generate a bridging risk by separately defining the gate contact hole and leading out the gate conductive layer in the layout, solving the problem of complex process caused by the height difference between the upper surface of the gate conductive layer and the upper surface of the semiconductor layer, simplifying the process steps, and saving the manufacturing cost. In addition, no gate conductive layer is formed in the first end region and the second end region, preventing the formed shielded-gate contact hole from extending into the gate conductive layer and affecting the yield of the device. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0144] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A preparation method of a shield-gate trench MOSFET structure, characterized in that, including the following steps: providing a semiconductor layer, and forming a plurality of first trenches spaced apart along the X direction in the semiconductor layer, wherein the openings of the first trenches face upward and extend along the Y direction, and the X direction is perpendicular to the Y direction; successively forming a dielectric material layer and a conductive material layer in the first trenches, wherein the dielectric material layer is located on the inner walls and bottom surface of the first trenches and wraps the side walls and bottom surface of the conductive material layer; defining a first end region, a gate lead-out region, and a second end region successively arranged along the Y direction in the first trenches, forming a second trench in a preset region of the gate lead-out region, the second trench opening from the top of the conductive material layer and extending downward, and the conductive material layer in the first trenches outside the second trench constitutes a shielding gate layer; etching the dielectric material layer between the first end region and the second end region to obtain third trenches located on both sides of the shielding gate layer and on both sides of the second trench along the X direction, the third trenches communicating with the second trench in the X direction, and the dielectric material layer in the first trenches outside the third trenches constitutes a dielectric layer; successively forming a gate dielectric layer and a gate conductive layer in the third trenches and the second trenches, and the gate dielectric layer is located on the inner walls and bottom surface of the second trenches and the third trenches, and the gate dielectric layer wraps the side walls and bottom surface of the gate conductive layer; forming a shielding gate contact hole with the bottom extending to the shielding gate layer, and forming a gate contact hole with the bottom extending into the gate conductive layer in the second trench.

2. The manufacturing method of the shield gate trench MOSFET structure according to claim 1, characterized in that: The upper surface of the gate conductive layer is flush with the upper surface of the semiconductor layer.

3. The manufacturing method of the shielded gate trench MOSFET structure according to claim 1, characterized in that: The shielding gate contact holes are distributed in the shielding gate layer in the first end region and the second end region.

4. The manufacturing method of the shield gate trench MOSFET structure according to claim 1, characterized in that: The upper surface of the dielectric layer in the first end region is flush with the upper surface of the semiconductor layer, and the upper surface of the dielectric layer in the second end region is flush with the upper surface of the semiconductor layer.

5. The manufacturing method of the shield gate trench MOSFET structure according to claim 1, characterized in that: The length of the third trenches along the Y direction is the same as the length of the gate lead-out region.

6. The manufacturing method of the shield gate trench MOSFET structure according to claim 1, characterized in that: The depth of the second trench is less than the depth of the third trench.

7. The manufacturing method of the shield gate trench MOSFET structure according to claim 1, characterized in that: After forming the gate conductive layer and before forming the gate contact hole and the shielding gate contact hole, it further includes the step of forming a second-conductivity-type body region and a first-conductivity-type source region, and the body region is located on the upper surface layer of the semiconductor layer between two adjacent first trenches, and the source region is located on the upper surface layer of the body region.

8. The manufacturing method of the shield gate trench MOSFET structure according to claim 7, characterized in that: After forming the body region and the source region and before forming the gate contact hole and the shielding gate contact hole, it further includes the step of forming an interlayer dielectric layer on the upper surface of the semiconductor layer.

9. The manufacturing method of the shield gate trench MOSFET structure according to claim 8, characterized in that: After forming the gate contact hole and the shielding gate contact hole, it further includes the steps of forming a source electrode, a gate electrode, a drain electrode, and a passivation layer.

10. A shielded gate trench MOSFET structure, characterized in that, including: a semiconductor layer; a plurality of first trenches, located in the semiconductor layer, spaced apart along the X direction, and the openings of the first trenches face upward and extend along the Y direction, the X direction is perpendicular to the Y direction, and the first trenches include a first end region, a gate lead-out region, and a second end region successively arranged along the Y direction; A dielectric layer, located on the inner wall and bottom surface of the first trench; A shielding gate layer, filling the first trench, and the side wall and bottom surface of the shielding gate layer are wrapped by the dielectric layer; A second trench, located in a preset area of the gate lead-out region, and the second trench has an upward opening, and the bottom surface and the side wall in the Y direction of the second trench are both the shielding gate layer; A third trench, located above the dielectric layer between the first end region and the second end region, and the third trench is located on both sides of the shielding gate layer and on both sides of the second trench along the X direction, and the third trench communicates with the second trench in the X direction; A gate dielectric layer and a gate conductive layer, the gate dielectric layer is located on the inner wall and bottom surface of the second trench and the third trench, and the gate conductive layer is located in the second trench and the third trench and is wrapped by the gate dielectric layer; A shielding gate contact hole and a gate contact hole, the bottom of the shielding gate contact hole extends into the shielding gate layer, and the gate contact hole is located in the second trench and the bottom extends into the gate conductive layer.

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