Metal interconnect structure and preparation method thereof

Abstract

The present invention provides a metal interconnect structure and a preparation method, the preparation method comprising the steps of: depositing a metal material layer and a photoresist layer on a dielectric layer in sequence; then patterning the photoresist layer, etching the metal material layer with the patterned photoresist layer as a mask to form a metal layer, the top corners of the metal layer are in a rounded shape; finally depositing a second dielectric layer to cover the metal layer. Among them, dry etching includes two stages. In the first stage, the consumption of the photoresist layer is enhanced by reducing the etching selectivity, and at the same time, a suitable etching gas is selected to form the edge of the photoresist layer into a rounded shape; in the second stage, the etching selectivity is increased to increase the consumption of the metal material layer. In this stage, as the edge of the photoresist layer gradually shrinks, the exposed metal layer is also gradually etched, and finally the top corners of the metal layer are formed into a rounded shape. Thereby, problems such as cracks caused by stress concentration are avoided, the performance and service life of the device are improved, and the stability is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a metal interconnection structure and a preparation method thereof. Background Art

[0002] With the continuous advancement of ultra-large-scale integrated circuit process technology, the characteristic size of semiconductor devices continues to shrink, and the performance of semiconductor devices is getting stronger and stronger. Metal interconnection structure is an indispensable structure for semiconductor devices, such as copper-aluminum interconnection (Cu / Al), tungsten-copper interconnection (W / Cu), tungsten-aluminum interconnection (W / Al) and other interconnection structures. In the semiconductor manufacturing process, the quality of the formed metal interconnection structure has a great influence on the performance of semiconductor devices. In order to connect the integrated circuits composed of various components, metal materials with relatively high conductivity are usually used, but as the size of semiconductor devices continues to shrink, the interconnection structure becomes narrower and narrower, which also puts forward new requirements for the stability of the metal interconnection structure.

[0003] like Figure 3 As shown, in a common metal interconnect structure, the metal layer 12 electrically connected to the metal plug 11 is coated by the second dielectric layer 201. The second dielectric layer 201 formed will cause a greater stress effect on the metal layer 12, especially at the edge position of the top corner of the metal layer 12, where the stress is more concentrated. Due to the excessive local stress, cracks are very likely to occur, causing adverse effects, such as affecting the conductivity and causing excessive local resistance and severe heat generation, thereby affecting the performance and service life of the device and reducing the quality of the device. Especially when the second dielectric layer is thicker, the stress at the top corner of the metal layer is greater, which will eventually cause cracks in the dielectric layer. When the metal interconnect structure is applied to automotive electronic devices, its safety and stability should be guaranteed.

[0004] Therefore, a method needs to be proposed to improve the morphology of the metal layer and eliminate the adverse effects caused by stress.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a metal interconnect structure and a preparation method thereof, so as to solve the problems in the prior art that the metal layer is prone to cracks and has poor stability.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a metal interconnect structure, the method comprising the following steps:

[0008] S1: providing a first dielectric layer, wherein a metal plug is formed in the first dielectric layer;

[0009] S2: depositing a metal material layer and a photoresist layer in sequence on the dielectric layer;

[0010] S3: patterning the photoresist layer, and using the patterned photoresist layer as a mask to dry-etch the metal material layer to form a metal layer electrically connected to the metal plug, wherein the top corners of the metal layer are rounded;

[0011] S4: depositing a second dielectric layer on the first dielectric layer to cover the metal layer.

[0012] Preferably, in step S2, the thickness ratio of the metal material layer to the photoresist layer is 1:0.7 to 1:1.5, and the thickness of the photoresist layer is

[0013] Preferably, the dry etching gas in step S3 includes one or any one of boron trichloride, silicon tetrachloride, carbon tetrachloride, trifluoromethane, oxygen, chlorine, nitrogen, and sulfur hexafluoride.

[0014] Preferably, step S3 includes a first stage and a second stage;

[0015] In the first stage, the consumption of the photoresist layer is enhanced by reducing the etching selectivity, so that the thickness of the edge of the photoresist layer is reduced to 0, and a rounded shape with a relative height gradually increasing from the outer edge to the inside is formed, and at the same time, the upper part of the metal material layer not covered by the photoresist layer is also removed;

[0016] In the second stage, the consumption of the metal material layer is increased by increasing the etching selectivity. As the edge of the photoresist layer gradually shrinks, the exposed metal layer is also gradually etched, and finally the rounded shape of the edge of the photoresist layer formed in the first stage is transferred to the metal layer, so that the top corner of the metal layer is formed into a rounded shape.

[0017] Preferably, the etching selection ratio in the first stage is 1:1-2:1, and the etching gas includes boron trichloride and oxygen.

[0018] Preferably, the etching selectivity ratio in the second stage is greater than 3:1, and the etching gas includes trifluoromethane.

[0019] Preferably, after step S3, a cleaning process for residual photoresist is also included.

[0020] Preferably, the material of the first dielectric layer and the second dielectric layer includes silicon oxide.

[0021] Preferably, the material of the metal plug is tungsten.

[0022] Preferably, the metal material layer is an aluminum-copper alloy.

[0023] The present invention also provides a metal interconnect structure, comprising:

[0024] a first dielectric layer, wherein a metal plug is formed in the first dielectric layer;

[0025] a metal layer, the metal layer being electrically connected to the metal plug, and having a rounded top corner;

[0026] A second dielectric layer is formed on the first dielectric layer and covers the metal layer.

[0027] Preferably, the metal layer is obtained by dry etching a metal material layer.

[0028] Preferably, the material of the first dielectric layer and the second dielectric layer includes silicon oxide.

[0029] Preferably, the material of the metal plug is tungsten.

[0030] Preferably, the metal layer is an aluminum-copper alloy.

[0031] As described above, the present invention provides a metal interconnect structure and a preparation method, the preparation method comprising the steps of: depositing a metal material layer and a photoresist layer on a dielectric layer in sequence; then patterning the photoresist layer, etching the metal material layer with the patterned photoresist layer as a mask to form a metal layer, the top corners of the metal layer being in a rounded shape; and finally depositing a second dielectric layer to cover the metal layer. Among them, dry etching includes two stages. In the first stage of etching, the consumption of the photoresist layer is enhanced by reducing the etching selectivity, and at the same time, a suitable etching gas is selected to form the edge of the photoresist layer into a rounded shape; in the second stage of etching, the etching selectivity is increased to increase the consumption of the metal material layer. In this stage, as the edge of the photoresist layer gradually shrinks, the exposed metal layer is also gradually etched, and finally the rounded shape of the edge of the photoresist layer formed in the first stage is transferred to the metal layer, that is, the top corners of the metal layer are formed into a rounded shape. In addition, the thickness of the photoresist layer is also limited, so that the edge is more easily thinned into a rounded shape. The metal layer of the metal interconnect structure is ultimately formed into a rounded shape, eliminating edges, making stress more dispersed, avoiding problems such as cracks caused by stress concentration, and thereby improving device performance and service life and improving stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure after the photoresist layer is patterned in the prior art.

[0033] Figure 2It is a schematic diagram of the structure after etching the metal material layer in the prior art.

[0034] Figure 3 It is a schematic diagram of the structure of the interconnection structure in the prior art.

[0035] Figure 4 It is a schematic diagram showing the structure of sequentially forming a metal material layer and a photoresist layer in the present invention.

[0036] Figure 5 Shown is a schematic structural diagram of patterning the photoresist layer in the present invention.

[0037] Figure 6 It is a schematic diagram of the structure after the first stage etching in the present invention.

[0038] Figure 7 It is a schematic diagram of the structure after the second stage etching in the present invention.

[0039] Figure 8 It is a schematic diagram of an interconnect structure with a rounded metal layer formed in the present invention.

[0040] Component number description

[0041] 101 First dielectric layer

[0042] 102 Metal material layer

[0043] 103 Photoresist layer

[0044] 201 Second dielectric layer

[0045] 11 Metal plug

[0046] 12 Metal Layer DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0049] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0050] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0051] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0052] Photolithography is usually used in the process of preparing metal interconnect structures. Photolithography is the process of transferring patterns to photoresist. Then the patterned photoresist is used as a mask to transfer the pattern to the underlying material layers. This process is called etching, which selectively etches away the parts of the thin layer that are not covered by the photoresist. Etching usually includes two basic methods: wet chemical etching and dry etching.

[0053] Wet etching is to immerse the wafer in a corrosive solution. It has isotropy, that is, the lateral etching is equal to the longitudinal etching. Its biggest disadvantage is that lateral drilling will occur, resulting in a decrease in the resolution of the etched pattern. Dry etching refers to a method of removing substances by using a plasma-activated chemical reaction or by bombarding with a high-energy ion beam. Because no solution is used in etching, it is called dry etching. In dry etching, it is anisotropic, that is, the longitudinal etching rate is much greater than the lateral etching rate. In this way, the material below the edge of the photoresist will not be etched because it is protected by the photoresist. In order to achieve the high-precision pattern transfer required by the process of large-scale integrated circuits, dry etching has developed rapidly.

[0054] like Figure 1-Figure 3As shown, the metal interconnection structure in the prior art includes the following steps: forming a metal material layer 102 above a first dielectric layer 101; then forming a photoresist layer 103 above the metal material layer 102, and patterning the photoresist layer 103; then dry-etching the metal material layer 102 using the patterned photoresist layer 103 as a mask to form a metal layer 12, the metal layer 12 is electrically connected to the metal plug 11 located in the first dielectric layer 101, and finally forming a second dielectric layer 201 to cover the metal layer 12.

[0055] In the metal interconnect structure formed by the above-mentioned existing method, the second dielectric layer 201 formed will cause a large stress impact on the metal layer 12, especially the edge position at the top corner of the metal layer 12, where the stress is more concentrated. Due to the excessive local stress, cracks are very likely to occur, causing adverse effects, such as affecting the conductive performance and causing excessive local resistance and severe heat generation, thereby affecting the performance and service life of the device and reducing the quality of the chip.

[0056] Therefore, the present invention improves the dry etching process, and finally forms the top corner of the metal layer 12 into a rounded shape, thereby dispersing the stress distribution, improving the structural stability of the metal layer, and improving the final device performance.

[0057] Embodiment 1

[0058] This embodiment provides a method for preparing a metal interconnection layer. Figure 4-Figure 8 As shown, the specific steps include:

[0059] S1: providing a first dielectric layer 101, wherein a metal plug 11 is formed in the first dielectric layer 101;

[0060] S2: depositing a metal material layer 102 and a photoresist layer 103 on the dielectric layer 101 in sequence;

[0061] S3: patterning the photoresist layer 103, and etching the metal material layer 102 using the patterned photoresist layer 103 as a mask to form a metal layer 12 electrically connected to the metal plug 11, wherein the top corners of the metal layer 12 are rounded;

[0062] S4 : depositing a second dielectric layer 201 on the first dielectric layer 101 to cover the metal layer 12 .

[0063] Specifically, Figure 4As shown, in step S1, the first dielectric layer includes but is not limited to a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer, and may also be a single layer or a multilayer structure. In this embodiment, a silicon oxide layer is preferably used. Then, a plurality of vertical through holes are formed in the first dielectric layer by an etching process, and then a metal plug 11 is deposited in the vertical through hole. The metal plug 11 is preferably tungsten. Metal tungsten is often used to make conductive plugs to connect adjacent metal layers due to its good conductivity and step coverage. In addition, after depositing metal tungsten, a process of flattening the surface of the first dielectric layer may also be included, such as removing the metal tungsten outside the vertical through hole by chemical mechanical grinding, or thinning the first dielectric layer to a desired thickness, so as to further obtain a flat surface to facilitate the subsequent formation of the metal material layer 102.

[0064] Specifically, Figure 4 As shown, in step S2, the metal material layer 102 is formed on the surface of the first dielectric layer 101 by using a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process. The metal material layer can be one or any of copper, aluminum, gold, silver, nickel, and cobalt. In this embodiment, the metal material layer 102 is preferably an aluminum-copper alloy, wherein the material aluminum has the advantages of low resistance, easy deposition and etching, and is commonly used in conductive interconnect structures. After forming the metal material layer 102, the photoresist layer 103 is formed on the surface of the metal material layer, and the photoresist layer 103 can be obtained by spin coating. The thickness of the photoresist layer should not be too thick, and the specific reason is: in dry etching, although the material located below the edge of the photoresist can be protected by the photoresist and will not be etched. However, in the process of dry etching, the plasma will bombard and etch the photoresist layer at the same time, especially at the edge of the photoresist layer, because the upper surface and the side are etched synchronously, it is easy to be thinned. Therefore, this characteristic can be used to make the edge of the photoresist layer thinned and rounded during etching, thereby further facilitating the formation of rounded corners at the top corners of the metal layer 12 in the subsequent step S3. Preferably The thickness ratio of the metal material layer 102 to the photoresist layer 103 is 1:0.7 to 1:1.5, preferably 1:1.27. The metal material layer 102 is a sandwich structure, including upper and lower adhesive layers and a main body layer sandwiched between the adhesive layers. As an example, the thickness of the adhesive layer is The thickness of the main layer is

[0065] Specifically, in step S3, the metal material layer 102 is etched using the patterned photoresist layer 103 as a mask to form the metal layer 12, which includes two stages:

[0066] The first stage is the initial stage of etching, and the consumption of the photoresist layer 103 can be enhanced by reducing the etching selectivity, so that the thickness of the edge of the photoresist layer is reduced to 0, and a rounded shape with a relative height gradually increasing from the outer edge to the inside is formed, and at the same time, the upper part of the metal material layer 102 not covered by the photoresist layer is also removed. Figure 6 As shown. The etching selectivity is the ratio of the etching rate of the material layer (corresponding to the metal material layer 102) to the etching rate of the mask layer (corresponding to the photoresist layer 103). In the initial stage of etching, the etching selectivity is adjusted to 1:1 to 2:1, and the etching gas includes but is not limited to one or any of boron trichloride (BC13), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), trifluoromethane (CHF3), oxygen (O2), chlorine (C12), nitrogen (N2), and sulfur hexafluoride (SF6). As an implementation scheme, the etching selectivity is adjusted by adjusting the proportion of the etching gas. For example, the selective etching gas includes boron trichloride (BC13) and oxygen (O2). In the first stage, the proportion of oxygen is increased, and the oxygen will continuously etch the photoresist. At the same time, the oxygen will form an oxide layer (aluminum oxide) on the surface of the metal material layer, reducing the consumption of the metal material layer. In addition, the etching of the chlorine-based gas is isotropic, which is more conducive to the lateral etching of the photoresist layer. In addition, the upper surface and the side surface at the edge of the photoresist layer are etched simultaneously, so it is easy to thin the edge of the photoresist layer into a rounded shape.

[0067] Next, the second stage is performed, in which the consumption of the metal material layer 102 is increased by increasing the etching selectivity. In this stage, the edge of the photoresist layer is etched away. At the same time, as the edge of the photoresist layer gradually shrinks, the exposed metal layer is also gradually etched, and finally the rounded shape of the edge of the photoresist layer formed in the first stage is transferred to the metal layer 12, that is, the top corner of the metal layer 12 is formed into a rounded shape, as shown in FIG. Figure 7 As shown. In this stage, the etching selectivity is adjusted to be greater than 3:1. As an implementation scheme, the selective etching gas includes trifluoromethane (CHF3). The etching of trifluoromethane (CHF3) is anisotropic and will react with carbon atoms in the photoresist to generate polymers that are deposited on the metal sidewalls, protecting the sidewalls from ion bombardment and reaction with the reaction gas, thereby obtaining good anisotropic etching and avoiding lateral drilling of the metal material layer 102. The etching time of the first stage and the second stage can be adjusted according to actual needs.

[0068] Furthermore, after etching is completed, a cleaning process for residual photoresist is also included. Oxygen plasma can be used to remove the residual photoresist, and an oxide layer can be formed on the metal surface to protect the metal. Deionized water is then used for rinsing, especially to clean and remove the etching residues deposited on the metal surface to prevent these residues from continuing to react with the metal and corroding the metal.

[0069] Specifically, in step S4, Figure 8 As shown, the formed second dielectric layer 201 is similar to the first dielectric layer 101, and may also include but not limited to a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer, and may be a single layer or a multilayer structure. In this embodiment, the second dielectric layer 201 is also preferably a silicon oxide layer. In addition, this step may also include an annealing process to release stress and densify the oxide layer.

[0070] This embodiment provides a method for preparing a metal interconnect structure, including the steps of: depositing a metal material layer and a photoresist layer on a dielectric layer in sequence; then patterning the photoresist layer, etching the metal material layer with the patterned photoresist layer as a mask to form a metal layer, and the top corners of the metal layer are rounded; finally, depositing a second dielectric layer to cover the metal layer. Among them, dry etching includes two stages. In the first stage of etching, the consumption of the photoresist layer is enhanced by reducing the etching selectivity, and at the same time, a suitable etching gas is selected to form the edge of the photoresist layer into a rounded shape; in the second stage of etching, the etching selectivity is increased to increase the consumption of the metal material layer. In this stage, as the edge of the photoresist layer gradually shrinks, the exposed metal layer is also gradually etched, and finally the rounded shape of the edge of the photoresist layer formed in the first stage is transferred to the metal layer, that is, the top corners of the metal layer are formed into a rounded shape. In addition, the thickness of the photoresist layer is also limited, so that the edge is more easily thinned into a rounded shape. The metal layer of the metal interconnect structure is ultimately formed into a rounded shape, eliminating edges, making stress more dispersed, avoiding problems such as cracks caused by stress concentration, and thereby improving device performance and service life and improving stability.

[0071] Embodiment 2

[0072] This embodiment provides a metal interconnection structure, which can be obtained by the preparation method of the above embodiment, but is not limited to the above preparation method. Figure 8 As shown, the metal interconnect structure specifically includes:

[0073] A first dielectric layer 101, wherein a metal plug 11 is formed in the first dielectric layer 101;

[0074] A metal layer 12, wherein the metal layer 12 is electrically connected to the metal plug 11, and the top corners of the metal layer 12 are rounded;

[0075] The second dielectric layer 201 is formed on the first dielectric layer 101 and covers the metal layer 12 .

[0076] Specifically, the first dielectric layer includes but is not limited to a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer, and may also be a single layer or a multilayer structure, and in this embodiment, a silicon oxide layer is preferred. A plurality of vertical through holes may be formed in the first dielectric layer by an etching process, and then a metal plug 11 is deposited in the vertical through hole, and the metal plug 11 is preferably tungsten. Metal tungsten is often used to make conductive plugs to connect adjacent metal layers due to its good conductivity and step coverage.

[0077] Furthermore, the metal layer 12 is obtained by dry etching the metal material layer 102. Specifically, the metal material layer 102 can be formed on the surface of the first dielectric layer 101 by using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The metal material layer 102 can be one or any of copper, aluminum, gold, silver, nickel, and cobalt. In this embodiment, the metal material layer 102 is preferably an aluminum-copper alloy, wherein the material aluminum has the advantages of low resistance, easy deposition and etching, and is commonly used in conductive interconnect structures. After forming the metal material layer 102, the photoresist layer 103 is formed on the surface of the metal material layer, and then the metal material layer 102 is dry-etched using the patterned photoresist layer 103 as a mask to form the metal layer 12.

[0078] Furthermore, in the dry etching process, it is divided into two stages. The first stage is the initial stage of etching. The consumption of the photoresist layer 103 can be enhanced by reducing the etching selectivity, so that the thickness at the edge of the photoresist layer is reduced to 0, and a rounded shape with a relative height gradually increasing from the outer edge to the inside is formed, and the upper part of the metal material layer 102 not covered by the photoresist layer is also removed. The etching selectivity is the ratio of the etching rate of the material layer (corresponding to the metal material layer 102) to the mask layer (corresponding to the photoresist layer 103). In the initial stage of etching, the etching selectivity is adjusted to 1:1 to 2:1, and the etching gas includes but is not limited to one or any of boron trichloride (BC13), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), trifluoromethane (CHF3), oxygen (O2), chlorine (C12), nitrogen (N2), and sulfur hexafluoride (SF6). As an implementation scheme, the etching selectivity is adjusted by adjusting the proportion of the etching gas. For example, the selective etching gas includes boron trichloride (BC13) and oxygen (O2). In the first stage, the proportion of oxygen is increased, and the oxygen will continuously etch the photoresist. At the same time, the oxygen will form an oxide layer (aluminum oxide) on the surface of the metal material layer, reducing the consumption of the metal material layer. In addition, the etching of the chlorine-based gas is isotropic, which is more conducive to the lateral etching of the photoresist layer. In addition, the upper surface and the side surface at the edge of the photoresist layer are etched simultaneously, so it is easy to thin the edge of the photoresist layer into a rounded shape.

[0079] Next, the second stage is carried out, and the consumption of the metal material layer 102 is increased by increasing the etching selectivity. In this stage, the edge of the photoresist layer is etched away. At the same time, as the edge of the photoresist layer gradually shrinks, the exposed metal layer is also gradually etched, and finally the rounded shape of the edge of the photoresist layer formed in the first stage is transferred to the metal layer 12, that is, the top corner of the metal layer 12 is formed into a rounded shape. In this stage, the etching selectivity is adjusted to be greater than 3:1. As an implementation scheme, the selective etching gas includes trifluoromethane (CHF3). The etching of trifluoromethane (CHF3) is anisotropic, and it will react with carbon atoms in the photoresist to generate polymers that are deposited on the metal side walls, protecting the side walls from ion bombardment and not reacting with the reaction gas, thereby obtaining good anisotropic etching and avoiding lateral drilling of the metal material layer 102. The etching time of the first stage and the second stage can be adjusted according to actual needs.

[0080] Furthermore, after completing the rounding of the metal layer 12, the second dielectric layer 201 is deposited to form the second dielectric layer 201. The second dielectric layer 201 is similar to the first dielectric layer 101, and may include but not be limited to a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer. It may be a single-layer or multi-layer structure. In this embodiment, the second dielectric layer 201 is also preferably a silicon oxide layer.

[0081] In summary, the present invention provides a metal interconnect structure and a preparation method, the preparation method comprising the steps of: depositing a metal material layer and a photoresist layer on a dielectric layer in sequence; then patterning the photoresist layer, etching the metal material layer with the patterned photoresist layer as a mask to form a metal layer, the top corners of the metal layer being in a rounded shape; and finally depositing a second dielectric layer to cover the metal layer. Among them, dry etching includes two stages. In the first stage of etching, the consumption of the photoresist layer is enhanced by reducing the etching selectivity, and at the same time, a suitable etching gas is selected to form the edge of the photoresist layer into a rounded shape; in the second stage of etching, the etching selectivity is increased to increase the consumption of the metal material layer. In this stage, as the edge of the photoresist layer gradually shrinks, the exposed metal layer is also gradually etched, and finally the rounded shape of the edge of the photoresist layer formed in the first stage is transferred to the metal layer, that is, the top corners of the metal layer are formed into a rounded shape. In addition, the thickness of the photoresist layer is also limited, so that the edge is more easily thinned into a rounded shape. The metal layer of the metal interconnect structure is ultimately formed into a rounded shape, eliminating edges, making stress more dispersed, avoiding problems such as cracks caused by stress concentration, and thereby improving device performance and service life and improving stability.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a metal interconnect structure, characterized in that: The preparation method comprises the following steps: S1: providing a first dielectric layer, wherein a metal plug is formed in the first dielectric layer; S2: depositing a metal material layer and a photoresist layer in sequence on the dielectric layer; S3: Patterning the photoresist layer, using the patterned photoresist layer as a mask to dry-etch the metal material layer to form a metal layer electrically connected to the metal plug, wherein the top corners of the metal layer are rounded; wherein the step S3 includes a first stage and a second stage; in the first stage, the consumption of the photoresist layer is enhanced by reducing the etching selectivity, so that the thickness at the edge of the photoresist layer is reduced to 0, and a rounded shape with a relative height gradually increasing from the outer edge to the inside is formed, and at the same time, the upper part of the metal material layer not covered by the photoresist layer is also removed; in the second stage, the consumption of the metal material layer is increased by increasing the etching selectivity, and as the edge of the photoresist layer gradually shrinks, the exposed metal layer is also gradually etched, and finally the rounded shape of the edge of the photoresist layer formed in the first stage is transferred to the metal layer, so that the top corner of the metal layer is formed into a rounded shape; S4: depositing a second dielectric layer on the first dielectric layer to cover the metal layer.

2. The preparation method according to claim 1, characterized in that: In step S2, the thickness ratio of the metal material layer to the photoresist layer is 1:0.7 to 1:1.5, and the thickness of the photoresist layer is 3. The preparation method according to claim 1, characterized in that: The dry etching gas in step S3 includes one or any one of boron trichloride, silicon tetrachloride, carbon tetrachloride, trifluoromethane, oxygen, chlorine, nitrogen, and sulfur hexafluoride.

4. The preparation method according to claim 1, characterized in that: The etching selection ratio in the first stage is 1:1-2:1, and the etching gas includes boron trichloride and oxygen.

5. The preparation method according to claim 1, characterized in that: The etching selectivity ratio in the second stage is greater than 3:1, and the etching gas includes trifluoromethane.

6. The preparation method according to claim 1, characterized in that: After step S3, a cleaning process of residual photoresist is also included.

7. The preparation method according to claim 1, characterized in that: The materials of the first dielectric layer and the second dielectric layer include silicon oxide.

8. The preparation method according to claim 1, characterized in that: The material of the metal plug is tungsten.

9. The preparation method according to claim 1, characterized in that: The metal material layer is an aluminum-copper alloy.

10. A metal interconnect structure, characterized in that: The metal interconnect structure is formed by using the preparation method according to any one of claims 1 to 9, and the metal interconnect structure comprises: a first dielectric layer, wherein a metal plug is formed in the first dielectric layer; a metal layer, the metal layer being electrically connected to the metal plug, and having a rounded top corner; A second dielectric layer is formed on the first dielectric layer and covers the metal layer.

11. The metal interconnect structure according to claim 10, characterized in that: The metal layer is obtained by dry etching the metal material layer.

12. The metal interconnect structure according to claim 10, characterized in that The materials of the first dielectric layer and the second dielectric layer include silicon oxide.

13. The metal interconnect structure according to claim 10, characterized in that The material of the metal plug is tungsten.

14. The metal interconnect structure according to claim 10, characterized in that The metal layer is an aluminum-copper alloy.

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