Semiconductor device

Abstract

This disclosure relates to a semiconductor device. A semiconductor device includes: a first insulating layer; a plurality of first electrodes penetrating the first insulating layer; a plurality of second electrodes penetrating the first insulating layer and located between the plurality of first electrodes; a first high-dielectric-constant layer having a dielectric constant higher than that of the first insulating layer; a plurality of third electrodes penetrating the first high-dielectric-constant layer and respectively connected to the plurality of first electrodes; and a plurality of fourth electrodes penetrating the first high-dielectric-constant layer and located between the plurality of third electrodes.

Description

Technical Field

[0001] This disclosure generally relates to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. With the integration density of semiconductor devices in which memory cells are formed in a single layer on a substrate reaching its limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate has recently been proposed. Various structures and manufacturing methods have been developed to improve the operational reliability of three-dimensional semiconductor devices. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device may be provided, comprising: a first insulating layer; a plurality of first electrodes penetrating the first insulating layer; a plurality of second electrodes penetrating the first insulating layer and located between the plurality of first electrodes; a first high-dielectric-constant layer having a dielectric constant higher than that of the first insulating layer; a plurality of third electrodes penetrating the first high-dielectric-constant layer and respectively connected to the plurality of first electrodes; and a plurality of fourth electrodes penetrating the first high-dielectric-constant layer and located between the plurality of third electrodes.

[0004] According to another aspect of this disclosure, a semiconductor device may be provided, comprising: a first high-dielectric-constant layer; a plurality of first electrodes penetrating the first high-dielectric-constant layer; a plurality of second electrodes penetrating the first high-dielectric-constant layer to a depth different from the depth of the plurality of first electrodes; a second high-dielectric-constant layer located on the first high-dielectric-constant layer; a plurality of third electrodes penetrating the second high-dielectric-constant layer and electrically connected to the plurality of second electrodes; and a plurality of fourth electrodes penetrating the second high-dielectric-constant layer to a depth different from the depth of the plurality of third electrodes, the plurality of fourth electrodes being spaced apart from the plurality of first electrodes.

[0005] According to another aspect of this disclosure, a semiconductor device may be provided, comprising: a first insulating layer; a first electrode penetrating the first insulating layer; a second electrode penetrating the first insulating layer and adjacent to the first electrode; a first high dielectric constant layer having a dielectric constant higher than that of the first insulating layer; a third electrode penetrating the first high dielectric constant layer and connected to the first electrode; and a fourth electrode penetrating the first high dielectric constant layer and adjacent to the third electrode. Attached Figure Description

[0006] Examples of implementation methods will now be described below with reference to the accompanying drawings. However, these examples may be implemented in different forms and should not be construed as limiting oneself to the implementation methods set forth herein.

[0007] In the accompanying drawings, dimensions may be enlarged for clarity. It should be understood that when an element is referred to as being "between" two elements, that element may be the only element between the two elements, or there may be one or more intermediate elements. The same reference numerals always denote the same elements.

[0008] Figure 1A , Figure 1B and Figure 1C This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0009] Figure 2A , Figure 2B and Figure 2C This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0010] Figure 3A and Figure 3B This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0011] Figure 4A , Figure 4B and Figure 4C This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0012] Figure 5A and Figure 5B This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0013] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F and Figure 6GThis is a view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0014] Figure 7A and Figure 7B This is a view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0015] Figure 8A and Figure 8B This is a view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0016] Figure 9A , Figure 9B , Figure 9C and Figure 9D This is a view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0017] Figure 10 This is a schematic diagram illustrating a memory system according to one embodiment of the present disclosure.

[0018] Figure 11 This is a schematic diagram illustrating a memory system according to one embodiment of the present disclosure.

[0019] Figure 12 This is a schematic diagram illustrating a memory system according to one embodiment of the present disclosure.

[0020] Figure 13 This is a schematic diagram illustrating a memory system according to one embodiment of the present disclosure.

[0021] Figure 14 This is a schematic diagram illustrating a memory system according to one embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural or functional descriptions disclosed herein are merely illustrative and are used to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0023] The embodiments provide a semiconductor device with a stable structure and improved properties, as well as a method for manufacturing the semiconductor device.

[0024] Figures 1A to 1C This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 1B It can be Figure 1A The layout, and Figure 1A It can be along Figure 1B The cross-sectional view taken by line A-A' is shown.

[0025] Reference Figures 1A to 1C The semiconductor device may include a high dielectric constant layer HL, a first electrode E1, a second electrode E2, a third electrode E3, and a fourth electrode E4. The semiconductor device may also include a first capping layer C1, a second capping layer C2, a first line L1 or a second line L2, or a combination thereof.

[0026] The high dielectric constant layer HL may include a first high dielectric constant layer HL1 and a second high dielectric constant layer HL2. Each of the first high dielectric constant layer HL1 and the second high dielectric constant layer HL2 may include a high dielectric constant (high k) material. The first high dielectric constant layer HL1 and the second high dielectric constant layer HL2 may include the same high dielectric constant material or different high dielectric constant materials. The second high dielectric constant layer HL2 may be located on top of the first high dielectric constant layer HL1.

[0027] The first electrode E1 and the second electrode E2 can penetrate the first high dielectric constant layer HL1. Each of the first electrode E1 and the second electrode E2 can have a columnar shape, and can also be a planar shape such as a circle, ellipse, or polygon. The first electrode E1 and the second electrode E2 can be arranged along a first direction I and a second direction II intersecting the first direction I. In the first direction I, the first electrode E1 and the second electrode E2 can be arranged alternately. In the second direction II, the first electrode E1 and the second electrode E2 can be arranged alternately. In one embodiment, the first electrode E1 can be adjacent to the second electrode E2, such as... Figure 1A As shown.

[0028] A first capping layer C1 may be located at the bottom of a first high-dielectric-constant layer HL1. A second capping layer C2 may be interposed between the first high-dielectric-constant layer HL1 and the second high-dielectric-constant layer HL2. The first capping layer C1 and the second capping layer C2 may minimize or prevent metal migration from the first electrode E1, the second electrode E2, the third electrode E3, or the fourth electrode E4 to the peripheral layers. Furthermore, the first capping layer C1 and the second capping layer C2 may be used as etch stop layers in the semiconductor device manufacturing process. In one embodiment, the first capping layer C1 and the second capping layer C2 may include a nitride.

[0029] The third electrode E3 can be positioned corresponding to the first electrode E1. The third electrode E3 can penetrate the second high dielectric constant layer HL2 and is connected to the first electrode E1. When the second capping layer C2 is located between the first high dielectric constant layer HL1 and the second high dielectric constant layer HL2, the third electrode E3 can penetrate the second capping layer C2.

[0030] The fourth electrode E4 can be disposed between the third electrodes E3. The fourth electrode E4 can be positioned corresponding to the second electrode E2. The fourth electrode E4 can penetrate the second high dielectric constant layer HL2 and is connected to the second electrode E2. When the second capping layer C2 is located between the first high dielectric constant layer HL1 and the second high dielectric constant layer HL2, the fourth electrode E4 can penetrate the second capping layer C2.

[0031] The third electrode E3 and the fourth electrode E4 can be arranged along a first direction I and a second direction II intersecting the first direction I. In the first direction I, the third electrode E3 and the fourth electrode E4 can be arranged alternately. In the second direction II, the third electrode E3 and the fourth electrode E4 can be arranged alternately. In one embodiment, the third electrode E3 can be adjacent to the fourth electrode E4, such as... Figure 1A As shown.

[0032] The first line L1 can extend along a third direction III, intersecting with the first direction I and the second direction II. Each of the first lines L1 can be electrically connected to a third electrode E3 arranged along the third direction III. The second line L2 can extend along the third direction III. Each of the second lines L2 can be electrically connected to a fourth electrode E4 arranged along the third direction III. The second lines L2 can be located between the first lines L1. The first lines L1 and the second lines L2 can be arranged alternately.

[0033] According to the above structure, the first capacitor electrode CE1, the second capacitor electrode CE2, the first high-dielectric-constant layer HL1, and the second high-dielectric-constant layer HL2 can constitute a capacitor CAP. In one embodiment, as... Figures 1A to 1C As shown, one or more first capacitor electrodes CE1 and one or more second capacitor electrodes CE2, a first high-dielectric-constant layer HL1, and a second high-dielectric-constant layer HL2 can constitute a capacitor CAP. The first capacitor electrode CE1 may include one of the first electrodes E1 and one of the third electrodes E3 electrically connected to each other. The second capacitor electrode CE2 may include one of the second electrodes E2 and one of the fourth electrodes E4 electrically connected to each other. For example, as... Figure 1A As shown, the first capacitor electrode CE1 includes a first electrode E1 and a third electrode E3 that are electrically connected to each other. For example, as... Figure 1A As shown, the second capacitor electrode includes a second electrode E2 and a fourth electrode E4 that are electrically connected to each other.

[0034] Since capacitor CAP includes first plug-type electrodes to fourth plug-type electrodes E1 to E4, its capacitance can be further increased compared to capacitors that include linear electrodes, and a breakdown voltage margin can be ensured. Furthermore, since capacitor CAP includes a first high-dielectric-constant layer HL1 and a second high-dielectric-constant layer HL2, its capacitance can be increased compared to capacitors that do not include high-dielectric-constant layers.

[0035] Furthermore, although the embodiment has described a capacitor CAP having a double-layer structure in which a first high dielectric constant layer HL1 and a second high dielectric constant layer HL2 are stacked, this disclosure is not limited thereto. The capacitor CAP may include three or more high dielectric constant layers stacked together.

[0036] Figures 2A to 2C This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 2B It can be Figure 2A The layout, and Figure 2A It can be along Figure 2B The diagram shows a cross-section taken along line B-B'. Descriptions that overlap with the above will be omitted in the following text.

[0037] Reference Figures 2A to 2C The semiconductor device may include an insulating layer IL, a first electrode E1, a second electrode E2, a high dielectric constant layer HL, a third electrode E3, and a fourth electrode E4. The semiconductor device may also include a capping layer C, a first line L1 or a second line L2, or a combination thereof.

[0038] The insulating layer IL may include oxides, such as silicon oxide. In one embodiment, the insulating layer IL may include a high-density plasma (HDP) oxide layer or a tetraethyl orthosilicate (TEOS) oxide layer, or a combination thereof.

[0039] The high dielectric constant layer HL can be located on top of or at the bottom of the insulating layer IL. The high dielectric constant layer HL can include materials with a dielectric constant higher than that of the insulating layer IL. The high dielectric constant layer HL can include high dielectric constant (high k) materials, such as hafnium oxide (HfO). x The capping layer can be inserted between the insulating layer IL and the high dielectric constant layer HL. In one embodiment, the capping layer C can be inserted between the insulating layer IL and the high dielectric constant layer HL, regardless of whether the insulating layer IL is located above or below the high dielectric constant layer HL.

[0040] The first electrode E1 and the second electrode E2 can penetrate the insulating layer IL. The first electrode E1 and the second electrode E2 can be arranged along a first direction I and a second direction II intersecting the first direction I. The first electrode E1 and the second electrode E2 can be arranged alternately along the first direction I and the second direction II.

[0041] The third electrode E3 can penetrate the high dielectric constant layer HL or penetrate both the high dielectric constant layer HL and the capping layer C. The third electrode E3 can be connected to the first electrode E1. The fourth electrode E4 can be located between the third electrodes E3. The fourth electrode E4 can penetrate the high dielectric constant layer HL or penetrate both the high dielectric constant layer HL and the capping layer C. The fourth electrode E4 can be connected to the second electrode E2.

[0042] The third electrode E3 and the fourth electrode E4 can be arranged along the first direction I and the second direction II. The third electrode E3 and the fourth electrode E4 can be arranged alternately along the first direction I and the second direction II.

[0043] Each of the first lines L1 can extend along the third direction III and is electrically connected to the third electrode E3 arranged along the third direction III. Each of the second lines L2 can extend along the third direction III and is electrically connected to the fourth electrode E4 arranged along the third direction III. The first lines L1 and the second lines L2 can be arranged alternately.

[0044] According to the above structure, the first capacitor electrode CE1, the second capacitor electrode CE2, the insulating layer IL, and the high dielectric constant layer HL can constitute a capacitor CAP. In one embodiment, as... Figures 2A to 2C As shown, one or more first capacitor electrodes CE1 and one or more second capacitor electrodes CE2, a high dielectric constant layer HL, and an insulating layer IL can constitute a capacitor CAP. The first capacitor electrode CE1 may include one of the first electrodes E1 and one of the third electrodes E3 electrically connected to each other. The second capacitor electrode CE2 may include one of the second electrodes E2 and one of the fourth electrodes E4 electrically connected to each other. For example, as... Figure 2A As shown, the first capacitor electrode CE1 includes a first electrode E1 and a third electrode E3 that are electrically connected to each other. For example, as... Figure 2A As shown, the second capacitor electrode includes a second electrode E2 and a fourth electrode E4 that are electrically connected to each other.

[0045] Because capacitor CAP includes an insulating layer IL and a high dielectric constant layer HL, its capacitance can be increased compared to capacitors without a high dielectric constant layer. Furthermore, the combination of the insulating layer IL and the high dielectric constant layer allows for adjustment of the capacitance of capacitor CAP.

[0046] Figure 3A and Figure 3B This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 3A It can be along Figure 3B The diagram shows a cross-section taken along line C-C'. Descriptions that overlap with the above will be omitted in the following text.

[0047] Reference Figure 3A and Figure 3B The semiconductor device may include an insulating layer IL, a first electrode E1, a second electrode E2, a first high dielectric constant layer HL1, a third electrode E3, and a fourth electrode E4. The semiconductor device may also include a substrate SUB, a first capping layer C1, a second capping layer C2, a second high dielectric constant layer HL2, a fifth electrode E5, or a sixth electrode E6, or a combination thereof.

[0048] A second high-dielectric-constant layer HL2 may be located on top of the first high-dielectric-constant layer HL1. The second high-dielectric-constant layer HL2 may include a material with a dielectric constant higher than that of the insulating layer IL. The second high-dielectric-constant layer HL2 may include a high-dielectric-constant (high-k) material, such as hafnium oxide (HfO). x The second high dielectric constant layer HL2 may include the same high dielectric constant material as the first high dielectric constant layer HL1, or may include a high dielectric constant material different from the high dielectric constant material of the first high dielectric constant layer HL1.

[0049] The second capping layer C2 can be interposed between the first high-dielectric-constant layer HL1 and the second high-dielectric-constant layer HL2. The second capping layer C2 can be used to prevent or mitigate the migration of metals included in the third electrode E3 or the fourth electrode E4. Furthermore, the second capping layer C2 can be used as an etch stop layer in the semiconductor device manufacturing process. The second capping layer C2 can include the same material as the first capping layer C1, or it can include a different material than the first capping layer C1. In one embodiment, the second capping layer C2 can include a nitride.

[0050] The fifth electrode E5 can be positioned corresponding to the third electrode E3. The fifth electrode E5 can penetrate the second high dielectric constant layer HL2 and can be connected to the third electrode E3. When the second capping layer C2 is located between the first high dielectric constant layer HL1 and the second high dielectric constant layer HL2, the fifth electrode E5 can penetrate the second capping layer C2.

[0051] The sixth electrode E6 can be located between the fifth electrodes E5. The sixth electrode E6 can be positioned corresponding to the fourth electrode E4. The sixth electrode E6 can penetrate the second high dielectric constant layer HL2 and can be connected to the fourth electrode E4. When the second capping layer C2 is located between the first high dielectric constant layer HL1 and the second high dielectric constant layer HL2, the sixth electrode E6 can penetrate the second capping layer C2.

[0052] The fifth electrode E5 and the sixth electrode E6 can be arranged along the first direction I and the second direction II. In the first direction I, the fifth electrode E5 and the sixth electrode E6 can be arranged alternately. In the second direction II, the fifth electrode E5 and the sixth electrode E6 can be arranged alternately.

[0053] The substrate SUB may include a first active region A1 and a second active region A2. The substrate SUB may also include an isolation layer ISO. The first active region A1 and the second active region A2 may be defined in the substrate SUB by the isolation layer ISO.

[0054] The first active region A1 can be connected to the first electrode E1 and includes a first type of impurity. The first type of impurity can include N-type impurities, such as phosphorus (P), arsenic (As), or antimony (Sb). The second active region A2 can be connected to the second electrode E2 and includes a second type of impurity. The second type of impurity can include P-type impurities, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0055] Each of the first active regions A1 can extend along the third direction III and is electrically connected to a first electrode E1 arranged along the third direction III. Each of the second active regions A2 can extend along the third direction III and is electrically connected to a second electrode E2 arranged along the third direction III. The first active regions A1 and the second active regions A2 can be arranged alternately.

[0056] According to the above structure, one of the first capacitor electrode CE1, the second capacitor electrode CE2, the insulating layer IL, the first high dielectric constant layer HL1, the second high dielectric constant layer HL2, the first active region A1, and the second active region A2 can constitute a capacitor CAP. In one embodiment, as shown... Figure 3A and Figure 3BAs shown, one or more first capacitor electrodes CE1 and one or more second capacitor electrodes CE2, an insulating layer IL, a first high-dielectric-constant layer HL1, a second high-dielectric-constant layer HL2, one or more first active regions A1, and one or more second active regions A2 can constitute a capacitor CAP. The first capacitor electrode CE1 may include one of the first electrodes E1, one of the third electrodes E3, and one of the fifth electrodes E5, all electrically connected to each other. The second capacitor electrode CE2 may include one of the second electrodes E2, one of the fourth electrodes E4, and one of the sixth electrodes E6, all electrically connected to each other. For example, as... Figure 3A As shown, the first capacitor electrode CE1 includes a first electrode E1, a third electrode E3, and a fifth electrode E5 that are electrically connected to each other. For example, as... Figure 3A As shown, the second capacitor electrode includes a second electrode E2, a fourth electrode E4, and a sixth electrode E6 that are electrically connected to each other.

[0057] Since capacitor CAP includes an insulating layer IL, a first high dielectric constant layer HL1, and a second high dielectric constant layer HL2, the capacitance of capacitor CAP can be increased compared to a capacitor that does not include a high dielectric constant layer. Furthermore, the first electrodes E1 can be electrically connected to each other using a first active region A1, and the second electrodes E2 can be electrically connected to each other using a second active region A2.

[0058] Figures 4A to 4C This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 4A It can be along Figure 4B The diagram shows a cross-sectional view taken by line D-D'. Descriptions that overlap with the above will be omitted in the following text.

[0059] Reference Figures 4A to 4C The semiconductor device may include a first insulating layer IL1, a first electrode E1, a second electrode E2, a first high dielectric constant layer HL1, a third electrode E3, and a fourth electrode E4. The semiconductor device may also include a substrate SUB, a transistor TR, a first capping layer C1, a second capping layer C2, a second high dielectric constant layer HL2, a fifth electrode E5, a sixth electrode E6, a seventh electrode E7, or an eighth electrode E8, or a combination thereof.

[0060] The transistor TR can be located on the substrate SUB. The transistor TR can include a gate electrode G, a gate insulating layer GI, and a junction J. The gate electrode G can be located on the substrate SUB. The gate insulating layer GI can be located between the substrate SUB and the gate electrode G. The junction J can be located on both sides of the gate electrode G within the substrate SUB. The junction J can be a region doped with N-type or P-type impurities.

[0061] The first electrode E1 can penetrate the first insulating layer IL1 and is electrically connected to the gate electrode G. The first electrode E1 can be positioned corresponding to the third electrode E3. The second electrode E2 can penetrate the first insulating layer IL1 and is electrically connected to the junction J. The second electrode E2 can be located on both sides of the gate electrode G. The second electrodes E2 can be electrically connected to each other through a third line L3. The third line L3 can be located in the first insulating layer IL1.

[0062] The third electrode E3 can penetrate the first high dielectric constant layer HL1 and the first capping layer C1, and can be connected to the first electrode E1. The fourth electrode E4 can penetrate the first high dielectric constant layer HL1 and the first capping layer C1. The fourth electrode E4 can be located above the gate electrode G and spaced apart from the second electrode E2.

[0063] The second insulating layer IL2 may surround the sidewall HL1_SW of the first high-dielectric-constant layer HL1. In one embodiment, the first high-dielectric-constant layer HL1 may be formed by depositing a high-dielectric-constant material in an opening formed by etching the second insulating layer IL2. The seventh electrode E7 may penetrate the second insulating layer IL2 and the first capping layer C1, and may be connected to the second electrode E2. The number of seventh electrodes E7 may be equal to or different from the number of second electrodes E2. In one embodiment, the number of seventh electrodes E7 may be less than the number of second electrodes E2, and only a portion of the second electrodes E2 may be connected to the seventh electrodes E7.

[0064] The fifth electrode E5 can penetrate the second high-dielectric-constant layer HL2 and the second capping layer C2, and is connected to the third electrode E3. The sixth electrode E6 can be located between the fifth electrodes E5. The sixth electrode E6 can penetrate the second high-dielectric-constant layer HL2 and the second capping layer C2, and is connected to the fourth electrode E4.

[0065] The third insulating layer IL3 may surround the sidewall HL2_SW of the second high-dielectric-constant layer HL2. In one embodiment, the second high-dielectric-constant layer HL2 may be formed by depositing a high-dielectric-constant material in an opening formed by etching the third insulating layer IL3. The eighth electrode E8 may penetrate the third insulating layer IL3 and the second capping layer C2, and may be connected to the seventh electrode E7, respectively.

[0066] Each of the first lines L1 can extend along the third direction III and is electrically connected to the fifth electrode E5 arranged along the third direction III. Therefore, the gate electrode G, the first electrode E1, the third electrode E3, and the fifth electrode E5 are electrically connected to each other, thereby forming the first capacitor electrode CE1.

[0067] Each of the second lines L2 can extend along the third direction III, and the sixth electrode E6, which is arranged along the third direction III, is electrically connected to the eighth electrode E8. Therefore, the junction J, the second electrode E2, the seventh electrode E7, the eighth electrode E8, the fourth electrode E4, and the sixth electrode E6 are electrically connected to each other, thereby forming the second capacitor electrode CE2.

[0068] According to the above structure, the first capacitor electrode CE1, the second capacitor electrode CE2, the first insulating layer IL1, the first high dielectric constant layer HL1, the second high dielectric constant layer HL2, and the transistor TR can constitute a capacitor CAP.

[0069] Since capacitor CAP includes a first insulating layer IL1, a first high dielectric constant layer HL1, and a second high dielectric constant layer HL2, the capacitance of capacitor CAP can be increased compared to a capacitor that does not include a high dielectric constant layer. Furthermore, the first electrodes E1 can be electrically connected to each other using a gate electrode G, and the second electrodes E2 can be electrically connected to each other using a junction J or a third line L3.

[0070] Figure 5A and Figure 5B This is a view showing the structure of a semiconductor device according to one embodiment of the present disclosure.

[0071] Reference Figure 5A and Figure 5B The semiconductor device may include a first high dielectric constant layer HL1, a first electrode E1, a second electrode E2, a second high dielectric constant layer HL2, a third electrode E3, and a fourth electrode E4. The semiconductor device may also include an insulating layer IL, a first capping layer C1, a second capping layer C2, a fifth electrode E5, or a combination thereof.

[0072] The first electrode E1 can penetrate the first high-dielectric-constant layer HL1 or penetrate both the first high-dielectric-constant layer HL1 and the first capping layer C1. The first electrodes E1 can be arranged alternately along a first direction I and a second direction II. The second electrode E2 can penetrate the first high-dielectric-constant layer HL1 with a length different from that of the first electrode E1. The second electrode E2 can penetrate the first high-dielectric-constant layer HL1 to a certain depth. Each of the second electrodes E2 can extend along the first direction I.

[0073] The third electrode E3 can penetrate the second high dielectric constant layer HL2 and the second capping layer C2. The third electrode E3 can be arranged alternately along the first direction I and the second direction II. The third electrode E3 can be connected to the second electrode E2. Each of the second electrodes E2 can be electrically connected to the third electrode E3 arranged along the first direction I.

[0074] The fourth electrode E4 can penetrate the second high-dielectric-constant layer HL2 to a depth different from that of the third electrode E3. The fourth electrode E4 can penetrate the second high-dielectric-constant layer HL2 to a partial depth and is spaced apart from the first electrode E1. Each of the fourth electrodes E4 can extend along a first direction I.

[0075] The insulating layer IL may be located at the bottom of the first high dielectric constant layer HL1. The fifth electrode E5 may penetrate the insulating layer IL. In one embodiment, the fifth electrode E5 may penetrate the insulating layer IL to a certain depth. The fifth electrode E5 may extend along a first direction I. Each of the fifth electrodes E5 may be electrically connected to a first electrode E1 arranged along the first direction I. The fourth electrode E4 and the fifth electrode E5, which overlap each other in the stacking direction, may be electrically connected to each other via a contact plug CT.

[0076] According to the above structure, the first capacitor electrode CE1, the second capacitor electrode CE2, the insulating layer IL, the first high dielectric constant layer HL1, and the second high dielectric constant layer HL2 can constitute a capacitor CAP. The first capacitor electrode CE1 may include a first electrode E1, a fourth electrode E4, and a fifth electrode E5 that are electrically connected to each other. The second capacitor electrode CE2 may include a second electrode E2 and a third electrode E3 that are electrically connected to each other.

[0077] Since the capacitor CAP includes an insulating layer IL, a first high-dielectric-constant layer HL1, and a second high-dielectric-constant layer HL2, its capacitance can be increased compared to a capacitor that does not include a high-dielectric-constant layer. Furthermore, the combination of plug-type electrodes and linear electrodes allows for adjustment of the capacitance of the capacitor CAP. Depending on the application of the capacitor CAP, the capacitance can be increased by increasing the number of plug-type electrodes, or decreased by increasing the number of linear electrodes.

[0078] Figures 6A to 6G This is a view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. In the following description, portions that are repeated above will be omitted.

[0079] Reference Figure 6A A first capping layer 21 is formed. The first capping layer 21 may include a nitride. Subsequently, a first insulating layer 22 is formed on the first capping layer 21. The first insulating layer 22 may include an insulating material, such as silicon oxide. Subsequently, a first opening OP1 is formed by etching the first insulating layer 22. The first opening OP1 may have a depth that exposes the first capping layer 21. When etching the first insulating layer 22, the first capping layer 21 may serve as an etch stop layer.

[0080] Reference Figure 6BA first high dielectric constant layer 23 is formed in the first opening OP1. The first high dielectric constant layer 23 may include a high dielectric constant (high k) material, such as hafnium oxide (HfO). x In one embodiment, the first high-dielectric-constant layer 23 can be formed by depositing a high-dielectric-constant material to fill the first opening OP1, and then planarizing the high-dielectric-constant material until the surface of the first insulating layer 22 is exposed. The planarization process can use a chemical mechanical polishing (CMP) process.

[0081] Reference Figure 6C A second opening OP2 is formed that penetrates the first high-dielectric-constant layer 23. The second opening OP2 can be arranged along a first direction and a second direction intersecting the first direction. Each of the second openings OP2 can have a plane with a circular, elliptical, or polygonal shape, etc. The second opening OP2 can be formed using a photolithography process. Since the second opening OP2 is formed with a aperture shape, the width balance, etc., can be improved in the exposure process compared to forming a linear opening. The second opening OP2 can have a depth that exposes the first capping layer 21. When etching the first high-dielectric-constant layer 23, the first capping layer 21 can be used as an etch stop layer.

[0082] When the second opening OP2 is formed, a third opening OP3 that penetrates the first insulating layer 22 can be formed. The third opening OP3 can have a depth that exposes the first cover layer 21.

[0083] Reference Figure 6D A first conductive layer 24 is formed in the second opening OP2. While forming the first conductive layer 24, a second conductive layer 25 may be formed in the third opening OP3. In one embodiment, after depositing conductive material to fill the second opening OP2 and the third opening OP3, the conductive material is planarized until the surfaces of the first high-dielectric-constant layer 23 and the first insulating layer 22 are exposed. The conductive material may include a metal, such as tungsten (W), copper (Cu), or molybdenum (Mo).

[0084] Subsequently, a second capping layer 26 is formed. The second capping layer 26 may include the same material as the first capping layer 21, or may include a different material than the first capping layer 21. In one embodiment, the second capping layer 26 may include a nitride.

[0085] Reference Figure 6EA second insulating layer 27 is formed on the second cover layer 26. Subsequently, a fourth opening OP4 is formed by etching the second insulating layer 27. The fourth opening OP4 may have a depth that exposes the second cover layer 26. The second cover layer 26 may serve as an etch stop layer when the second insulating layer 27 is etched. Subsequently, a second high-dielectric-constant layer 28 is formed in the fourth opening OP4. The second high-dielectric-constant layer 28 may comprise a high-dielectric-constant (high-k) material, such as hafnium oxide (HfO). x ).

[0086] Reference Figure 6F A fifth opening OP5 is formed, penetrating the second high-dielectric-constant layer 28. The fifth opening OP5 can be arranged along a first direction and a second direction intersecting the first direction. Each of the fifth openings OP5 can be a plane with a circular, elliptical, or polygonal shape, etc. The fifth opening OP5 can be formed using a photolithography process. Because the fifth opening OP5 is formed with a aperture shape, width balance, etc., can be improved in the exposure process compared to forming a linear opening.

[0087] The fifth opening OP5 may have a depth that exposes the first conductive layer 24 while penetrating the second cover layer 26. When forming the fifth opening OP5, a sixth opening OP6 that penetrates the second insulating layer 27 may be formed. The sixth opening OP6 may have a depth that exposes the second conductive layer 25.

[0088] Reference Figure 6G A third conductive layer 29 is formed in the fifth opening OP5. The third conductive layer 29 can be connected to the first conductive layer 24. When forming the third conductive layer 29, a fourth conductive layer 30 can be formed in the sixth opening OP6. The fourth conductive layer 30 can be connected to the second conductive layer 25.

[0089] The first conductive layer 24, the third conductive layer 29, the first high dielectric constant layer 23, and the second high dielectric constant layer 28 can constitute a capacitor. The second conductive layer 25 and the fourth conductive layer 30 can be part of the capacitor or part of an interconnect structure such as a contact plug.

[0090] According to the manufacturing method described above, the first conductive layer 24 and the third conductive layer 29, which serve as electrodes for a capacitor, can be formed using the second opening OP2 and the fifth opening OP5 of the aperture type. Furthermore, the dielectric of the capacitor can be formed using the first high-dielectric-constant layer 23 and the second high-dielectric-constant layer 28. Therefore, the manufacturing process of the semiconductor device can be improved, and the capacitance of the capacitor can be increased.

[0091] Figure 7A and Figure 7BThis is a view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. In the following description, portions that are repeated above will be omitted.

[0092] Reference Figure 7A A first active region 40A and a second active region 40B are formed in the substrate 40. The first active region 40A may include N-type impurities, and the second active region 40B may include P-type impurities. In one embodiment, the first active region 40A and the second active region 40B may be defined by forming an isolation layer 41 in the substrate 40.

[0093] Subsequently, an insulating layer 42 is formed. The insulating layer 42 may include an oxide, such as silicon oxide. Then, a first conductive layer 43 is formed penetrating the insulating layer 42. The first conductive layer 43 may be connected to a first active region 40A or a second active region 40B. Subsequently, a first capping layer 44 is formed. The first capping layer 44 may include a nitride.

[0094] Reference Figure 7B A first high dielectric constant layer 45 is formed. The first high dielectric constant layer 45 may include a high dielectric constant (high k) material, such as hafnium oxide (HfO). x Subsequently, a second conductive layer 46 is formed that penetrates the first high dielectric constant layer 45 and the first capping layer 44. The second conductive layer 46 can be connected to the first conductive layer 43.

[0095] Subsequently, a second capping layer 47 is formed on the first high-dielectric-constant layer 45 and the second conductive layer 46. The second capping layer 47 may include the same material as the first capping layer 44, or may include a different material than the first capping layer 44. Subsequently, a second high-dielectric-constant layer 48 is formed on the second capping layer 47. The second high-dielectric-constant layer 48 may include the same high-dielectric-constant (high-k) material as the first high-dielectric-constant layer 45, or may include a high-dielectric-constant (high-k) material different from the first high-dielectric-constant layer 45. Subsequently, a third conductive layer 49 is formed penetrating the second high-dielectric-constant layer 48 and the second capping layer 47. The third conductive layer 49 may be connected to the second conductive layer 46.

[0096] According to the manufacturing method described above, a first plug-type conductive layer 43, a second plug-type conductive layer 46, and a third plug-type conductive layer 49, which serve as electrodes for a capacitor, can be formed. The dielectric of the capacitor can be formed using a first high-dielectric-constant layer 45 and a second high-dielectric-constant layer 48. Furthermore, the first conductive layer 43 can be electrically connected to each other using a first active region 40A and a second active region 40B. Therefore, the manufacturing process of the semiconductor device can be improved, and the capacitance of the capacitor can be increased.

[0097] Figure 8A and Figure 8BThis is a view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. In the following description, portions that are repeated above will be omitted.

[0098] Reference Figure 8A An isolation layer 51 and a transistor TR are formed on a substrate 50. The transistor TR may include a gate electrode 53, a gate insulating layer 52, and a junction 54. Subsequently, after forming a first insulating layer 55, a first conductive layer 56 is formed that penetrates the first insulating layer 55. The first conductive layer 56 may be connected to the gate electrode 53 or the junction 54. Subsequently, a first capping layer 57 is formed.

[0099] Reference Figure 8B A second insulating layer 58 is formed on the first cover layer 57. Subsequently, after forming an opening by etching the second insulating layer 58, a first high-dielectric-constant layer 59 is formed in the opening. Then, a second conductive layer 60 is formed. The second conductive layer 60 can penetrate either the second insulating layer 58 or the first high-dielectric-constant layer 59. The second conductive layer 60 can be connected to the first conductive layer 56, respectively.

[0100] Subsequently, a second capping layer 61 is formed on the second insulating layer 58 and the first high-dielectric-constant layer 59. Then, a third insulating layer 62 is formed on the second capping layer 61. Next, after forming an opening by etching the third insulating layer 62, a second high-dielectric-constant layer 63 is formed in the opening. Then, a third conductive layer 64 is formed. The third conductive layer 64 can penetrate either the third insulating layer 62 or the second high-dielectric-constant layer 63. The third conductive layer 64 can be connected to the second conductive layer 60, respectively.

[0101] According to the manufacturing method described above, a first plug-type conductive layer 56, a second plug-type conductive layer 60, and a third plug-type conductive layer 64, which serve as electrodes for a capacitor, can be formed. The dielectric of the capacitor can be formed using a first insulating layer 55, a first high-dielectric-constant layer 59, and a second high-dielectric-constant layer 63. Furthermore, a portion of the first conductive layers 56 can be electrically connected to each other using a gate electrode 53. Therefore, the manufacturing process of the semiconductor device can be improved, and the capacitance of the capacitor can be increased.

[0102] Figures 9A to 9D This is a view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. In the following description, portions that are repeated above will be omitted.

[0103] Reference Figure 9A A first conductive layer 72 is formed in the first insulating layer 71. The first conductive layer 72 may be formed to penetrate the first insulating layer 71 to a certain depth. The first conductive layer 72 may have a linear shape extending in a first direction. Subsequently, a first cover layer 73 is formed on the first insulating layer 71.

[0104] Subsequently, a first high-dielectric-constant layer 74 is formed on the first capping layer 73. Then, a first opening OP1 penetrating the first high-dielectric-constant layer 74 is formed. The first opening OP1 may be arranged along a first direction and a second direction intersecting the first direction. The first opening OP1 may expose the first capping layer 73. Subsequently, sacrificial layers 75 are formed in the first opening OP1. In one embodiment, the sacrificial layer 75 may include spin-coated carbon (SOC).

[0105] Reference Figure 9B A second opening OP2 is formed, penetrating the first high-dielectric-constant layer 74. The second opening OP2 can penetrate the first high-dielectric-constant layer 74 to a certain depth. The second opening OP2 can extend along the first direction. When forming the second opening OP2, the sacrificial layer 75 can be partially etched, thus making the first opening OP1 partially open.

[0106] Reference Figure 9C The sacrificial layer 75 is removed. Then, the first opening OP1 is extended by etching the first capping layer 73 exposed via the first opening OP1. Thus, the first conductive layer 72 can be exposed. Subsequently, a second conductive layer 76A is formed in the first opening OP1, and a second conductive layer 76B is formed in the second opening OP2. Then, a second capping layer 77 is formed on the first high-dielectric-constant layer 74.

[0107] Reference Figure 9D A second high-dielectric-constant layer 78 is formed on the second capping layer 77. Subsequently, a third conductive layer 79A is formed that penetrates the second high-dielectric-constant layer 78 and the second capping layer 77, and a third conductive layer 79B is formed that penetrates the second high-dielectric-constant layer 78 to a certain depth. The third conductive layers 79A and 79B can be formed by a process similar to that used to form the second conductive layers 76A and 76B.

[0108] According to the manufacturing method described above, the first conductive layer 72, the second conductive layers 76A and 76B, and the third conductive layers 79A and 79B, which serve as electrodes for a capacitor, can be formed using a combination of plug-type and wire-type electrodes. The dielectric of the capacitor can be formed using a first insulating layer 71, a first high-dielectric-constant layer 74, and a second high-dielectric-constant layer 78. Therefore, the manufacturing process of semiconductor devices can be improved, and the capacitance of the capacitor can be increased.

[0109] Figure 10 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0110] Reference Figure 10The memory system 1000 may include a memory device 1200 configured to store data and a controller 1100 configured to communicate between the memory device 1200 and the host 2000.

[0111] The host 2000 can be a device or system that stores data in or retrieves data from the memory system 1000. The host 2000 can generate requests for various operations and output these requests to the memory system 1000. These requests may include programming requests for programming operations, read requests for read operations, and erase requests for erase operations. The host 2000 can communicate with the memory system 1000 through various interfaces, such as: Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS) or Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Digital Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0112] The host 2000 may include at least one of a computer, portable digital device, tablet computer, digital camera, digital audio player, television, wireless communication device and cellular phone, but the embodiments disclosed herein are not limited thereto.

[0113] The controller 1100 can control the overall operation of the memory system 1000. The controller 1100 can control the memory device 1200 according to requests from the host 2000. The controller 1100 can control the memory device 1200 to perform programming operations, read operations, and erase operations, etc., according to requests from the host 2000. Alternatively, the controller 1100 can perform background operations, etc., without any requests from the host 2000, to improve the performance of the memory system 1000.

[0114] The controller 1100 can send control signals and data signals to the memory device 1200 to control the operation of the memory device 1200. The control signals and data signals can be sent to the memory device 1200 through different input / output lines. Data signals may include commands, addresses, or data. Control signals can be used to distinguish the time periods of input data signals.

[0115] The memory device 1200 can perform programming operations, reading operations, and erasing operations under the control of the controller 1100. The memory device 1200 can be implemented as a volatile memory device whose stored data is lost when power is interrupted, or a non-volatile memory device that retains stored data even when power is interrupted. The memory device 1200 can be [referenced above]. Figures 1A to 5B The semiconductor device described herein. The memory device 1200 may be as described above. Figures 6A to 9D A semiconductor device manufactured by the described manufacturing method. In one embodiment, the semiconductor device may include: a first insulating layer; a first electrode penetrating the first insulating layer; a second electrode penetrating the first insulating layer and located between the first electrodes; a first high dielectric constant layer comprising a material with a dielectric constant higher than that of the first insulating layer; a third electrode penetrating the first high dielectric constant layer and respectively connected to the first electrodes; and a fourth electrode penetrating the first high dielectric constant layer and located between the third electrodes.

[0116] Figure 11 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0117] Reference Figure 11 The memory system 30000 can be implemented as a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 capable of controlling the operation of the memory device 2200.

[0118] The controller 2100 can control the data access operations of the memory device 2200, such as programming operations, erasing operations, or reading operations, under the control of the processor 3100.

[0119] Data programmed in memory device 2200 can be output via display 3200 under the control of controller 2100.

[0120] The radio transceiver 3300 can transmit / receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the controller 2100 or the display 3200. The controller 2100 can send the signals processed by the processor 3100 to the memory device 2200. Furthermore, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 is a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and can be implemented as, for example, a touchpad or computer mouse pointing device, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200, so that data output from the controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

[0121] In some implementations, the controller 2100, which controls the operation of the memory device 2200, may be implemented as part of the processor 3100 or as a separate chip from the processor 3100.

[0122] Figure 12 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0123] Reference Figure 12 The memory system 40000 can be implemented as a personal computer (PC), tablet PC, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

[0124] The memory system 40000 may include a memory device 2200 and a controller 2100 capable of controlling the data processing operations of the memory device 2200.

[0125] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on data input through the input device 4200. For example, the input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0126] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the controller 2100. In some embodiments, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a separate chip from the processor 4100.

[0127] Figure 13 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0128] Reference Figure 13 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile terminal with a digital camera attached, a smartphone with a digital camera attached, or a tablet PC with a digital camera attached.

[0129] The memory system 50000 may include a memory device 2200 and a controller 2100, the controller 2100 being able to control data processing operations of the memory device 2200, such as programming operations, erasing operations, or reading operations.

[0130] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals, and the converted digital signals can be sent to the processor 5100 or the controller 2100. Under the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 2200 through the controller 2100. Furthermore, under the control of the processor 5100 or the controller 2100, data stored in the memory device 2200 can be output through the display 5300.

[0131] In some implementations, the controller 2100, which controls the operation of the memory device 2200, may be implemented as part of the processor 5100 or as a separate chip from the processor 5100.

[0132] Figure 14 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0133] Reference Figure 14 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100.

[0134] The controller 2100 can control the data exchange between the memory device 2200 and the card interface 7100. In some embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but this disclosure is not limited thereto.

[0135] Card interface 7100 can interface for data exchange between host 60000 and controller 2100 according to the protocol of host 60000. In some embodiments, card interface 7100 can support Universal Serial Bus (USB) protocol and chip-to-chip (IC) USB protocol. Card interface 7100 can represent hardware, software embedded in hardware, or signal transmission scheme capable of supporting the protocol used by host 60000.

[0136] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (e.g., PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box), the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 under the control of the microprocessor 6100.

[0137] According to this disclosure, memory cells are stacked in three dimensions, thereby improving the integration density of the semiconductor device. Furthermore, the semiconductor device can have a stable structure and improved reliability.

[0138] Examples of embodiments of the present disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is for the purpose of explaining embodiments of the present disclosure only. Therefore, the present disclosure is not limited to the embodiments described above, and many variations can be made within the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that various variations can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

[0139] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the meaning commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms with dictionary definitions shall be understood to have a meaning consistent with the context of the relevant art. Unless clearly defined in this application, terms shall not be interpreted in an ideal or overly formal manner.

[0140] Cross-reference to related applications

[0141] This application claims priority to Korean Patent Application No. 10-2021-0035531, filed on March 18, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: First insulating layer; A plurality of first electrodes, wherein the plurality of first electrodes penetrate the first insulating layer; A plurality of second electrodes, the plurality of second electrodes penetrating the first insulating layer, each of the plurality of second electrodes being located between the plurality of first electrodes; A first high dielectric constant layer, wherein the dielectric constant of the first high dielectric constant layer is higher than the dielectric constant of the first insulating layer; A plurality of third electrodes, the plurality of third electrodes penetrating the first high dielectric constant layer, and the plurality of third electrodes being respectively connected to the plurality of first electrodes; as well as A plurality of fourth electrodes, each of which penetrates the first high dielectric constant layer, and each of the plurality of fourth electrodes is located between the plurality of third electrodes; as well as A cover layer is inserted between the first insulating layer and the first high dielectric constant layer.

2. The semiconductor device according to claim 1, wherein, The plurality of third electrodes and the plurality of fourth electrodes are arranged alternately along a first direction and a second direction intersecting the first direction.

3. The semiconductor device according to claim 2, further comprising: A first line extends along a third direction that intersects the first direction and the second direction, and each of the first lines is electrically connected to a third electrode arranged along the third direction among the plurality of third electrodes. as well as The second line extends along the third direction and is electrically connected to the fourth electrode arranged along the third direction among the plurality of fourth electrodes.

4. The semiconductor device of claim 1, further comprising a capacitor configured with a first capacitor electrode and a second capacitor electrode, the first capacitor electrode comprising a first electrode of a plurality of first electrodes and a third electrode of a plurality of third electrodes electrically connected to each other, and the second capacitor electrode comprising a second electrode of a plurality of second electrodes and a fourth electrode of a plurality of fourth electrodes electrically connected to each other.

5. The semiconductor device according to claim 1, further comprising: A second high dielectric constant layer is located on top of the first high dielectric constant layer, and the dielectric constant of the second high dielectric constant layer is higher than that of the first insulating layer. A plurality of fifth electrodes, the plurality of fifth electrodes penetrating the second high dielectric constant layer, and the plurality of fifth electrodes being respectively connected to the plurality of third electrodes; as well as A plurality of sixth electrodes, the plurality of sixth electrodes penetrating the second high dielectric constant layer, and the plurality of sixth electrodes being respectively connected to the plurality of fourth electrodes.

6. The semiconductor device of claim 1, further comprising a substrate, the substrate including a plurality of first active regions respectively connected to the plurality of first electrodes and including a first type of impurity, and a plurality of second active regions respectively connected to the plurality of second electrodes and including a second type of impurity.

7. The semiconductor device according to claim 6, wherein, The plurality of first active regions include N-type impurities, and the plurality of second active regions include P-type impurities.

8. The semiconductor device according to claim 6, wherein, The plurality of first electrodes and the plurality of second electrodes are arranged alternately along a first direction and a second direction intersecting the first direction, and Each of the plurality of first active regions and each of the plurality of second active regions extends along a third direction intersecting the first direction and the second direction.

9. The semiconductor device according to claim 1, further comprising: A substrate, wherein the substrate is located at the bottom of the first insulating layer; A gate electrode is located between the substrate and the plurality of first electrodes, and the gate electrode is electrically connected to the plurality of first electrodes; as well as A junction is formed in the substrate and is electrically connected to the plurality of second electrodes.

10. The semiconductor device of claim 9, further comprising a capacitor configured with a first capacitor electrode and a second capacitor electrode, the first capacitor electrode comprising the gate electrode, the plurality of first electrodes and the plurality of third electrodes electrically connected to each other, and the second capacitor electrode comprising the junction, the plurality of second electrodes and the plurality of fourth electrodes electrically connected to each other.

11. The semiconductor device of claim 9, further comprising: A second high dielectric constant layer is located on top of the first high dielectric constant layer, and the dielectric constant of the second high dielectric constant layer is higher than that of the first insulating layer. A plurality of fifth electrodes, the plurality of fifth electrodes penetrating the second high dielectric constant layer, and the plurality of fifth electrodes being respectively connected to the plurality of third electrodes; as well as A plurality of sixth electrodes, the plurality of sixth electrodes penetrating the second high dielectric constant layer, and the plurality of sixth electrodes being respectively connected to the plurality of fourth electrodes.

12. The semiconductor device of claim 11, further comprising: A second insulating layer is located on the first insulating layer and surrounds the sidewall of the first high dielectric constant layer. A third insulating layer is located on the second insulating layer and surrounds the sidewall of the second high dielectric constant layer; A plurality of seventh electrodes, the plurality of seventh electrodes penetrating the second insulating layer, and the plurality of seventh electrodes being respectively connected to the plurality of second electrodes; as well as A plurality of eighth electrodes, the plurality of eighth electrodes penetrating the third insulating layer, and the plurality of eighth electrodes being respectively connected to the plurality of seventh electrodes.

13. The semiconductor device of claim 12, further comprising a capacitor configured with first capacitor electrodes and second capacitor electrodes, the first capacitor electrodes comprising the plurality of first electrodes, the plurality of third electrodes and the plurality of fifth electrodes electrically connected to each other, and the second capacitor electrodes comprising the plurality of second electrodes, the plurality of seventh electrodes, the plurality of eighth electrodes, the plurality of fourth electrodes and the plurality of sixth electrodes electrically connected to each other.

14. A semiconductor device, the semiconductor device comprising: First high dielectric constant layer; A plurality of first electrodes, the plurality of first electrodes penetrating the first high dielectric constant layer; A plurality of second electrodes, the plurality of second electrodes extending into the first high dielectric constant layer to a depth different from the depth of the plurality of first electrodes; A second high dielectric constant layer is located on top of the first high dielectric constant layer; A plurality of third electrodes, the plurality of third electrodes penetrating the second high dielectric constant layer, and the plurality of third electrodes being electrically connected to the plurality of second electrodes; as well as A plurality of fourth electrodes extending into the second high dielectric constant layer to a depth different from that of the plurality of third electrodes, the plurality of fourth electrodes being spaced apart from the plurality of first electrodes.

15. The semiconductor device according to claim 14, wherein, The plurality of first electrodes are arranged along a first direction and a second direction intersecting the first direction, and The plurality of second electrodes extend along the first direction.

16. The semiconductor device according to claim 15, wherein, The plurality of third electrodes are arranged along the first direction and the second direction, and each of the plurality of second electrodes is connected to the third electrode arranged along the first direction.

17. The semiconductor device of claim 14, further comprising: An insulating layer, the insulating layer being located at the bottom of the first high dielectric constant layer; as well as A plurality of fifth electrodes, wherein the plurality of fifth electrodes partially penetrate the insulating layer, and the plurality of fifth electrodes are connected to the plurality of first electrodes.

18. The semiconductor device according to claim 17, wherein, Each of the plurality of fifth electrodes extends along a first direction and connects to a first electrode arranged along the first direction among the plurality of first electrodes.

19. A semiconductor device, the semiconductor device comprising: First insulating layer; The first electrode penetrates the first insulating layer; The second electrode penetrates the first insulating layer and is adjacent to the first electrode. A first high dielectric constant layer, wherein the dielectric constant of the first high dielectric constant layer is higher than the dielectric constant of the first insulating layer; A third electrode, which penetrates the first high dielectric constant layer, is connected to the first electrode; A fourth electrode, which penetrates the first high dielectric constant layer, is adjacent to the third electrode; as well as A cover layer is inserted between the first insulating layer and the first high dielectric constant layer.

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