Terahertz frequency doubler chip, manufacturing method and communication device

Abstract

The application provides a terahertz frequency multiplier chip, a preparation method and a communication device. The terahertz frequency multiplier chip comprises a first wafer chip and a second wafer chip; a first integrated circuit is arranged on the front surface of the first wafer chip, and a second integrated circuit is arranged on the front surface of the second wafer chip; the first integrated circuit and the second integrated circuit are electrically connected and used for frequency multiplication; and the back surface of the first wafer chip and the back surface of the second wafer chip are arranged back to back. The terahertz frequency multiplier circuit is prepared on the two wafer chips arranged back to back, so that the volume of the terahertz frequency multiplier chip is effectively reduced, the synthesis efficiency is high, and the tolerance power and the output power of the chip are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a terahertz frequency multiplier chip, a preparation method and a communication device. BACKGROUND

[0002] Terahertz refers to electromagnetic waves with a frequency of 0.1-10 THz, which has wide application prospects in the fields of mobile communication, imaging and detection. The frequency multiplier is a core component for realizing a terahertz frequency band power source. The design of a terahertz frequency band high-power frequency multiplier currently faces many bottlenecks in terms of heat and electricity, and power synthesis technology is one of the key technologies for breaking through these bottlenecks.

[0003] In the prior art, a waveguide is usually used for power synthesis, but the waveguide power synthesis has the problems of large volume, large phase error and low efficiency, and cannot meet the actual application requirements. SUMMARY

[0004] Embodiments of the present application provide a terahertz frequency multiplier chip, a preparation method and a communication device to solve the problems of large volume and low efficiency of waveguide power synthesis in the prior art.

[0005] In a first aspect, embodiments of the present application provide a terahertz frequency multiplier chip, comprising: a first wafer chip and a second wafer chip.

[0006] The front surface of the first wafer chip is provided with a first integrated circuit, and the front surface of the second wafer chip is provided with a second integrated circuit. The first integrated circuit and the second integrated circuit are electrically connected and used for frequency multiplication.

[0007] The back surface of the first wafer chip and the back surface of the second wafer chip are arranged back to back.

[0008] In a possible implementation, the back surface of the first wafer chip and the back surface of the second wafer chip are connected by bonding to realize the connection of the first integrated circuit and the second integrated circuit.

[0009] In a possible implementation, the bonding material is organic glue, Si, SiO2 or SiN.

[0010] In a possible implementation, the bonding method is heating or pressurization.

[0011] In a possible implementation, the material of the epitaxial layer of the first wafer chip and the second wafer chip is Si, Ge, GeSi, GaAs, InP, GaN, AlN, InN, SiC, ZnO, Ga2O3, graphene or diamond.

[0012] In a second aspect, embodiments of the present application provide a preparation method of a terahertz frequency multiplier chip, comprising:

[0013] A first integrated circuit is fabricated on the front side of a first epitaxial wafer to form a first initial chip;

[0014] A second integrated circuit is fabricated on the front side of the second epitaxial wafer to form a second initial chip;

[0015] The first initial chip and the second initial chip are thinned to form a first wafer chip and a second wafer chip;

[0016] The first wafer chip and the second wafer chip are bonded back to back to achieve the connection between the first integrated circuit and the second integrated circuit.

[0017] In one possible implementation, the thickness of the first and second wafer chips after thinning ranges from 5 μm to 100 μm.

[0018] Thirdly, embodiments of the present invention provide a communication device, including the terahertz frequency multiplier chip provided in the first aspect of the present invention.

[0019] This invention provides a terahertz frequency multiplier chip, its fabrication method, and a communication device. The terahertz frequency multiplier chip includes a first wafer chip and a second wafer chip. A first integrated circuit is disposed on the front side of the first wafer chip, and a second integrated circuit is disposed on the front side of the second wafer chip. The first and second integrated circuits are electrically connected for frequency multiplication. The back sides of the first and second wafer chips are arranged back-to-back. This invention fabricates the terahertz frequency multiplier circuit on two back-to-back wafer chips, effectively reducing the size of the terahertz frequency multiplier chip, achieving high synthesis efficiency, and improving the chip's power tolerance and output power. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a front view of a terahertz frequency multiplier chip provided in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram illustrating the implementation process of a terahertz frequency multiplier chip fabrication method provided in an embodiment of the present invention;

[0023] Figure 3 This is a top view of the first epitaxial wafer provided in an embodiment of the present invention;

[0024] Figure 4This is a top view of the first initial chip provided in an embodiment of the present invention;

[0025] Figure 5 This is a front view of the first wafer chip provided in an embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0027] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0028] The implementation of the present invention will be described in detail below with reference to the accompanying drawings:

[0029] Figure 1 This is a schematic diagram of a terahertz frequency multiplier chip provided in an embodiment of the present invention. (Refer to...) Figure 1 The terahertz frequency multiplier chip includes: a first wafer chip 12 and a second wafer chip 22;

[0030] A first integrated circuit is disposed on the front side of the first wafer chip 12, and a second integrated circuit is disposed on the front side of the second wafer chip 22. The first integrated circuit and the second integrated circuit are electrically connected for frequency multiplication.

[0031] The back side of the first wafer chip 12 and the back side of the second wafer chip 22 are arranged back to back.

[0032] In China's terahertz band communication or radar circuits, a stable terahertz source is both the challenge and the ultimate goal of circuit design. As the frequency increases, the performance of the devices deteriorates dramatically. Therefore, frequency multiplication and power combining techniques are typically used to multiply the fundamental frequency signal to achieve a stable local oscillator output.

[0033] In this embodiment of the invention, two wafer chips (first wafer chip 12 and second wafer chip 22) are arranged back-to-back, and a terahertz frequency multiplier circuit is fabricated on the two wafer chips (for example, the first integrated circuit and the second integrated circuit form a complete frequency doubler circuit), thus reducing the size of the terahertz frequency multiplier chip. Simultaneously, the terahertz frequency multiplier circuit is directly fabricated on the two wafer chips, requiring no subsequent equipment, resulting in small errors and high synthesis efficiency.

[0034] Furthermore, due to the back-to-back configuration, higher power output can be achieved within the same volume, effectively improving the power tolerance and output power of the terahertz frequency multiplier chip.

[0035] In one possible implementation, the back side of the first wafer chip 12 and the back side of the second wafer chip 22 can be bonded together to connect the first integrated circuit and the second integrated circuit.

[0036] The first wafer chip 12 and the second wafer chip 22 are arranged back to back. In this embodiment of the invention, a bonding process can be used to directly fix the first wafer chip 12 and the second wafer chip together, thereby realizing the electrical connection between the first integrated circuit and the second integrated circuit, so that the first integrated circuit and the second integrated circuit form a complete terahertz frequency multiplier circuit.

[0037] In one possible implementation, the bonding materials can be organic adhesives, Si, SiO2, or SiN.

[0038] In one possible implementation, the bonding method can be heating or pressurizing.

[0039] In one possible implementation, the epitaxial layer of the first wafer chip 12 and the second wafer chip 22 can be made of Si, Ge, GeSi, GaAs, InP, GaN, AlN, InN, SiC, ZnO, Ga2O3, graphene, or diamond.

[0040] In this embodiment of the invention, the first wafer chip 12 and the second wafer chip 22 can be directly mounted back-to-back in the cavity, which is simple to assemble and has small assembly errors.

[0041] Corresponding to the aforementioned terahertz frequency multiplier chip, Figure 2 A method for fabricating a terahertz frequency multiplier chip is shown. The fabrication method includes:

[0042] S101: Fabricate a first integrated circuit on the front side of the first epitaxial wafer to form a first initial chip;

[0043] S102: Fabricate a second integrated circuit on the front side of the second epitaxial wafer to form a second initial chip;

[0044] S103: Thinning the first initial chip and the second initial chip to form the first wafer chip 12 and the second wafer chip 22;

[0045] S104: Bond the first wafer chip 12 and the second wafer chip 22 back to back to realize the connection between the first integrated circuit and the second integrated circuit.

[0046] Because of the mismatch in atomic spacing in the crystal structure of a wafer, defects such as voids and protrusions can occur, leading to quality problems. Therefore, in this embodiment of the invention, an epitaxial wafer with an epitaxial layer is used to fabricate a first integrated circuit and a second integrated circuit on the epitaxial wafer, forming a first initial chip and a second initial chip. To improve electrical performance, heat dissipation efficiency, and reduce chip size, the back sides of the fabricated first and second initial chips are ground and thinned, and then bonded back-to-back to electrically connect the first and second integrated circuits, forming a complete frequency multiplier circuit.

[0047] In this embodiment of the invention, each component of a complete frequency multiplier circuit is fabricated on two separate wafer chips, forming a back-to-back structure. This increases device density, reduces the size of the frequency multiplier, and simultaneously improves frequency multiplication efficiency. It also effectively improves the power tolerance and output power of the terahertz frequency multiplier chip within the same volume.

[0048] In one possible implementation, the thickness of the first wafer chip 12 and the second wafer chip 22 after thinning can range from 5 μm to 100 μm.

[0049] In one possible implementation, the aforementioned terahertz frequency multiplier chip is electrically connected to external devices via Liang's leads.

[0050] The fabrication method of the above-mentioned terahertz frequency multiplier chip is described in detail below with reference to specific embodiments.

[0051] 1. Reference Figure 3 Provide the first epitaxial wafer 10;

[0052] 2. Reference Figure 4 and Figure 5 A first initial chip 11 is fabricated on the first epitaxial wafer 10, and then thinned to obtain a first wafer chip 12.

[0053] 3. The second initial chip was prepared using the same method, and then thinned to obtain the second wafer chip 22.

[0054] 4. Reference Figure 1 The first wafer chip 12 and the second wafer chip 22 are bonded back to back to form a complete terahertz frequency multiplier chip.

[0055] Corresponding to the above embodiments, this embodiment of the invention also provides a communication device, including the terahertz frequency multiplier chip provided in the above embodiments of the invention, and having the advantages of the above terahertz frequency multiplier chip, which will not be repeated here.

[0056] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A terahertz frequency multiplier chip, characterized in that, include: First wafer chip and second wafer chip; The first wafer chip has a first integrated circuit disposed on its front side, and the second wafer chip has a second integrated circuit disposed on its front side. The first integrated circuit and the second integrated circuit are electrically connected for frequency multiplication. The back sides of the first wafer chip and the back sides of the second wafer chip are arranged back to back, so that the first integrated circuit and the second integrated circuit form a complete terahertz frequency multiplier circuit.

2. The terahertz frequency multiplier chip as described in claim 1, characterized in that, The back sides of the first wafer chip and the back sides of the second wafer chip are bonded together to connect the first integrated circuit and the second integrated circuit.

3. The terahertz frequency multiplier chip as described in claim 2, characterized in that, The bonding material is an organic adhesive, Si, SiO2, or SiN.

4. The terahertz frequency multiplier chip as described in claim 2, characterized in that, The bonding method is heating or pressurizing.

5. The terahertz frequency multiplier chip according to any one of claims 1 to 4, characterized in that, The epitaxial layer of the first wafer chip and the second wafer chip is made of Si, Ge, GeSi, GaAs, InP, GaN, AlN, InN, SiC, ZnO, Ga2O3, graphene, or diamond.

6. A method for fabricating a terahertz frequency multiplier chip, characterized in that, include: A first integrated circuit is fabricated on the front side of a first epitaxial wafer to form a first initial chip; A second integrated circuit is fabricated on the front side of the second epitaxial wafer to form a second initial chip; The first initial chip and the second initial chip are thinned to form a first wafer chip and a second wafer chip; The first wafer chip and the second wafer chip are bonded back to back to connect the first integrated circuit and the second integrated circuit, so that the first integrated circuit and the second integrated circuit form a complete terahertz frequency multiplier circuit.

7. The method for fabricating a terahertz frequency multiplier chip as described in claim 6, characterized in that, After thinning, the thickness of the first wafer chip and the second wafer chip ranges from 5μm to 100μm.

8. A communication device, characterized in that, Including the terahertz frequency multiplier chip as described in any one of claims 1 to 5.

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