A vertical Hall device array and a preparation method thereof
By introducing an N-type well and buried layer structure into the vertical Hall device, combining the slot isolation and alternating interconnection method to optimize the current path, the magnetic induction accuracy and integration problems of the vertical Hall device are solved, achieving higher measurement accuracy and lower area occupation.
Patent Information
- Application Number
- CN202210966491.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-12
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2042-08-12
AI Technical Summary
The mismatch voltage of traditional vertical Hall devices affects magnetic induction accuracy and occupies a large chip area, making it difficult to achieve high integration.
The N-type well and N-type buried layer structure are adopted, combined with the groove isolation structure and the alternating interconnection method, and the current paths of multiple vertical Hall devices are formed to optimize the current distribution to improve magnetic induction accuracy and reduce area.
Improves magnetic induction accuracy, reduces the area of vertical Hall devices, and enhances device stability and integration.
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Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit design, and particularly to a vertical Hall device array and a preparation method thereof. Background Art
[0002] With the development of science and technology, Hall sensors based on CMOS technology have received increasing attention because they are easy to integrate with CMOS circuits and can achieve low cost and high integration. Integrated Hall chips are also increasingly applied in fields such as automotive manufacturing, medical electronics, and mobile communication. Hall sensors are mainly divided into horizontal Hall devices and vertical Hall devices. Horizontal Hall sensors are mainly used to detect the magnetic field component perpendicular to the chip surface direction, and their preparation process is relatively simple and has excellent performance; vertical Hall sensors are mainly used to detect the magnetic field component parallel to the chip surface direction. When the vertical Hall device works, the bias current needs to first flow into the device from the surface input electrode, and then flow out from the surface output electrode after passing through a "U" - shaped path inside the device. Such a complex path will affect the Hall induction accuracy of the vertical Hall device, and there will be a mismatch voltage, that is, even in the case of zero magnetic field, there is also a potential difference between the two Hall electrode ports.
[0003] In order to reduce the mismatch voltage of vertical Hall devices, an alternating interconnection method is usually adopted. By alternately connecting the different electrodes of multiple vertical Hall devices, each signal path flows through the same area of the Hall device, thereby effectively reducing the initial offset disturbance of the device. The traditional alternating interconnection method is realized by interconnecting multiple separate vertical Hall devices, but this will occupy a large chip area and pose a challenge to the high integration of the chip. Summary of the Invention
[0004] In order to solve the deficiencies of the existing technology, the purpose of the present application is to provide a vertical Hall device array and a preparation method thereof, which utilize an N - type well and multiple N - type buried layer structures located in the N - type well to improve the magnetic induction accuracy of the vertical Hall device, make the device have lower mismatch disturbance under low - magnetic - field conditions, and reduce the area of the device.
[0005] To achieve the above purpose, the vertical Hall device array provided by the present application includes:
[0006] A P - type substrate;
[0007] An N - type well disposed on the P - type substrate;
[0008] A trench isolation structure disposed on the surface of the N - type well;
[0009] Multiple vertical Hall devices evenly distributed on the N - type well;
[0010] The multiple vertical Hall devices are connected by an alternating interconnection method.
[0011] Further, the number of the vertical Hall devices is 4N, where N is a positive integer greater than or equal to 1.
[0012] Further, the depth of the trench isolation structure is greater than 0.5 μm.
[0013] Further, the vertical Hall device further includes an N-type buried layer disposed at the bottom of the N-type well and a port structure located above the N-type buried layer.
[0014] Further, the relationship between the distance between the vertical Hall devices and the width of the N-type buried layer is:
[0015] where L1 is the distance between the vertical Hall devices and L2 is the width of the N-type buried layer.
[0016] Further, the port structure includes a first ohmic electrode, a second ohmic electrode, a first Hall electrode, and a second Hall electrode, where
[0017] the second Hall electrode is located at both ends of the port structure and is short-circuited by a metal wire;
[0018] An N+ region is disposed below the first ohmic electrode, the second ohmic electrode, the first Hall electrode, and the second Hall electrode, so that the first ohmic electrode, the second ohmic electrode, the first Hall electrode, and the second Hall electrode respectively form ohmic contacts with the N-type well.
[0019] Further, the trench isolation structure is respectively located between the first ohmic electrode, the second ohmic electrode, the first Hall electrode, and the second Hall electrode, and between the vertical Hall devices.
[0020] Further, the relationship between the distance between the first Hall electrode and the first ohmic electrode and the distance between the second ohmic electrode and the first Hall electrode is:
[0021] where L3 is the distance between the first Hall electrode and the first ohmic electrode and L4 is the distance between the second ohmic electrode and the first Hall electrode.
[0022] Still further, the multiple vertical Hall devices are connected by an alternating interconnection method, including:
[0023] The first ohmic electrode of the (1 + m)-th Hall device, the first Hall electrode of the (2 + m)-th Hall device, the second ohmic electrode of the (3 + m)-th Hall device, and the second Hall electrode of the (4 + m)-th Hall device are interconnected to form a current excitation signal input port;
[0024] The second ohmic electrode of the (1 + m)-th Hall device, the second Hall electrode of the (2 + m)-th Hall device, the first ohmic electrode of the (3 + m)-th Hall device, and the first Hall electrode of the (4 + m)-th Hall device are interconnected to form a current excitation signal output port;
[0025] The first Hall electrode of the (1 + m)-th Hall device, the second ohmic electrode of the (2 + m)-th Hall device, the second Hall electrode of the (3 + m)-th Hall device, and the first ohmic electrode of the (4 + m)-th Hall device are interconnected to form a first Hall potential detection port;
[0026] The second Hall electrode of the (1 + m)-th Hall device, the first ohmic electrode of the (2 + m)-th Hall device, the first Hall electrode of the (3 + m)-th Hall device, and the second ohmic electrode of the (4 + m)-th Hall device are interconnected to form a second Hall potential detection port;
[0027] where m = 4(M - 1) and M is an integer greater than or equal to 1.
[0028] To achieve the above object, the present application also provides a method for manufacturing a vertical Hall device array, including the following steps:
[0029] Form an N-type well on a P-type substrate;
[0030] Inject high-energy N-type ions into the N-type well to form an N-type buried layer;
[0031] Use a dry etching method to etch a trench structure on the surface of the N-type well;
[0032] Form an N+ region on the surface of the N-type well by high-energy phosphorus ion implantation;
[0033] Lithographically define metal electrode lead holes on the surface of the N+ region and deposit a metal layer to form metal contacts.
[0034] Furthermore, the step of using a dry etching method to etch a trench structure on the surface of the N-type well further includes: filling the trench region with silicon dioxide using chemical vapor deposition.
[0035] Compared with the prior art, the present application has the following advantages:
[0036] (1) Adopting an N-type buried layer structure can introduce a low-resistance region at the bottom of the N-type well. After the current flows into the device from the input electrode, due to the attraction of the low-resistance buried layer region, the current will preferentially flow downward, form a "U"-shaped path inside the device, and then flow out from the surface output electrode. As Figure 4 shown, after the current flows into the vertical Hall device from the first ohmic electrode, it will preferentially move downward to the low-resistance region with a buried layer. Subsequently, the current will move along the buried layer region and finally flow out from the second ohmic electrode of the vertical Hall device. Thus, overall, the current path is "U"-shaped. The "U"-shaped current path can increase the longitudinal current component in the vertical Hall device. According to the left-hand rule, the higher the proportion of the longitudinal current, the more moving electrons will be deflected in the direction of motion by the Lorentz force, thereby generating a larger Hall potential difference at the Hall electrode and improving the measurement accuracy of the magnetic field.
[0037] (2) Multiple N-type buried layer structures with a certain spacing restrict the current flow region in the vertical Hall device array by taking advantage of the characteristic that the current tends to flow through the low-resistance region, making the current flow paths in each vertical Hall device concentrate within the corresponding N-type buried layer region (as Figure 5 ). By introducing multiple N-type buried layers, it is ensured that each vertical Hall device can have independent current flow under the condition of sharing an N-type well, guaranteeing the stable working state of each vertical Hall device.
[0038] (3) The trench isolation structure located between the device electrodes increases the surface equivalent resistance by extending the current path between the electrodes. This can not only achieve isolation between devices and block the surface current flow, avoiding the short-circuit effect caused by the current flowing along the surface between the electrodes. The increase in surface resistance can further increase the longitudinal current component and improve the measurement accuracy of the magnetic induction of the device.
[0039] (4) The trench isolation structure on the surface of the vertical Hall device array and the multiple spaced N-type buried layer structures inside realize the integration of multiple vertical Hall devices in an N-type well while the working states of each vertical Hall device do not affect each other, effectively reducing the area of the vertical Hall array, reducing the area of the magnetic induction region, and improving the integration degree of the Hall chip. Brief Description of the Drawings
[0040] The drawings are used to provide a further understanding of the present application and, together with the embodiments of the present application, are used to explain the present application, but do not constitute a limitation to the present application:
[0041] Figure 1 is a top view of the vertical Hall device array of the present application;
[0042] Figure 2 isFigure 1 Cross-sectional view of the vertical Hall device array of the present application along the A-A' section;
[0043] Figure 3 is Figure 1 Cross-sectional view of the vertical Hall device array of the present application along the B-B' section;
[0044] Figure 4 is Figure 1 Schematic diagram of the current distribution of the vertical Hall device array of the present application along the A-A' section;
[0045] Figure 5 is Figure 1 Schematic diagram of the current distribution of the vertical Hall device array of the present application along the B-B' section;
[0046] Figure 6 Schematic diagram of the alternate connection method adopted by the vertical Hall device array of the present application.
[0047] Figure 7 Flowchart of the preparation method of the vertical Hall device array of the present application.
[0048] In the figure, there are P-type substrate 1, N-type well 2, N-type buried layer 3, trench isolation structure 4, device port 5, N+ region 6, first ohmic electrode 51, second ohmic electrode 52, first Hall electrode 53 and second Hall electrode 54. Detailed implementation manners
[0049] Hereinafter, embodiments of the present application will be described in more detail with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not used to limit the protection scope of the present application.
[0050] It should be understood that the various steps described in the method embodiments of the present application can be executed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present application is not limited in this regard.
[0051] The term "including" and its variants used herein are open-ended, that is, "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.
[0052] It should be noted that the modifications of "one" and "multiple" mentioned in this application are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly specified in the context, it should be understood as "one or more". "Multiple" should be understood as two or more.
[0053] Next, embodiments of the present application will be described in detail with reference to the accompanying drawings.
[0054] Embodiment 1
[0055] In the embodiment of the present application, the vertical Hall device array uses a P-type material as the substrate, has an N-type well in the P-type substrate, and an N+ region is provided on the surface of the N-type well for ohmic contact with the metal electrode; the metal electrodes of the vertical Hall device array are arranged in a certain lateral pitch and longitudinal pitch to form a metal electrode array; the trench isolation structure located between the metal electrodes isolates the metal electrode array to form the electrodes of each vertical Hall device. A plurality of independent N-type buried layers are provided at the bottom of the N-type well, and the N-type buried layers are located directly below each vertical Hall device to form a vertical Hall device with a buried layer structure, and each vertical device constitutes a vertical Hall device array with a segmented buried layer structure.
[0056] Figure 1 is a top view of the vertical Hall device array of the present application, Figure 2 is Figure 1 a cross-sectional view of the vertical Hall device array of the present application taken along A-A', Figure 3 is Figure 1 a cross-sectional view of the vertical Hall device array of the present application taken along B-B', as Figures 1 - 3 shown, the vertical Hall device array of the present application includes a P-type substrate 1, an N-type well 2, a plurality of N-type buried layers 3, a plurality of vertical Hall devices, and a trench isolation structure 4, wherein,
[0057] The N-type well 2 is located in the P-type substrate 1;
[0058] A plurality of N-type buried layers 3 are provided at the bottom of the N-type well 2.
[0059] A plurality of vertical Hall devices are equally spaced in the N-type well 2 to form a vertical Hall device array.
[0060] The trench isolation structure 4 is a multi-trench structure and is located on the surface of the N-type well 2 (the surface of the vertical Hall device array), and silicon dioxide is filled in each trench.
[0061] Each vertical Hall device includes an N-type buried layer 3, a trench isolation structure 4, a device port 5, and an N+ region 6.
[0062] A plurality of N+ regions for ohmic contact with the metal are provided on the top of the N-type well 2;
[0063] Metal electrode lead holes are formed in the upper part of each N+ region, and a metal layer forms a metal contact as device port 5.
[0064] In the embodiment of the present application, the number of vertical Hall devices in the N-type well 2 is 4*N, where N is a positive integer greater than or equal to 1.
[0065] In the embodiment of the present application, the number of N-type buried layers 3 is 4*N, where N is a positive integer greater than or equal to 1, and is consistent with the number of vertical Hall devices.
[0066] In the embodiment of the present application, each vertical Hall device has a five-port structure and is respectively located directly above the N-type buried layer 3. Among them, the two outer ports are short-circuited by metal wires, so that the five ports form four signal electrodes, namely the first ohmic electrode 51, the second ohmic electrode 52, the first Hall electrode 53, and the second Hall electrode 54.
[0067] Below the first ohmic electrode 51, the second ohmic electrode 52, the first Hall electrode 53, and the second Hall electrode 54, N+ regions 6 formed by high-concentration N-type doping are respectively arranged, so that the metal electrode forms an ohmic contact with the N-type well 2.
[0068] In the embodiment of the present application, the relationship between the distance L1 between vertical Hall devices and the width L2 of the N-type buried layer 3 is: The relationship between the spacing L3 between the first Hall electrode 53 and the first ohmic electrode 51 and the spacing L4 between the second ohmic electrode 52 and the first Hall electrode 53 is:
[0069] In the embodiment of the present application, the trench depth (H) of the trench isolation structure 4 is greater than 0.5 μm.
[0070] Figure 4 For Figure 1 The schematic diagram of the current distribution of the cross-section A-A' of the vertical Hall device array of the present application is shown in Figure 4. After the current flows into the vertical Hall device from the first ohmic electrode, it will preferentially move downward to the low-resistance region with the buried layer. Subsequently, the current will move along the buried layer region and finally flow out of the vertical Hall device from the second ohmic electrode. Therefore, overall, the current path is in a "U" shape. The "U"-shaped current path can increase the longitudinal current component in the vertical Hall device. According to the left-hand rule, the higher the longitudinal current ratio, the more moving electrons will be deflected in the direction of motion by the Lorentz force, thereby generating a larger Hall potential difference at the Hall electrode and improving the measurement accuracy of the magnetic field.
[0071] Figure 5 For Figure 1Schematic diagram of the current distribution of the cross-section B-B' of the vertical Hall device array of the present application, as shown in Figure 5. The vertical Hall device of the present application adopts an N-type buried layer structure. By utilizing the characteristic that current tends to flow through low-resistance regions, the current flow regions flowing into the vertical Hall device array are restricted, so that the current flow paths in each vertical Hall device are concentrated within the corresponding N-type buried layer region (such as Figure 5 ). Through the introduction of multiple N-type buried layers, it is ensured that the currents in each vertical Hall device can flow independently under the condition of sharing one N-type well, ensuring the stable operation state of each vertical Hall device.
[0072] Figure 6 Schematic diagram of the alternate connection method adopted by the vertical Hall device array of the present application, as Figure 6 shown. In the vertical Hall device array of the present application, an alternate interconnection method is adopted between the signal electrodes of multiple vertical Hall devices, and four signals alternately flow through the four signal electrodes of the vertical Hall device. The specific connection method is as follows:
[0073] (1) The first ohmic electrode 51 of the (1 + m)-th Hall device, the first Hall electrode 53 of the (2 + m)-th Hall device, the second ohmic electrode 52 of the (3 + m)-th Hall device, and the second Hall electrode 54 of the (4 + m)-th Hall device are interconnected to form a current excitation signal input port Iin. Wherein, m = 4(M - 1), and M is 1, 2, 3....
[0074] (2) The second ohmic electrode 52 of the (1 + m)-th Hall device, the second Hall electrode 54 of the (2 + m)-th Hall device, the first ohmic electrode 51 of the (3 + m)-th Hall device, and the first Hall electrode 53 of the (4 + m)-th Hall device are interconnected to form a current excitation signal output port Iout. Wherein, m = 4(M - 1), and M is 1, 2, 3....
[0075] (3) The first Hall electrode 53 of the (1 + m)-th Hall device, the second ohmic electrode 52 of the (2 + m)-th Hall device, the second Hall electrode 54 of the (3 + m)-th Hall device, and the first ohmic electrode 51 of the (4 + m)-th Hall device are interconnected to form a first Hall potential detection port Vhall1. Wherein, m = 4(M - 1), and M is 1, 2, 3....
[0076] (4) The second Hall electrode 54 of the (1 + m)-th Hall device, the first ohmic electrode 51 of the (2 + m)-th Hall device, the first Hall electrode 53 of the (3 + m)-th Hall device, and the second ohmic electrode 52 of the (4 + m)-th Hall device are interconnected to form a second Hall potential detection port Vhall2; wherein, m = 4(M - 1), and M is 1, 2, 3....
[0077] Example 2
[0078] Figure 7 The following is a flowchart of the preparation method of the vertical Hall device array of the present application. The preparation method of the vertical Hall device array of the present application will be described in detail below with reference to Figure 7 .
[0079] First, in the first step, the P-type substrate 1 is pre-cleaned, and then an N-type well 2 is formed by N-type ion implantation followed by high-temperature annealing, as shown in (a) of Figure 7 .
[0080] In the second step, high-energy N-type ions are implanted to form an N-type buried layer 3. As shown in (b) of Figure 7 .
[0081] In the third step, a dry etching process is used to etch a trench structure 4 on the surface of the N-type well 2, as shown in (c) of Figure 7 ; then chemical vapor deposition is used to fill the trench area with silicon dioxide, as shown in (d) of Figure 7 .
[0082] In the fourth step, an N+ region 6 is formed in the N-type well 2 by high-energy phosphorus ion implantation for forming an ohmic contact with metal, as shown in (e) of Figure 7 .
[0083] In the fifth step, a metal electrode lead-out hole is lithographed on the N+ region 6, a metal layer is deposited, and the excess metal is etched to form a metal contact, as shown in (f) of Figure 7 .
[0084] Finally, it should be noted that: Although the present application has been described in detail with reference to the embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.
Claims
1. A vertical Hall device array, characterized in that, Including, P-type substrate; N-type well disposed on the P-type substrate; Trench isolation structure disposed on the surface of the N-type well; Multiple vertical Hall devices equally spaced on the N-type well; The multiple vertical Hall devices are connected by an alternating interconnection method; Further including an N-type buried layer disposed at the bottom of the N-type well and a port structure above the N-type buried layer.
2. The vertical Hall device array according to claim 1, wherein The number of the vertical Hall devices is 4N, where N is a positive integer greater than or equal to 1.
3. The vertical Hall device array according to claim 1, wherein The depth of the trench isolation structure is greater than 0.5 μm.
4. The vertical Hall device array according to claim 1, characterized in that The relationship between the distance between the vertical Hall devices and the width of the N-type buried layer is as follows: Wherein, L1 is the distance between the vertical Hall devices, and L2 is the width of the N-type buried layer.
5. The vertical Hall device array according to claim 1, characterized in that, The port structure includes a first ohmic electrode, a second ohmic electrode, a first Hall electrode, and a second Hall electrode, wherein, The second Hall electrodes are located at both ends of the port structure and are short-circuited by metal wires; An N+ region is disposed below the first ohmic electrode, the second ohmic electrode, the first Hall electrode, and the second Hall electrode, so that the first ohmic electrode, the second ohmic electrode, the first Hall electrode, and the second Hall electrode respectively form ohmic contacts with the N-type well.
6. The vertical Hall device array according to claim 5, wherein The trench isolation structure is respectively located between the first ohmic electrode, the second ohmic electrode, the first Hall electrode, and the second Hall electrode, and between the vertical Hall devices.
7. The vertical Hall device array according to claim 6, wherein The relationship between the distance between the first Hall electrode and the first ohmic electrode and the distance between the second ohmic electrode and the first Hall electrode is: Wherein, L3 is the distance between the first Hall electrode and the first ohmic electrode, and L4 is the distance between the second ohmic electrode and the first Hall electrode.
8. The vertical Hall device array according to claim 1, wherein The multiple vertical Hall devices are connected by an alternating interconnection method, including: The first ohmic electrode of the (1 + m)-th Hall device, the first Hall electrode of the (2 + m)-th Hall device, the second ohmic electrode of the (3 + m)-th Hall device, and the second Hall electrode of the (4 + m)-th Hall device are connected to form a current excitation signal input port; The second ohmic electrode of the (1 + m)-th Hall device, the second Hall electrode of the (2 + m)-th Hall device, the first ohmic electrode of the (3 + m)-th Hall device, and the first Hall electrode of the (4 + m)-th Hall device are connected to form a current excitation signal output port; The first Hall electrode of the (1 + m)-th Hall device, the second ohmic electrode of the (2 + m)-th Hall device, the second Hall electrode of the (3 + m)-th Hall device, and the first ohmic electrode of the (4 + m)-th Hall device are connected to form a first Hall potential detection port; The second Hall electrode of the (1 + m)-th Hall device, the first ohmic electrode of the (2 + m)-th Hall device, the first Hall electrode of the (3 + m)-th Hall device, and the second ohmic electrode of the (4 + m)-th Hall device are connected to form a second Hall potential detection port; Wherein, m = 4(M - 1), and M is an integer greater than or equal to 1.
9. A method for manufacturing a vertical Hall device array, including the following steps: Form an N-type well on the P-type substrate; Inject high-energy N-type ions into the N-type well to form an N-type buried layer; Etch a trench structure on the surface of the N-type well using a dry etching method; Form an N+ region on the surface of the N-type well by high-energy phosphorus ion implantation; Lithographically pattern a metal electrode lead-out hole on the surface of the N+ region, and deposit a metal layer to form a metal contact; Connect multiple said metal electrodes using an alternating interconnection method.
10. The method for preparing the vertical Hall device array according to claim 9, wherein The step of etching a trench structure on the surface of the N-type well using a dry etching method further includes: filling the trench region with silicon dioxide using chemical vapor deposition.
Citation Information
Patent Citations
Vertical Hall device array
CN217847959U