Display substrate and manufacturing method thereof, and display device

Abstract

The present disclosure relates to a display substrate and a manufacturing method thereof, and a display device, wherein a first auxiliary conductive portion is provided on a side of the first active portion of the display substrate away from or away from the third active portion, and one of the first source and the drain is connected to the first auxiliary conductive portion through a via. It is understandable that when etching the corresponding via, the first auxiliary conductive portion is exposed to the etching gas, and the conductive auxiliary layer is made of a conductive material that is not easily oxidized, and cannot dissociate an oxide bond to react with the etching gas, and naturally will not form a metal oxide, so the working performance of the oxide thin film transistor will be less affected.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Oxide thin-film transistors have become the first choice for large-size, high-resolution, low-power, and narrow-border display panels due to their advantages such as high electron mobility, low off-state current, and simple preparation process.

[0003] However, during the manufacturing process of such oxide thin film transistors, a metal oxide layer is easily formed on the surface of the oxide active layer, resulting in a large contact resistance between the oxide active layer and the first source-drain metal layer, which affects the stability of the working performance of the oxide thin film transistor.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display substrate and a manufacturing method thereof, and a display device.

[0006] According to one aspect of the present disclosure, a display substrate is provided, comprising a base substrate, an oxide active layer, an auxiliary conductive layer, a first gate insulating layer, a first gate electrode, an interlayer insulating layer and a first source-drain metal layer, wherein the oxide active layer is arranged on the base substrate, the oxide active layer comprises a second active portion and a first active portion and a third active portion arranged on opposite sides of the second active portion; the auxiliary conductive layer comprises at least one auxiliary conductive portion, and the auxiliary conductive portion is arranged on one side of the first active portion or the third active portion; the first gate insulating layer is arranged on a side of the oxide active layer away from the base substrate and covers the auxiliary conductive layer; the first gate electrode is arranged on a side of the first gate insulating layer away from the base substrate, and the orthographic projection of the first gate electrode on the base substrate coincides with the orthographic projection of the second active portion on the base substrate; the interlayer insulating layer is arranged on a side of the first gate electrode away from the base substrate; the first source-drain metal layer comprises a first source electrode and a drain electrode, and one of the first source electrode and the drain electrode is connected to the auxiliary conductive portion through a via.

[0007] In one embodiment of the present disclosure, the auxiliary conductive layer includes two auxiliary conductive parts, which are respectively arranged on one side of the first active part and the third active part, and the first source and the drain are connected to the two auxiliary conductive parts through vias.

[0008] In one embodiment of the present disclosure, two auxiliary conductive parts are respectively arranged on a side of the first active part and the third active part away from the base substrate, the orthographic projection of one auxiliary conductive part on the base substrate is located within the orthographic projection of the first active part on the base substrate, and the orthographic projection of the other auxiliary conductive part on the base substrate is located within the orthographic projection of the third active part on the base substrate.

[0009] In one embodiment of the present disclosure, two auxiliary conductive parts are respectively arranged on a surface of the first active part and the third active part close to the base substrate, the orthographic projections of the two auxiliary conductive parts on the base substrate both exceed the edge of the orthographic projection of the oxide active layer on the base substrate, the first source is connected to a portion of an auxiliary conductive part that does not overlap with the active layer, and the drain is connected to a portion of the other auxiliary conductive part that does not overlap with the active layer.

[0010] In one embodiment of the present disclosure, the orthographic projections of the two auxiliary conductive parts on the base substrate both extend beyond the edge of the orthographic projection of the oxide active layer on the base substrate by 3 um-5 um.

[0011] In one embodiment of the present disclosure, the display substrate also includes a second gate and a second gate insulating layer, the second gate is arranged between the base substrate and the oxide active layer, the second gate insulating layer is arranged between the second gate and the oxide active layer, covering the second gate, and the orthographic projection of the second gate on the base substrate coincides with the orthographic projection of the second active portion on the base substrate.

[0012] According to another aspect of the present disclosure, a display device is provided. The display device includes the display substrate provided in one aspect of the present disclosure.

[0013] According to another aspect of the present disclosure, a method for manufacturing a display substrate is provided, the method comprising:

[0014] providing a substrate base plate;

[0015] Forming an oxide active layer on the base substrate, the oxide active layer comprising a second active portion and a first active portion and a third active portion disposed on opposite sides of the second active portion;

[0016] forming an auxiliary conductive layer on one side of the oxide active layer, wherein the auxiliary conductive layer comprises at least one auxiliary conductive portion, and the auxiliary conductive portion is disposed on one side of at least one of the first active portion or the third active portion;

[0017] forming a first gate insulating layer on a side of the oxide active layer and the auxiliary conductive layer away from the substrate;

[0018] forming a first gate electrode on a side of the first gate insulating layer away from the substrate;

[0019] forming an interlayer insulating layer on a side of the first gate away from the substrate;

[0020] forming a via hole passing through the interlayer insulating layer and the first gate insulating layer;

[0021] A first source electrode and a drain electrode are formed on a side of the interlayer insulating layer away from the base substrate, and at least one of the first source electrode and the drain electrode is connected to the auxiliary conductive part through a via hole.

[0022] In one embodiment of the present disclosure, forming an auxiliary conductive layer on one side of the oxide active layer includes:

[0023] forming an auxiliary conductive layer on a side of the oxide active layer away from the substrate;

[0024] The auxiliary conductive layer is patterned to retain the auxiliary conductive portion on at least one of the first active portion or the third active portion, or the auxiliary conductive portion is printed on at least one of the first active portion or the third active portion by nanoimprinting.

[0025] In one embodiment of the present disclosure, forming an auxiliary conductive layer on one side of the oxide active layer includes:

[0026] forming an auxiliary conductive layer on a side of the oxide active layer close to the substrate;

[0027] The auxiliary conductive layer is patterned to retain the auxiliary conductive portion on at least one of the active portion or the third active portion, and the orthographic projection of the auxiliary conductive portion on the base substrate exceeds the edge of the orthographic projection of the oxide active layer on the base substrate.

[0028] In the display substrate disclosed in the present invention, an auxiliary conductive part is provided on a side of the first active part away from or the third active part, and one of the first source and the drain is connected to the auxiliary conductive part through a via. It is understandable that when etching the corresponding via, the auxiliary conductive part is exposed to the etching gas, and the conductive auxiliary layer is usually made of a conductive material that is not easily oxidized, and cannot dissociate an oxide bond to react with the etching gas, and naturally will not form a metal oxide, so the working performance of the oxide thin film transistor will be less affected.

[0029] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0031] Figure 1It is a schematic structural diagram of a display substrate involved in an embodiment of the present disclosure.

[0032] Figure 2 It is a schematic structural diagram of another display substrate involved in an embodiment of the present disclosure.

[0033] Figure 3 It is a schematic structural diagram of another display substrate involved in an embodiment of the present disclosure.

[0034] Figure 4 The figure is a schematic diagram of the structure of another display substrate involved in the embodiment of the present disclosure.

[0035] Figure 5 It is a schematic structural diagram of another display substrate involved in an embodiment of the present disclosure.

[0036] Figure 6 The present invention is a flow chart of a method for manufacturing a display substrate according to an embodiment of the present disclosure.

[0037] Description of reference numerals:

[0038] 11. Base substrate, 12. Buffer layer, 13. Oxide thin film transistor, 130. Auxiliary conductive layer, 1301. Third auxiliary conductive part, 1302. First auxiliary conductive part, 131. Oxide active layer, 1311. First active part, 1312. Second active part, 1313. Third active part, 132. First gate insulating layer, 133. First gate, 134. Second gate, 135. Interlayer insulating layer, 136. First source, 137. Drain, 138. Second gate insulating layer, 139. Second source, 14. Planarization layer group, 141. First planarization layer, 142. Second planarization layer, 15. Pixel defining layer, 16. Sub-pixel, 161. Pixel electrode, 162. Light-emitting layer, 163. Common electrode, 17. Encapsulation layer, 171. First inorganic encapsulation layer, 172. Organic encapsulation layer, 173. Second inorganic encapsulation layer. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0040] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0041] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0042] The oxide semiconductor materials in existing oxide thin film transistors are mostly indium gallium zinc oxide (IGZO) materials. The performance of oxide thin film transistors is mainly reflected in the performance of the oxide semiconductor layer. In the process of oxide semiconductor layer manufacturing, during the via etching process, the oxide semiconductor layer is exposed to the etching gas, which can cause significant damage to the exposed surface of the oxide semiconductor layer, so that more oxide bonds are dissociated from the oxide semiconductor layer, and the dissociated oxide bonds can react with the first source and drain metal layer through the vias, thereby forming a metal oxide layer on the exposed surface of the oxide semiconductor layer. The metal oxide layer makes the contact resistance between the oxide active layer and the first source and drain metal layer larger, which will affect the stability of the working performance of the oxide thin film transistor, and further affect the display effect of the display substrate.

[0043] Based on this, the present disclosure provides a display substrate. Figures 1 to 5As shown, the display substrate includes a base substrate 11, an oxide active layer 131, an auxiliary conductive layer 130, a first gate insulating layer 132, a first gate electrode 133, an interlayer insulating layer 135 and a first source-drain metal layer. The oxide active layer 131 is disposed on the base substrate 11. The oxide active layer 131 includes a first active portion 1312 and a first active portion 1311 and a third active portion 1313 disposed on opposite sides of the first active portion 1312. The auxiliary conductive layer 130 includes at least one auxiliary conductive portion, which is disposed on one side of the first active portion 1311 or the third active portion 1313. The first gate insulating layer 132 is arranged on the side of the oxide active layer 131 away from the base substrate 11, and covers the auxiliary conductive layer 130; the first gate 133 is arranged on the side of the first gate insulating layer 132 away from the base substrate 11, and the orthographic projection of the first gate 133 on the base substrate 11 coincides with the orthographic projection of the first active portion 1312 on the base substrate 11; the interlayer insulating layer 135 is arranged on the side of the first gate 133 away from the base substrate 11; the first source-drain metal layer includes a first source 136 and a drain 137, and one of the first source 136 and the drain 137 is connected to the auxiliary conductive portion through a via.

[0044] An auxiliary conductive portion is provided on one side of the first active portion 1311 away from or away from the third active portion 1313, and one of the first source 136 and the drain 137 is connected to the auxiliary conductive portion through a via. It can be understood that when etching the corresponding via, the auxiliary conductive portion is exposed to the etching gas, and the conductive auxiliary layer is usually made of a conductive material that is not easily oxidized, and cannot dissociate an oxide bond to react with the etching gas, and naturally will not form a metal oxide, so the working performance of the oxide thin film transistor 13 will be less affected.

[0045] It should be noted that the material of the substrate can be glass materials such as soda-lime glass, quartz glass, sapphire glass, or metal materials such as stainless steel, aluminum, nickel, etc. The substrate can also be a flexible substrate, for example, the material of the substrate can be polyimide (PI). The substrate can also be a composite of multiple layers of materials, for example, the substrate can include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0046] The oxide active layer refers to the type used in the existing oxide thin film transistor 13, including but not limited to ZnO, MgZnO, Zn-Sn-O (ZTO), In-Zn-O (IZO), SnO2, Ga2O3, In-Ga-O (IGO), In2O3, In-Sn-O (ITO) and In-Ga-Zn-O (IGZO). In general, the oxide semiconductor layer includes indium gallium zinc oxide (IGZO).

[0047] The material of the auxiliary conductive layer 130 includes, but is not limited to, molybdenum (Mo), aluminum (Al), neodymium (Nd), and titanium (Ti). Molybdenum alloy, aluminum alloy, neodymium alloy, titanium alloy, and titanium nitride (TiN) may also be used. The auxiliary conductive layer is usually set as one layer, such as a layer of molybdenum or a layer of titanium. The auxiliary conductive layer includes one layer. It can also be set as two or more layers, for example: the auxiliary conductive layer includes three metal layers of different materials, such as a layer of molybdenum, a layer of aluminum, a layer of neodymium or aluminum, a layer of neodymium, and a layer of titanium, which are not listed here one by one; it can also be that a layer of metal of different material is set between two layers of metal of the same material, for example, two layers of titanium and a layer of aluminum between the two layers of titanium.

[0048] The material of the first gate insulating layer can be SiO2.

[0049] The material of the first gate electrode and the material of the auxiliary conductive layer may be the same, which will not be described in detail herein.

[0050] The interlayer insulating layer may be made of SiO2 or SiNx.

[0051] The material of the first source-drain metal layer and the material of the auxiliary conductive layer may be the same, and will not be described in detail herein.

[0052] The oxide active layer 131 includes a first active portion 1312 and a first active portion 1311 and a third active portion 1313 disposed on opposite sides of the first active portion 1312; the auxiliary conductive layer 130 includes a first auxiliary conductive portion 1302, and the first auxiliary conductive portion 1302 is disposed on one side of the first active portion 1311 or the third active portion 1313; the first gate insulating layer 132 is disposed on a side of the oxide active layer 131 away from the substrate 11, and covers the auxiliary conductive layer 130. The first gate electrode 133 is arranged on a side of the first gate insulating layer 132 away from the substrate 11, and the orthographic projection of the first gate electrode 133 on the substrate 11 coincides with the orthographic projection of the first active portion 1312 on the substrate 11; the interlayer insulating layer 135 is arranged on a side of the first gate electrode 133 away from the substrate 11; the first source-drain metal layer includes a first source electrode 136 and a drain electrode 137, and one of the first source electrode 136 and the drain electrode 137 is connected to the first auxiliary conductive portion 1302 through a via.

[0053] It is understandable that the auxiliary conductive portion may be provided on only one side of the first active portion 1311 or the third active portion 1313, for example, the auxiliary conductive portion may be provided on only one side of the first active portion 1311. In this case, the third active portion 1313 is still exposed to the etching gas, so that a metal oxide layer is formed on the surface of the third active portion 1313, and the working performance of the oxide thin film transistor 13 is still affected.

[0054] Therefore, auxiliary conductive parts are usually arranged on both the first active part 1311 and the first active part 1312, and the two auxiliary conductive parts are defined as the first auxiliary conductive part 1302 and the third auxiliary conductive part 1301, the first auxiliary conductive part 1302 is arranged on one side of the first active part 1311 or the third active part 1313, and the third auxiliary conductive part 1301 is arranged on one side of the other of the first active part 1311 or the third active part 1313, one of the first source 136 and the drain 137 is connected to the first auxiliary conductive part 1302 through a via, and the other of the first source 136 and the drain 137 is connected to the third auxiliary conductive part 1301 through a via. When etching two vias, the first auxiliary conductive part 1302 and the third auxiliary conductive part 1301 are exposed to the etching gas, and the first active part 1311 and the third active part 1313 are both covered by the auxiliary conductive layer 130. The entire active layer will not form metal oxide, and the impact on the working performance of the oxide thin film transistor 13 will be further reduced or eliminated.

[0055] like Figure 1 and Figure 2 As shown, in one embodiment of the disclosed embodiment, the auxiliary conductive layer 130 is disposed on a side of the oxide active layer 131 away from the base substrate 11 .

[0056] See also Figure 1 , an auxiliary conductive portion may be provided on a side of the first active portion 1311 or the third active portion 1313 that is away from the base substrate 11. For example, a third auxiliary conductive portion 1301 may be provided on a side of the third active portion 1313 that is away from the base substrate 11. The orthographic projection of the third auxiliary conductive portion 1301 on the base substrate 11 is located within the orthographic projection of the third active portion 1313 on the base substrate 11. The first source electrode 136 is connected to the third auxiliary conductive portion 1301 through a via. Exemplarily, the orthographic projection of the third auxiliary conductive portion 1301 on the base substrate 11 may coincide with the orthographic projection of the third active portion 1313 on the base substrate 11.

[0057] See also Figure 2, auxiliary conductive portions may be provided on the side of the first active portion 1311 and the third active portion 1313 away from the base substrate 11. Specifically, the first auxiliary conductive portion 1302 is provided on the side of the first active portion 1311 away from the base substrate 11, and the orthographic projection of the first auxiliary conductive portion 1302 on the base substrate 11 is located within the orthographic projection of the first active portion 1311 on the base substrate 11. The third auxiliary conductive portion 1301 is provided on the side of the third active portion 1313 away from the base substrate 11, and the orthographic projection of the third auxiliary conductive portion 1301 on the base substrate 11 is located within the orthographic projection of the third active portion 1313 on the base substrate 11. Exemplarily, the orthographic projection of the first auxiliary conductive portion 1302 on the base substrate 11 may coincide with the orthographic projection of the first active portion 1311 on the base substrate 11, and the orthographic projection of the third auxiliary conductive portion 1301 on the base substrate 11 coincides with the orthographic projection of the third active portion 1313 on the base substrate 11.

[0058] A first gate insulating layer 132 is provided on one side of the oxide active layer 131 and the auxiliary conductive layer 130 away from the base substrate 11, and the first gate insulating layer 132 covers the oxide active layer 131 and the auxiliary conductive layer 130. A first gate 133 is provided on one side of the first gate insulating layer 132 away from the base substrate 11, and the orthographic projection of the first gate 133 on the base substrate 11 coincides with the orthographic projection of the first active portion 1312 on the base substrate 11. An interlayer insulating layer 135 is provided on one side of the first gate 133 away from the base substrate 11, and the interlayer insulating layer 135 covers the first gate 133 and the first gate insulating layer 132. The interlayer insulating layer 135 and the first gate insulating layer 132 are provided with vias corresponding to the first source 136 and the drain 137. A first source-drain metal layer is disposed on one side of the interlayer insulating layer 135 away from the base substrate 11 . The first source-drain metal layer includes a first source electrode 136 and a drain electrode 137 . The first source electrode 136 and the drain electrode 137 are respectively connected to the first auxiliary conductive part 1302 and the third auxiliary conductive part 1301 through vias.

[0059] It should be emphasized that the orthographic projection of the via corresponding to the first source 136 on the base substrate 11 is located within the orthographic projection of the first auxiliary conductive portion 1302 on the base substrate 11, and the orthographic projection of the via corresponding to the drain 137 on the base substrate 11 is located within the orthographic projection of the third auxiliary conductive portion 1301 on the base substrate 11. It can be understood that the area of ​​the first auxiliary conductive portion 1302 is larger than the area of ​​the via corresponding to the first source 136, and the area of ​​the third auxiliary conductive portion 1301 is larger than the area of ​​the via corresponding to the drain 137.

[0060] It can be understood that when the via holes are formed by etching the interlayer insulating layer 135 and the first gate insulating layer 132 , the via hole etching process can be protected by the auxiliary conductive layer 130 to prevent the oxide active layer 131 from being damaged.

[0061] like Figure 3 and Figure 4 As shown, in one embodiment of the present disclosure, the auxiliary conductive layer 130 is disposed on a side of the oxide active layer 131 that is away from the substrate 11. Figure 1 and Figure 2 The difference of the oxide thin film transistor 13 is that the auxiliary conductive layer 130 is arranged on one side of the base substrate 11 , and the oxide active layer 131 is arranged on a side of the auxiliary conductive layer 130 away from the base substrate 11 .

[0062] See also Figure 3 A portion of the oxide active layer 131 overlaps the third auxiliary conductive portion 1301, a portion of the third auxiliary conductive portion 1301 overlaps with the oxide active layer 131, and another portion of the third auxiliary conductive portion 1301 does not overlap with the oxide active layer 131, and the drain 137 is connected to another portion of the third auxiliary conductive portion 1301 that does not overlap with the active layer.

[0063] See also Figure 4 Alternatively, a portion of the oxide active layer 131 is located between the first auxiliary conductive portion 1302 and the third auxiliary conductive portion 1301, and another portion overlaps the first auxiliary conductive portion 1302 and the third auxiliary conductive portion 1301. The edge of the orthographic projection of the oxide active layer 131 on the base substrate 11 is located within the orthographic projection of the auxiliary conductive layer 130 on the base substrate 11, that is, the edge of the orthographic projection of the auxiliary conductive layer 130 on the base substrate 11 exceeds the edge of the orthographic projection of the oxide active layer 131 on the base substrate 11.

[0064] Generally, the edge of the orthographic projection of the auxiliary conductive layer 130 on the base substrate 11 exceeds the edge of the orthographic projection of the oxide active layer 131 on the base substrate 11 by 3-5 um. Specifically, the orthographic projection of the first auxiliary conductive portion 1302 on the base substrate 11 exceeds the edge of the orthographic projection of the oxide active layer 131 on the base substrate 11 by 3-5 um, and the orthographic projection of the third auxiliary conductive portion 1301 on the base substrate 11 exceeds the edge of the orthographic projection of the oxide active layer 131 on the base substrate 11 by 3-5 um.

[0065] It can be understood that a portion of the first auxiliary conductive part 1302 overlaps with the oxide active layer 131, the first source 136 is connected to another portion of the first auxiliary conductive part 1302 that does not overlap with the oxide active layer 131, a portion of the third auxiliary conductive part 1301 overlaps with the oxide active layer 131, and the drain 137 is connected to another portion of the third auxiliary conductive part 1301 that does not overlap with the active layer.

[0066] It should be noted that the overlapping portion of the oxide active layer 131 and the first auxiliary conductive portion 1302 is part or all of the first active portion 1311, the overlapping portion of the oxide active layer 131 and the third auxiliary conductive portion 1301 is part or all of the third active portion 1313, and the first active portion 1312 does not overlap with the auxiliary conductive layer 130.

[0067] The first source electrode 136 passes through the interlayer insulating layer 135 and the first gate insulating layer 132, and is connected to a portion of the first auxiliary conductive portion 1302 that does not overlap with the active layer. The drain electrode 137 passes through the interlayer insulating layer 135 and the first gate insulating layer 132, and is connected to a portion of the third auxiliary conductive portion 1301 that does not overlap with the active layer.

[0068] See also Figure 5 , it can also be that one of the first active portion 1311 and the third active portion 1313 is provided with an auxiliary conductive portion on a side away from the base substrate 11, and the other is provided with an auxiliary conductive portion on a side close to the base substrate 11. Specifically, the first active portion 1311 is provided with a first auxiliary conductive portion 1302 on a side away from the base substrate 11, and the third active portion 1313 is provided with a third auxiliary conductive portion 1301 on a side close to the base substrate 11, the orthographic projection of the first auxiliary conductive portion 1302 on the base substrate 11 coincides with the orthographic projection of the first active portion 1311 on the base substrate 11, and the orthographic projection of the third auxiliary conductive portion 1301 on the base substrate 11 exceeds the edge of the orthographic projection of the oxide active layer 131 on the base substrate 11 by 3-5 um.

[0069] in addition, Figures 3 to 5 The oxide thin film transistor 13 shown is a double-deletion structure, and the oxide thin film transistor 13 further includes a second gate 134 and a second gate insulating layer 138, and the second gate 134 and the second gate insulating layer 138 are arranged between the base substrate 11 and the oxide active layer 131. Specifically, the second gate 134 is arranged between the base substrate 11 and the oxide active layer 131, and the second gate insulating layer 138 is arranged between the second gate 134 and the oxide active layer 131. The second gate insulating layer 138 covers the second gate 134, and the orthographic projection of the second gate 134 on the base substrate 11 coincides with the orthographic projection of the first active portion 1312 on the base substrate 11.

[0070] The oxide active layer 131, the auxiliary conductive layer 130, the first gate insulating layer 132, the first gate electrode 133, the interlayer insulating layer 135, the first source electrode 136 and the drain electrode 137 constitute an oxide thin film transistor 13. A first planarization layer 141 may be provided on a side of the first source electrode 136 and the drain electrode 137 away from the base substrate 11, a second source-drain metal layer may be provided on a side of the first planarization layer 141 away from the base substrate 11, a second planarization layer 142 may be provided on a side of the second source-drain metal layer away from the base substrate 11, and the second planarization layer 142 covers the second source-drain metal layer and a side of the first planarization layer 141 away from the base substrate 11. The second source-drain metal layer includes a second source electrode 139, and the second source electrode 139 is connected to the first source electrode 136 through a via.

[0071] It should be noted that, regardless of the structure of the oxide thin film transistor, a buffer layer 12 is usually provided between the oxide thin film transistor 13 and the base substrate 11 , and the oxide thin film transistor 13 is provided on a side of the buffer layer 12 away from the base substrate 11 .

[0072] The display substrate provided in the embodiment of the present disclosure includes a plurality of oxide thin film transistors 13. In addition to the plurality of oxide thin film transistors 13, a pixel layer is provided on a side of the plurality of oxide thin film transistors 13 away from the base substrate 11. The first planarization layer 141 and the second planarization layer 142 form a planarization layer group 14, and the pixel layer can be provided on a side of the planarization layer group 14 away from the base substrate 11.

[0073] The pixel layer includes a pixel defining layer 15 and a plurality of sub-pixels 16. The pixel defining layer 15 has a plurality of pixel openings, and the plurality of sub-pixels 16 are respectively arranged in the plurality of pixel openings. The plurality of sub-pixels 16 are arrayed and distributed on the side of the planarization layer group 14 away from the base substrate 11. It should be noted that the sub-pixels may include red sub-pixels, green sub-pixels, and blue sub-pixels according to different luminescent colors.

[0074] The sub-pixel 16 may include a plurality of pixel electrodes 161, a light-emitting layer 162 and a common electrode 163, wherein the pixel electrode 161 is located on a surface of the planarization layer group 14 away from the base substrate 11, the light-emitting layer 162 is located on a surface of the pixel electrode 161 away from the base substrate 11, and the common electrode 163 is located on a surface of the light-emitting layer 162 away from the base substrate 11.

[0075] The pixel electrode 161 is connected to the first source electrode 136 or the second source electrode 139. When the driving circuit layer 13 only includes the first source electrode 136 and the first planarization layer 141, the pixel electrode 161 is connected to the first source electrode 136 through the via hole on the first planarization layer 141, and the pixel definition layer 15 is provided to cover the first electrode 161 and the first planarization layer 141. When the driving circuit layer 13 also includes the second source-drain metal layer and the second planarization layer 142, the pixel electrode 161 is connected to the second source electrode 139 through the via hole on the second planarization layer 142, and the pixel definition layer 15 is provided to cover the second first source-drain metal layer and the second planarization layer 142.

[0076] The common electrode 163 can be used as a cathode, and the pixel electrode 161 can be used as an anode. The pixel electrode 161 is connected to the positive electrode of the power supply, and the common electrode 163 is connected to the negative electrode of the power supply. A signal can be applied through the pixel electrode 161 and the common electrode 163 to drive the light-emitting layer 162 to emit light to display an image. The specific light-emitting principle will not be described in detail here. The light-emitting layer 162 may include an electro-induced organic light-emitting material. For example, the light-emitting layer 162 may include an auxiliary layer and a light-emitting material layer sequentially stacked on the pixel electrode 161. Generally, a pattern area is set on the mask plate, and the auxiliary layer of different color sub-pixels and the light-emitting layer 162 of different color sub-pixels are formed by evaporation and other processes.

[0077] In addition, the display substrate of the present disclosure may further include an encapsulation layer 17, which is disposed on a side of the pixel layer 16 away from the base substrate 11, thereby encapsulating the pixel layer 16 to prevent water and oxygen corrosion. The encapsulation layer 17 may be a single-layer or multi-layer structure, and the material of the encapsulation layer 17 may include organic or inorganic materials, which are not particularly limited here.

[0078] In this embodiment, the encapsulation layer 17 may include a first inorganic encapsulation layer 171, an organic encapsulation layer 172 and a second inorganic encapsulation layer 173. The first inorganic encapsulation layer 171 is arranged on the side of the pixel layer 16 away from the base substrate 11, the organic encapsulation layer 172 is arranged on the side of the first inorganic encapsulation layer 171 away from the base substrate 11, and the second inorganic encapsulation layer 173 is arranged on the side of the organic encapsulation layer 172 away from the base substrate 11.

[0079] Below Figures 1 to 5 The method for manufacturing an oxide thin film transistor is described below. Figure 6 As shown, the production method includes:

[0080] Step S10, providing a base substrate, and forming an oxide active layer on the base substrate, wherein the oxide active layer includes a second active portion and a first active portion and a third active portion disposed on opposite sides of the second active portion;

[0081] Step S20, forming an auxiliary conductive layer on one side of the oxide active layer, wherein the auxiliary conductive layer includes at least one auxiliary conductive portion, and the auxiliary conductive portion is disposed on one side of at least one of the first active portion or the third active portion;

[0082] Step S30, forming a first gate insulating layer on a side of the oxide active layer and the auxiliary conductive layer away from the substrate;

[0083] Step S40, forming a first gate on a side of the first gate insulating layer away from the substrate;

[0084] Step S50, forming an interlayer insulating layer on a side of the first gate away from the substrate;

[0085] Step S60, forming a via hole passing through the interlayer insulating layer and the first gate insulating layer;

[0086] Step S70: forming a first source and a drain on a side of the interlayer insulating layer away from the base substrate, and at least one of the first source and the drain is connected to the auxiliary conductive part through a via hole.

[0087] In step S10, a base substrate is provided. The material of the base substrate can be selected according to actual needs. In one embodiment of the present disclosure, the base substrate can be a base substrate of an inorganic material or a base substrate of an organic material.

[0088] When forming an oxide active layer on a substrate, a buffer layer may be first formed on the substrate, and then the oxide active layer may be formed on the side of the buffer layer away from the substrate. The buffer layer is generally deposited on the substrate by plasma enhanced chemical vapor deposition (PECVD), and the active layer is generally formed on the buffer layer by a coating process, and the coating process may specifically be a magnetron sputtering process. The material of the buffer layer may be an inorganic insulating material such as silicon oxide or silicon nitride. The buffer layer may be a single layer of inorganic material or a multi-layered layer of inorganic material. The thickness of the buffer layer is generally between 100 and 200 nm. The thickness of the oxide active layer is generally After the oxide active layer is plated, the substrate is placed in an annealing furnace for annealing.

[0089] The entire oxide active layer is patterned to form a patterned oxide active layer, which includes a first active portion, a second active portion and a third active portion. The first active portion and the third active portion are doped with heavy metals using a mask process to achieve conductorization of the first active portion and the third active portion, while the second active portion still maintains semiconductor properties.

[0090] In step S20, an auxiliary conductive layer is deposited on the oxide active layer, and the auxiliary conductive part on one side of the first active part can be retained, that is, only the first auxiliary conductive part is retained. The auxiliary conductive parts on one side of the first active part and one side of the third active part can also be retained at the same time, that is, the first auxiliary conductive part and the third auxiliary conductive part.

[0091] When the auxiliary conductive layer is arranged on a side of the active layer away from the base substrate, the orthographic projection of one auxiliary conductive part on the base substrate coincides with the orthographic projection of the first active part on the base substrate, and the orthographic projection of another auxiliary conductive part on the base substrate coincides with the orthographic projection of the third active part on the base substrate.

[0092] When forming the auxiliary conductive layer of the structure, the auxiliary conductive part is formed by patterning the auxiliary conductive layer, or by printing on the oxide active layer by nano-imprinting.

[0093] When the auxiliary conductive layer is arranged on a side of the active layer close to the base substrate, the orthographic projection of one auxiliary conductive part on the base substrate exceeds the edge of the orthographic projection of the oxide active layer on the base substrate, and the orthographic projection of another auxiliary conductive part on the base substrate exceeds the edge of the orthographic projection of the oxide active layer on the base substrate.

[0094] When forming the auxiliary conductive layer of the structure, the auxiliary conductive layer is patterned to retain the auxiliary conductive part on at least one of the active part or the third active part, and the orthographic projection of the auxiliary conductive part on the base substrate exceeds the edge of the orthographic projection of the oxide active layer on the base substrate.

[0095] In step S30, a first gate insulating layer is deposited, and the first gate insulating layer covers the second active portion, the first auxiliary conductive portion, the third auxiliary conductive portion and the buffer layer. The thickness of the gate insulating layer is generally

[0096] In step S40, a first gate metal layer is deposited and patterned to form a first gate. The thickness of the first gate metal layer is generally

[0097] In step S50, an interlayer insulating layer is deposited, and the interlayer insulating layer covers the gate electrode and the gate insulating layer. The thickness of the interlayer insulating layer is

[0098] In step S60, the interlayer insulating layer and the gate insulating layer are etched to form vias extending to the surfaces of the first auxiliary conductive portion and the third auxiliary conductive portion respectively. Due to the protection of the auxiliary conductive layer, the via etching process can avoid damage to the oxide active layer.

[0099] In step S70, a first source-drain metal layer is formed on a side of the interlayer insulating layer away from the base substrate, and the first source-drain metal layer is patterned to form a first source and a drain. The first source is connected to the first auxiliary conductive part through a via, and the drain is connected to the third auxiliary conductive part through a via.

[0100] A first planarization layer can be formed on a side of the first source / drain metal layer away from the base substrate, a second source electrode can be formed on a side of the first planarization layer away from the base substrate, a second planarization layer can be formed on a side of the second source electrode away from the base substrate, a pixel electrode layer can be formed on a side of the second planarization layer away from the base substrate, a pixel opening can be provided on the pixel electrode layer to expose the second planarization layer, a pixel electrode can be formed in the pixel opening, a light-emitting layer can be formed on a side of the pixel electrode away from the base substrate, a common electrode can be formed on a side of the light-emitting layer away from the base substrate, and an encapsulation layer can be formed on a side of the common electrode away from the base substrate.

[0101] The present disclosure provides a display device, which may include any one of the display substrates described above.

[0102] It should be noted that, in addition to the display substrate, the display device also includes other necessary parts and components, such as a housing, a circuit board, a power cord, etc. Those skilled in the art may make corresponding supplements according to the specific use requirements of the display device, which will not be repeated here.

[0103] The display device can be a traditional electronic device, such as a mobile phone, a computer, a television, and a camcorder, or it can be an emerging wearable device, such as VR glasses, which are not listed here one by one.

[0104] This application is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not disclosed in the present disclosure. The description and embodiments are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0105] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display substrate, characterized in that: include: substrate substrate; An oxide active layer, disposed on the base substrate, the oxide active layer comprising a second active portion and a first active portion and a third active portion disposed on opposite sides of the second active portion; an auxiliary conductive layer, comprising at least one auxiliary conductive portion, wherein the auxiliary conductive portion is disposed on one side of the first active portion or the third active portion; A first gate insulating layer, disposed on a side of the oxide active layer away from the substrate and covering the auxiliary conductive layer; A first gate is disposed on a side of the first gate insulating layer away from the base substrate, and an orthographic projection of the first gate on the base substrate coincides with an orthographic projection of the second active portion on the base substrate; An interlayer insulating layer, provided on a side of the first gate away from the substrate; The first source-drain metal layer includes a first source electrode and a drain electrode, wherein one of the first source electrode and the drain electrode is connected to the auxiliary conductive part through a via hole.

2. The display substrate according to claim 1, characterized in that: The auxiliary conductive layer includes two auxiliary conductive parts, the two auxiliary conductive parts are respectively arranged on one side of the first active part and the third active part, and the first source and the drain are connected to the two auxiliary conductive parts through vias.

3. The display substrate according to claim 2, characterized in that: The two auxiliary conductive parts are respectively arranged on a side of the first active part and the third active part away from the base substrate, the orthographic projection of one auxiliary conductive part on the base substrate is located within the orthographic projection of the first active part on the base substrate, and the orthographic projection of the other auxiliary conductive part on the base substrate is located within the orthographic projection of the third active part on the base substrate.

4. The display substrate according to claim 2, characterized in that: The two auxiliary conductive parts are respectively arranged on a surface of the first active part and the third active part close to the base substrate, the orthographic projections of the two auxiliary conductive parts on the base substrate both exceed the edge of the orthographic projection of the oxide active layer on the base substrate, the first source is connected to the part of the one auxiliary conductive part that does not overlap with the active layer, and the drain is connected to the part of the other auxiliary conductive part that does not overlap with the active layer.

5. The display substrate according to claim 4, characterized in that: The orthographic projections of the two auxiliary conductive parts on the base substrate both extend beyond the edge of the orthographic projection of the oxide active layer on the base substrate by 3 um-5 um.

6. The display substrate according to claim 4, characterized in that: The display substrate also includes a second gate and a second gate insulating layer, the second gate is arranged between the base substrate and the oxide active layer, the second gate insulating layer is arranged between the second gate and the oxide active layer, covering the second gate, and the orthographic projection of the second gate on the base substrate coincides with the orthographic projection of the second active portion on the base substrate.

7. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 6.

8. A method for manufacturing a display substrate according to claim 1, characterized in that: The method comprises: providing a substrate base plate; Forming an oxide active layer on the base substrate, the oxide active layer comprising a second active portion and a first active portion and a third active portion disposed on opposite sides of the second active portion; forming an auxiliary conductive layer on one side of the oxide active layer, wherein the auxiliary conductive layer comprises at least one auxiliary conductive portion, and the auxiliary conductive portion is disposed on one side of at least one of the first active portion or the third active portion; forming a first gate insulating layer on a side of the oxide active layer and the auxiliary conductive layer away from the substrate; forming a first gate on a side of the first gate insulating layer away from the base substrate; forming an interlayer insulating layer on a side of the first gate away from the substrate; forming a via hole passing through the interlayer insulating layer and the first gate insulating layer; A first source and a drain are formed on a side of the interlayer insulating layer away from the base substrate, and at least one of the first source and the drain is connected to the auxiliary conductive part through a via hole.

9. The method for manufacturing a display substrate according to claim 8, characterized in that: Forming an auxiliary conductive layer on one side of the oxide active layer comprises: forming an auxiliary conductive layer on a side of the oxide active layer away from the substrate; The auxiliary conductive layer is patterned to retain the auxiliary conductive portion on at least one of the first active portion or the third active portion, or an auxiliary conductive portion is printed on at least one of the first active portion or the third active portion by nanoimprinting.

10. The method for manufacturing a display substrate according to claim 8, characterized in that: Forming an auxiliary conductive layer on one side of the oxide active layer comprises: forming an auxiliary conductive layer on a side of the oxide active layer close to the substrate; The auxiliary conductive layer is patterned to retain the auxiliary conductive portion on at least one of the active portion or the third active portion, wherein the orthographic projection of the auxiliary conductive portion on the base substrate exceeds the edge of the orthographic projection of the oxide active layer on the base substrate.

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